1 /*
2 * Copyright 2015-2017 Pengutronix, Lucas Stach <kernel@pengutronix.de>
3 * Copyright 2011-2013 Freescale Semiconductor, Inc.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/io.h>
16 #include <linux/of_device.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_domain.h>
19 #include <linux/regmap.h>
20 #include <linux/regulator/consumer.h>
21
22 #define GPC_CNTR 0x000
23
24 #define GPC_PGC_CTRL_OFFS 0x0
25 #define GPC_PGC_PUPSCR_OFFS 0x4
26 #define GPC_PGC_PDNSCR_OFFS 0x8
27 #define GPC_PGC_SW2ISO_SHIFT 0x8
28 #define GPC_PGC_SW_SHIFT 0x0
29
30 #define GPC_PGC_PCI_PDN 0x200
31 #define GPC_PGC_PCI_SR 0x20c
32
33 #define GPC_PGC_GPU_PDN 0x260
34 #define GPC_PGC_GPU_PUPSCR 0x264
35 #define GPC_PGC_GPU_PDNSCR 0x268
36 #define GPC_PGC_GPU_SR 0x26c
37
38 #define GPC_PGC_DISP_PDN 0x240
39 #define GPC_PGC_DISP_SR 0x24c
40
41 #define GPU_VPU_PUP_REQ BIT(1)
42 #define GPU_VPU_PDN_REQ BIT(0)
43
44 #define GPC_CLK_MAX 6
45
46 #define PGC_DOMAIN_FLAG_NO_PD BIT(0)
47
48 struct imx_pm_domain {
49 struct generic_pm_domain base;
50 struct regmap *regmap;
51 struct regulator *supply;
52 struct clk *clk[GPC_CLK_MAX];
53 int num_clks;
54 unsigned int reg_offs;
55 signed char cntr_pdn_bit;
56 unsigned int ipg_rate_mhz;
57 };
58
59 static inline struct imx_pm_domain *
to_imx_pm_domain(struct generic_pm_domain * genpd)60 to_imx_pm_domain(struct generic_pm_domain *genpd)
61 {
62 return container_of(genpd, struct imx_pm_domain, base);
63 }
64
imx6_pm_domain_power_off(struct generic_pm_domain * genpd)65 static int imx6_pm_domain_power_off(struct generic_pm_domain *genpd)
66 {
67 struct imx_pm_domain *pd = to_imx_pm_domain(genpd);
68 int iso, iso2sw;
69 u32 val;
70
71 /* Read ISO and ISO2SW power down delays */
72 regmap_read(pd->regmap, pd->reg_offs + GPC_PGC_PUPSCR_OFFS, &val);
73 iso = val & 0x3f;
74 iso2sw = (val >> 8) & 0x3f;
75
76 /* Gate off domain when powered down */
77 regmap_update_bits(pd->regmap, pd->reg_offs + GPC_PGC_CTRL_OFFS,
78 0x1, 0x1);
79
80 /* Request GPC to power down domain */
81 val = BIT(pd->cntr_pdn_bit);
82 regmap_update_bits(pd->regmap, GPC_CNTR, val, val);
83
84 /* Wait ISO + ISO2SW IPG clock cycles */
85 udelay(DIV_ROUND_UP(iso + iso2sw, pd->ipg_rate_mhz));
86
87 if (pd->supply)
88 regulator_disable(pd->supply);
89
90 return 0;
91 }
92
imx6_pm_domain_power_on(struct generic_pm_domain * genpd)93 static int imx6_pm_domain_power_on(struct generic_pm_domain *genpd)
94 {
95 struct imx_pm_domain *pd = to_imx_pm_domain(genpd);
96 int i, ret, sw, sw2iso;
97 u32 val;
98
99 if (pd->supply) {
100 ret = regulator_enable(pd->supply);
101 if (ret) {
102 pr_err("%s: failed to enable regulator: %d\n",
103 __func__, ret);
104 return ret;
105 }
106 }
107
108 /* Enable reset clocks for all devices in the domain */
109 for (i = 0; i < pd->num_clks; i++)
110 clk_prepare_enable(pd->clk[i]);
111
112 /* Gate off domain when powered down */
113 regmap_update_bits(pd->regmap, pd->reg_offs + GPC_PGC_CTRL_OFFS,
114 0x1, 0x1);
115
116 /* Read ISO and ISO2SW power up delays */
117 regmap_read(pd->regmap, pd->reg_offs + GPC_PGC_PUPSCR_OFFS, &val);
118 sw = val & 0x3f;
119 sw2iso = (val >> 8) & 0x3f;
120
121 /* Request GPC to power up domain */
122 val = BIT(pd->cntr_pdn_bit + 1);
123 regmap_update_bits(pd->regmap, GPC_CNTR, val, val);
124
125 /* Wait ISO + ISO2SW IPG clock cycles */
126 udelay(DIV_ROUND_UP(sw + sw2iso, pd->ipg_rate_mhz));
127
128 /* Disable reset clocks for all devices in the domain */
129 for (i = 0; i < pd->num_clks; i++)
130 clk_disable_unprepare(pd->clk[i]);
131
132 return 0;
133 }
134
imx_pgc_get_clocks(struct device * dev,struct imx_pm_domain * domain)135 static int imx_pgc_get_clocks(struct device *dev, struct imx_pm_domain *domain)
136 {
137 int i, ret;
138
139 for (i = 0; ; i++) {
140 struct clk *clk = of_clk_get(dev->of_node, i);
141 if (IS_ERR(clk))
142 break;
143 if (i >= GPC_CLK_MAX) {
144 dev_err(dev, "more than %d clocks\n", GPC_CLK_MAX);
145 ret = -EINVAL;
146 goto clk_err;
147 }
148 domain->clk[i] = clk;
149 }
150 domain->num_clks = i;
151
152 return 0;
153
154 clk_err:
155 while (i--)
156 clk_put(domain->clk[i]);
157
158 return ret;
159 }
160
imx_pgc_put_clocks(struct imx_pm_domain * domain)161 static void imx_pgc_put_clocks(struct imx_pm_domain *domain)
162 {
163 int i;
164
165 for (i = domain->num_clks - 1; i >= 0; i--)
166 clk_put(domain->clk[i]);
167 }
168
imx_pgc_parse_dt(struct device * dev,struct imx_pm_domain * domain)169 static int imx_pgc_parse_dt(struct device *dev, struct imx_pm_domain *domain)
170 {
171 /* try to get the domain supply regulator */
172 domain->supply = devm_regulator_get_optional(dev, "power");
173 if (IS_ERR(domain->supply)) {
174 if (PTR_ERR(domain->supply) == -ENODEV)
175 domain->supply = NULL;
176 else
177 return PTR_ERR(domain->supply);
178 }
179
180 /* try to get all clocks needed for reset propagation */
181 return imx_pgc_get_clocks(dev, domain);
182 }
183
imx_pgc_power_domain_probe(struct platform_device * pdev)184 static int imx_pgc_power_domain_probe(struct platform_device *pdev)
185 {
186 struct imx_pm_domain *domain = pdev->dev.platform_data;
187 struct device *dev = &pdev->dev;
188 int ret;
189
190 /* if this PD is associated with a DT node try to parse it */
191 if (dev->of_node) {
192 ret = imx_pgc_parse_dt(dev, domain);
193 if (ret)
194 return ret;
195 }
196
197 /* initially power on the domain */
198 if (domain->base.power_on)
199 domain->base.power_on(&domain->base);
200
201 if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
202 pm_genpd_init(&domain->base, NULL, false);
203 ret = of_genpd_add_provider_simple(dev->of_node, &domain->base);
204 if (ret)
205 goto genpd_err;
206 }
207
208 device_link_add(dev, dev->parent, DL_FLAG_AUTOREMOVE_CONSUMER);
209
210 return 0;
211
212 genpd_err:
213 pm_genpd_remove(&domain->base);
214 imx_pgc_put_clocks(domain);
215
216 return ret;
217 }
218
imx_pgc_power_domain_remove(struct platform_device * pdev)219 static int imx_pgc_power_domain_remove(struct platform_device *pdev)
220 {
221 struct imx_pm_domain *domain = pdev->dev.platform_data;
222
223 if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
224 of_genpd_del_provider(pdev->dev.of_node);
225 pm_genpd_remove(&domain->base);
226 imx_pgc_put_clocks(domain);
227 }
228
229 return 0;
230 }
231
232 static const struct platform_device_id imx_pgc_power_domain_id[] = {
233 { "imx-pgc-power-domain"},
234 { },
235 };
236
237 static struct platform_driver imx_pgc_power_domain_driver = {
238 .driver = {
239 .name = "imx-pgc-pd",
240 },
241 .probe = imx_pgc_power_domain_probe,
242 .remove = imx_pgc_power_domain_remove,
243 .id_table = imx_pgc_power_domain_id,
244 };
245 builtin_platform_driver(imx_pgc_power_domain_driver)
246
247 #define GPC_PGC_DOMAIN_ARM 0
248 #define GPC_PGC_DOMAIN_PU 1
249 #define GPC_PGC_DOMAIN_DISPLAY 2
250
251 static struct genpd_power_state imx6_pm_domain_pu_state = {
252 .power_off_latency_ns = 25000,
253 .power_on_latency_ns = 2000000,
254 };
255
256 static struct imx_pm_domain imx_gpc_domains[] = {
257 {
258 .base = {
259 .name = "ARM",
260 .flags = GENPD_FLAG_ALWAYS_ON,
261 },
262 }, {
263 .base = {
264 .name = "PU",
265 .power_off = imx6_pm_domain_power_off,
266 .power_on = imx6_pm_domain_power_on,
267 .states = &imx6_pm_domain_pu_state,
268 .state_count = 1,
269 },
270 .reg_offs = 0x260,
271 .cntr_pdn_bit = 0,
272 }, {
273 .base = {
274 .name = "DISPLAY",
275 .power_off = imx6_pm_domain_power_off,
276 .power_on = imx6_pm_domain_power_on,
277 },
278 .reg_offs = 0x240,
279 .cntr_pdn_bit = 4,
280 }, {
281 .base = {
282 .name = "PCI",
283 .power_off = imx6_pm_domain_power_off,
284 .power_on = imx6_pm_domain_power_on,
285 },
286 .reg_offs = 0x200,
287 .cntr_pdn_bit = 6,
288 },
289 };
290
291 struct imx_gpc_dt_data {
292 int num_domains;
293 bool err009619_present;
294 bool err006287_present;
295 };
296
297 static const struct imx_gpc_dt_data imx6q_dt_data = {
298 .num_domains = 2,
299 .err009619_present = false,
300 .err006287_present = false,
301 };
302
303 static const struct imx_gpc_dt_data imx6qp_dt_data = {
304 .num_domains = 2,
305 .err009619_present = true,
306 .err006287_present = false,
307 };
308
309 static const struct imx_gpc_dt_data imx6sl_dt_data = {
310 .num_domains = 3,
311 .err009619_present = false,
312 .err006287_present = true,
313 };
314
315 static const struct imx_gpc_dt_data imx6sx_dt_data = {
316 .num_domains = 4,
317 .err009619_present = false,
318 .err006287_present = false,
319 };
320
321 static const struct of_device_id imx_gpc_dt_ids[] = {
322 { .compatible = "fsl,imx6q-gpc", .data = &imx6q_dt_data },
323 { .compatible = "fsl,imx6qp-gpc", .data = &imx6qp_dt_data },
324 { .compatible = "fsl,imx6sl-gpc", .data = &imx6sl_dt_data },
325 { .compatible = "fsl,imx6sx-gpc", .data = &imx6sx_dt_data },
326 { }
327 };
328
329 static const struct regmap_range yes_ranges[] = {
330 regmap_reg_range(GPC_CNTR, GPC_CNTR),
331 regmap_reg_range(GPC_PGC_PCI_PDN, GPC_PGC_PCI_SR),
332 regmap_reg_range(GPC_PGC_GPU_PDN, GPC_PGC_GPU_SR),
333 regmap_reg_range(GPC_PGC_DISP_PDN, GPC_PGC_DISP_SR),
334 };
335
336 static const struct regmap_access_table access_table = {
337 .yes_ranges = yes_ranges,
338 .n_yes_ranges = ARRAY_SIZE(yes_ranges),
339 };
340
341 static const struct regmap_config imx_gpc_regmap_config = {
342 .reg_bits = 32,
343 .val_bits = 32,
344 .reg_stride = 4,
345 .rd_table = &access_table,
346 .wr_table = &access_table,
347 .max_register = 0x2ac,
348 };
349
350 static struct generic_pm_domain *imx_gpc_onecell_domains[] = {
351 &imx_gpc_domains[0].base,
352 &imx_gpc_domains[1].base,
353 };
354
355 static struct genpd_onecell_data imx_gpc_onecell_data = {
356 .domains = imx_gpc_onecell_domains,
357 .num_domains = 2,
358 };
359
imx_gpc_old_dt_init(struct device * dev,struct regmap * regmap,unsigned int num_domains)360 static int imx_gpc_old_dt_init(struct device *dev, struct regmap *regmap,
361 unsigned int num_domains)
362 {
363 struct imx_pm_domain *domain;
364 int i, ret;
365
366 for (i = 0; i < num_domains; i++) {
367 domain = &imx_gpc_domains[i];
368 domain->regmap = regmap;
369 domain->ipg_rate_mhz = 66;
370
371 if (i == 1) {
372 domain->supply = devm_regulator_get(dev, "pu");
373 if (IS_ERR(domain->supply))
374 return PTR_ERR(domain->supply);
375
376 ret = imx_pgc_get_clocks(dev, domain);
377 if (ret)
378 goto clk_err;
379
380 domain->base.power_on(&domain->base);
381 }
382 }
383
384 for (i = 0; i < num_domains; i++)
385 pm_genpd_init(&imx_gpc_domains[i].base, NULL, false);
386
387 if (IS_ENABLED(CONFIG_PM_GENERIC_DOMAINS)) {
388 ret = of_genpd_add_provider_onecell(dev->of_node,
389 &imx_gpc_onecell_data);
390 if (ret)
391 goto genpd_err;
392 }
393
394 return 0;
395
396 genpd_err:
397 for (i = 0; i < num_domains; i++)
398 pm_genpd_remove(&imx_gpc_domains[i].base);
399 imx_pgc_put_clocks(&imx_gpc_domains[GPC_PGC_DOMAIN_PU]);
400 clk_err:
401 return ret;
402 }
403
imx_gpc_probe(struct platform_device * pdev)404 static int imx_gpc_probe(struct platform_device *pdev)
405 {
406 const struct of_device_id *of_id =
407 of_match_device(imx_gpc_dt_ids, &pdev->dev);
408 const struct imx_gpc_dt_data *of_id_data = of_id->data;
409 struct device_node *pgc_node;
410 struct regmap *regmap;
411 struct resource *res;
412 void __iomem *base;
413 int ret;
414
415 pgc_node = of_get_child_by_name(pdev->dev.of_node, "pgc");
416
417 /* bail out if DT too old and doesn't provide the necessary info */
418 if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells") &&
419 !pgc_node)
420 return 0;
421
422 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
423 base = devm_ioremap_resource(&pdev->dev, res);
424 if (IS_ERR(base))
425 return PTR_ERR(base);
426
427 regmap = devm_regmap_init_mmio_clk(&pdev->dev, NULL, base,
428 &imx_gpc_regmap_config);
429 if (IS_ERR(regmap)) {
430 ret = PTR_ERR(regmap);
431 dev_err(&pdev->dev, "failed to init regmap: %d\n",
432 ret);
433 return ret;
434 }
435
436 /* Disable PU power down in normal operation if ERR009619 is present */
437 if (of_id_data->err009619_present)
438 imx_gpc_domains[GPC_PGC_DOMAIN_PU].base.flags |=
439 GENPD_FLAG_ALWAYS_ON;
440
441 /* Keep DISP always on if ERR006287 is present */
442 if (of_id_data->err006287_present)
443 imx_gpc_domains[GPC_PGC_DOMAIN_DISPLAY].base.flags |=
444 GENPD_FLAG_ALWAYS_ON;
445
446 if (!pgc_node) {
447 ret = imx_gpc_old_dt_init(&pdev->dev, regmap,
448 of_id_data->num_domains);
449 if (ret)
450 return ret;
451 } else {
452 struct imx_pm_domain *domain;
453 struct platform_device *pd_pdev;
454 struct device_node *np;
455 struct clk *ipg_clk;
456 unsigned int ipg_rate_mhz;
457 int domain_index;
458
459 ipg_clk = devm_clk_get(&pdev->dev, "ipg");
460 if (IS_ERR(ipg_clk))
461 return PTR_ERR(ipg_clk);
462 ipg_rate_mhz = clk_get_rate(ipg_clk) / 1000000;
463
464 for_each_child_of_node(pgc_node, np) {
465 ret = of_property_read_u32(np, "reg", &domain_index);
466 if (ret) {
467 of_node_put(np);
468 return ret;
469 }
470 if (domain_index >= of_id_data->num_domains)
471 continue;
472
473 pd_pdev = platform_device_alloc("imx-pgc-power-domain",
474 domain_index);
475 if (!pd_pdev) {
476 of_node_put(np);
477 return -ENOMEM;
478 }
479
480 ret = platform_device_add_data(pd_pdev,
481 &imx_gpc_domains[domain_index],
482 sizeof(imx_gpc_domains[domain_index]));
483 if (ret) {
484 platform_device_put(pd_pdev);
485 of_node_put(np);
486 return ret;
487 }
488 domain = pd_pdev->dev.platform_data;
489 domain->regmap = regmap;
490 domain->ipg_rate_mhz = ipg_rate_mhz;
491
492 pd_pdev->dev.parent = &pdev->dev;
493 pd_pdev->dev.of_node = np;
494
495 ret = platform_device_add(pd_pdev);
496 if (ret) {
497 platform_device_put(pd_pdev);
498 of_node_put(np);
499 return ret;
500 }
501 }
502 }
503
504 return 0;
505 }
506
imx_gpc_remove(struct platform_device * pdev)507 static int imx_gpc_remove(struct platform_device *pdev)
508 {
509 struct device_node *pgc_node;
510 int ret;
511
512 pgc_node = of_get_child_by_name(pdev->dev.of_node, "pgc");
513
514 /* bail out if DT too old and doesn't provide the necessary info */
515 if (!of_property_read_bool(pdev->dev.of_node, "#power-domain-cells") &&
516 !pgc_node)
517 return 0;
518
519 /*
520 * If the old DT binding is used the toplevel driver needs to
521 * de-register the power domains
522 */
523 if (!pgc_node) {
524 of_genpd_del_provider(pdev->dev.of_node);
525
526 ret = pm_genpd_remove(&imx_gpc_domains[GPC_PGC_DOMAIN_PU].base);
527 if (ret)
528 return ret;
529 imx_pgc_put_clocks(&imx_gpc_domains[GPC_PGC_DOMAIN_PU]);
530
531 ret = pm_genpd_remove(&imx_gpc_domains[GPC_PGC_DOMAIN_ARM].base);
532 if (ret)
533 return ret;
534 }
535
536 return 0;
537 }
538
539 static struct platform_driver imx_gpc_driver = {
540 .driver = {
541 .name = "imx-gpc",
542 .of_match_table = imx_gpc_dt_ids,
543 },
544 .probe = imx_gpc_probe,
545 .remove = imx_gpc_remove,
546 };
547 builtin_platform_driver(imx_gpc_driver)
548
