1 /*
2 * QUICC Engine GPIOs
3 *
4 * Copyright (c) MontaVista Software, Inc. 2008.
5 *
6 * Author: Anton Vorontsov <avorontsov@ru.mvista.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14 #include <linux/kernel.h>
15 #include <linux/init.h>
16 #include <linux/spinlock.h>
17 #include <linux/err.h>
18 #include <linux/io.h>
19 #include <linux/of.h>
20 #include <linux/of_gpio.h>
21 #include <linux/gpio/driver.h>
22 /* FIXME: needed for gpio_to_chip() get rid of this */
23 #include <linux/gpio.h>
24 #include <linux/slab.h>
25 #include <linux/export.h>
26 #include <soc/fsl/qe/qe.h>
27
28 struct qe_gpio_chip {
29 struct of_mm_gpio_chip mm_gc;
30 spinlock_t lock;
31
32 unsigned long pin_flags[QE_PIO_PINS];
33 #define QE_PIN_REQUESTED 0
34
35 /* shadowed data register to clear/set bits safely */
36 u32 cpdata;
37
38 /* saved_regs used to restore dedicated functions */
39 struct qe_pio_regs saved_regs;
40 };
41
qe_gpio_save_regs(struct of_mm_gpio_chip * mm_gc)42 static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
43 {
44 struct qe_gpio_chip *qe_gc =
45 container_of(mm_gc, struct qe_gpio_chip, mm_gc);
46 struct qe_pio_regs __iomem *regs = mm_gc->regs;
47
48 qe_gc->cpdata = in_be32(®s->cpdata);
49 qe_gc->saved_regs.cpdata = qe_gc->cpdata;
50 qe_gc->saved_regs.cpdir1 = in_be32(®s->cpdir1);
51 qe_gc->saved_regs.cpdir2 = in_be32(®s->cpdir2);
52 qe_gc->saved_regs.cppar1 = in_be32(®s->cppar1);
53 qe_gc->saved_regs.cppar2 = in_be32(®s->cppar2);
54 qe_gc->saved_regs.cpodr = in_be32(®s->cpodr);
55 }
56
qe_gpio_get(struct gpio_chip * gc,unsigned int gpio)57 static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
58 {
59 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
60 struct qe_pio_regs __iomem *regs = mm_gc->regs;
61 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
62
63 return !!(in_be32(®s->cpdata) & pin_mask);
64 }
65
qe_gpio_set(struct gpio_chip * gc,unsigned int gpio,int val)66 static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
67 {
68 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
69 struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
70 struct qe_pio_regs __iomem *regs = mm_gc->regs;
71 unsigned long flags;
72 u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
73
74 spin_lock_irqsave(&qe_gc->lock, flags);
75
76 if (val)
77 qe_gc->cpdata |= pin_mask;
78 else
79 qe_gc->cpdata &= ~pin_mask;
80
81 out_be32(®s->cpdata, qe_gc->cpdata);
82
83 spin_unlock_irqrestore(&qe_gc->lock, flags);
84 }
85
qe_gpio_set_multiple(struct gpio_chip * gc,unsigned long * mask,unsigned long * bits)86 static void qe_gpio_set_multiple(struct gpio_chip *gc,
87 unsigned long *mask, unsigned long *bits)
88 {
89 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
90 struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
91 struct qe_pio_regs __iomem *regs = mm_gc->regs;
92 unsigned long flags;
93 int i;
94
95 spin_lock_irqsave(&qe_gc->lock, flags);
96
97 for (i = 0; i < gc->ngpio; i++) {
98 if (*mask == 0)
99 break;
100 if (__test_and_clear_bit(i, mask)) {
101 if (test_bit(i, bits))
102 qe_gc->cpdata |= (1U << (QE_PIO_PINS - 1 - i));
103 else
104 qe_gc->cpdata &= ~(1U << (QE_PIO_PINS - 1 - i));
105 }
106 }
107
108 out_be32(®s->cpdata, qe_gc->cpdata);
109
110 spin_unlock_irqrestore(&qe_gc->lock, flags);
111 }
112
qe_gpio_dir_in(struct gpio_chip * gc,unsigned int gpio)113 static int qe_gpio_dir_in(struct gpio_chip *gc, unsigned int gpio)
114 {
115 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
116 struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
117 unsigned long flags;
118
119 spin_lock_irqsave(&qe_gc->lock, flags);
120
121 __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_IN, 0, 0, 0);
122
123 spin_unlock_irqrestore(&qe_gc->lock, flags);
124
125 return 0;
126 }
127
qe_gpio_dir_out(struct gpio_chip * gc,unsigned int gpio,int val)128 static int qe_gpio_dir_out(struct gpio_chip *gc, unsigned int gpio, int val)
129 {
130 struct of_mm_gpio_chip *mm_gc = to_of_mm_gpio_chip(gc);
131 struct qe_gpio_chip *qe_gc = gpiochip_get_data(gc);
132 unsigned long flags;
133
134 qe_gpio_set(gc, gpio, val);
135
136 spin_lock_irqsave(&qe_gc->lock, flags);
137
138 __par_io_config_pin(mm_gc->regs, gpio, QE_PIO_DIR_OUT, 0, 0, 0);
139
140 spin_unlock_irqrestore(&qe_gc->lock, flags);
141
142 return 0;
143 }
144
145 struct qe_pin {
146 /*
147 * The qe_gpio_chip name is unfortunate, we should change that to
148 * something like qe_pio_controller. Someday.
149 */
150 struct qe_gpio_chip *controller;
151 int num;
152 };
153
154 /**
155 * qe_pin_request - Request a QE pin
156 * @np: device node to get a pin from
157 * @index: index of a pin in the device tree
158 * Context: non-atomic
159 *
160 * This function return qe_pin so that you could use it with the rest of
161 * the QE Pin Multiplexing API.
162 */
qe_pin_request(struct device_node * np,int index)163 struct qe_pin *qe_pin_request(struct device_node *np, int index)
164 {
165 struct qe_pin *qe_pin;
166 struct gpio_chip *gc;
167 struct of_mm_gpio_chip *mm_gc;
168 struct qe_gpio_chip *qe_gc;
169 int err;
170 unsigned long flags;
171
172 qe_pin = kzalloc(sizeof(*qe_pin), GFP_KERNEL);
173 if (!qe_pin) {
174 pr_debug("%s: can't allocate memory\n", __func__);
175 return ERR_PTR(-ENOMEM);
176 }
177
178 err = of_get_gpio(np, index);
179 if (err < 0)
180 goto err0;
181 gc = gpio_to_chip(err);
182 if (WARN_ON(!gc))
183 goto err0;
184
185 if (!of_device_is_compatible(gc->of_node, "fsl,mpc8323-qe-pario-bank")) {
186 pr_debug("%s: tried to get a non-qe pin\n", __func__);
187 err = -EINVAL;
188 goto err0;
189 }
190
191 mm_gc = to_of_mm_gpio_chip(gc);
192 qe_gc = gpiochip_get_data(gc);
193
194 spin_lock_irqsave(&qe_gc->lock, flags);
195
196 err -= gc->base;
197 if (test_and_set_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[err]) == 0) {
198 qe_pin->controller = qe_gc;
199 qe_pin->num = err;
200 err = 0;
201 } else {
202 err = -EBUSY;
203 }
204
205 spin_unlock_irqrestore(&qe_gc->lock, flags);
206
207 if (!err)
208 return qe_pin;
209 err0:
210 kfree(qe_pin);
211 pr_debug("%s failed with status %d\n", __func__, err);
212 return ERR_PTR(err);
213 }
214 EXPORT_SYMBOL(qe_pin_request);
215
216 /**
217 * qe_pin_free - Free a pin
218 * @qe_pin: pointer to the qe_pin structure
219 * Context: any
220 *
221 * This function frees the qe_pin structure and makes a pin available
222 * for further qe_pin_request() calls.
223 */
qe_pin_free(struct qe_pin * qe_pin)224 void qe_pin_free(struct qe_pin *qe_pin)
225 {
226 struct qe_gpio_chip *qe_gc = qe_pin->controller;
227 unsigned long flags;
228 const int pin = qe_pin->num;
229
230 spin_lock_irqsave(&qe_gc->lock, flags);
231 test_and_clear_bit(QE_PIN_REQUESTED, &qe_gc->pin_flags[pin]);
232 spin_unlock_irqrestore(&qe_gc->lock, flags);
233
234 kfree(qe_pin);
235 }
236 EXPORT_SYMBOL(qe_pin_free);
237
238 /**
239 * qe_pin_set_dedicated - Revert a pin to a dedicated peripheral function mode
240 * @qe_pin: pointer to the qe_pin structure
241 * Context: any
242 *
243 * This function resets a pin to a dedicated peripheral function that
244 * has been set up by the firmware.
245 */
qe_pin_set_dedicated(struct qe_pin * qe_pin)246 void qe_pin_set_dedicated(struct qe_pin *qe_pin)
247 {
248 struct qe_gpio_chip *qe_gc = qe_pin->controller;
249 struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
250 struct qe_pio_regs *sregs = &qe_gc->saved_regs;
251 int pin = qe_pin->num;
252 u32 mask1 = 1 << (QE_PIO_PINS - (pin + 1));
253 u32 mask2 = 0x3 << (QE_PIO_PINS - (pin % (QE_PIO_PINS / 2) + 1) * 2);
254 bool second_reg = pin > (QE_PIO_PINS / 2) - 1;
255 unsigned long flags;
256
257 spin_lock_irqsave(&qe_gc->lock, flags);
258
259 if (second_reg) {
260 clrsetbits_be32(®s->cpdir2, mask2, sregs->cpdir2 & mask2);
261 clrsetbits_be32(®s->cppar2, mask2, sregs->cppar2 & mask2);
262 } else {
263 clrsetbits_be32(®s->cpdir1, mask2, sregs->cpdir1 & mask2);
264 clrsetbits_be32(®s->cppar1, mask2, sregs->cppar1 & mask2);
265 }
266
267 if (sregs->cpdata & mask1)
268 qe_gc->cpdata |= mask1;
269 else
270 qe_gc->cpdata &= ~mask1;
271
272 out_be32(®s->cpdata, qe_gc->cpdata);
273 clrsetbits_be32(®s->cpodr, mask1, sregs->cpodr & mask1);
274
275 spin_unlock_irqrestore(&qe_gc->lock, flags);
276 }
277 EXPORT_SYMBOL(qe_pin_set_dedicated);
278
279 /**
280 * qe_pin_set_gpio - Set a pin to the GPIO mode
281 * @qe_pin: pointer to the qe_pin structure
282 * Context: any
283 *
284 * This function sets a pin to the GPIO mode.
285 */
qe_pin_set_gpio(struct qe_pin * qe_pin)286 void qe_pin_set_gpio(struct qe_pin *qe_pin)
287 {
288 struct qe_gpio_chip *qe_gc = qe_pin->controller;
289 struct qe_pio_regs __iomem *regs = qe_gc->mm_gc.regs;
290 unsigned long flags;
291
292 spin_lock_irqsave(&qe_gc->lock, flags);
293
294 /* Let's make it input by default, GPIO API is able to change that. */
295 __par_io_config_pin(regs, qe_pin->num, QE_PIO_DIR_IN, 0, 0, 0);
296
297 spin_unlock_irqrestore(&qe_gc->lock, flags);
298 }
299 EXPORT_SYMBOL(qe_pin_set_gpio);
300
qe_add_gpiochips(void)301 static int __init qe_add_gpiochips(void)
302 {
303 struct device_node *np;
304
305 for_each_compatible_node(np, NULL, "fsl,mpc8323-qe-pario-bank") {
306 int ret;
307 struct qe_gpio_chip *qe_gc;
308 struct of_mm_gpio_chip *mm_gc;
309 struct gpio_chip *gc;
310
311 qe_gc = kzalloc(sizeof(*qe_gc), GFP_KERNEL);
312 if (!qe_gc) {
313 ret = -ENOMEM;
314 goto err;
315 }
316
317 spin_lock_init(&qe_gc->lock);
318
319 mm_gc = &qe_gc->mm_gc;
320 gc = &mm_gc->gc;
321
322 mm_gc->save_regs = qe_gpio_save_regs;
323 gc->ngpio = QE_PIO_PINS;
324 gc->direction_input = qe_gpio_dir_in;
325 gc->direction_output = qe_gpio_dir_out;
326 gc->get = qe_gpio_get;
327 gc->set = qe_gpio_set;
328 gc->set_multiple = qe_gpio_set_multiple;
329
330 ret = of_mm_gpiochip_add_data(np, mm_gc, qe_gc);
331 if (ret)
332 goto err;
333 continue;
334 err:
335 pr_err("%pOF: registration failed with status %d\n",
336 np, ret);
337 kfree(qe_gc);
338 /* try others anyway */
339 }
340 return 0;
341 }
342 arch_initcall(qe_add_gpiochips);
343
