1 /*
2  * drivers/scsi/ufs/unipro.h
3  *
4  * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License as published by
8  * the Free Software Foundation; either version 2 of the License, or
9  * (at your option) any later version.
10  */
11 
12 #ifndef _UNIPRO_H_
13 #define _UNIPRO_H_
14 
15 /*
16  * M-TX Configuration Attributes
17  */
18 #define TX_HIBERN8TIME_CAPABILITY		0x000F
19 #define TX_MODE					0x0021
20 #define TX_HSRATE_SERIES			0x0022
21 #define TX_HSGEAR				0x0023
22 #define TX_PWMGEAR				0x0024
23 #define TX_AMPLITUDE				0x0025
24 #define TX_HS_SLEWRATE				0x0026
25 #define TX_SYNC_SOURCE				0x0027
26 #define TX_HS_SYNC_LENGTH			0x0028
27 #define TX_HS_PREPARE_LENGTH			0x0029
28 #define TX_LS_PREPARE_LENGTH			0x002A
29 #define TX_HIBERN8_CONTROL			0x002B
30 #define TX_LCC_ENABLE				0x002C
31 #define TX_PWM_BURST_CLOSURE_EXTENSION		0x002D
32 #define TX_BYPASS_8B10B_ENABLE			0x002E
33 #define TX_DRIVER_POLARITY			0x002F
34 #define TX_HS_UNTERMINATED_LINE_DRIVE_ENABLE	0x0030
35 #define TX_LS_TERMINATED_LINE_DRIVE_ENABLE	0x0031
36 #define TX_LCC_SEQUENCER			0x0032
37 #define TX_MIN_ACTIVATETIME			0x0033
38 #define TX_PWM_G6_G7_SYNC_LENGTH		0x0034
39 #define TX_REFCLKFREQ				0x00EB
40 #define TX_CFGCLKFREQVAL			0x00EC
41 #define	CFGEXTRATTR				0x00F0
42 #define DITHERCTRL2				0x00F1
43 
44 /*
45  * M-RX Configuration Attributes
46  */
47 #define RX_MODE					0x00A1
48 #define RX_HSRATE_SERIES			0x00A2
49 #define RX_HSGEAR				0x00A3
50 #define RX_PWMGEAR				0x00A4
51 #define RX_LS_TERMINATED_ENABLE			0x00A5
52 #define RX_HS_UNTERMINATED_ENABLE		0x00A6
53 #define RX_ENTER_HIBERN8			0x00A7
54 #define RX_BYPASS_8B10B_ENABLE			0x00A8
55 #define RX_TERMINATION_FORCE_ENABLE		0x0089
56 #define RX_MIN_ACTIVATETIME_CAPABILITY		0x008F
57 #define RX_HIBERN8TIME_CAPABILITY		0x0092
58 #define RX_REFCLKFREQ				0x00EB
59 #define	RX_CFGCLKFREQVAL			0x00EC
60 #define CFGWIDEINLN				0x00F0
61 #define CFGRXCDR8				0x00BA
62 #define ENARXDIRECTCFG4				0x00F2
63 #define CFGRXOVR8				0x00BD
64 #define RXDIRECTCTRL2				0x00C7
65 #define ENARXDIRECTCFG3				0x00F3
66 #define RXCALCTRL				0x00B4
67 #define ENARXDIRECTCFG2				0x00F4
68 #define CFGRXOVR4				0x00E9
69 #define RXSQCTRL				0x00B5
70 #define CFGRXOVR6				0x00BF
71 
72 #define is_mphy_tx_attr(attr)			(attr < RX_MODE)
73 #define RX_MIN_ACTIVATETIME_UNIT_US		100
74 #define HIBERN8TIME_UNIT_US			100
75 
76 /*
77  * Common Block Attributes
78  */
79 #define TX_GLOBALHIBERNATE			UNIPRO_CB_OFFSET(0x002B)
80 #define REFCLKMODE				UNIPRO_CB_OFFSET(0x00BF)
81 #define DIRECTCTRL19				UNIPRO_CB_OFFSET(0x00CD)
82 #define DIRECTCTRL10				UNIPRO_CB_OFFSET(0x00E6)
83 #define CDIRECTCTRL6				UNIPRO_CB_OFFSET(0x00EA)
84 #define RTOBSERVESELECT				UNIPRO_CB_OFFSET(0x00F0)
85 #define CBDIVFACTOR				UNIPRO_CB_OFFSET(0x00F1)
86 #define CBDCOCTRL5				UNIPRO_CB_OFFSET(0x00F3)
87 #define CBPRGPLL2				UNIPRO_CB_OFFSET(0x00F8)
88 #define CBPRGTUNING				UNIPRO_CB_OFFSET(0x00FB)
89 
90 #define UNIPRO_CB_OFFSET(x)			(0x8000 | x)
91 
92 /*
93  * PHY Adpater attributes
94  */
95 #define PA_ACTIVETXDATALANES	0x1560
96 #define PA_ACTIVERXDATALANES	0x1580
97 #define PA_TXTRAILINGCLOCKS	0x1564
98 #define PA_PHY_TYPE		0x1500
99 #define PA_AVAILTXDATALANES	0x1520
100 #define PA_AVAILRXDATALANES	0x1540
101 #define PA_MINRXTRAILINGCLOCKS	0x1543
102 #define PA_TXPWRSTATUS		0x1567
103 #define PA_RXPWRSTATUS		0x1582
104 #define PA_TXFORCECLOCK		0x1562
105 #define PA_TXPWRMODE		0x1563
106 #define PA_LEGACYDPHYESCDL	0x1570
107 #define PA_MAXTXSPEEDFAST	0x1521
108 #define PA_MAXTXSPEEDSLOW	0x1522
109 #define PA_MAXRXSPEEDFAST	0x1541
110 #define PA_MAXRXSPEEDSLOW	0x1542
111 #define PA_TXLINKSTARTUPHS	0x1544
112 #define PA_LOCAL_TX_LCC_ENABLE	0x155E
113 #define PA_TXSPEEDFAST		0x1565
114 #define PA_TXSPEEDSLOW		0x1566
115 #define PA_REMOTEVERINFO	0x15A0
116 #define PA_TXGEAR		0x1568
117 #define PA_TXTERMINATION	0x1569
118 #define PA_HSSERIES		0x156A
119 #define PA_PWRMODE		0x1571
120 #define PA_RXGEAR		0x1583
121 #define PA_RXTERMINATION	0x1584
122 #define PA_MAXRXPWMGEAR		0x1586
123 #define PA_MAXRXHSGEAR		0x1587
124 #define PA_RXHSUNTERMCAP	0x15A5
125 #define PA_RXLSTERMCAP		0x15A6
126 #define PA_GRANULARITY		0x15AA
127 #define PA_PACPREQTIMEOUT	0x1590
128 #define PA_PACPREQEOBTIMEOUT	0x1591
129 #define PA_HIBERN8TIME		0x15A7
130 #define PA_LOCALVERINFO		0x15A9
131 #define PA_TACTIVATE		0x15A8
132 #define PA_PACPFRAMECOUNT	0x15C0
133 #define PA_PACPERRORCOUNT	0x15C1
134 #define PA_PHYTESTCONTROL	0x15C2
135 #define PA_PWRMODEUSERDATA0	0x15B0
136 #define PA_PWRMODEUSERDATA1	0x15B1
137 #define PA_PWRMODEUSERDATA2	0x15B2
138 #define PA_PWRMODEUSERDATA3	0x15B3
139 #define PA_PWRMODEUSERDATA4	0x15B4
140 #define PA_PWRMODEUSERDATA5	0x15B5
141 #define PA_PWRMODEUSERDATA6	0x15B6
142 #define PA_PWRMODEUSERDATA7	0x15B7
143 #define PA_PWRMODEUSERDATA8	0x15B8
144 #define PA_PWRMODEUSERDATA9	0x15B9
145 #define PA_PWRMODEUSERDATA10	0x15BA
146 #define PA_PWRMODEUSERDATA11	0x15BB
147 #define PA_CONNECTEDTXDATALANES	0x1561
148 #define PA_CONNECTEDRXDATALANES	0x1581
149 #define PA_LOGICALLANEMAP	0x15A1
150 #define PA_SLEEPNOCONFIGTIME	0x15A2
151 #define PA_STALLNOCONFIGTIME	0x15A3
152 #define PA_SAVECONFIGTIME	0x15A4
153 
154 #define PA_TACTIVATE_TIME_UNIT_US	10
155 #define PA_HIBERN8_TIME_UNIT_US		100
156 
157 /*Other attributes*/
158 #define VS_MPHYCFGUPDT		0xD085
159 #define VS_DEBUGOMC		0xD09E
160 #define VS_POWERSTATE		0xD083
161 
162 #define PA_GRANULARITY_MIN_VAL	1
163 #define PA_GRANULARITY_MAX_VAL	6
164 
165 /* PHY Adapter Protocol Constants */
166 #define PA_MAXDATALANES	4
167 
168 /* PA power modes */
169 enum {
170 	FAST_MODE	= 1,
171 	SLOW_MODE	= 2,
172 	FASTAUTO_MODE	= 4,
173 	SLOWAUTO_MODE	= 5,
174 	UNCHANGED	= 7,
175 };
176 
177 /* PA TX/RX Frequency Series */
178 enum {
179 	PA_HS_MODE_A	= 1,
180 	PA_HS_MODE_B	= 2,
181 };
182 
183 enum ufs_pwm_gear_tag {
184 	UFS_PWM_DONT_CHANGE,	/* Don't change Gear */
185 	UFS_PWM_G1,		/* PWM Gear 1 (default for reset) */
186 	UFS_PWM_G2,		/* PWM Gear 2 */
187 	UFS_PWM_G3,		/* PWM Gear 3 */
188 	UFS_PWM_G4,		/* PWM Gear 4 */
189 	UFS_PWM_G5,		/* PWM Gear 5 */
190 	UFS_PWM_G6,		/* PWM Gear 6 */
191 	UFS_PWM_G7,		/* PWM Gear 7 */
192 };
193 
194 enum ufs_hs_gear_tag {
195 	UFS_HS_DONT_CHANGE,	/* Don't change Gear */
196 	UFS_HS_G1,		/* HS Gear 1 (default for reset) */
197 	UFS_HS_G2,		/* HS Gear 2 */
198 	UFS_HS_G3,		/* HS Gear 3 */
199 };
200 
201 enum ufs_unipro_ver {
202 	UFS_UNIPRO_VER_RESERVED = 0,
203 	UFS_UNIPRO_VER_1_40 = 1, /* UniPro version 1.40 */
204 	UFS_UNIPRO_VER_1_41 = 2, /* UniPro version 1.41 */
205 	UFS_UNIPRO_VER_1_6 = 3,  /* UniPro version 1.6 */
206 	UFS_UNIPRO_VER_MAX = 4,  /* UniPro unsupported version */
207 	/* UniPro version field mask in PA_LOCALVERINFO */
208 	UFS_UNIPRO_VER_MASK = 0xF,
209 };
210 
211 /*
212  * Data Link Layer Attributes
213  */
214 #define DL_TC0TXFCTHRESHOLD	0x2040
215 #define DL_FC0PROTTIMEOUTVAL	0x2041
216 #define DL_TC0REPLAYTIMEOUTVAL	0x2042
217 #define DL_AFC0REQTIMEOUTVAL	0x2043
218 #define DL_AFC0CREDITTHRESHOLD	0x2044
219 #define DL_TC0OUTACKTHRESHOLD	0x2045
220 #define DL_TC1TXFCTHRESHOLD	0x2060
221 #define DL_FC1PROTTIMEOUTVAL	0x2061
222 #define DL_TC1REPLAYTIMEOUTVAL	0x2062
223 #define DL_AFC1REQTIMEOUTVAL	0x2063
224 #define DL_AFC1CREDITTHRESHOLD	0x2064
225 #define DL_TC1OUTACKTHRESHOLD	0x2065
226 #define DL_TXPREEMPTIONCAP	0x2000
227 #define DL_TC0TXMAXSDUSIZE	0x2001
228 #define DL_TC0RXINITCREDITVAL	0x2002
229 #define DL_TC0TXBUFFERSIZE	0x2005
230 #define DL_PEERTC0PRESENT	0x2046
231 #define DL_PEERTC0RXINITCREVAL	0x2047
232 #define DL_TC1TXMAXSDUSIZE	0x2003
233 #define DL_TC1RXINITCREDITVAL	0x2004
234 #define DL_TC1TXBUFFERSIZE	0x2006
235 #define DL_PEERTC1PRESENT	0x2066
236 #define DL_PEERTC1RXINITCREVAL	0x2067
237 
238 /*
239  * Network Layer Attributes
240  */
241 #define N_DEVICEID		0x3000
242 #define N_DEVICEID_VALID	0x3001
243 #define N_TC0TXMAXSDUSIZE	0x3020
244 #define N_TC1TXMAXSDUSIZE	0x3021
245 
246 /*
247  * Transport Layer Attributes
248  */
249 #define T_NUMCPORTS		0x4000
250 #define T_NUMTESTFEATURES	0x4001
251 #define T_CONNECTIONSTATE	0x4020
252 #define T_PEERDEVICEID		0x4021
253 #define T_PEERCPORTID		0x4022
254 #define T_TRAFFICCLASS		0x4023
255 #define T_PROTOCOLID		0x4024
256 #define T_CPORTFLAGS		0x4025
257 #define T_TXTOKENVALUE		0x4026
258 #define T_RXTOKENVALUE		0x4027
259 #define T_LOCALBUFFERSPACE	0x4028
260 #define T_PEERBUFFERSPACE	0x4029
261 #define T_CREDITSTOSEND		0x402A
262 #define T_CPORTMODE		0x402B
263 #define T_TC0TXMAXSDUSIZE	0x4060
264 #define T_TC1TXMAXSDUSIZE	0x4061
265 
266 #ifdef FALSE
267 #undef FALSE
268 #endif
269 
270 #ifdef TRUE
271 #undef TRUE
272 #endif
273 
274 /* Boolean attribute values */
275 enum {
276 	FALSE = 0,
277 	TRUE,
278 };
279 
280 #endif /* _UNIPRO_H_ */
281