1 /* 2 * Copyright (c) 2017, HiSilicon. All rights reserved. 3 * 4 * Released under the GPLv2 only. 5 * SPDX-License-Identifier: GPL-2.0 6 */ 7 8 #ifndef UFS_HISI_H_ 9 #define UFS_HISI_H_ 10 11 #define HBRN8_POLL_TOUT_MS 1000 12 13 /* 14 * ufs sysctrl specific define 15 */ 16 #define PSW_POWER_CTRL (0x04) 17 #define PHY_ISO_EN (0x08) 18 #define HC_LP_CTRL (0x0C) 19 #define PHY_CLK_CTRL (0x10) 20 #define PSW_CLK_CTRL (0x14) 21 #define CLOCK_GATE_BYPASS (0x18) 22 #define RESET_CTRL_EN (0x1C) 23 #define UFS_SYSCTRL (0x5C) 24 #define UFS_DEVICE_RESET_CTRL (0x60) 25 26 #define BIT_UFS_PSW_ISO_CTRL (1 << 16) 27 #define BIT_UFS_PSW_MTCMOS_EN (1 << 0) 28 #define BIT_UFS_REFCLK_ISO_EN (1 << 16) 29 #define BIT_UFS_PHY_ISO_CTRL (1 << 0) 30 #define BIT_SYSCTRL_LP_ISOL_EN (1 << 16) 31 #define BIT_SYSCTRL_PWR_READY (1 << 8) 32 #define BIT_SYSCTRL_REF_CLOCK_EN (1 << 24) 33 #define MASK_SYSCTRL_REF_CLOCK_SEL (0x3 << 8) 34 #define MASK_SYSCTRL_CFG_CLOCK_FREQ (0xFF) 35 #define UFS_FREQ_CFG_CLK (0x39) 36 #define BIT_SYSCTRL_PSW_CLK_EN (1 << 4) 37 #define MASK_UFS_CLK_GATE_BYPASS (0x3F) 38 #define BIT_SYSCTRL_LP_RESET_N (1 << 0) 39 #define BIT_UFS_REFCLK_SRC_SEl (1 << 0) 40 #define MASK_UFS_SYSCRTL_BYPASS (0x3F << 16) 41 #define MASK_UFS_DEVICE_RESET (0x1 << 16) 42 #define BIT_UFS_DEVICE_RESET (0x1) 43 44 /* 45 * M-TX Configuration Attributes for Hixxxx 46 */ 47 #define MPHY_TX_FSM_STATE 0x41 48 #define TX_FSM_HIBERN8 0x1 49 50 /* 51 * Hixxxx UFS HC specific Registers 52 */ 53 enum { 54 UFS_REG_OCPTHRTL = 0xc0, 55 UFS_REG_OOCPR = 0xc4, 56 57 UFS_REG_CDACFG = 0xd0, 58 UFS_REG_CDATX1 = 0xd4, 59 UFS_REG_CDATX2 = 0xd8, 60 UFS_REG_CDARX1 = 0xdc, 61 UFS_REG_CDARX2 = 0xe0, 62 UFS_REG_CDASTA = 0xe4, 63 64 UFS_REG_LBMCFG = 0xf0, 65 UFS_REG_LBMSTA = 0xf4, 66 UFS_REG_UFSMODE = 0xf8, 67 68 UFS_REG_HCLKDIV = 0xfc, 69 }; 70 71 /* AHIT - Auto-Hibernate Idle Timer */ 72 #define UFS_AHIT_AH8ITV_MASK 0x3FF 73 74 /* REG UFS_REG_OCPTHRTL definition */ 75 #define UFS_HCLKDIV_NORMAL_VALUE 0xE4 76 77 /* vendor specific pre-defined parameters */ 78 #define SLOW 1 79 #define FAST 2 80 81 #define UFS_HISI_LIMIT_NUM_LANES_RX 2 82 #define UFS_HISI_LIMIT_NUM_LANES_TX 2 83 #define UFS_HISI_LIMIT_HSGEAR_RX UFS_HS_G3 84 #define UFS_HISI_LIMIT_HSGEAR_TX UFS_HS_G3 85 #define UFS_HISI_LIMIT_PWMGEAR_RX UFS_PWM_G4 86 #define UFS_HISI_LIMIT_PWMGEAR_TX UFS_PWM_G4 87 #define UFS_HISI_LIMIT_RX_PWR_PWM SLOW_MODE 88 #define UFS_HISI_LIMIT_TX_PWR_PWM SLOW_MODE 89 #define UFS_HISI_LIMIT_RX_PWR_HS FAST_MODE 90 #define UFS_HISI_LIMIT_TX_PWR_HS FAST_MODE 91 #define UFS_HISI_LIMIT_HS_RATE PA_HS_MODE_B 92 #define UFS_HISI_LIMIT_DESIRED_MODE FAST 93 94 struct ufs_hisi_host { 95 struct ufs_hba *hba; 96 void __iomem *ufs_sys_ctrl; 97 98 struct reset_control *rst; 99 100 uint64_t caps; 101 102 bool in_suspend; 103 }; 104 105 #define ufs_sys_ctrl_writel(host, val, reg) \ 106 writel((val), (host)->ufs_sys_ctrl + (reg)) 107 #define ufs_sys_ctrl_readl(host, reg) readl((host)->ufs_sys_ctrl + (reg)) 108 #define ufs_sys_ctrl_set_bits(host, mask, reg) \ 109 ufs_sys_ctrl_writel( \ 110 (host), ((mask) | (ufs_sys_ctrl_readl((host), (reg)))), (reg)) 111 #define ufs_sys_ctrl_clr_bits(host, mask, reg) \ 112 ufs_sys_ctrl_writel((host), \ 113 ((~(mask)) & (ufs_sys_ctrl_readl((host), (reg)))), \ 114 (reg)) 115 #endif /* UFS_HISI_H_ */ 116
