1 /* 2 * Marvell 88SE64xx hardware specific head file 3 * 4 * Copyright 2007 Red Hat, Inc. 5 * Copyright 2008 Marvell. <kewei@marvell.com> 6 * Copyright 2009-2011 Marvell. <yuxiangl@marvell.com> 7 * 8 * This file is licensed under GPLv2. 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; version 2 of the 13 * License. 14 * 15 * This program is distributed in the hope that it will be useful, 16 * but WITHOUT ANY WARRANTY; without even the implied warranty of 17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 18 * General Public License for more details. 19 * 20 * You should have received a copy of the GNU General Public License 21 * along with this program; if not, write to the Free Software 22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 23 * USA 24 */ 25 26 #ifndef _MVS64XX_REG_H_ 27 #define _MVS64XX_REG_H_ 28 29 #include <linux/types.h> 30 31 #define MAX_LINK_RATE SAS_LINK_RATE_3_0_GBPS 32 33 /* enhanced mode registers (BAR4) */ 34 enum hw_registers { 35 MVS_GBL_CTL = 0x04, /* global control */ 36 MVS_GBL_INT_STAT = 0x08, /* global irq status */ 37 MVS_GBL_PI = 0x0C, /* ports implemented bitmask */ 38 39 MVS_PHY_CTL = 0x40, /* SOC PHY Control */ 40 MVS_PORTS_IMP = 0x9C, /* SOC Port Implemented */ 41 42 MVS_GBL_PORT_TYPE = 0xa0, /* port type */ 43 44 MVS_CTL = 0x100, /* SAS/SATA port configuration */ 45 MVS_PCS = 0x104, /* SAS/SATA port control/status */ 46 MVS_CMD_LIST_LO = 0x108, /* cmd list addr */ 47 MVS_CMD_LIST_HI = 0x10C, 48 MVS_RX_FIS_LO = 0x110, /* RX FIS list addr */ 49 MVS_RX_FIS_HI = 0x114, 50 51 MVS_TX_CFG = 0x120, /* TX configuration */ 52 MVS_TX_LO = 0x124, /* TX (delivery) ring addr */ 53 MVS_TX_HI = 0x128, 54 55 MVS_TX_PROD_IDX = 0x12C, /* TX producer pointer */ 56 MVS_TX_CONS_IDX = 0x130, /* TX consumer pointer (RO) */ 57 MVS_RX_CFG = 0x134, /* RX configuration */ 58 MVS_RX_LO = 0x138, /* RX (completion) ring addr */ 59 MVS_RX_HI = 0x13C, 60 MVS_RX_CONS_IDX = 0x140, /* RX consumer pointer (RO) */ 61 62 MVS_INT_COAL = 0x148, /* Int coalescing config */ 63 MVS_INT_COAL_TMOUT = 0x14C, /* Int coalescing timeout */ 64 MVS_INT_STAT = 0x150, /* Central int status */ 65 MVS_INT_MASK = 0x154, /* Central int enable */ 66 MVS_INT_STAT_SRS_0 = 0x158, /* SATA register set status */ 67 MVS_INT_MASK_SRS_0 = 0x15C, 68 69 /* ports 1-3 follow after this */ 70 MVS_P0_INT_STAT = 0x160, /* port0 interrupt status */ 71 MVS_P0_INT_MASK = 0x164, /* port0 interrupt mask */ 72 /* ports 5-7 follow after this */ 73 MVS_P4_INT_STAT = 0x200, /* Port4 interrupt status */ 74 MVS_P4_INT_MASK = 0x204, /* Port4 interrupt enable mask */ 75 76 /* ports 1-3 follow after this */ 77 MVS_P0_SER_CTLSTAT = 0x180, /* port0 serial control/status */ 78 /* ports 5-7 follow after this */ 79 MVS_P4_SER_CTLSTAT = 0x220, /* port4 serial control/status */ 80 81 MVS_CMD_ADDR = 0x1B8, /* Command register port (addr) */ 82 MVS_CMD_DATA = 0x1BC, /* Command register port (data) */ 83 84 /* ports 1-3 follow after this */ 85 MVS_P0_CFG_ADDR = 0x1C0, /* port0 phy register address */ 86 MVS_P0_CFG_DATA = 0x1C4, /* port0 phy register data */ 87 /* ports 5-7 follow after this */ 88 MVS_P4_CFG_ADDR = 0x230, /* Port4 config address */ 89 MVS_P4_CFG_DATA = 0x234, /* Port4 config data */ 90 91 /* ports 1-3 follow after this */ 92 MVS_P0_VSR_ADDR = 0x1E0, /* port0 VSR address */ 93 MVS_P0_VSR_DATA = 0x1E4, /* port0 VSR data */ 94 /* ports 5-7 follow after this */ 95 MVS_P4_VSR_ADDR = 0x250, /* port4 VSR addr */ 96 MVS_P4_VSR_DATA = 0x254, /* port4 VSR data */ 97 }; 98 99 enum pci_cfg_registers { 100 PCR_PHY_CTL = 0x40, 101 PCR_PHY_CTL2 = 0x90, 102 PCR_DEV_CTRL = 0xE8, 103 PCR_LINK_STAT = 0xF2, 104 }; 105 106 /* SAS/SATA Vendor Specific Port Registers */ 107 enum sas_sata_vsp_regs { 108 VSR_PHY_STAT = 0x00, /* Phy Status */ 109 VSR_PHY_MODE1 = 0x01, /* phy tx */ 110 VSR_PHY_MODE2 = 0x02, /* tx scc */ 111 VSR_PHY_MODE3 = 0x03, /* pll */ 112 VSR_PHY_MODE4 = 0x04, /* VCO */ 113 VSR_PHY_MODE5 = 0x05, /* Rx */ 114 VSR_PHY_MODE6 = 0x06, /* CDR */ 115 VSR_PHY_MODE7 = 0x07, /* Impedance */ 116 VSR_PHY_MODE8 = 0x08, /* Voltage */ 117 VSR_PHY_MODE9 = 0x09, /* Test */ 118 VSR_PHY_MODE10 = 0x0A, /* Power */ 119 VSR_PHY_MODE11 = 0x0B, /* Phy Mode */ 120 VSR_PHY_VS0 = 0x0C, /* Vednor Specific 0 */ 121 VSR_PHY_VS1 = 0x0D, /* Vednor Specific 1 */ 122 }; 123 124 enum chip_register_bits { 125 PHY_MIN_SPP_PHYS_LINK_RATE_MASK = (0xF << 8), 126 PHY_MAX_SPP_PHYS_LINK_RATE_MASK = (0xF << 12), 127 PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET = (16), 128 PHY_NEG_SPP_PHYS_LINK_RATE_MASK = 129 (0xF << PHY_NEG_SPP_PHYS_LINK_RATE_MASK_OFFSET), 130 }; 131 132 #define MAX_SG_ENTRY 64 133 134 struct mvs_prd { 135 __le64 addr; /* 64-bit buffer address */ 136 __le32 reserved; 137 __le32 len; /* 16-bit length */ 138 }; 139 140 #define SPI_CTRL_REG 0xc0 141 #define SPI_CTRL_VENDOR_ENABLE (1U<<29) 142 #define SPI_CTRL_SPIRDY (1U<<22) 143 #define SPI_CTRL_SPISTART (1U<<20) 144 145 #define SPI_CMD_REG 0xc4 146 #define SPI_DATA_REG 0xc8 147 148 #define SPI_CTRL_REG_64XX 0x10 149 #define SPI_CMD_REG_64XX 0x14 150 #define SPI_DATA_REG_64XX 0x18 151 152 #endif 153
