1 /*
2 * R8A7740 processor support
3 *
4 * Copyright (C) 2011 Renesas Solutions Corp.
5 * Copyright (C) 2011 Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; version 2 of the
10 * License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
20 */
21 #include <linux/io.h>
22 #include <linux/kernel.h>
23 #include <linux/pinctrl/pinconf-generic.h>
24
25 #include "sh_pfc.h"
26
27 #define CPU_ALL_PORT(fn, pfx, sfx) \
28 PORT_10(0, fn, pfx, sfx), PORT_90(0, fn, pfx, sfx), \
29 PORT_10(100, fn, pfx##10, sfx), PORT_90(100, fn, pfx##1, sfx), \
30 PORT_10(200, fn, pfx##20, sfx), \
31 PORT_1(210, fn, pfx##210, sfx), PORT_1(211, fn, pfx##211, sfx)
32
33 #define IRQC_PIN_MUX(irq, pin) \
34 static const unsigned int intc_irq##irq##_pins[] = { \
35 pin, \
36 }; \
37 static const unsigned int intc_irq##irq##_mux[] = { \
38 IRQ##irq##_MARK, \
39 }
40
41 #define IRQC_PINS_MUX(irq, idx, pin) \
42 static const unsigned int intc_irq##irq##_##idx##_pins[] = { \
43 pin, \
44 }; \
45 static const unsigned int intc_irq##irq##_##idx##_mux[] = { \
46 IRQ##irq##_PORT##pin##_MARK, \
47 }
48
49 enum {
50 PINMUX_RESERVED = 0,
51
52 /* PORT0_DATA -> PORT211_DATA */
53 PINMUX_DATA_BEGIN,
54 PORT_ALL(DATA),
55 PINMUX_DATA_END,
56
57 /* PORT0_IN -> PORT211_IN */
58 PINMUX_INPUT_BEGIN,
59 PORT_ALL(IN),
60 PINMUX_INPUT_END,
61
62 /* PORT0_OUT -> PORT211_OUT */
63 PINMUX_OUTPUT_BEGIN,
64 PORT_ALL(OUT),
65 PINMUX_OUTPUT_END,
66
67 PINMUX_FUNCTION_BEGIN,
68 PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT211_FN_IN */
69 PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT211_FN_OUT */
70 PORT_ALL(FN0), /* PORT0_FN0 -> PORT211_FN0 */
71 PORT_ALL(FN1), /* PORT0_FN1 -> PORT211_FN1 */
72 PORT_ALL(FN2), /* PORT0_FN2 -> PORT211_FN2 */
73 PORT_ALL(FN3), /* PORT0_FN3 -> PORT211_FN3 */
74 PORT_ALL(FN4), /* PORT0_FN4 -> PORT211_FN4 */
75 PORT_ALL(FN5), /* PORT0_FN5 -> PORT211_FN5 */
76 PORT_ALL(FN6), /* PORT0_FN6 -> PORT211_FN6 */
77 PORT_ALL(FN7), /* PORT0_FN7 -> PORT211_FN7 */
78
79 MSEL1CR_31_0, MSEL1CR_31_1,
80 MSEL1CR_30_0, MSEL1CR_30_1,
81 MSEL1CR_29_0, MSEL1CR_29_1,
82 MSEL1CR_28_0, MSEL1CR_28_1,
83 MSEL1CR_27_0, MSEL1CR_27_1,
84 MSEL1CR_26_0, MSEL1CR_26_1,
85 MSEL1CR_16_0, MSEL1CR_16_1,
86 MSEL1CR_15_0, MSEL1CR_15_1,
87 MSEL1CR_14_0, MSEL1CR_14_1,
88 MSEL1CR_13_0, MSEL1CR_13_1,
89 MSEL1CR_12_0, MSEL1CR_12_1,
90 MSEL1CR_9_0, MSEL1CR_9_1,
91 MSEL1CR_7_0, MSEL1CR_7_1,
92 MSEL1CR_6_0, MSEL1CR_6_1,
93 MSEL1CR_5_0, MSEL1CR_5_1,
94 MSEL1CR_4_0, MSEL1CR_4_1,
95 MSEL1CR_3_0, MSEL1CR_3_1,
96 MSEL1CR_2_0, MSEL1CR_2_1,
97 MSEL1CR_0_0, MSEL1CR_0_1,
98
99 MSEL3CR_15_0, MSEL3CR_15_1, /* Trace / Debug ? */
100 MSEL3CR_6_0, MSEL3CR_6_1,
101
102 MSEL4CR_19_0, MSEL4CR_19_1,
103 MSEL4CR_18_0, MSEL4CR_18_1,
104 MSEL4CR_15_0, MSEL4CR_15_1,
105 MSEL4CR_10_0, MSEL4CR_10_1,
106 MSEL4CR_6_0, MSEL4CR_6_1,
107 MSEL4CR_4_0, MSEL4CR_4_1,
108 MSEL4CR_1_0, MSEL4CR_1_1,
109
110 MSEL5CR_31_0, MSEL5CR_31_1, /* irq/fiq output */
111 MSEL5CR_30_0, MSEL5CR_30_1,
112 MSEL5CR_29_0, MSEL5CR_29_1,
113 MSEL5CR_27_0, MSEL5CR_27_1,
114 MSEL5CR_25_0, MSEL5CR_25_1,
115 MSEL5CR_23_0, MSEL5CR_23_1,
116 MSEL5CR_21_0, MSEL5CR_21_1,
117 MSEL5CR_19_0, MSEL5CR_19_1,
118 MSEL5CR_17_0, MSEL5CR_17_1,
119 MSEL5CR_15_0, MSEL5CR_15_1,
120 MSEL5CR_14_0, MSEL5CR_14_1,
121 MSEL5CR_13_0, MSEL5CR_13_1,
122 MSEL5CR_12_0, MSEL5CR_12_1,
123 MSEL5CR_11_0, MSEL5CR_11_1,
124 MSEL5CR_10_0, MSEL5CR_10_1,
125 MSEL5CR_8_0, MSEL5CR_8_1,
126 MSEL5CR_7_0, MSEL5CR_7_1,
127 MSEL5CR_6_0, MSEL5CR_6_1,
128 MSEL5CR_5_0, MSEL5CR_5_1,
129 MSEL5CR_4_0, MSEL5CR_4_1,
130 MSEL5CR_3_0, MSEL5CR_3_1,
131 MSEL5CR_2_0, MSEL5CR_2_1,
132 MSEL5CR_0_0, MSEL5CR_0_1,
133 PINMUX_FUNCTION_END,
134
135 PINMUX_MARK_BEGIN,
136
137 /* IRQ */
138 IRQ0_PORT2_MARK, IRQ0_PORT13_MARK,
139 IRQ1_MARK,
140 IRQ2_PORT11_MARK, IRQ2_PORT12_MARK,
141 IRQ3_PORT10_MARK, IRQ3_PORT14_MARK,
142 IRQ4_PORT15_MARK, IRQ4_PORT172_MARK,
143 IRQ5_PORT0_MARK, IRQ5_PORT1_MARK,
144 IRQ6_PORT121_MARK, IRQ6_PORT173_MARK,
145 IRQ7_PORT120_MARK, IRQ7_PORT209_MARK,
146 IRQ8_MARK,
147 IRQ9_PORT118_MARK, IRQ9_PORT210_MARK,
148 IRQ10_MARK,
149 IRQ11_MARK,
150 IRQ12_PORT42_MARK, IRQ12_PORT97_MARK,
151 IRQ13_PORT64_MARK, IRQ13_PORT98_MARK,
152 IRQ14_PORT63_MARK, IRQ14_PORT99_MARK,
153 IRQ15_PORT62_MARK, IRQ15_PORT100_MARK,
154 IRQ16_PORT68_MARK, IRQ16_PORT211_MARK,
155 IRQ17_MARK,
156 IRQ18_MARK,
157 IRQ19_MARK,
158 IRQ20_MARK,
159 IRQ21_MARK,
160 IRQ22_MARK,
161 IRQ23_MARK,
162 IRQ24_MARK,
163 IRQ25_MARK,
164 IRQ26_PORT58_MARK, IRQ26_PORT81_MARK,
165 IRQ27_PORT57_MARK, IRQ27_PORT168_MARK,
166 IRQ28_PORT56_MARK, IRQ28_PORT169_MARK,
167 IRQ29_PORT50_MARK, IRQ29_PORT170_MARK,
168 IRQ30_PORT49_MARK, IRQ30_PORT171_MARK,
169 IRQ31_PORT41_MARK, IRQ31_PORT167_MARK,
170
171 /* Function */
172
173 /* DBGT */
174 DBGMDT2_MARK, DBGMDT1_MARK, DBGMDT0_MARK,
175 DBGMD10_MARK, DBGMD11_MARK, DBGMD20_MARK,
176 DBGMD21_MARK,
177
178 /* FSI-A */
179 FSIAISLD_PORT0_MARK, /* FSIAISLD Port 0/5 */
180 FSIAISLD_PORT5_MARK,
181 FSIASPDIF_PORT9_MARK, /* FSIASPDIF Port 9/18 */
182 FSIASPDIF_PORT18_MARK,
183 FSIAOSLD1_MARK, FSIAOSLD2_MARK, FSIAOLR_MARK,
184 FSIAOBT_MARK, FSIAOSLD_MARK, FSIAOMC_MARK,
185 FSIACK_MARK, FSIAILR_MARK, FSIAIBT_MARK,
186
187 /* FSI-B */
188 FSIBCK_MARK,
189
190 /* FMSI */
191 FMSISLD_PORT1_MARK, /* FMSISLD Port 1/6 */
192 FMSISLD_PORT6_MARK,
193 FMSIILR_MARK, FMSIIBT_MARK, FMSIOLR_MARK, FMSIOBT_MARK,
194 FMSICK_MARK, FMSOILR_MARK, FMSOIBT_MARK, FMSOOLR_MARK,
195 FMSOOBT_MARK, FMSOSLD_MARK, FMSOCK_MARK,
196
197 /* SCIFA0 */
198 SCIFA0_SCK_MARK, SCIFA0_CTS_MARK, SCIFA0_RTS_MARK,
199 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
200
201 /* SCIFA1 */
202 SCIFA1_CTS_MARK, SCIFA1_SCK_MARK, SCIFA1_RXD_MARK,
203 SCIFA1_TXD_MARK, SCIFA1_RTS_MARK,
204
205 /* SCIFA2 */
206 SCIFA2_SCK_PORT22_MARK, /* SCIFA2_SCK Port 22/199 */
207 SCIFA2_SCK_PORT199_MARK,
208 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
209 SCIFA2_CTS_MARK, SCIFA2_RTS_MARK,
210
211 /* SCIFA3 */
212 SCIFA3_RTS_PORT105_MARK, /* MSEL5CR_8_0 */
213 SCIFA3_SCK_PORT116_MARK,
214 SCIFA3_CTS_PORT117_MARK,
215 SCIFA3_RXD_PORT174_MARK,
216 SCIFA3_TXD_PORT175_MARK,
217
218 SCIFA3_RTS_PORT161_MARK, /* MSEL5CR_8_1 */
219 SCIFA3_SCK_PORT158_MARK,
220 SCIFA3_CTS_PORT162_MARK,
221 SCIFA3_RXD_PORT159_MARK,
222 SCIFA3_TXD_PORT160_MARK,
223
224 /* SCIFA4 */
225 SCIFA4_RXD_PORT12_MARK, /* MSEL5CR[12:11] = 00 */
226 SCIFA4_TXD_PORT13_MARK,
227
228 SCIFA4_RXD_PORT204_MARK, /* MSEL5CR[12:11] = 01 */
229 SCIFA4_TXD_PORT203_MARK,
230
231 SCIFA4_RXD_PORT94_MARK, /* MSEL5CR[12:11] = 10 */
232 SCIFA4_TXD_PORT93_MARK,
233
234 SCIFA4_SCK_PORT21_MARK, /* SCIFA4_SCK Port 21/205 */
235 SCIFA4_SCK_PORT205_MARK,
236
237 /* SCIFA5 */
238 SCIFA5_TXD_PORT20_MARK, /* MSEL5CR[15:14] = 00 */
239 SCIFA5_RXD_PORT10_MARK,
240
241 SCIFA5_RXD_PORT207_MARK, /* MSEL5CR[15:14] = 01 */
242 SCIFA5_TXD_PORT208_MARK,
243
244 SCIFA5_TXD_PORT91_MARK, /* MSEL5CR[15:14] = 10 */
245 SCIFA5_RXD_PORT92_MARK,
246
247 SCIFA5_SCK_PORT23_MARK, /* SCIFA5_SCK Port 23/206 */
248 SCIFA5_SCK_PORT206_MARK,
249
250 /* SCIFA6 */
251 SCIFA6_SCK_MARK, SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
252
253 /* SCIFA7 */
254 SCIFA7_TXD_MARK, SCIFA7_RXD_MARK,
255
256 /* SCIFB */
257 SCIFB_SCK_PORT190_MARK, /* MSEL5CR_17_0 */
258 SCIFB_RXD_PORT191_MARK,
259 SCIFB_TXD_PORT192_MARK,
260 SCIFB_RTS_PORT186_MARK,
261 SCIFB_CTS_PORT187_MARK,
262
263 SCIFB_SCK_PORT2_MARK, /* MSEL5CR_17_1 */
264 SCIFB_RXD_PORT3_MARK,
265 SCIFB_TXD_PORT4_MARK,
266 SCIFB_RTS_PORT172_MARK,
267 SCIFB_CTS_PORT173_MARK,
268
269 /* LCD0 */
270 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
271 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
272 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
273 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
274 LCD0_D16_MARK, LCD0_D17_MARK,
275 LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
276 LCD0_DCK_MARK, LCD0_VSYN_MARK, /* for RGB */
277 LCD0_HSYN_MARK, LCD0_DISP_MARK, /* for RGB */
278 LCD0_WR_MARK, LCD0_RD_MARK, /* for SYS */
279 LCD0_CS_MARK, LCD0_RS_MARK, /* for SYS */
280
281 LCD0_D21_PORT158_MARK, LCD0_D23_PORT159_MARK, /* MSEL5CR_6_1 */
282 LCD0_D22_PORT160_MARK, LCD0_D20_PORT161_MARK,
283 LCD0_D19_PORT162_MARK, LCD0_D18_PORT163_MARK,
284 LCD0_LCLK_PORT165_MARK,
285
286 LCD0_D18_PORT40_MARK, LCD0_D22_PORT0_MARK, /* MSEL5CR_6_0 */
287 LCD0_D23_PORT1_MARK, LCD0_D21_PORT2_MARK,
288 LCD0_D20_PORT3_MARK, LCD0_D19_PORT4_MARK,
289 LCD0_LCLK_PORT102_MARK,
290
291 /* LCD1 */
292 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
293 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
294 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
295 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
296 LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
297 LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
298 LCD1_DON_MARK, LCD1_VCPWC_MARK,
299 LCD1_LCLK_MARK, LCD1_VEPWC_MARK,
300
301 LCD1_DCK_MARK, LCD1_VSYN_MARK, /* for RGB */
302 LCD1_HSYN_MARK, LCD1_DISP_MARK, /* for RGB */
303 LCD1_RS_MARK, LCD1_CS_MARK, /* for SYS */
304 LCD1_RD_MARK, LCD1_WR_MARK, /* for SYS */
305
306 /* RSPI */
307 RSPI_SSL0_A_MARK, RSPI_SSL1_A_MARK, RSPI_SSL2_A_MARK,
308 RSPI_SSL3_A_MARK, RSPI_CK_A_MARK, RSPI_MOSI_A_MARK,
309 RSPI_MISO_A_MARK,
310
311 /* VIO CKO */
312 VIO_CKO1_MARK, /* needs fixup */
313 VIO_CKO2_MARK,
314 VIO_CKO_1_MARK,
315 VIO_CKO_MARK,
316
317 /* VIO0 */
318 VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
319 VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
320 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
321 VIO0_D12_MARK, VIO0_VD_MARK, VIO0_HD_MARK, VIO0_CLK_MARK,
322 VIO0_FIELD_MARK,
323
324 VIO0_D13_PORT26_MARK, /* MSEL5CR_27_0 */
325 VIO0_D14_PORT25_MARK,
326 VIO0_D15_PORT24_MARK,
327
328 VIO0_D13_PORT22_MARK, /* MSEL5CR_27_1 */
329 VIO0_D14_PORT95_MARK,
330 VIO0_D15_PORT96_MARK,
331
332 /* VIO1 */
333 VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
334 VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
335 VIO1_VD_MARK, VIO1_HD_MARK, VIO1_CLK_MARK, VIO1_FIELD_MARK,
336
337 /* TPU0 */
338 TPU0TO0_MARK, TPU0TO1_MARK, TPU0TO3_MARK,
339 TPU0TO2_PORT66_MARK, /* TPU0TO2 Port 66/202 */
340 TPU0TO2_PORT202_MARK,
341
342 /* SSP1 0 */
343 STP0_IPD0_MARK, STP0_IPD1_MARK, STP0_IPD2_MARK, STP0_IPD3_MARK,
344 STP0_IPD4_MARK, STP0_IPD5_MARK, STP0_IPD6_MARK, STP0_IPD7_MARK,
345 STP0_IPEN_MARK, STP0_IPCLK_MARK, STP0_IPSYNC_MARK,
346
347 /* SSP1 1 */
348 STP1_IPD1_MARK, STP1_IPD2_MARK, STP1_IPD3_MARK, STP1_IPD4_MARK,
349 STP1_IPD5_MARK, STP1_IPD6_MARK, STP1_IPD7_MARK, STP1_IPCLK_MARK,
350 STP1_IPSYNC_MARK,
351
352 STP1_IPD0_PORT186_MARK, /* MSEL5CR_23_0 */
353 STP1_IPEN_PORT187_MARK,
354
355 STP1_IPD0_PORT194_MARK, /* MSEL5CR_23_1 */
356 STP1_IPEN_PORT193_MARK,
357
358 /* SIM */
359 SIM_RST_MARK, SIM_CLK_MARK,
360 SIM_D_PORT22_MARK, /* SIM_D Port 22/199 */
361 SIM_D_PORT199_MARK,
362
363 /* SDHI0 */
364 SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
365 SDHI0_CD_MARK, SDHI0_WP_MARK, SDHI0_CMD_MARK, SDHI0_CLK_MARK,
366
367 /* SDHI1 */
368 SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
369 SDHI1_CD_MARK, SDHI1_WP_MARK, SDHI1_CMD_MARK, SDHI1_CLK_MARK,
370
371 /* SDHI2 */
372 SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
373 SDHI2_CLK_MARK, SDHI2_CMD_MARK,
374
375 SDHI2_CD_PORT24_MARK, /* MSEL5CR_19_0 */
376 SDHI2_WP_PORT25_MARK,
377
378 SDHI2_WP_PORT177_MARK, /* MSEL5CR_19_1 */
379 SDHI2_CD_PORT202_MARK,
380
381 /* MSIOF2 */
382 MSIOF2_TXD_MARK, MSIOF2_RXD_MARK, MSIOF2_TSCK_MARK,
383 MSIOF2_SS2_MARK, MSIOF2_TSYNC_MARK, MSIOF2_SS1_MARK,
384 MSIOF2_MCK1_MARK, MSIOF2_MCK0_MARK, MSIOF2_RSYNC_MARK,
385 MSIOF2_RSCK_MARK,
386
387 /* KEYSC */
388 KEYIN4_MARK, KEYIN5_MARK, KEYIN6_MARK, KEYIN7_MARK,
389 KEYOUT0_MARK, KEYOUT1_MARK, KEYOUT2_MARK, KEYOUT3_MARK,
390 KEYOUT4_MARK, KEYOUT5_MARK, KEYOUT6_MARK, KEYOUT7_MARK,
391
392 KEYIN0_PORT43_MARK, /* MSEL4CR_18_0 */
393 KEYIN1_PORT44_MARK,
394 KEYIN2_PORT45_MARK,
395 KEYIN3_PORT46_MARK,
396
397 KEYIN0_PORT58_MARK, /* MSEL4CR_18_1 */
398 KEYIN1_PORT57_MARK,
399 KEYIN2_PORT56_MARK,
400 KEYIN3_PORT55_MARK,
401
402 /* VOU */
403 DV_D0_MARK, DV_D1_MARK, DV_D2_MARK, DV_D3_MARK,
404 DV_D4_MARK, DV_D5_MARK, DV_D6_MARK, DV_D7_MARK,
405 DV_D8_MARK, DV_D9_MARK, DV_D10_MARK, DV_D11_MARK,
406 DV_D12_MARK, DV_D13_MARK, DV_D14_MARK, DV_D15_MARK,
407 DV_CLK_MARK, DV_VSYNC_MARK, DV_HSYNC_MARK,
408
409 /* MEMC */
410 MEMC_AD0_MARK, MEMC_AD1_MARK, MEMC_AD2_MARK, MEMC_AD3_MARK,
411 MEMC_AD4_MARK, MEMC_AD5_MARK, MEMC_AD6_MARK, MEMC_AD7_MARK,
412 MEMC_AD8_MARK, MEMC_AD9_MARK, MEMC_AD10_MARK, MEMC_AD11_MARK,
413 MEMC_AD12_MARK, MEMC_AD13_MARK, MEMC_AD14_MARK, MEMC_AD15_MARK,
414 MEMC_CS0_MARK, MEMC_INT_MARK, MEMC_NWE_MARK, MEMC_NOE_MARK,
415
416 MEMC_CS1_MARK, /* MSEL4CR_6_0 */
417 MEMC_ADV_MARK,
418 MEMC_WAIT_MARK,
419 MEMC_BUSCLK_MARK,
420
421 MEMC_A1_MARK, /* MSEL4CR_6_1 */
422 MEMC_DREQ0_MARK,
423 MEMC_DREQ1_MARK,
424 MEMC_A0_MARK,
425
426 /* MMC */
427 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK,
428 MMC0_D3_PORT71_MARK, MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK,
429 MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK, MMC0_CLK_PORT66_MARK,
430 MMC0_CMD_PORT67_MARK, /* MSEL4CR_15_0 */
431
432 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK,
433 MMC1_D3_PORT146_MARK, MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK,
434 MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK, MMC1_CLK_PORT103_MARK,
435 MMC1_CMD_PORT104_MARK, /* MSEL4CR_15_1 */
436
437 /* MSIOF0 */
438 MSIOF0_SS1_MARK, MSIOF0_SS2_MARK, MSIOF0_RXD_MARK,
439 MSIOF0_TXD_MARK, MSIOF0_MCK0_MARK, MSIOF0_MCK1_MARK,
440 MSIOF0_RSYNC_MARK, MSIOF0_RSCK_MARK, MSIOF0_TSCK_MARK,
441 MSIOF0_TSYNC_MARK,
442
443 /* MSIOF1 */
444 MSIOF1_RSCK_MARK, MSIOF1_RSYNC_MARK,
445 MSIOF1_MCK0_MARK, MSIOF1_MCK1_MARK,
446
447 MSIOF1_SS2_PORT116_MARK, MSIOF1_SS1_PORT117_MARK,
448 MSIOF1_RXD_PORT118_MARK, MSIOF1_TXD_PORT119_MARK,
449 MSIOF1_TSYNC_PORT120_MARK,
450 MSIOF1_TSCK_PORT121_MARK, /* MSEL4CR_10_0 */
451
452 MSIOF1_SS1_PORT67_MARK, MSIOF1_TSCK_PORT72_MARK,
453 MSIOF1_TSYNC_PORT73_MARK, MSIOF1_TXD_PORT74_MARK,
454 MSIOF1_RXD_PORT75_MARK,
455 MSIOF1_SS2_PORT202_MARK, /* MSEL4CR_10_1 */
456
457 /* GPIO */
458 GPO0_MARK, GPI0_MARK, GPO1_MARK, GPI1_MARK,
459
460 /* USB0 */
461 USB0_OCI_MARK, USB0_PPON_MARK, VBUS_MARK,
462
463 /* USB1 */
464 USB1_OCI_MARK, USB1_PPON_MARK,
465
466 /* BBIF1 */
467 BBIF1_RXD_MARK, BBIF1_TXD_MARK, BBIF1_TSYNC_MARK,
468 BBIF1_TSCK_MARK, BBIF1_RSCK_MARK, BBIF1_RSYNC_MARK,
469 BBIF1_FLOW_MARK, BBIF1_RX_FLOW_N_MARK,
470
471 /* BBIF2 */
472 BBIF2_TXD2_PORT5_MARK, /* MSEL5CR_0_0 */
473 BBIF2_RXD2_PORT60_MARK,
474 BBIF2_TSYNC2_PORT6_MARK,
475 BBIF2_TSCK2_PORT59_MARK,
476
477 BBIF2_RXD2_PORT90_MARK, /* MSEL5CR_0_1 */
478 BBIF2_TXD2_PORT183_MARK,
479 BBIF2_TSCK2_PORT89_MARK,
480 BBIF2_TSYNC2_PORT184_MARK,
481
482 /* BSC / FLCTL / PCMCIA */
483 CS0_MARK, CS2_MARK, CS4_MARK,
484 CS5B_MARK, CS6A_MARK,
485 CS5A_PORT105_MARK, /* CS5A PORT 19/105 */
486 CS5A_PORT19_MARK,
487 IOIS16_MARK, /* ? */
488
489 A0_MARK, A1_MARK, A2_MARK, A3_MARK,
490 A4_FOE_MARK, /* share with FLCTL */
491 A5_FCDE_MARK, /* share with FLCTL */
492 A6_MARK, A7_MARK, A8_MARK, A9_MARK,
493 A10_MARK, A11_MARK, A12_MARK, A13_MARK,
494 A14_MARK, A15_MARK, A16_MARK, A17_MARK,
495 A18_MARK, A19_MARK, A20_MARK, A21_MARK,
496 A22_MARK, A23_MARK, A24_MARK, A25_MARK,
497 A26_MARK,
498
499 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, /* share with FLCTL */
500 D3_NAF3_MARK, D4_NAF4_MARK, D5_NAF5_MARK, /* share with FLCTL */
501 D6_NAF6_MARK, D7_NAF7_MARK, D8_NAF8_MARK, /* share with FLCTL */
502 D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK, /* share with FLCTL */
503 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, /* share with FLCTL */
504 D15_NAF15_MARK, /* share with FLCTL */
505 D16_MARK, D17_MARK, D18_MARK, D19_MARK,
506 D20_MARK, D21_MARK, D22_MARK, D23_MARK,
507 D24_MARK, D25_MARK, D26_MARK, D27_MARK,
508 D28_MARK, D29_MARK, D30_MARK, D31_MARK,
509
510 WE0_FWE_MARK, /* share with FLCTL */
511 WE1_MARK,
512 WE2_ICIORD_MARK, /* share with PCMCIA */
513 WE3_ICIOWR_MARK, /* share with PCMCIA */
514 CKO_MARK, BS_MARK, RDWR_MARK,
515 RD_FSC_MARK, /* share with FLCTL */
516 WAIT_PORT177_MARK, /* WAIT Port 90/177 */
517 WAIT_PORT90_MARK,
518
519 FCE0_MARK, FCE1_MARK, FRB_MARK, /* FLCTL */
520
521 /* IRDA */
522 IRDA_FIRSEL_MARK, IRDA_IN_MARK, IRDA_OUT_MARK,
523
524 /* ATAPI */
525 IDE_D0_MARK, IDE_D1_MARK, IDE_D2_MARK, IDE_D3_MARK,
526 IDE_D4_MARK, IDE_D5_MARK, IDE_D6_MARK, IDE_D7_MARK,
527 IDE_D8_MARK, IDE_D9_MARK, IDE_D10_MARK, IDE_D11_MARK,
528 IDE_D12_MARK, IDE_D13_MARK, IDE_D14_MARK, IDE_D15_MARK,
529 IDE_A0_MARK, IDE_A1_MARK, IDE_A2_MARK, IDE_CS0_MARK,
530 IDE_CS1_MARK, IDE_IOWR_MARK, IDE_IORD_MARK, IDE_IORDY_MARK,
531 IDE_INT_MARK, IDE_RST_MARK, IDE_DIRECTION_MARK,
532 IDE_EXBUF_ENB_MARK, IDE_IODACK_MARK, IDE_IODREQ_MARK,
533
534 /* RMII */
535 RMII_CRS_DV_MARK, RMII_RX_ER_MARK, RMII_RXD0_MARK,
536 RMII_RXD1_MARK, RMII_TX_EN_MARK, RMII_TXD0_MARK,
537 RMII_MDC_MARK, RMII_TXD1_MARK, RMII_MDIO_MARK,
538 RMII_REF50CK_MARK, /* for RMII */
539 RMII_REF125CK_MARK, /* for GMII */
540
541 /* GEther */
542 ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_ETXD0_MARK, ET_ETXD1_MARK,
543 ET_ETXD2_MARK, ET_ETXD3_MARK,
544 ET_ETXD4_MARK, ET_ETXD5_MARK, /* for GEther */
545 ET_ETXD6_MARK, ET_ETXD7_MARK, /* for GEther */
546 ET_COL_MARK, ET_TX_ER_MARK, ET_RX_CLK_MARK, ET_RX_DV_MARK,
547 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
548 ET_ERXD4_MARK, ET_ERXD5_MARK, /* for GEther */
549 ET_ERXD6_MARK, ET_ERXD7_MARK, /* for GEther */
550 ET_RX_ER_MARK, ET_CRS_MARK, ET_MDC_MARK, ET_MDIO_MARK,
551 ET_LINK_MARK, ET_PHY_INT_MARK, ET_WOL_MARK, ET_GTX_CLK_MARK,
552
553 /* DMA0 */
554 DREQ0_MARK, DACK0_MARK,
555
556 /* DMA1 */
557 DREQ1_MARK, DACK1_MARK,
558
559 /* SYSC */
560 RESETOUTS_MARK, RESETP_PULLUP_MARK, RESETP_PLAIN_MARK,
561
562 /* IRREM */
563 IROUT_MARK,
564
565 /* SDENC */
566 SDENC_CPG_MARK, SDENC_DV_CLKI_MARK,
567
568 /* HDMI */
569 HDMI_HPD_MARK, HDMI_CEC_MARK,
570
571 /* DEBUG */
572 EDEBGREQ_PULLUP_MARK, /* for JTAG */
573 EDEBGREQ_PULLDOWN_MARK,
574
575 TRACEAUD_FROM_VIO_MARK, /* for TRACE/AUD */
576 TRACEAUD_FROM_LCDC0_MARK,
577 TRACEAUD_FROM_MEMC_MARK,
578
579 PINMUX_MARK_END,
580 };
581
582 static const u16 pinmux_data[] = {
583 PINMUX_DATA_ALL(),
584
585 /* Port0 */
586 PINMUX_DATA(DBGMDT2_MARK, PORT0_FN1),
587 PINMUX_DATA(FSIAISLD_PORT0_MARK, PORT0_FN2, MSEL5CR_3_0),
588 PINMUX_DATA(FSIAOSLD1_MARK, PORT0_FN3),
589 PINMUX_DATA(LCD0_D22_PORT0_MARK, PORT0_FN4, MSEL5CR_6_0),
590 PINMUX_DATA(SCIFA7_RXD_MARK, PORT0_FN6),
591 PINMUX_DATA(LCD1_D4_MARK, PORT0_FN7),
592 PINMUX_DATA(IRQ5_PORT0_MARK, PORT0_FN0, MSEL1CR_5_0),
593
594 /* Port1 */
595 PINMUX_DATA(DBGMDT1_MARK, PORT1_FN1),
596 PINMUX_DATA(FMSISLD_PORT1_MARK, PORT1_FN2, MSEL5CR_5_0),
597 PINMUX_DATA(FSIAOSLD2_MARK, PORT1_FN3),
598 PINMUX_DATA(LCD0_D23_PORT1_MARK, PORT1_FN4, MSEL5CR_6_0),
599 PINMUX_DATA(SCIFA7_TXD_MARK, PORT1_FN6),
600 PINMUX_DATA(LCD1_D3_MARK, PORT1_FN7),
601 PINMUX_DATA(IRQ5_PORT1_MARK, PORT1_FN0, MSEL1CR_5_1),
602
603 /* Port2 */
604 PINMUX_DATA(DBGMDT0_MARK, PORT2_FN1),
605 PINMUX_DATA(SCIFB_SCK_PORT2_MARK, PORT2_FN2, MSEL5CR_17_1),
606 PINMUX_DATA(LCD0_D21_PORT2_MARK, PORT2_FN4, MSEL5CR_6_0),
607 PINMUX_DATA(LCD1_D2_MARK, PORT2_FN7),
608 PINMUX_DATA(IRQ0_PORT2_MARK, PORT2_FN0, MSEL1CR_0_1),
609
610 /* Port3 */
611 PINMUX_DATA(DBGMD21_MARK, PORT3_FN1),
612 PINMUX_DATA(SCIFB_RXD_PORT3_MARK, PORT3_FN2, MSEL5CR_17_1),
613 PINMUX_DATA(LCD0_D20_PORT3_MARK, PORT3_FN4, MSEL5CR_6_0),
614 PINMUX_DATA(LCD1_D1_MARK, PORT3_FN7),
615
616 /* Port4 */
617 PINMUX_DATA(DBGMD20_MARK, PORT4_FN1),
618 PINMUX_DATA(SCIFB_TXD_PORT4_MARK, PORT4_FN2, MSEL5CR_17_1),
619 PINMUX_DATA(LCD0_D19_PORT4_MARK, PORT4_FN4, MSEL5CR_6_0),
620 PINMUX_DATA(LCD1_D0_MARK, PORT4_FN7),
621
622 /* Port5 */
623 PINMUX_DATA(DBGMD11_MARK, PORT5_FN1),
624 PINMUX_DATA(BBIF2_TXD2_PORT5_MARK, PORT5_FN2, MSEL5CR_0_0),
625 PINMUX_DATA(FSIAISLD_PORT5_MARK, PORT5_FN4, MSEL5CR_3_1),
626 PINMUX_DATA(RSPI_SSL0_A_MARK, PORT5_FN6),
627 PINMUX_DATA(LCD1_VCPWC_MARK, PORT5_FN7),
628
629 /* Port6 */
630 PINMUX_DATA(DBGMD10_MARK, PORT6_FN1),
631 PINMUX_DATA(BBIF2_TSYNC2_PORT6_MARK, PORT6_FN2, MSEL5CR_0_0),
632 PINMUX_DATA(FMSISLD_PORT6_MARK, PORT6_FN4, MSEL5CR_5_1),
633 PINMUX_DATA(RSPI_SSL1_A_MARK, PORT6_FN6),
634 PINMUX_DATA(LCD1_VEPWC_MARK, PORT6_FN7),
635
636 /* Port7 */
637 PINMUX_DATA(FSIAOLR_MARK, PORT7_FN1),
638
639 /* Port8 */
640 PINMUX_DATA(FSIAOBT_MARK, PORT8_FN1),
641
642 /* Port9 */
643 PINMUX_DATA(FSIAOSLD_MARK, PORT9_FN1),
644 PINMUX_DATA(FSIASPDIF_PORT9_MARK, PORT9_FN2, MSEL5CR_4_0),
645
646 /* Port10 */
647 PINMUX_DATA(FSIAOMC_MARK, PORT10_FN1),
648 PINMUX_DATA(SCIFA5_RXD_PORT10_MARK, PORT10_FN3, MSEL5CR_14_0, MSEL5CR_15_0),
649 PINMUX_DATA(IRQ3_PORT10_MARK, PORT10_FN0, MSEL1CR_3_0),
650
651 /* Port11 */
652 PINMUX_DATA(FSIACK_MARK, PORT11_FN1),
653 PINMUX_DATA(FSIBCK_MARK, PORT11_FN2),
654 PINMUX_DATA(IRQ2_PORT11_MARK, PORT11_FN0, MSEL1CR_2_0),
655
656 /* Port12 */
657 PINMUX_DATA(FSIAILR_MARK, PORT12_FN1),
658 PINMUX_DATA(SCIFA4_RXD_PORT12_MARK, PORT12_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
659 PINMUX_DATA(LCD1_RS_MARK, PORT12_FN6),
660 PINMUX_DATA(LCD1_DISP_MARK, PORT12_FN7),
661 PINMUX_DATA(IRQ2_PORT12_MARK, PORT12_FN0, MSEL1CR_2_1),
662
663 /* Port13 */
664 PINMUX_DATA(FSIAIBT_MARK, PORT13_FN1),
665 PINMUX_DATA(SCIFA4_TXD_PORT13_MARK, PORT13_FN2, MSEL5CR_12_0, MSEL5CR_11_0),
666 PINMUX_DATA(LCD1_RD_MARK, PORT13_FN7),
667 PINMUX_DATA(IRQ0_PORT13_MARK, PORT13_FN0, MSEL1CR_0_0),
668
669 /* Port14 */
670 PINMUX_DATA(FMSOILR_MARK, PORT14_FN1),
671 PINMUX_DATA(FMSIILR_MARK, PORT14_FN2),
672 PINMUX_DATA(VIO_CKO1_MARK, PORT14_FN3),
673 PINMUX_DATA(LCD1_D23_MARK, PORT14_FN7),
674 PINMUX_DATA(IRQ3_PORT14_MARK, PORT14_FN0, MSEL1CR_3_1),
675
676 /* Port15 */
677 PINMUX_DATA(FMSOIBT_MARK, PORT15_FN1),
678 PINMUX_DATA(FMSIIBT_MARK, PORT15_FN2),
679 PINMUX_DATA(VIO_CKO2_MARK, PORT15_FN3),
680 PINMUX_DATA(LCD1_D22_MARK, PORT15_FN7),
681 PINMUX_DATA(IRQ4_PORT15_MARK, PORT15_FN0, MSEL1CR_4_0),
682
683 /* Port16 */
684 PINMUX_DATA(FMSOOLR_MARK, PORT16_FN1),
685 PINMUX_DATA(FMSIOLR_MARK, PORT16_FN2),
686
687 /* Port17 */
688 PINMUX_DATA(FMSOOBT_MARK, PORT17_FN1),
689 PINMUX_DATA(FMSIOBT_MARK, PORT17_FN2),
690
691 /* Port18 */
692 PINMUX_DATA(FMSOSLD_MARK, PORT18_FN1),
693 PINMUX_DATA(FSIASPDIF_PORT18_MARK, PORT18_FN2, MSEL5CR_4_1),
694
695 /* Port19 */
696 PINMUX_DATA(FMSICK_MARK, PORT19_FN1),
697 PINMUX_DATA(CS5A_PORT19_MARK, PORT19_FN7, MSEL5CR_2_1),
698 PINMUX_DATA(IRQ10_MARK, PORT19_FN0),
699
700 /* Port20 */
701 PINMUX_DATA(FMSOCK_MARK, PORT20_FN1),
702 PINMUX_DATA(SCIFA5_TXD_PORT20_MARK, PORT20_FN3, MSEL5CR_15_0, MSEL5CR_14_0),
703 PINMUX_DATA(IRQ1_MARK, PORT20_FN0),
704
705 /* Port21 */
706 PINMUX_DATA(SCIFA1_CTS_MARK, PORT21_FN1),
707 PINMUX_DATA(SCIFA4_SCK_PORT21_MARK, PORT21_FN2, MSEL5CR_10_0),
708 PINMUX_DATA(TPU0TO1_MARK, PORT21_FN4),
709 PINMUX_DATA(VIO1_FIELD_MARK, PORT21_FN5),
710 PINMUX_DATA(STP0_IPD5_MARK, PORT21_FN6),
711 PINMUX_DATA(LCD1_D10_MARK, PORT21_FN7),
712
713 /* Port22 */
714 PINMUX_DATA(SCIFA2_SCK_PORT22_MARK, PORT22_FN1, MSEL5CR_7_0),
715 PINMUX_DATA(SIM_D_PORT22_MARK, PORT22_FN4, MSEL5CR_21_0),
716 PINMUX_DATA(VIO0_D13_PORT22_MARK, PORT22_FN7, MSEL5CR_27_1),
717
718 /* Port23 */
719 PINMUX_DATA(SCIFA1_RTS_MARK, PORT23_FN1),
720 PINMUX_DATA(SCIFA5_SCK_PORT23_MARK, PORT23_FN3, MSEL5CR_13_0),
721 PINMUX_DATA(TPU0TO0_MARK, PORT23_FN4),
722 PINMUX_DATA(VIO_CKO_1_MARK, PORT23_FN5),
723 PINMUX_DATA(STP0_IPD2_MARK, PORT23_FN6),
724 PINMUX_DATA(LCD1_D7_MARK, PORT23_FN7),
725
726 /* Port24 */
727 PINMUX_DATA(VIO0_D15_PORT24_MARK, PORT24_FN1, MSEL5CR_27_0),
728 PINMUX_DATA(VIO1_D7_MARK, PORT24_FN5),
729 PINMUX_DATA(SCIFA6_SCK_MARK, PORT24_FN6),
730 PINMUX_DATA(SDHI2_CD_PORT24_MARK, PORT24_FN7, MSEL5CR_19_0),
731
732 /* Port25 */
733 PINMUX_DATA(VIO0_D14_PORT25_MARK, PORT25_FN1, MSEL5CR_27_0),
734 PINMUX_DATA(VIO1_D6_MARK, PORT25_FN5),
735 PINMUX_DATA(SCIFA6_RXD_MARK, PORT25_FN6),
736 PINMUX_DATA(SDHI2_WP_PORT25_MARK, PORT25_FN7, MSEL5CR_19_0),
737
738 /* Port26 */
739 PINMUX_DATA(VIO0_D13_PORT26_MARK, PORT26_FN1, MSEL5CR_27_0),
740 PINMUX_DATA(VIO1_D5_MARK, PORT26_FN5),
741 PINMUX_DATA(SCIFA6_TXD_MARK, PORT26_FN6),
742
743 /* Port27 - Port39 Function */
744 PINMUX_DATA(VIO0_D7_MARK, PORT27_FN1),
745 PINMUX_DATA(VIO0_D6_MARK, PORT28_FN1),
746 PINMUX_DATA(VIO0_D5_MARK, PORT29_FN1),
747 PINMUX_DATA(VIO0_D4_MARK, PORT30_FN1),
748 PINMUX_DATA(VIO0_D3_MARK, PORT31_FN1),
749 PINMUX_DATA(VIO0_D2_MARK, PORT32_FN1),
750 PINMUX_DATA(VIO0_D1_MARK, PORT33_FN1),
751 PINMUX_DATA(VIO0_D0_MARK, PORT34_FN1),
752 PINMUX_DATA(VIO0_CLK_MARK, PORT35_FN1),
753 PINMUX_DATA(VIO_CKO_MARK, PORT36_FN1),
754 PINMUX_DATA(VIO0_HD_MARK, PORT37_FN1),
755 PINMUX_DATA(VIO0_FIELD_MARK, PORT38_FN1),
756 PINMUX_DATA(VIO0_VD_MARK, PORT39_FN1),
757
758 /* Port38 IRQ */
759 PINMUX_DATA(IRQ25_MARK, PORT38_FN0),
760
761 /* Port40 */
762 PINMUX_DATA(LCD0_D18_PORT40_MARK, PORT40_FN4, MSEL5CR_6_0),
763 PINMUX_DATA(RSPI_CK_A_MARK, PORT40_FN6),
764 PINMUX_DATA(LCD1_LCLK_MARK, PORT40_FN7),
765
766 /* Port41 */
767 PINMUX_DATA(LCD0_D17_MARK, PORT41_FN1),
768 PINMUX_DATA(MSIOF2_SS1_MARK, PORT41_FN2),
769 PINMUX_DATA(IRQ31_PORT41_MARK, PORT41_FN0, MSEL1CR_31_1),
770
771 /* Port42 */
772 PINMUX_DATA(LCD0_D16_MARK, PORT42_FN1),
773 PINMUX_DATA(MSIOF2_MCK1_MARK, PORT42_FN2),
774 PINMUX_DATA(IRQ12_PORT42_MARK, PORT42_FN0, MSEL1CR_12_1),
775
776 /* Port43 */
777 PINMUX_DATA(LCD0_D15_MARK, PORT43_FN1),
778 PINMUX_DATA(MSIOF2_MCK0_MARK, PORT43_FN2),
779 PINMUX_DATA(KEYIN0_PORT43_MARK, PORT43_FN3, MSEL4CR_18_0),
780 PINMUX_DATA(DV_D15_MARK, PORT43_FN6),
781
782 /* Port44 */
783 PINMUX_DATA(LCD0_D14_MARK, PORT44_FN1),
784 PINMUX_DATA(MSIOF2_RSYNC_MARK, PORT44_FN2),
785 PINMUX_DATA(KEYIN1_PORT44_MARK, PORT44_FN3, MSEL4CR_18_0),
786 PINMUX_DATA(DV_D14_MARK, PORT44_FN6),
787
788 /* Port45 */
789 PINMUX_DATA(LCD0_D13_MARK, PORT45_FN1),
790 PINMUX_DATA(MSIOF2_RSCK_MARK, PORT45_FN2),
791 PINMUX_DATA(KEYIN2_PORT45_MARK, PORT45_FN3, MSEL4CR_18_0),
792 PINMUX_DATA(DV_D13_MARK, PORT45_FN6),
793
794 /* Port46 */
795 PINMUX_DATA(LCD0_D12_MARK, PORT46_FN1),
796 PINMUX_DATA(KEYIN3_PORT46_MARK, PORT46_FN3, MSEL4CR_18_0),
797 PINMUX_DATA(DV_D12_MARK, PORT46_FN6),
798
799 /* Port47 */
800 PINMUX_DATA(LCD0_D11_MARK, PORT47_FN1),
801 PINMUX_DATA(KEYIN4_MARK, PORT47_FN3),
802 PINMUX_DATA(DV_D11_MARK, PORT47_FN6),
803
804 /* Port48 */
805 PINMUX_DATA(LCD0_D10_MARK, PORT48_FN1),
806 PINMUX_DATA(KEYIN5_MARK, PORT48_FN3),
807 PINMUX_DATA(DV_D10_MARK, PORT48_FN6),
808
809 /* Port49 */
810 PINMUX_DATA(LCD0_D9_MARK, PORT49_FN1),
811 PINMUX_DATA(KEYIN6_MARK, PORT49_FN3),
812 PINMUX_DATA(DV_D9_MARK, PORT49_FN6),
813 PINMUX_DATA(IRQ30_PORT49_MARK, PORT49_FN0, MSEL1CR_30_1),
814
815 /* Port50 */
816 PINMUX_DATA(LCD0_D8_MARK, PORT50_FN1),
817 PINMUX_DATA(KEYIN7_MARK, PORT50_FN3),
818 PINMUX_DATA(DV_D8_MARK, PORT50_FN6),
819 PINMUX_DATA(IRQ29_PORT50_MARK, PORT50_FN0, MSEL1CR_29_1),
820
821 /* Port51 */
822 PINMUX_DATA(LCD0_D7_MARK, PORT51_FN1),
823 PINMUX_DATA(KEYOUT0_MARK, PORT51_FN3),
824 PINMUX_DATA(DV_D7_MARK, PORT51_FN6),
825
826 /* Port52 */
827 PINMUX_DATA(LCD0_D6_MARK, PORT52_FN1),
828 PINMUX_DATA(KEYOUT1_MARK, PORT52_FN3),
829 PINMUX_DATA(DV_D6_MARK, PORT52_FN6),
830
831 /* Port53 */
832 PINMUX_DATA(LCD0_D5_MARK, PORT53_FN1),
833 PINMUX_DATA(KEYOUT2_MARK, PORT53_FN3),
834 PINMUX_DATA(DV_D5_MARK, PORT53_FN6),
835
836 /* Port54 */
837 PINMUX_DATA(LCD0_D4_MARK, PORT54_FN1),
838 PINMUX_DATA(KEYOUT3_MARK, PORT54_FN3),
839 PINMUX_DATA(DV_D4_MARK, PORT54_FN6),
840
841 /* Port55 */
842 PINMUX_DATA(LCD0_D3_MARK, PORT55_FN1),
843 PINMUX_DATA(KEYOUT4_MARK, PORT55_FN3),
844 PINMUX_DATA(KEYIN3_PORT55_MARK, PORT55_FN4, MSEL4CR_18_1),
845 PINMUX_DATA(DV_D3_MARK, PORT55_FN6),
846
847 /* Port56 */
848 PINMUX_DATA(LCD0_D2_MARK, PORT56_FN1),
849 PINMUX_DATA(KEYOUT5_MARK, PORT56_FN3),
850 PINMUX_DATA(KEYIN2_PORT56_MARK, PORT56_FN4, MSEL4CR_18_1),
851 PINMUX_DATA(DV_D2_MARK, PORT56_FN6),
852 PINMUX_DATA(IRQ28_PORT56_MARK, PORT56_FN0, MSEL1CR_28_1),
853
854 /* Port57 */
855 PINMUX_DATA(LCD0_D1_MARK, PORT57_FN1),
856 PINMUX_DATA(KEYOUT6_MARK, PORT57_FN3),
857 PINMUX_DATA(KEYIN1_PORT57_MARK, PORT57_FN4, MSEL4CR_18_1),
858 PINMUX_DATA(DV_D1_MARK, PORT57_FN6),
859 PINMUX_DATA(IRQ27_PORT57_MARK, PORT57_FN0, MSEL1CR_27_1),
860
861 /* Port58 */
862 PINMUX_DATA(LCD0_D0_MARK, PORT58_FN1, MSEL3CR_6_0),
863 PINMUX_DATA(KEYOUT7_MARK, PORT58_FN3),
864 PINMUX_DATA(KEYIN0_PORT58_MARK, PORT58_FN4, MSEL4CR_18_1),
865 PINMUX_DATA(DV_D0_MARK, PORT58_FN6),
866 PINMUX_DATA(IRQ26_PORT58_MARK, PORT58_FN0, MSEL1CR_26_1),
867
868 /* Port59 */
869 PINMUX_DATA(LCD0_VCPWC_MARK, PORT59_FN1),
870 PINMUX_DATA(BBIF2_TSCK2_PORT59_MARK, PORT59_FN2, MSEL5CR_0_0),
871 PINMUX_DATA(RSPI_MOSI_A_MARK, PORT59_FN6),
872
873 /* Port60 */
874 PINMUX_DATA(LCD0_VEPWC_MARK, PORT60_FN1),
875 PINMUX_DATA(BBIF2_RXD2_PORT60_MARK, PORT60_FN2, MSEL5CR_0_0),
876 PINMUX_DATA(RSPI_MISO_A_MARK, PORT60_FN6),
877
878 /* Port61 */
879 PINMUX_DATA(LCD0_DON_MARK, PORT61_FN1),
880 PINMUX_DATA(MSIOF2_TXD_MARK, PORT61_FN2),
881
882 /* Port62 */
883 PINMUX_DATA(LCD0_DCK_MARK, PORT62_FN1),
884 PINMUX_DATA(LCD0_WR_MARK, PORT62_FN4),
885 PINMUX_DATA(DV_CLK_MARK, PORT62_FN6),
886 PINMUX_DATA(IRQ15_PORT62_MARK, PORT62_FN0, MSEL1CR_15_1),
887
888 /* Port63 */
889 PINMUX_DATA(LCD0_VSYN_MARK, PORT63_FN1),
890 PINMUX_DATA(DV_VSYNC_MARK, PORT63_FN6),
891 PINMUX_DATA(IRQ14_PORT63_MARK, PORT63_FN0, MSEL1CR_14_1),
892
893 /* Port64 */
894 PINMUX_DATA(LCD0_HSYN_MARK, PORT64_FN1),
895 PINMUX_DATA(LCD0_CS_MARK, PORT64_FN4),
896 PINMUX_DATA(DV_HSYNC_MARK, PORT64_FN6),
897 PINMUX_DATA(IRQ13_PORT64_MARK, PORT64_FN0, MSEL1CR_13_1),
898
899 /* Port65 */
900 PINMUX_DATA(LCD0_DISP_MARK, PORT65_FN1),
901 PINMUX_DATA(MSIOF2_TSCK_MARK, PORT65_FN2),
902 PINMUX_DATA(LCD0_RS_MARK, PORT65_FN4),
903
904 /* Port66 */
905 PINMUX_DATA(MEMC_INT_MARK, PORT66_FN1),
906 PINMUX_DATA(TPU0TO2_PORT66_MARK, PORT66_FN3, MSEL5CR_25_0),
907 PINMUX_DATA(MMC0_CLK_PORT66_MARK, PORT66_FN4, MSEL4CR_15_0),
908 PINMUX_DATA(SDHI1_CLK_MARK, PORT66_FN6),
909
910 /* Port67 - Port73 Function1 */
911 PINMUX_DATA(MEMC_CS0_MARK, PORT67_FN1),
912 PINMUX_DATA(MEMC_AD8_MARK, PORT68_FN1),
913 PINMUX_DATA(MEMC_AD9_MARK, PORT69_FN1),
914 PINMUX_DATA(MEMC_AD10_MARK, PORT70_FN1),
915 PINMUX_DATA(MEMC_AD11_MARK, PORT71_FN1),
916 PINMUX_DATA(MEMC_AD12_MARK, PORT72_FN1),
917 PINMUX_DATA(MEMC_AD13_MARK, PORT73_FN1),
918
919 /* Port67 - Port73 Function2 */
920 PINMUX_DATA(MSIOF1_SS1_PORT67_MARK, PORT67_FN2, MSEL4CR_10_1),
921 PINMUX_DATA(MSIOF1_RSCK_MARK, PORT68_FN2),
922 PINMUX_DATA(MSIOF1_RSYNC_MARK, PORT69_FN2),
923 PINMUX_DATA(MSIOF1_MCK0_MARK, PORT70_FN2),
924 PINMUX_DATA(MSIOF1_MCK1_MARK, PORT71_FN2),
925 PINMUX_DATA(MSIOF1_TSCK_PORT72_MARK, PORT72_FN2, MSEL4CR_10_1),
926 PINMUX_DATA(MSIOF1_TSYNC_PORT73_MARK, PORT73_FN2, MSEL4CR_10_1),
927
928 /* Port67 - Port73 Function4 */
929 PINMUX_DATA(MMC0_CMD_PORT67_MARK, PORT67_FN4, MSEL4CR_15_0),
930 PINMUX_DATA(MMC0_D0_PORT68_MARK, PORT68_FN4, MSEL4CR_15_0),
931 PINMUX_DATA(MMC0_D1_PORT69_MARK, PORT69_FN4, MSEL4CR_15_0),
932 PINMUX_DATA(MMC0_D2_PORT70_MARK, PORT70_FN4, MSEL4CR_15_0),
933 PINMUX_DATA(MMC0_D3_PORT71_MARK, PORT71_FN4, MSEL4CR_15_0),
934 PINMUX_DATA(MMC0_D4_PORT72_MARK, PORT72_FN4, MSEL4CR_15_0),
935 PINMUX_DATA(MMC0_D5_PORT73_MARK, PORT73_FN4, MSEL4CR_15_0),
936
937 /* Port67 - Port73 Function6 */
938 PINMUX_DATA(SDHI1_CMD_MARK, PORT67_FN6),
939 PINMUX_DATA(SDHI1_D0_MARK, PORT68_FN6),
940 PINMUX_DATA(SDHI1_D1_MARK, PORT69_FN6),
941 PINMUX_DATA(SDHI1_D2_MARK, PORT70_FN6),
942 PINMUX_DATA(SDHI1_D3_MARK, PORT71_FN6),
943 PINMUX_DATA(SDHI1_CD_MARK, PORT72_FN6),
944 PINMUX_DATA(SDHI1_WP_MARK, PORT73_FN6),
945
946 /* Port67 - Port71 IRQ */
947 PINMUX_DATA(IRQ20_MARK, PORT67_FN0),
948 PINMUX_DATA(IRQ16_PORT68_MARK, PORT68_FN0, MSEL1CR_16_0),
949 PINMUX_DATA(IRQ17_MARK, PORT69_FN0),
950 PINMUX_DATA(IRQ18_MARK, PORT70_FN0),
951 PINMUX_DATA(IRQ19_MARK, PORT71_FN0),
952
953 /* Port74 */
954 PINMUX_DATA(MEMC_AD14_MARK, PORT74_FN1),
955 PINMUX_DATA(MSIOF1_TXD_PORT74_MARK, PORT74_FN2, MSEL4CR_10_1),
956 PINMUX_DATA(MMC0_D6_PORT74_MARK, PORT74_FN4, MSEL4CR_15_0),
957 PINMUX_DATA(STP1_IPD7_MARK, PORT74_FN6),
958 PINMUX_DATA(LCD1_D21_MARK, PORT74_FN7),
959
960 /* Port75 */
961 PINMUX_DATA(MEMC_AD15_MARK, PORT75_FN1),
962 PINMUX_DATA(MSIOF1_RXD_PORT75_MARK, PORT75_FN2, MSEL4CR_10_1),
963 PINMUX_DATA(MMC0_D7_PORT75_MARK, PORT75_FN4, MSEL4CR_15_0),
964 PINMUX_DATA(STP1_IPD6_MARK, PORT75_FN6),
965 PINMUX_DATA(LCD1_D20_MARK, PORT75_FN7),
966
967 /* Port76 - Port80 Function */
968 PINMUX_DATA(SDHI0_CMD_MARK, PORT76_FN1),
969 PINMUX_DATA(SDHI0_D0_MARK, PORT77_FN1),
970 PINMUX_DATA(SDHI0_D1_MARK, PORT78_FN1),
971 PINMUX_DATA(SDHI0_D2_MARK, PORT79_FN1),
972 PINMUX_DATA(SDHI0_D3_MARK, PORT80_FN1),
973
974 /* Port81 */
975 PINMUX_DATA(SDHI0_CD_MARK, PORT81_FN1),
976 PINMUX_DATA(IRQ26_PORT81_MARK, PORT81_FN0, MSEL1CR_26_0),
977
978 /* Port82 - Port88 Function */
979 PINMUX_DATA(SDHI0_CLK_MARK, PORT82_FN1),
980 PINMUX_DATA(SDHI0_WP_MARK, PORT83_FN1),
981 PINMUX_DATA(RESETOUTS_MARK, PORT84_FN1),
982 PINMUX_DATA(USB0_PPON_MARK, PORT85_FN1),
983 PINMUX_DATA(USB0_OCI_MARK, PORT86_FN1),
984 PINMUX_DATA(USB1_PPON_MARK, PORT87_FN1),
985 PINMUX_DATA(USB1_OCI_MARK, PORT88_FN1),
986
987 /* Port89 */
988 PINMUX_DATA(DREQ0_MARK, PORT89_FN1),
989 PINMUX_DATA(BBIF2_TSCK2_PORT89_MARK, PORT89_FN2, MSEL5CR_0_1),
990 PINMUX_DATA(RSPI_SSL3_A_MARK, PORT89_FN6),
991
992 /* Port90 */
993 PINMUX_DATA(DACK0_MARK, PORT90_FN1),
994 PINMUX_DATA(BBIF2_RXD2_PORT90_MARK, PORT90_FN2, MSEL5CR_0_1),
995 PINMUX_DATA(RSPI_SSL2_A_MARK, PORT90_FN6),
996 PINMUX_DATA(WAIT_PORT90_MARK, PORT90_FN7, MSEL5CR_2_1),
997
998 /* Port91 */
999 PINMUX_DATA(MEMC_AD0_MARK, PORT91_FN1),
1000 PINMUX_DATA(BBIF1_RXD_MARK, PORT91_FN2),
1001 PINMUX_DATA(SCIFA5_TXD_PORT91_MARK, PORT91_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
1002 PINMUX_DATA(LCD1_D5_MARK, PORT91_FN7),
1003
1004 /* Port92 */
1005 PINMUX_DATA(MEMC_AD1_MARK, PORT92_FN1),
1006 PINMUX_DATA(BBIF1_TSYNC_MARK, PORT92_FN2),
1007 PINMUX_DATA(SCIFA5_RXD_PORT92_MARK, PORT92_FN3, MSEL5CR_15_1, MSEL5CR_14_0),
1008 PINMUX_DATA(STP0_IPD1_MARK, PORT92_FN6),
1009 PINMUX_DATA(LCD1_D6_MARK, PORT92_FN7),
1010
1011 /* Port93 */
1012 PINMUX_DATA(MEMC_AD2_MARK, PORT93_FN1),
1013 PINMUX_DATA(BBIF1_TSCK_MARK, PORT93_FN2),
1014 PINMUX_DATA(SCIFA4_TXD_PORT93_MARK, PORT93_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
1015 PINMUX_DATA(STP0_IPD3_MARK, PORT93_FN6),
1016 PINMUX_DATA(LCD1_D8_MARK, PORT93_FN7),
1017
1018 /* Port94 */
1019 PINMUX_DATA(MEMC_AD3_MARK, PORT94_FN1),
1020 PINMUX_DATA(BBIF1_TXD_MARK, PORT94_FN2),
1021 PINMUX_DATA(SCIFA4_RXD_PORT94_MARK, PORT94_FN3, MSEL5CR_12_1, MSEL5CR_11_0),
1022 PINMUX_DATA(STP0_IPD4_MARK, PORT94_FN6),
1023 PINMUX_DATA(LCD1_D9_MARK, PORT94_FN7),
1024
1025 /* Port95 */
1026 PINMUX_DATA(MEMC_CS1_MARK, PORT95_FN1, MSEL4CR_6_0),
1027 PINMUX_DATA(MEMC_A1_MARK, PORT95_FN1, MSEL4CR_6_1),
1028
1029 PINMUX_DATA(SCIFA2_CTS_MARK, PORT95_FN2),
1030 PINMUX_DATA(SIM_RST_MARK, PORT95_FN4),
1031 PINMUX_DATA(VIO0_D14_PORT95_MARK, PORT95_FN7, MSEL5CR_27_1),
1032 PINMUX_DATA(IRQ22_MARK, PORT95_FN0),
1033
1034 /* Port96 */
1035 PINMUX_DATA(MEMC_ADV_MARK, PORT96_FN1, MSEL4CR_6_0),
1036 PINMUX_DATA(MEMC_DREQ0_MARK, PORT96_FN1, MSEL4CR_6_1),
1037
1038 PINMUX_DATA(SCIFA2_RTS_MARK, PORT96_FN2),
1039 PINMUX_DATA(SIM_CLK_MARK, PORT96_FN4),
1040 PINMUX_DATA(VIO0_D15_PORT96_MARK, PORT96_FN7, MSEL5CR_27_1),
1041 PINMUX_DATA(IRQ23_MARK, PORT96_FN0),
1042
1043 /* Port97 */
1044 PINMUX_DATA(MEMC_AD4_MARK, PORT97_FN1),
1045 PINMUX_DATA(BBIF1_RSCK_MARK, PORT97_FN2),
1046 PINMUX_DATA(LCD1_CS_MARK, PORT97_FN6),
1047 PINMUX_DATA(LCD1_HSYN_MARK, PORT97_FN7),
1048 PINMUX_DATA(IRQ12_PORT97_MARK, PORT97_FN0, MSEL1CR_12_0),
1049
1050 /* Port98 */
1051 PINMUX_DATA(MEMC_AD5_MARK, PORT98_FN1),
1052 PINMUX_DATA(BBIF1_RSYNC_MARK, PORT98_FN2),
1053 PINMUX_DATA(LCD1_VSYN_MARK, PORT98_FN7),
1054 PINMUX_DATA(IRQ13_PORT98_MARK, PORT98_FN0, MSEL1CR_13_0),
1055
1056 /* Port99 */
1057 PINMUX_DATA(MEMC_AD6_MARK, PORT99_FN1),
1058 PINMUX_DATA(BBIF1_FLOW_MARK, PORT99_FN2),
1059 PINMUX_DATA(LCD1_WR_MARK, PORT99_FN6),
1060 PINMUX_DATA(LCD1_DCK_MARK, PORT99_FN7),
1061 PINMUX_DATA(IRQ14_PORT99_MARK, PORT99_FN0, MSEL1CR_14_0),
1062
1063 /* Port100 */
1064 PINMUX_DATA(MEMC_AD7_MARK, PORT100_FN1),
1065 PINMUX_DATA(BBIF1_RX_FLOW_N_MARK, PORT100_FN2),
1066 PINMUX_DATA(LCD1_DON_MARK, PORT100_FN7),
1067 PINMUX_DATA(IRQ15_PORT100_MARK, PORT100_FN0, MSEL1CR_15_0),
1068
1069 /* Port101 */
1070 PINMUX_DATA(FCE0_MARK, PORT101_FN1),
1071
1072 /* Port102 */
1073 PINMUX_DATA(FRB_MARK, PORT102_FN1),
1074 PINMUX_DATA(LCD0_LCLK_PORT102_MARK, PORT102_FN4, MSEL5CR_6_0),
1075
1076 /* Port103 */
1077 PINMUX_DATA(CS5B_MARK, PORT103_FN1),
1078 PINMUX_DATA(FCE1_MARK, PORT103_FN2),
1079 PINMUX_DATA(MMC1_CLK_PORT103_MARK, PORT103_FN3, MSEL4CR_15_1),
1080
1081 /* Port104 */
1082 PINMUX_DATA(CS6A_MARK, PORT104_FN1),
1083 PINMUX_DATA(MMC1_CMD_PORT104_MARK, PORT104_FN3, MSEL4CR_15_1),
1084 PINMUX_DATA(IRQ11_MARK, PORT104_FN0),
1085
1086 /* Port105 */
1087 PINMUX_DATA(CS5A_PORT105_MARK, PORT105_FN1, MSEL5CR_2_0),
1088 PINMUX_DATA(SCIFA3_RTS_PORT105_MARK, PORT105_FN4, MSEL5CR_8_0),
1089
1090 /* Port106 */
1091 PINMUX_DATA(IOIS16_MARK, PORT106_FN1),
1092 PINMUX_DATA(IDE_EXBUF_ENB_MARK, PORT106_FN6),
1093
1094 /* Port107 - Port115 Function */
1095 PINMUX_DATA(WE3_ICIOWR_MARK, PORT107_FN1),
1096 PINMUX_DATA(WE2_ICIORD_MARK, PORT108_FN1),
1097 PINMUX_DATA(CS0_MARK, PORT109_FN1),
1098 PINMUX_DATA(CS2_MARK, PORT110_FN1),
1099 PINMUX_DATA(CS4_MARK, PORT111_FN1),
1100 PINMUX_DATA(WE1_MARK, PORT112_FN1),
1101 PINMUX_DATA(WE0_FWE_MARK, PORT113_FN1),
1102 PINMUX_DATA(RDWR_MARK, PORT114_FN1),
1103 PINMUX_DATA(RD_FSC_MARK, PORT115_FN1),
1104
1105 /* Port116 */
1106 PINMUX_DATA(A25_MARK, PORT116_FN1),
1107 PINMUX_DATA(MSIOF0_SS2_MARK, PORT116_FN2),
1108 PINMUX_DATA(MSIOF1_SS2_PORT116_MARK, PORT116_FN3, MSEL4CR_10_0),
1109 PINMUX_DATA(SCIFA3_SCK_PORT116_MARK, PORT116_FN4, MSEL5CR_8_0),
1110 PINMUX_DATA(GPO1_MARK, PORT116_FN5),
1111
1112 /* Port117 */
1113 PINMUX_DATA(A24_MARK, PORT117_FN1),
1114 PINMUX_DATA(MSIOF0_SS1_MARK, PORT117_FN2),
1115 PINMUX_DATA(MSIOF1_SS1_PORT117_MARK, PORT117_FN3, MSEL4CR_10_0),
1116 PINMUX_DATA(SCIFA3_CTS_PORT117_MARK, PORT117_FN4, MSEL5CR_8_0),
1117 PINMUX_DATA(GPO0_MARK, PORT117_FN5),
1118
1119 /* Port118 */
1120 PINMUX_DATA(A23_MARK, PORT118_FN1),
1121 PINMUX_DATA(MSIOF0_MCK1_MARK, PORT118_FN2),
1122 PINMUX_DATA(MSIOF1_RXD_PORT118_MARK, PORT118_FN3, MSEL4CR_10_0),
1123 PINMUX_DATA(GPI1_MARK, PORT118_FN5),
1124 PINMUX_DATA(IRQ9_PORT118_MARK, PORT118_FN0, MSEL1CR_9_0),
1125
1126 /* Port119 */
1127 PINMUX_DATA(A22_MARK, PORT119_FN1),
1128 PINMUX_DATA(MSIOF0_MCK0_MARK, PORT119_FN2),
1129 PINMUX_DATA(MSIOF1_TXD_PORT119_MARK, PORT119_FN3, MSEL4CR_10_0),
1130 PINMUX_DATA(GPI0_MARK, PORT119_FN5),
1131 PINMUX_DATA(IRQ8_MARK, PORT119_FN0),
1132
1133 /* Port120 */
1134 PINMUX_DATA(A21_MARK, PORT120_FN1),
1135 PINMUX_DATA(MSIOF0_RSYNC_MARK, PORT120_FN2),
1136 PINMUX_DATA(MSIOF1_TSYNC_PORT120_MARK, PORT120_FN3, MSEL4CR_10_0),
1137 PINMUX_DATA(IRQ7_PORT120_MARK, PORT120_FN0, MSEL1CR_7_1),
1138
1139 /* Port121 */
1140 PINMUX_DATA(A20_MARK, PORT121_FN1),
1141 PINMUX_DATA(MSIOF0_RSCK_MARK, PORT121_FN2),
1142 PINMUX_DATA(MSIOF1_TSCK_PORT121_MARK, PORT121_FN3, MSEL4CR_10_0),
1143 PINMUX_DATA(IRQ6_PORT121_MARK, PORT121_FN0, MSEL1CR_6_0),
1144
1145 /* Port122 */
1146 PINMUX_DATA(A19_MARK, PORT122_FN1),
1147 PINMUX_DATA(MSIOF0_RXD_MARK, PORT122_FN2),
1148
1149 /* Port123 */
1150 PINMUX_DATA(A18_MARK, PORT123_FN1),
1151 PINMUX_DATA(MSIOF0_TSCK_MARK, PORT123_FN2),
1152
1153 /* Port124 */
1154 PINMUX_DATA(A17_MARK, PORT124_FN1),
1155 PINMUX_DATA(MSIOF0_TSYNC_MARK, PORT124_FN2),
1156
1157 /* Port125 - Port141 Function */
1158 PINMUX_DATA(A16_MARK, PORT125_FN1),
1159 PINMUX_DATA(A15_MARK, PORT126_FN1),
1160 PINMUX_DATA(A14_MARK, PORT127_FN1),
1161 PINMUX_DATA(A13_MARK, PORT128_FN1),
1162 PINMUX_DATA(A12_MARK, PORT129_FN1),
1163 PINMUX_DATA(A11_MARK, PORT130_FN1),
1164 PINMUX_DATA(A10_MARK, PORT131_FN1),
1165 PINMUX_DATA(A9_MARK, PORT132_FN1),
1166 PINMUX_DATA(A8_MARK, PORT133_FN1),
1167 PINMUX_DATA(A7_MARK, PORT134_FN1),
1168 PINMUX_DATA(A6_MARK, PORT135_FN1),
1169 PINMUX_DATA(A5_FCDE_MARK, PORT136_FN1),
1170 PINMUX_DATA(A4_FOE_MARK, PORT137_FN1),
1171 PINMUX_DATA(A3_MARK, PORT138_FN1),
1172 PINMUX_DATA(A2_MARK, PORT139_FN1),
1173 PINMUX_DATA(A1_MARK, PORT140_FN1),
1174 PINMUX_DATA(CKO_MARK, PORT141_FN1),
1175
1176 /* Port142 - Port157 Function1 */
1177 PINMUX_DATA(D15_NAF15_MARK, PORT142_FN1),
1178 PINMUX_DATA(D14_NAF14_MARK, PORT143_FN1),
1179 PINMUX_DATA(D13_NAF13_MARK, PORT144_FN1),
1180 PINMUX_DATA(D12_NAF12_MARK, PORT145_FN1),
1181 PINMUX_DATA(D11_NAF11_MARK, PORT146_FN1),
1182 PINMUX_DATA(D10_NAF10_MARK, PORT147_FN1),
1183 PINMUX_DATA(D9_NAF9_MARK, PORT148_FN1),
1184 PINMUX_DATA(D8_NAF8_MARK, PORT149_FN1),
1185 PINMUX_DATA(D7_NAF7_MARK, PORT150_FN1),
1186 PINMUX_DATA(D6_NAF6_MARK, PORT151_FN1),
1187 PINMUX_DATA(D5_NAF5_MARK, PORT152_FN1),
1188 PINMUX_DATA(D4_NAF4_MARK, PORT153_FN1),
1189 PINMUX_DATA(D3_NAF3_MARK, PORT154_FN1),
1190 PINMUX_DATA(D2_NAF2_MARK, PORT155_FN1),
1191 PINMUX_DATA(D1_NAF1_MARK, PORT156_FN1),
1192 PINMUX_DATA(D0_NAF0_MARK, PORT157_FN1),
1193
1194 /* Port142 - Port149 Function3 */
1195 PINMUX_DATA(MMC1_D7_PORT142_MARK, PORT142_FN3, MSEL4CR_15_1),
1196 PINMUX_DATA(MMC1_D6_PORT143_MARK, PORT143_FN3, MSEL4CR_15_1),
1197 PINMUX_DATA(MMC1_D5_PORT144_MARK, PORT144_FN3, MSEL4CR_15_1),
1198 PINMUX_DATA(MMC1_D4_PORT145_MARK, PORT145_FN3, MSEL4CR_15_1),
1199 PINMUX_DATA(MMC1_D3_PORT146_MARK, PORT146_FN3, MSEL4CR_15_1),
1200 PINMUX_DATA(MMC1_D2_PORT147_MARK, PORT147_FN3, MSEL4CR_15_1),
1201 PINMUX_DATA(MMC1_D1_PORT148_MARK, PORT148_FN3, MSEL4CR_15_1),
1202 PINMUX_DATA(MMC1_D0_PORT149_MARK, PORT149_FN3, MSEL4CR_15_1),
1203
1204 /* Port158 */
1205 PINMUX_DATA(D31_MARK, PORT158_FN1),
1206 PINMUX_DATA(SCIFA3_SCK_PORT158_MARK, PORT158_FN2, MSEL5CR_8_1),
1207 PINMUX_DATA(RMII_REF125CK_MARK, PORT158_FN3),
1208 PINMUX_DATA(LCD0_D21_PORT158_MARK, PORT158_FN4, MSEL5CR_6_1),
1209 PINMUX_DATA(IRDA_FIRSEL_MARK, PORT158_FN5),
1210 PINMUX_DATA(IDE_D15_MARK, PORT158_FN6),
1211
1212 /* Port159 */
1213 PINMUX_DATA(D30_MARK, PORT159_FN1),
1214 PINMUX_DATA(SCIFA3_RXD_PORT159_MARK, PORT159_FN2, MSEL5CR_8_1),
1215 PINMUX_DATA(RMII_REF50CK_MARK, PORT159_FN3),
1216 PINMUX_DATA(LCD0_D23_PORT159_MARK, PORT159_FN4, MSEL5CR_6_1),
1217 PINMUX_DATA(IDE_D14_MARK, PORT159_FN6),
1218
1219 /* Port160 */
1220 PINMUX_DATA(D29_MARK, PORT160_FN1),
1221 PINMUX_DATA(SCIFA3_TXD_PORT160_MARK, PORT160_FN2, MSEL5CR_8_1),
1222 PINMUX_DATA(LCD0_D22_PORT160_MARK, PORT160_FN4, MSEL5CR_6_1),
1223 PINMUX_DATA(VIO1_HD_MARK, PORT160_FN5),
1224 PINMUX_DATA(IDE_D13_MARK, PORT160_FN6),
1225
1226 /* Port161 */
1227 PINMUX_DATA(D28_MARK, PORT161_FN1),
1228 PINMUX_DATA(SCIFA3_RTS_PORT161_MARK, PORT161_FN2, MSEL5CR_8_1),
1229 PINMUX_DATA(ET_RX_DV_MARK, PORT161_FN3),
1230 PINMUX_DATA(LCD0_D20_PORT161_MARK, PORT161_FN4, MSEL5CR_6_1),
1231 PINMUX_DATA(IRDA_IN_MARK, PORT161_FN5),
1232 PINMUX_DATA(IDE_D12_MARK, PORT161_FN6),
1233
1234 /* Port162 */
1235 PINMUX_DATA(D27_MARK, PORT162_FN1),
1236 PINMUX_DATA(SCIFA3_CTS_PORT162_MARK, PORT162_FN2, MSEL5CR_8_1),
1237 PINMUX_DATA(LCD0_D19_PORT162_MARK, PORT162_FN4, MSEL5CR_6_1),
1238 PINMUX_DATA(IRDA_OUT_MARK, PORT162_FN5),
1239 PINMUX_DATA(IDE_D11_MARK, PORT162_FN6),
1240
1241 /* Port163 */
1242 PINMUX_DATA(D26_MARK, PORT163_FN1),
1243 PINMUX_DATA(MSIOF2_SS2_MARK, PORT163_FN2),
1244 PINMUX_DATA(ET_COL_MARK, PORT163_FN3),
1245 PINMUX_DATA(LCD0_D18_PORT163_MARK, PORT163_FN4, MSEL5CR_6_1),
1246 PINMUX_DATA(IROUT_MARK, PORT163_FN5),
1247 PINMUX_DATA(IDE_D10_MARK, PORT163_FN6),
1248
1249 /* Port164 */
1250 PINMUX_DATA(D25_MARK, PORT164_FN1),
1251 PINMUX_DATA(MSIOF2_TSYNC_MARK, PORT164_FN2),
1252 PINMUX_DATA(ET_PHY_INT_MARK, PORT164_FN3),
1253 PINMUX_DATA(LCD0_RD_MARK, PORT164_FN4),
1254 PINMUX_DATA(IDE_D9_MARK, PORT164_FN6),
1255
1256 /* Port165 */
1257 PINMUX_DATA(D24_MARK, PORT165_FN1),
1258 PINMUX_DATA(MSIOF2_RXD_MARK, PORT165_FN2),
1259 PINMUX_DATA(LCD0_LCLK_PORT165_MARK, PORT165_FN4, MSEL5CR_6_1),
1260 PINMUX_DATA(IDE_D8_MARK, PORT165_FN6),
1261
1262 /* Port166 - Port171 Function1 */
1263 PINMUX_DATA(D21_MARK, PORT166_FN1),
1264 PINMUX_DATA(D20_MARK, PORT167_FN1),
1265 PINMUX_DATA(D19_MARK, PORT168_FN1),
1266 PINMUX_DATA(D18_MARK, PORT169_FN1),
1267 PINMUX_DATA(D17_MARK, PORT170_FN1),
1268 PINMUX_DATA(D16_MARK, PORT171_FN1),
1269
1270 /* Port166 - Port171 Function3 */
1271 PINMUX_DATA(ET_ETXD5_MARK, PORT166_FN3),
1272 PINMUX_DATA(ET_ETXD4_MARK, PORT167_FN3),
1273 PINMUX_DATA(ET_ETXD3_MARK, PORT168_FN3),
1274 PINMUX_DATA(ET_ETXD2_MARK, PORT169_FN3),
1275 PINMUX_DATA(ET_ETXD1_MARK, PORT170_FN3),
1276 PINMUX_DATA(ET_ETXD0_MARK, PORT171_FN3),
1277
1278 /* Port166 - Port171 Function6 */
1279 PINMUX_DATA(IDE_D5_MARK, PORT166_FN6),
1280 PINMUX_DATA(IDE_D4_MARK, PORT167_FN6),
1281 PINMUX_DATA(IDE_D3_MARK, PORT168_FN6),
1282 PINMUX_DATA(IDE_D2_MARK, PORT169_FN6),
1283 PINMUX_DATA(IDE_D1_MARK, PORT170_FN6),
1284 PINMUX_DATA(IDE_D0_MARK, PORT171_FN6),
1285
1286 /* Port167 - Port171 IRQ */
1287 PINMUX_DATA(IRQ31_PORT167_MARK, PORT167_FN0, MSEL1CR_31_0),
1288 PINMUX_DATA(IRQ27_PORT168_MARK, PORT168_FN0, MSEL1CR_27_0),
1289 PINMUX_DATA(IRQ28_PORT169_MARK, PORT169_FN0, MSEL1CR_28_0),
1290 PINMUX_DATA(IRQ29_PORT170_MARK, PORT170_FN0, MSEL1CR_29_0),
1291 PINMUX_DATA(IRQ30_PORT171_MARK, PORT171_FN0, MSEL1CR_30_0),
1292
1293 /* Port172 */
1294 PINMUX_DATA(D23_MARK, PORT172_FN1),
1295 PINMUX_DATA(SCIFB_RTS_PORT172_MARK, PORT172_FN2, MSEL5CR_17_1),
1296 PINMUX_DATA(ET_ETXD7_MARK, PORT172_FN3),
1297 PINMUX_DATA(IDE_D7_MARK, PORT172_FN6),
1298 PINMUX_DATA(IRQ4_PORT172_MARK, PORT172_FN0, MSEL1CR_4_1),
1299
1300 /* Port173 */
1301 PINMUX_DATA(D22_MARK, PORT173_FN1),
1302 PINMUX_DATA(SCIFB_CTS_PORT173_MARK, PORT173_FN2, MSEL5CR_17_1),
1303 PINMUX_DATA(ET_ETXD6_MARK, PORT173_FN3),
1304 PINMUX_DATA(IDE_D6_MARK, PORT173_FN6),
1305 PINMUX_DATA(IRQ6_PORT173_MARK, PORT173_FN0, MSEL1CR_6_1),
1306
1307 /* Port174 */
1308 PINMUX_DATA(A26_MARK, PORT174_FN1),
1309 PINMUX_DATA(MSIOF0_TXD_MARK, PORT174_FN2),
1310 PINMUX_DATA(ET_RX_CLK_MARK, PORT174_FN3),
1311 PINMUX_DATA(SCIFA3_RXD_PORT174_MARK, PORT174_FN4, MSEL5CR_8_0),
1312
1313 /* Port175 */
1314 PINMUX_DATA(A0_MARK, PORT175_FN1),
1315 PINMUX_DATA(BS_MARK, PORT175_FN2),
1316 PINMUX_DATA(ET_WOL_MARK, PORT175_FN3),
1317 PINMUX_DATA(SCIFA3_TXD_PORT175_MARK, PORT175_FN4, MSEL5CR_8_0),
1318
1319 /* Port176 */
1320 PINMUX_DATA(ET_GTX_CLK_MARK, PORT176_FN3),
1321
1322 /* Port177 */
1323 PINMUX_DATA(WAIT_PORT177_MARK, PORT177_FN1, MSEL5CR_2_0),
1324 PINMUX_DATA(ET_LINK_MARK, PORT177_FN3),
1325 PINMUX_DATA(IDE_IOWR_MARK, PORT177_FN6),
1326 PINMUX_DATA(SDHI2_WP_PORT177_MARK, PORT177_FN7, MSEL5CR_19_1),
1327
1328 /* Port178 */
1329 PINMUX_DATA(VIO0_D12_MARK, PORT178_FN1),
1330 PINMUX_DATA(VIO1_D4_MARK, PORT178_FN5),
1331 PINMUX_DATA(IDE_IORD_MARK, PORT178_FN6),
1332
1333 /* Port179 */
1334 PINMUX_DATA(VIO0_D11_MARK, PORT179_FN1),
1335 PINMUX_DATA(VIO1_D3_MARK, PORT179_FN5),
1336 PINMUX_DATA(IDE_IORDY_MARK, PORT179_FN6),
1337
1338 /* Port180 */
1339 PINMUX_DATA(VIO0_D10_MARK, PORT180_FN1),
1340 PINMUX_DATA(TPU0TO3_MARK, PORT180_FN4),
1341 PINMUX_DATA(VIO1_D2_MARK, PORT180_FN5),
1342 PINMUX_DATA(IDE_INT_MARK, PORT180_FN6),
1343 PINMUX_DATA(IRQ24_MARK, PORT180_FN0),
1344
1345 /* Port181 */
1346 PINMUX_DATA(VIO0_D9_MARK, PORT181_FN1),
1347 PINMUX_DATA(VIO1_D1_MARK, PORT181_FN5),
1348 PINMUX_DATA(IDE_RST_MARK, PORT181_FN6),
1349
1350 /* Port182 */
1351 PINMUX_DATA(VIO0_D8_MARK, PORT182_FN1),
1352 PINMUX_DATA(VIO1_D0_MARK, PORT182_FN5),
1353 PINMUX_DATA(IDE_DIRECTION_MARK, PORT182_FN6),
1354
1355 /* Port183 */
1356 PINMUX_DATA(DREQ1_MARK, PORT183_FN1),
1357 PINMUX_DATA(BBIF2_TXD2_PORT183_MARK, PORT183_FN2, MSEL5CR_0_1),
1358 PINMUX_DATA(ET_TX_EN_MARK, PORT183_FN3),
1359
1360 /* Port184 */
1361 PINMUX_DATA(DACK1_MARK, PORT184_FN1),
1362 PINMUX_DATA(BBIF2_TSYNC2_PORT184_MARK, PORT184_FN2, MSEL5CR_0_1),
1363 PINMUX_DATA(ET_TX_CLK_MARK, PORT184_FN3),
1364
1365 /* Port185 - Port192 Function1 */
1366 PINMUX_DATA(SCIFA1_SCK_MARK, PORT185_FN1),
1367 PINMUX_DATA(SCIFB_RTS_PORT186_MARK, PORT186_FN1, MSEL5CR_17_0),
1368 PINMUX_DATA(SCIFB_CTS_PORT187_MARK, PORT187_FN1, MSEL5CR_17_0),
1369 PINMUX_DATA(SCIFA0_SCK_MARK, PORT188_FN1),
1370 PINMUX_DATA(SCIFB_SCK_PORT190_MARK, PORT190_FN1, MSEL5CR_17_0),
1371 PINMUX_DATA(SCIFB_RXD_PORT191_MARK, PORT191_FN1, MSEL5CR_17_0),
1372 PINMUX_DATA(SCIFB_TXD_PORT192_MARK, PORT192_FN1, MSEL5CR_17_0),
1373
1374 /* Port185 - Port192 Function3 */
1375 PINMUX_DATA(ET_ERXD0_MARK, PORT185_FN3),
1376 PINMUX_DATA(ET_ERXD1_MARK, PORT186_FN3),
1377 PINMUX_DATA(ET_ERXD2_MARK, PORT187_FN3),
1378 PINMUX_DATA(ET_ERXD3_MARK, PORT188_FN3),
1379 PINMUX_DATA(ET_ERXD4_MARK, PORT189_FN3),
1380 PINMUX_DATA(ET_ERXD5_MARK, PORT190_FN3),
1381 PINMUX_DATA(ET_ERXD6_MARK, PORT191_FN3),
1382 PINMUX_DATA(ET_ERXD7_MARK, PORT192_FN3),
1383
1384 /* Port185 - Port192 Function6 */
1385 PINMUX_DATA(STP1_IPCLK_MARK, PORT185_FN6),
1386 PINMUX_DATA(STP1_IPD0_PORT186_MARK, PORT186_FN6, MSEL5CR_23_0),
1387 PINMUX_DATA(STP1_IPEN_PORT187_MARK, PORT187_FN6, MSEL5CR_23_0),
1388 PINMUX_DATA(STP1_IPSYNC_MARK, PORT188_FN6),
1389 PINMUX_DATA(STP0_IPCLK_MARK, PORT189_FN6),
1390 PINMUX_DATA(STP0_IPD0_MARK, PORT190_FN6),
1391 PINMUX_DATA(STP0_IPEN_MARK, PORT191_FN6),
1392 PINMUX_DATA(STP0_IPSYNC_MARK, PORT192_FN6),
1393
1394 /* Port193 */
1395 PINMUX_DATA(SCIFA0_CTS_MARK, PORT193_FN1),
1396 PINMUX_DATA(RMII_CRS_DV_MARK, PORT193_FN3),
1397 PINMUX_DATA(STP1_IPEN_PORT193_MARK, PORT193_FN6, MSEL5CR_23_1), /* ? */
1398 PINMUX_DATA(LCD1_D17_MARK, PORT193_FN7),
1399
1400 /* Port194 */
1401 PINMUX_DATA(SCIFA0_RTS_MARK, PORT194_FN1),
1402 PINMUX_DATA(RMII_RX_ER_MARK, PORT194_FN3),
1403 PINMUX_DATA(STP1_IPD0_PORT194_MARK, PORT194_FN6, MSEL5CR_23_1), /* ? */
1404 PINMUX_DATA(LCD1_D16_MARK, PORT194_FN7),
1405
1406 /* Port195 */
1407 PINMUX_DATA(SCIFA1_RXD_MARK, PORT195_FN1),
1408 PINMUX_DATA(RMII_RXD0_MARK, PORT195_FN3),
1409 PINMUX_DATA(STP1_IPD3_MARK, PORT195_FN6),
1410 PINMUX_DATA(LCD1_D15_MARK, PORT195_FN7),
1411
1412 /* Port196 */
1413 PINMUX_DATA(SCIFA1_TXD_MARK, PORT196_FN1),
1414 PINMUX_DATA(RMII_RXD1_MARK, PORT196_FN3),
1415 PINMUX_DATA(STP1_IPD2_MARK, PORT196_FN6),
1416 PINMUX_DATA(LCD1_D14_MARK, PORT196_FN7),
1417
1418 /* Port197 */
1419 PINMUX_DATA(SCIFA0_RXD_MARK, PORT197_FN1),
1420 PINMUX_DATA(VIO1_CLK_MARK, PORT197_FN5),
1421 PINMUX_DATA(STP1_IPD5_MARK, PORT197_FN6),
1422 PINMUX_DATA(LCD1_D19_MARK, PORT197_FN7),
1423
1424 /* Port198 */
1425 PINMUX_DATA(SCIFA0_TXD_MARK, PORT198_FN1),
1426 PINMUX_DATA(VIO1_VD_MARK, PORT198_FN5),
1427 PINMUX_DATA(STP1_IPD4_MARK, PORT198_FN6),
1428 PINMUX_DATA(LCD1_D18_MARK, PORT198_FN7),
1429
1430 /* Port199 */
1431 PINMUX_DATA(MEMC_NWE_MARK, PORT199_FN1),
1432 PINMUX_DATA(SCIFA2_SCK_PORT199_MARK, PORT199_FN2, MSEL5CR_7_1),
1433 PINMUX_DATA(RMII_TX_EN_MARK, PORT199_FN3),
1434 PINMUX_DATA(SIM_D_PORT199_MARK, PORT199_FN4, MSEL5CR_21_1),
1435 PINMUX_DATA(STP1_IPD1_MARK, PORT199_FN6),
1436 PINMUX_DATA(LCD1_D13_MARK, PORT199_FN7),
1437
1438 /* Port200 */
1439 PINMUX_DATA(MEMC_NOE_MARK, PORT200_FN1),
1440 PINMUX_DATA(SCIFA2_RXD_MARK, PORT200_FN2),
1441 PINMUX_DATA(RMII_TXD0_MARK, PORT200_FN3),
1442 PINMUX_DATA(STP0_IPD7_MARK, PORT200_FN6),
1443 PINMUX_DATA(LCD1_D12_MARK, PORT200_FN7),
1444
1445 /* Port201 */
1446 PINMUX_DATA(MEMC_WAIT_MARK, PORT201_FN1, MSEL4CR_6_0),
1447 PINMUX_DATA(MEMC_DREQ1_MARK, PORT201_FN1, MSEL4CR_6_1),
1448
1449 PINMUX_DATA(SCIFA2_TXD_MARK, PORT201_FN2),
1450 PINMUX_DATA(RMII_TXD1_MARK, PORT201_FN3),
1451 PINMUX_DATA(STP0_IPD6_MARK, PORT201_FN6),
1452 PINMUX_DATA(LCD1_D11_MARK, PORT201_FN7),
1453
1454 /* Port202 */
1455 PINMUX_DATA(MEMC_BUSCLK_MARK, PORT202_FN1, MSEL4CR_6_0),
1456 PINMUX_DATA(MEMC_A0_MARK, PORT202_FN1, MSEL4CR_6_1),
1457
1458 PINMUX_DATA(MSIOF1_SS2_PORT202_MARK, PORT202_FN2, MSEL4CR_10_1),
1459 PINMUX_DATA(RMII_MDC_MARK, PORT202_FN3),
1460 PINMUX_DATA(TPU0TO2_PORT202_MARK, PORT202_FN4, MSEL5CR_25_1),
1461 PINMUX_DATA(IDE_CS0_MARK, PORT202_FN6),
1462 PINMUX_DATA(SDHI2_CD_PORT202_MARK, PORT202_FN7, MSEL5CR_19_1),
1463 PINMUX_DATA(IRQ21_MARK, PORT202_FN0),
1464
1465 /* Port203 - Port208 Function1 */
1466 PINMUX_DATA(SDHI2_CLK_MARK, PORT203_FN1),
1467 PINMUX_DATA(SDHI2_CMD_MARK, PORT204_FN1),
1468 PINMUX_DATA(SDHI2_D0_MARK, PORT205_FN1),
1469 PINMUX_DATA(SDHI2_D1_MARK, PORT206_FN1),
1470 PINMUX_DATA(SDHI2_D2_MARK, PORT207_FN1),
1471 PINMUX_DATA(SDHI2_D3_MARK, PORT208_FN1),
1472
1473 /* Port203 - Port208 Function3 */
1474 PINMUX_DATA(ET_TX_ER_MARK, PORT203_FN3),
1475 PINMUX_DATA(ET_RX_ER_MARK, PORT204_FN3),
1476 PINMUX_DATA(ET_CRS_MARK, PORT205_FN3),
1477 PINMUX_DATA(ET_MDC_MARK, PORT206_FN3),
1478 PINMUX_DATA(ET_MDIO_MARK, PORT207_FN3),
1479 PINMUX_DATA(RMII_MDIO_MARK, PORT208_FN3),
1480
1481 /* Port203 - Port208 Function6 */
1482 PINMUX_DATA(IDE_A2_MARK, PORT203_FN6),
1483 PINMUX_DATA(IDE_A1_MARK, PORT204_FN6),
1484 PINMUX_DATA(IDE_A0_MARK, PORT205_FN6),
1485 PINMUX_DATA(IDE_IODACK_MARK, PORT206_FN6),
1486 PINMUX_DATA(IDE_IODREQ_MARK, PORT207_FN6),
1487 PINMUX_DATA(IDE_CS1_MARK, PORT208_FN6),
1488
1489 /* Port203 - Port208 Function7 */
1490 PINMUX_DATA(SCIFA4_TXD_PORT203_MARK, PORT203_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
1491 PINMUX_DATA(SCIFA4_RXD_PORT204_MARK, PORT204_FN7, MSEL5CR_12_0, MSEL5CR_11_1),
1492 PINMUX_DATA(SCIFA4_SCK_PORT205_MARK, PORT205_FN7, MSEL5CR_10_1),
1493 PINMUX_DATA(SCIFA5_SCK_PORT206_MARK, PORT206_FN7, MSEL5CR_13_1),
1494 PINMUX_DATA(SCIFA5_RXD_PORT207_MARK, PORT207_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
1495 PINMUX_DATA(SCIFA5_TXD_PORT208_MARK, PORT208_FN7, MSEL5CR_15_0, MSEL5CR_14_1),
1496
1497 /* Port209 */
1498 PINMUX_DATA(VBUS_MARK, PORT209_FN1),
1499 PINMUX_DATA(IRQ7_PORT209_MARK, PORT209_FN0, MSEL1CR_7_0),
1500
1501 /* Port210 */
1502 PINMUX_DATA(IRQ9_PORT210_MARK, PORT210_FN0, MSEL1CR_9_1),
1503 PINMUX_DATA(HDMI_HPD_MARK, PORT210_FN1),
1504
1505 /* Port211 */
1506 PINMUX_DATA(IRQ16_PORT211_MARK, PORT211_FN0, MSEL1CR_16_1),
1507 PINMUX_DATA(HDMI_CEC_MARK, PORT211_FN1),
1508
1509 /* SDENC */
1510 PINMUX_DATA(SDENC_CPG_MARK, MSEL4CR_19_0),
1511 PINMUX_DATA(SDENC_DV_CLKI_MARK, MSEL4CR_19_1),
1512
1513 /* SYSC */
1514 PINMUX_DATA(RESETP_PULLUP_MARK, MSEL4CR_4_0),
1515 PINMUX_DATA(RESETP_PLAIN_MARK, MSEL4CR_4_1),
1516
1517 /* DEBUG */
1518 PINMUX_DATA(EDEBGREQ_PULLDOWN_MARK, MSEL4CR_1_0),
1519 PINMUX_DATA(EDEBGREQ_PULLUP_MARK, MSEL4CR_1_1),
1520
1521 PINMUX_DATA(TRACEAUD_FROM_VIO_MARK, MSEL5CR_30_0, MSEL5CR_29_0),
1522 PINMUX_DATA(TRACEAUD_FROM_LCDC0_MARK, MSEL5CR_30_0, MSEL5CR_29_1),
1523 PINMUX_DATA(TRACEAUD_FROM_MEMC_MARK, MSEL5CR_30_1, MSEL5CR_29_0),
1524 };
1525
1526 #define __I (SH_PFC_PIN_CFG_INPUT)
1527 #define __O (SH_PFC_PIN_CFG_OUTPUT)
1528 #define __IO (SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1529 #define __PD (SH_PFC_PIN_CFG_PULL_DOWN)
1530 #define __PU (SH_PFC_PIN_CFG_PULL_UP)
1531 #define __PUD (SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1532
1533 #define R8A7740_PIN_I_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PD)
1534 #define R8A7740_PIN_I_PU(pin) SH_PFC_PIN_CFG(pin, __I | __PU)
1535 #define R8A7740_PIN_I_PU_PD(pin) SH_PFC_PIN_CFG(pin, __I | __PUD)
1536 #define R8A7740_PIN_IO(pin) SH_PFC_PIN_CFG(pin, __IO)
1537 #define R8A7740_PIN_IO_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PD)
1538 #define R8A7740_PIN_IO_PU(pin) SH_PFC_PIN_CFG(pin, __IO | __PU)
1539 #define R8A7740_PIN_IO_PU_PD(pin) SH_PFC_PIN_CFG(pin, __IO | __PUD)
1540 #define R8A7740_PIN_O(pin) SH_PFC_PIN_CFG(pin, __O)
1541 #define R8A7740_PIN_O_PU_PD(pin) SH_PFC_PIN_CFG(pin, __O | __PUD)
1542
1543 static const struct sh_pfc_pin pinmux_pins[] = {
1544 /* Table 56-1 (I/O and Pull U/D) */
1545 R8A7740_PIN_IO_PD(0), R8A7740_PIN_IO_PD(1),
1546 R8A7740_PIN_IO_PD(2), R8A7740_PIN_IO_PD(3),
1547 R8A7740_PIN_IO_PD(4), R8A7740_PIN_IO_PD(5),
1548 R8A7740_PIN_IO_PD(6), R8A7740_PIN_IO(7),
1549 R8A7740_PIN_IO(8), R8A7740_PIN_IO(9),
1550 R8A7740_PIN_IO_PD(10), R8A7740_PIN_IO_PD(11),
1551 R8A7740_PIN_IO_PD(12), R8A7740_PIN_IO_PU_PD(13),
1552 R8A7740_PIN_IO_PD(14), R8A7740_PIN_IO_PD(15),
1553 R8A7740_PIN_IO_PD(16), R8A7740_PIN_IO_PD(17),
1554 R8A7740_PIN_IO(18), R8A7740_PIN_IO_PU(19),
1555 R8A7740_PIN_IO_PU_PD(20), R8A7740_PIN_IO_PD(21),
1556 R8A7740_PIN_IO_PU_PD(22), R8A7740_PIN_IO(23),
1557 R8A7740_PIN_IO_PU(24), R8A7740_PIN_IO_PU(25),
1558 R8A7740_PIN_IO_PU(26), R8A7740_PIN_IO_PU(27),
1559 R8A7740_PIN_IO_PU(28), R8A7740_PIN_IO_PU(29),
1560 R8A7740_PIN_IO_PU(30), R8A7740_PIN_IO_PD(31),
1561 R8A7740_PIN_IO_PD(32), R8A7740_PIN_IO_PD(33),
1562 R8A7740_PIN_IO_PD(34), R8A7740_PIN_IO_PU(35),
1563 R8A7740_PIN_IO_PU(36), R8A7740_PIN_IO_PD(37),
1564 R8A7740_PIN_IO_PU(38), R8A7740_PIN_IO_PD(39),
1565 R8A7740_PIN_IO_PU_PD(40), R8A7740_PIN_IO_PD(41),
1566 R8A7740_PIN_IO_PD(42), R8A7740_PIN_IO_PU_PD(43),
1567 R8A7740_PIN_IO_PU_PD(44), R8A7740_PIN_IO_PU_PD(45),
1568 R8A7740_PIN_IO_PU_PD(46), R8A7740_PIN_IO_PU_PD(47),
1569 R8A7740_PIN_IO_PU_PD(48), R8A7740_PIN_IO_PU_PD(49),
1570 R8A7740_PIN_IO_PU_PD(50), R8A7740_PIN_IO_PD(51),
1571 R8A7740_PIN_IO_PD(52), R8A7740_PIN_IO_PD(53),
1572 R8A7740_PIN_IO_PD(54), R8A7740_PIN_IO_PU_PD(55),
1573 R8A7740_PIN_IO_PU_PD(56), R8A7740_PIN_IO_PU_PD(57),
1574 R8A7740_PIN_IO_PU_PD(58), R8A7740_PIN_IO_PU_PD(59),
1575 R8A7740_PIN_IO_PU_PD(60), R8A7740_PIN_IO_PD(61),
1576 R8A7740_PIN_IO_PD(62), R8A7740_PIN_IO_PD(63),
1577 R8A7740_PIN_IO_PD(64), R8A7740_PIN_IO_PD(65),
1578 R8A7740_PIN_IO_PU_PD(66), R8A7740_PIN_IO_PU_PD(67),
1579 R8A7740_PIN_IO_PU_PD(68), R8A7740_PIN_IO_PU_PD(69),
1580 R8A7740_PIN_IO_PU_PD(70), R8A7740_PIN_IO_PU_PD(71),
1581 R8A7740_PIN_IO_PU_PD(72), R8A7740_PIN_IO_PU_PD(73),
1582 R8A7740_PIN_IO_PU_PD(74), R8A7740_PIN_IO_PU_PD(75),
1583 R8A7740_PIN_IO_PU_PD(76), R8A7740_PIN_IO_PU_PD(77),
1584 R8A7740_PIN_IO_PU_PD(78), R8A7740_PIN_IO_PU_PD(79),
1585 R8A7740_PIN_IO_PU_PD(80), R8A7740_PIN_IO_PU_PD(81),
1586 R8A7740_PIN_IO(82), R8A7740_PIN_IO_PU_PD(83),
1587 R8A7740_PIN_IO(84), R8A7740_PIN_IO_PD(85),
1588 R8A7740_PIN_IO_PD(86), R8A7740_PIN_IO_PD(87),
1589 R8A7740_PIN_IO_PD(88), R8A7740_PIN_IO_PD(89),
1590 R8A7740_PIN_IO_PD(90), R8A7740_PIN_IO_PU_PD(91),
1591 R8A7740_PIN_IO_PU_PD(92), R8A7740_PIN_IO_PU_PD(93),
1592 R8A7740_PIN_IO_PU_PD(94), R8A7740_PIN_IO_PU_PD(95),
1593 R8A7740_PIN_IO_PU_PD(96), R8A7740_PIN_IO_PU_PD(97),
1594 R8A7740_PIN_IO_PU_PD(98), R8A7740_PIN_IO_PU_PD(99),
1595 R8A7740_PIN_IO_PU_PD(100), R8A7740_PIN_IO(101),
1596 R8A7740_PIN_IO_PU(102), R8A7740_PIN_IO_PU_PD(103),
1597 R8A7740_PIN_IO_PU(104), R8A7740_PIN_IO_PU(105),
1598 R8A7740_PIN_IO_PU_PD(106), R8A7740_PIN_IO(107),
1599 R8A7740_PIN_IO(108), R8A7740_PIN_IO(109),
1600 R8A7740_PIN_IO(110), R8A7740_PIN_IO(111),
1601 R8A7740_PIN_IO(112), R8A7740_PIN_IO(113),
1602 R8A7740_PIN_IO_PU_PD(114), R8A7740_PIN_IO(115),
1603 R8A7740_PIN_IO_PD(116), R8A7740_PIN_IO_PD(117),
1604 R8A7740_PIN_IO_PD(118), R8A7740_PIN_IO_PD(119),
1605 R8A7740_PIN_IO_PD(120), R8A7740_PIN_IO_PD(121),
1606 R8A7740_PIN_IO_PD(122), R8A7740_PIN_IO_PD(123),
1607 R8A7740_PIN_IO_PD(124), R8A7740_PIN_IO(125),
1608 R8A7740_PIN_IO(126), R8A7740_PIN_IO(127),
1609 R8A7740_PIN_IO(128), R8A7740_PIN_IO(129),
1610 R8A7740_PIN_IO(130), R8A7740_PIN_IO(131),
1611 R8A7740_PIN_IO(132), R8A7740_PIN_IO(133),
1612 R8A7740_PIN_IO(134), R8A7740_PIN_IO(135),
1613 R8A7740_PIN_IO(136), R8A7740_PIN_IO(137),
1614 R8A7740_PIN_IO(138), R8A7740_PIN_IO(139),
1615 R8A7740_PIN_IO(140), R8A7740_PIN_IO(141),
1616 R8A7740_PIN_IO_PU(142), R8A7740_PIN_IO_PU(143),
1617 R8A7740_PIN_IO_PU(144), R8A7740_PIN_IO_PU(145),
1618 R8A7740_PIN_IO_PU(146), R8A7740_PIN_IO_PU(147),
1619 R8A7740_PIN_IO_PU(148), R8A7740_PIN_IO_PU(149),
1620 R8A7740_PIN_IO_PU(150), R8A7740_PIN_IO_PU(151),
1621 R8A7740_PIN_IO_PU(152), R8A7740_PIN_IO_PU(153),
1622 R8A7740_PIN_IO_PU(154), R8A7740_PIN_IO_PU(155),
1623 R8A7740_PIN_IO_PU(156), R8A7740_PIN_IO_PU(157),
1624 R8A7740_PIN_IO_PD(158), R8A7740_PIN_IO_PD(159),
1625 R8A7740_PIN_IO_PU_PD(160), R8A7740_PIN_IO_PD(161),
1626 R8A7740_PIN_IO_PD(162), R8A7740_PIN_IO_PD(163),
1627 R8A7740_PIN_IO_PD(164), R8A7740_PIN_IO_PD(165),
1628 R8A7740_PIN_IO_PU(166), R8A7740_PIN_IO_PU(167),
1629 R8A7740_PIN_IO_PU(168), R8A7740_PIN_IO_PU(169),
1630 R8A7740_PIN_IO_PU(170), R8A7740_PIN_IO_PU(171),
1631 R8A7740_PIN_IO_PD(172), R8A7740_PIN_IO_PD(173),
1632 R8A7740_PIN_IO_PD(174), R8A7740_PIN_IO_PD(175),
1633 R8A7740_PIN_IO_PU(176), R8A7740_PIN_IO_PU_PD(177),
1634 R8A7740_PIN_IO_PU(178), R8A7740_PIN_IO_PD(179),
1635 R8A7740_PIN_IO_PD(180), R8A7740_PIN_IO_PU(181),
1636 R8A7740_PIN_IO_PU(182), R8A7740_PIN_IO(183),
1637 R8A7740_PIN_IO_PD(184), R8A7740_PIN_IO_PD(185),
1638 R8A7740_PIN_IO_PD(186), R8A7740_PIN_IO_PD(187),
1639 R8A7740_PIN_IO_PD(188), R8A7740_PIN_IO_PD(189),
1640 R8A7740_PIN_IO_PD(190), R8A7740_PIN_IO_PD(191),
1641 R8A7740_PIN_IO_PD(192), R8A7740_PIN_IO_PU_PD(193),
1642 R8A7740_PIN_IO_PU_PD(194), R8A7740_PIN_IO_PD(195),
1643 R8A7740_PIN_IO_PU_PD(196), R8A7740_PIN_IO_PD(197),
1644 R8A7740_PIN_IO_PU_PD(198), R8A7740_PIN_IO_PU_PD(199),
1645 R8A7740_PIN_IO_PU_PD(200), R8A7740_PIN_IO_PU(201),
1646 R8A7740_PIN_IO_PU_PD(202), R8A7740_PIN_IO(203),
1647 R8A7740_PIN_IO_PU_PD(204), R8A7740_PIN_IO_PU_PD(205),
1648 R8A7740_PIN_IO_PU_PD(206), R8A7740_PIN_IO_PU_PD(207),
1649 R8A7740_PIN_IO_PU_PD(208), R8A7740_PIN_IO_PD(209),
1650 R8A7740_PIN_IO_PD(210), R8A7740_PIN_IO_PD(211),
1651 };
1652
1653 /* - BSC -------------------------------------------------------------------- */
1654 static const unsigned int bsc_data8_pins[] = {
1655 /* D[0:7] */
1656 157, 156, 155, 154, 153, 152, 151, 150,
1657 };
1658 static const unsigned int bsc_data8_mux[] = {
1659 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1660 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1661 };
1662 static const unsigned int bsc_data16_pins[] = {
1663 /* D[0:15] */
1664 157, 156, 155, 154, 153, 152, 151, 150,
1665 149, 148, 147, 146, 145, 144, 143, 142,
1666 };
1667 static const unsigned int bsc_data16_mux[] = {
1668 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1669 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1670 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1671 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1672 };
1673 static const unsigned int bsc_data32_pins[] = {
1674 /* D[0:31] */
1675 157, 156, 155, 154, 153, 152, 151, 150,
1676 149, 148, 147, 146, 145, 144, 143, 142,
1677 171, 170, 169, 168, 167, 166, 173, 172,
1678 165, 164, 163, 162, 161, 160, 159, 158,
1679 };
1680 static const unsigned int bsc_data32_mux[] = {
1681 D0_NAF0_MARK, D1_NAF1_MARK, D2_NAF2_MARK, D3_NAF3_MARK,
1682 D4_NAF4_MARK, D5_NAF5_MARK, D6_NAF6_MARK, D7_NAF7_MARK,
1683 D8_NAF8_MARK, D9_NAF9_MARK, D10_NAF10_MARK, D11_NAF11_MARK,
1684 D12_NAF12_MARK, D13_NAF13_MARK, D14_NAF14_MARK, D15_NAF15_MARK,
1685 D16_MARK, D17_MARK, D18_MARK, D19_MARK,
1686 D20_MARK, D21_MARK, D22_MARK, D23_MARK,
1687 D24_MARK, D25_MARK, D26_MARK, D27_MARK,
1688 D28_MARK, D29_MARK, D30_MARK, D31_MARK,
1689 };
1690 static const unsigned int bsc_cs0_pins[] = {
1691 /* CS */
1692 109,
1693 };
1694 static const unsigned int bsc_cs0_mux[] = {
1695 CS0_MARK,
1696 };
1697 static const unsigned int bsc_cs2_pins[] = {
1698 /* CS */
1699 110,
1700 };
1701 static const unsigned int bsc_cs2_mux[] = {
1702 CS2_MARK,
1703 };
1704 static const unsigned int bsc_cs4_pins[] = {
1705 /* CS */
1706 111,
1707 };
1708 static const unsigned int bsc_cs4_mux[] = {
1709 CS4_MARK,
1710 };
1711 static const unsigned int bsc_cs5a_0_pins[] = {
1712 /* CS */
1713 105,
1714 };
1715 static const unsigned int bsc_cs5a_0_mux[] = {
1716 CS5A_PORT105_MARK,
1717 };
1718 static const unsigned int bsc_cs5a_1_pins[] = {
1719 /* CS */
1720 19,
1721 };
1722 static const unsigned int bsc_cs5a_1_mux[] = {
1723 CS5A_PORT19_MARK,
1724 };
1725 static const unsigned int bsc_cs5b_pins[] = {
1726 /* CS */
1727 103,
1728 };
1729 static const unsigned int bsc_cs5b_mux[] = {
1730 CS5B_MARK,
1731 };
1732 static const unsigned int bsc_cs6a_pins[] = {
1733 /* CS */
1734 104,
1735 };
1736 static const unsigned int bsc_cs6a_mux[] = {
1737 CS6A_MARK,
1738 };
1739 static const unsigned int bsc_rd_we8_pins[] = {
1740 /* RD, WE[0] */
1741 115, 113,
1742 };
1743 static const unsigned int bsc_rd_we8_mux[] = {
1744 RD_FSC_MARK, WE0_FWE_MARK,
1745 };
1746 static const unsigned int bsc_rd_we16_pins[] = {
1747 /* RD, WE[0:1] */
1748 115, 113, 112,
1749 };
1750 static const unsigned int bsc_rd_we16_mux[] = {
1751 RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK,
1752 };
1753 static const unsigned int bsc_rd_we32_pins[] = {
1754 /* RD, WE[0:3] */
1755 115, 113, 112, 108, 107,
1756 };
1757 static const unsigned int bsc_rd_we32_mux[] = {
1758 RD_FSC_MARK, WE0_FWE_MARK, WE1_MARK, WE2_ICIORD_MARK, WE3_ICIOWR_MARK,
1759 };
1760 static const unsigned int bsc_bs_pins[] = {
1761 /* BS */
1762 175,
1763 };
1764 static const unsigned int bsc_bs_mux[] = {
1765 BS_MARK,
1766 };
1767 static const unsigned int bsc_rdwr_pins[] = {
1768 /* RDWR */
1769 114,
1770 };
1771 static const unsigned int bsc_rdwr_mux[] = {
1772 RDWR_MARK,
1773 };
1774 /* - CEU0 ------------------------------------------------------------------- */
1775 static const unsigned int ceu0_data_0_7_pins[] = {
1776 /* D[0:7] */
1777 34, 33, 32, 31, 30, 29, 28, 27,
1778 };
1779 static const unsigned int ceu0_data_0_7_mux[] = {
1780 VIO0_D0_MARK, VIO0_D1_MARK, VIO0_D2_MARK, VIO0_D3_MARK,
1781 VIO0_D4_MARK, VIO0_D5_MARK, VIO0_D6_MARK, VIO0_D7_MARK,
1782 };
1783 static const unsigned int ceu0_data_8_15_0_pins[] = {
1784 /* D[8:15] */
1785 182, 181, 180, 179, 178, 26, 25, 24,
1786 };
1787 static const unsigned int ceu0_data_8_15_0_mux[] = {
1788 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
1789 VIO0_D12_MARK, VIO0_D13_PORT26_MARK, VIO0_D14_PORT25_MARK,
1790 VIO0_D15_PORT24_MARK,
1791 };
1792 static const unsigned int ceu0_data_8_15_1_pins[] = {
1793 /* D[8:15] */
1794 182, 181, 180, 179, 178, 22, 95, 96,
1795 };
1796 static const unsigned int ceu0_data_8_15_1_mux[] = {
1797 VIO0_D8_MARK, VIO0_D9_MARK, VIO0_D10_MARK, VIO0_D11_MARK,
1798 VIO0_D12_MARK, VIO0_D13_PORT22_MARK, VIO0_D14_PORT95_MARK,
1799 VIO0_D15_PORT96_MARK,
1800 };
1801 static const unsigned int ceu0_clk_0_pins[] = {
1802 /* CKO */
1803 36,
1804 };
1805 static const unsigned int ceu0_clk_0_mux[] = {
1806 VIO_CKO_MARK,
1807 };
1808 static const unsigned int ceu0_clk_1_pins[] = {
1809 /* CKO */
1810 14,
1811 };
1812 static const unsigned int ceu0_clk_1_mux[] = {
1813 VIO_CKO1_MARK,
1814 };
1815 static const unsigned int ceu0_clk_2_pins[] = {
1816 /* CKO */
1817 15,
1818 };
1819 static const unsigned int ceu0_clk_2_mux[] = {
1820 VIO_CKO2_MARK,
1821 };
1822 static const unsigned int ceu0_sync_pins[] = {
1823 /* CLK, VD, HD */
1824 35, 39, 37,
1825 };
1826 static const unsigned int ceu0_sync_mux[] = {
1827 VIO0_CLK_MARK, VIO0_VD_MARK, VIO0_HD_MARK,
1828 };
1829 static const unsigned int ceu0_field_pins[] = {
1830 /* FIELD */
1831 38,
1832 };
1833 static const unsigned int ceu0_field_mux[] = {
1834 VIO0_FIELD_MARK,
1835 };
1836 /* - CEU1 ------------------------------------------------------------------- */
1837 static const unsigned int ceu1_data_pins[] = {
1838 /* D[0:7] */
1839 182, 181, 180, 179, 178, 26, 25, 24,
1840 };
1841 static const unsigned int ceu1_data_mux[] = {
1842 VIO1_D0_MARK, VIO1_D1_MARK, VIO1_D2_MARK, VIO1_D3_MARK,
1843 VIO1_D4_MARK, VIO1_D5_MARK, VIO1_D6_MARK, VIO1_D7_MARK,
1844 };
1845 static const unsigned int ceu1_clk_pins[] = {
1846 /* CKO */
1847 23,
1848 };
1849 static const unsigned int ceu1_clk_mux[] = {
1850 VIO_CKO_1_MARK,
1851 };
1852 static const unsigned int ceu1_sync_pins[] = {
1853 /* CLK, VD, HD */
1854 197, 198, 160,
1855 };
1856 static const unsigned int ceu1_sync_mux[] = {
1857 VIO1_CLK_MARK, VIO1_VD_MARK, VIO1_HD_MARK,
1858 };
1859 static const unsigned int ceu1_field_pins[] = {
1860 /* FIELD */
1861 21,
1862 };
1863 static const unsigned int ceu1_field_mux[] = {
1864 VIO1_FIELD_MARK,
1865 };
1866 /* - FSIA ------------------------------------------------------------------- */
1867 static const unsigned int fsia_mclk_in_pins[] = {
1868 /* CK */
1869 11,
1870 };
1871 static const unsigned int fsia_mclk_in_mux[] = {
1872 FSIACK_MARK,
1873 };
1874 static const unsigned int fsia_mclk_out_pins[] = {
1875 /* OMC */
1876 10,
1877 };
1878 static const unsigned int fsia_mclk_out_mux[] = {
1879 FSIAOMC_MARK,
1880 };
1881 static const unsigned int fsia_sclk_in_pins[] = {
1882 /* ILR, IBT */
1883 12, 13,
1884 };
1885 static const unsigned int fsia_sclk_in_mux[] = {
1886 FSIAILR_MARK, FSIAIBT_MARK,
1887 };
1888 static const unsigned int fsia_sclk_out_pins[] = {
1889 /* OLR, OBT */
1890 7, 8,
1891 };
1892 static const unsigned int fsia_sclk_out_mux[] = {
1893 FSIAOLR_MARK, FSIAOBT_MARK,
1894 };
1895 static const unsigned int fsia_data_in_0_pins[] = {
1896 /* ISLD */
1897 0,
1898 };
1899 static const unsigned int fsia_data_in_0_mux[] = {
1900 FSIAISLD_PORT0_MARK,
1901 };
1902 static const unsigned int fsia_data_in_1_pins[] = {
1903 /* ISLD */
1904 5,
1905 };
1906 static const unsigned int fsia_data_in_1_mux[] = {
1907 FSIAISLD_PORT5_MARK,
1908 };
1909 static const unsigned int fsia_data_out_0_pins[] = {
1910 /* OSLD */
1911 9,
1912 };
1913 static const unsigned int fsia_data_out_0_mux[] = {
1914 FSIAOSLD_MARK,
1915 };
1916 static const unsigned int fsia_data_out_1_pins[] = {
1917 /* OSLD */
1918 0,
1919 };
1920 static const unsigned int fsia_data_out_1_mux[] = {
1921 FSIAOSLD1_MARK,
1922 };
1923 static const unsigned int fsia_data_out_2_pins[] = {
1924 /* OSLD */
1925 1,
1926 };
1927 static const unsigned int fsia_data_out_2_mux[] = {
1928 FSIAOSLD2_MARK,
1929 };
1930 static const unsigned int fsia_spdif_0_pins[] = {
1931 /* SPDIF */
1932 9,
1933 };
1934 static const unsigned int fsia_spdif_0_mux[] = {
1935 FSIASPDIF_PORT9_MARK,
1936 };
1937 static const unsigned int fsia_spdif_1_pins[] = {
1938 /* SPDIF */
1939 18,
1940 };
1941 static const unsigned int fsia_spdif_1_mux[] = {
1942 FSIASPDIF_PORT18_MARK,
1943 };
1944 /* - FSIB ------------------------------------------------------------------- */
1945 static const unsigned int fsib_mclk_in_pins[] = {
1946 /* CK */
1947 11,
1948 };
1949 static const unsigned int fsib_mclk_in_mux[] = {
1950 FSIBCK_MARK,
1951 };
1952 /* - GETHER ----------------------------------------------------------------- */
1953 static const unsigned int gether_rmii_pins[] = {
1954 /* RXD[0:1], RX_ER, CRS_DV, TXD[0:1], TX_EN, REF_CLK, MDC, MDIO */
1955 195, 196, 194, 193, 200, 201, 199, 159, 202, 208,
1956 };
1957 static const unsigned int gether_rmii_mux[] = {
1958 RMII_RXD0_MARK, RMII_RXD1_MARK, RMII_RX_ER_MARK, RMII_CRS_DV_MARK,
1959 RMII_TXD0_MARK, RMII_TXD1_MARK, RMII_TX_EN_MARK, RMII_REF50CK_MARK,
1960 RMII_MDC_MARK, RMII_MDIO_MARK,
1961 };
1962 static const unsigned int gether_mii_pins[] = {
1963 /* RXD[0:3], RX_CLK, RX_DV, RX_ER
1964 * TXD[0:3], TX_CLK, TX_EN, TX_ER
1965 * CRS, COL, MDC, MDIO,
1966 */
1967 185, 186, 187, 188, 174, 161, 204,
1968 171, 170, 169, 168, 184, 183, 203,
1969 205, 163, 206, 207,
1970 };
1971 static const unsigned int gether_mii_mux[] = {
1972 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
1973 ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
1974 ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
1975 ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
1976 ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
1977 };
1978 static const unsigned int gether_gmii_pins[] = {
1979 /* RXD[0:7], RX_CLK, RX_DV, RX_ER
1980 * TXD[0:7], GTX_CLK, TX_CLK, TX_EN, TX_ER
1981 * CRS, COL, MDC, MDIO, REF125CK_MARK,
1982 */
1983 185, 186, 187, 188, 189, 190, 191, 192, 174, 161, 204,
1984 171, 170, 169, 168, 167, 166, 173, 172, 176, 184, 183, 203,
1985 205, 163, 206, 207,
1986 };
1987 static const unsigned int gether_gmii_mux[] = {
1988 ET_ERXD0_MARK, ET_ERXD1_MARK, ET_ERXD2_MARK, ET_ERXD3_MARK,
1989 ET_ERXD4_MARK, ET_ERXD5_MARK, ET_ERXD6_MARK, ET_ERXD7_MARK,
1990 ET_RX_CLK_MARK, ET_RX_DV_MARK, ET_RX_ER_MARK,
1991 ET_ETXD0_MARK, ET_ETXD1_MARK, ET_ETXD2_MARK, ET_ETXD3_MARK,
1992 ET_ETXD4_MARK, ET_ETXD5_MARK, ET_ETXD6_MARK, ET_ETXD7_MARK,
1993 ET_GTX_CLK_MARK, ET_TX_CLK_MARK, ET_TX_EN_MARK, ET_TX_ER_MARK,
1994 ET_CRS_MARK, ET_COL_MARK, ET_MDC_MARK, ET_MDIO_MARK,
1995 RMII_REF125CK_MARK,
1996 };
1997 static const unsigned int gether_int_pins[] = {
1998 /* PHY_INT */
1999 164,
2000 };
2001 static const unsigned int gether_int_mux[] = {
2002 ET_PHY_INT_MARK,
2003 };
2004 static const unsigned int gether_link_pins[] = {
2005 /* LINK */
2006 177,
2007 };
2008 static const unsigned int gether_link_mux[] = {
2009 ET_LINK_MARK,
2010 };
2011 static const unsigned int gether_wol_pins[] = {
2012 /* WOL */
2013 175,
2014 };
2015 static const unsigned int gether_wol_mux[] = {
2016 ET_WOL_MARK,
2017 };
2018 /* - HDMI ------------------------------------------------------------------- */
2019 static const unsigned int hdmi_pins[] = {
2020 /* HPD, CEC */
2021 210, 211,
2022 };
2023 static const unsigned int hdmi_mux[] = {
2024 HDMI_HPD_MARK, HDMI_CEC_MARK,
2025 };
2026 /* - INTC ------------------------------------------------------------------- */
2027 IRQC_PINS_MUX(0, 0, 2);
2028 IRQC_PINS_MUX(0, 1, 13);
2029 IRQC_PIN_MUX(1, 20);
2030 IRQC_PINS_MUX(2, 0, 11);
2031 IRQC_PINS_MUX(2, 1, 12);
2032 IRQC_PINS_MUX(3, 0, 10);
2033 IRQC_PINS_MUX(3, 1, 14);
2034 IRQC_PINS_MUX(4, 0, 15);
2035 IRQC_PINS_MUX(4, 1, 172);
2036 IRQC_PINS_MUX(5, 0, 0);
2037 IRQC_PINS_MUX(5, 1, 1);
2038 IRQC_PINS_MUX(6, 0, 121);
2039 IRQC_PINS_MUX(6, 1, 173);
2040 IRQC_PINS_MUX(7, 0, 120);
2041 IRQC_PINS_MUX(7, 1, 209);
2042 IRQC_PIN_MUX(8, 119);
2043 IRQC_PINS_MUX(9, 0, 118);
2044 IRQC_PINS_MUX(9, 1, 210);
2045 IRQC_PIN_MUX(10, 19);
2046 IRQC_PIN_MUX(11, 104);
2047 IRQC_PINS_MUX(12, 0, 42);
2048 IRQC_PINS_MUX(12, 1, 97);
2049 IRQC_PINS_MUX(13, 0, 64);
2050 IRQC_PINS_MUX(13, 1, 98);
2051 IRQC_PINS_MUX(14, 0, 63);
2052 IRQC_PINS_MUX(14, 1, 99);
2053 IRQC_PINS_MUX(15, 0, 62);
2054 IRQC_PINS_MUX(15, 1, 100);
2055 IRQC_PINS_MUX(16, 0, 68);
2056 IRQC_PINS_MUX(16, 1, 211);
2057 IRQC_PIN_MUX(17, 69);
2058 IRQC_PIN_MUX(18, 70);
2059 IRQC_PIN_MUX(19, 71);
2060 IRQC_PIN_MUX(20, 67);
2061 IRQC_PIN_MUX(21, 202);
2062 IRQC_PIN_MUX(22, 95);
2063 IRQC_PIN_MUX(23, 96);
2064 IRQC_PIN_MUX(24, 180);
2065 IRQC_PIN_MUX(25, 38);
2066 IRQC_PINS_MUX(26, 0, 58);
2067 IRQC_PINS_MUX(26, 1, 81);
2068 IRQC_PINS_MUX(27, 0, 57);
2069 IRQC_PINS_MUX(27, 1, 168);
2070 IRQC_PINS_MUX(28, 0, 56);
2071 IRQC_PINS_MUX(28, 1, 169);
2072 IRQC_PINS_MUX(29, 0, 50);
2073 IRQC_PINS_MUX(29, 1, 170);
2074 IRQC_PINS_MUX(30, 0, 49);
2075 IRQC_PINS_MUX(30, 1, 171);
2076 IRQC_PINS_MUX(31, 0, 41);
2077 IRQC_PINS_MUX(31, 1, 167);
2078
2079 /* - LCD0 ------------------------------------------------------------------- */
2080 static const unsigned int lcd0_data8_pins[] = {
2081 /* D[0:7] */
2082 58, 57, 56, 55, 54, 53, 52, 51,
2083 };
2084 static const unsigned int lcd0_data8_mux[] = {
2085 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2086 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2087 };
2088 static const unsigned int lcd0_data9_pins[] = {
2089 /* D[0:8] */
2090 58, 57, 56, 55, 54, 53, 52, 51,
2091 50,
2092 };
2093 static const unsigned int lcd0_data9_mux[] = {
2094 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2095 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2096 LCD0_D8_MARK,
2097 };
2098 static const unsigned int lcd0_data12_pins[] = {
2099 /* D[0:11] */
2100 58, 57, 56, 55, 54, 53, 52, 51,
2101 50, 49, 48, 47,
2102 };
2103 static const unsigned int lcd0_data12_mux[] = {
2104 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2105 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2106 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2107 };
2108 static const unsigned int lcd0_data16_pins[] = {
2109 /* D[0:15] */
2110 58, 57, 56, 55, 54, 53, 52, 51,
2111 50, 49, 48, 47, 46, 45, 44, 43,
2112 };
2113 static const unsigned int lcd0_data16_mux[] = {
2114 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2115 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2116 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2117 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2118 };
2119 static const unsigned int lcd0_data18_pins[] = {
2120 /* D[0:17] */
2121 58, 57, 56, 55, 54, 53, 52, 51,
2122 50, 49, 48, 47, 46, 45, 44, 43,
2123 42, 41,
2124 };
2125 static const unsigned int lcd0_data18_mux[] = {
2126 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2127 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2128 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2129 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2130 LCD0_D16_MARK, LCD0_D17_MARK,
2131 };
2132 static const unsigned int lcd0_data24_0_pins[] = {
2133 /* D[0:23] */
2134 58, 57, 56, 55, 54, 53, 52, 51,
2135 50, 49, 48, 47, 46, 45, 44, 43,
2136 42, 41, 40, 4, 3, 2, 0, 1,
2137 };
2138 static const unsigned int lcd0_data24_0_mux[] = {
2139 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2140 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2141 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2142 LCD0_D12_MARK, LCD0_D13_MARK, LCD0_D14_MARK, LCD0_D15_MARK,
2143 LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT40_MARK, LCD0_D19_PORT4_MARK,
2144 LCD0_D20_PORT3_MARK, LCD0_D21_PORT2_MARK, LCD0_D22_PORT0_MARK,
2145 LCD0_D23_PORT1_MARK,
2146 };
2147 static const unsigned int lcd0_data24_1_pins[] = {
2148 /* D[0:23] */
2149 58, 57, 56, 55, 54, 53, 52, 51,
2150 50, 49, 48, 47, 46, 45, 44, 43,
2151 42, 41, 163, 162, 161, 158, 160, 159,
2152 };
2153 static const unsigned int lcd0_data24_1_mux[] = {
2154 LCD0_D0_MARK, LCD0_D1_MARK, LCD0_D2_MARK, LCD0_D3_MARK,
2155 LCD0_D4_MARK, LCD0_D5_MARK, LCD0_D6_MARK, LCD0_D7_MARK,
2156 LCD0_D8_MARK, LCD0_D9_MARK, LCD0_D10_MARK, LCD0_D11_MARK,
2157 LCD0_D16_MARK, LCD0_D17_MARK, LCD0_D18_PORT163_MARK,
2158 LCD0_D19_PORT162_MARK, LCD0_D20_PORT161_MARK, LCD0_D21_PORT158_MARK,
2159 LCD0_D22_PORT160_MARK, LCD0_D23_PORT159_MARK,
2160 };
2161 static const unsigned int lcd0_display_pins[] = {
2162 /* DON, VCPWC, VEPWC */
2163 61, 59, 60,
2164 };
2165 static const unsigned int lcd0_display_mux[] = {
2166 LCD0_DON_MARK, LCD0_VCPWC_MARK, LCD0_VEPWC_MARK,
2167 };
2168 static const unsigned int lcd0_lclk_0_pins[] = {
2169 /* LCLK */
2170 102,
2171 };
2172 static const unsigned int lcd0_lclk_0_mux[] = {
2173 LCD0_LCLK_PORT102_MARK,
2174 };
2175 static const unsigned int lcd0_lclk_1_pins[] = {
2176 /* LCLK */
2177 165,
2178 };
2179 static const unsigned int lcd0_lclk_1_mux[] = {
2180 LCD0_LCLK_PORT165_MARK,
2181 };
2182 static const unsigned int lcd0_sync_pins[] = {
2183 /* VSYN, HSYN, DCK, DISP */
2184 63, 64, 62, 65,
2185 };
2186 static const unsigned int lcd0_sync_mux[] = {
2187 LCD0_VSYN_MARK, LCD0_HSYN_MARK, LCD0_DCK_MARK, LCD0_DISP_MARK,
2188 };
2189 static const unsigned int lcd0_sys_pins[] = {
2190 /* CS, WR, RD, RS */
2191 64, 62, 164, 65,
2192 };
2193 static const unsigned int lcd0_sys_mux[] = {
2194 LCD0_CS_MARK, LCD0_WR_MARK, LCD0_RD_MARK, LCD0_RS_MARK,
2195 };
2196 /* - LCD1 ------------------------------------------------------------------- */
2197 static const unsigned int lcd1_data8_pins[] = {
2198 /* D[0:7] */
2199 4, 3, 2, 1, 0, 91, 92, 23,
2200 };
2201 static const unsigned int lcd1_data8_mux[] = {
2202 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2203 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2204 };
2205 static const unsigned int lcd1_data9_pins[] = {
2206 /* D[0:8] */
2207 4, 3, 2, 1, 0, 91, 92, 23,
2208 93,
2209 };
2210 static const unsigned int lcd1_data9_mux[] = {
2211 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2212 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2213 LCD1_D8_MARK,
2214 };
2215 static const unsigned int lcd1_data12_pins[] = {
2216 /* D[0:11] */
2217 4, 3, 2, 1, 0, 91, 92, 23,
2218 93, 94, 21, 201,
2219 };
2220 static const unsigned int lcd1_data12_mux[] = {
2221 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2222 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2223 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2224 };
2225 static const unsigned int lcd1_data16_pins[] = {
2226 /* D[0:15] */
2227 4, 3, 2, 1, 0, 91, 92, 23,
2228 93, 94, 21, 201, 200, 199, 196, 195,
2229 };
2230 static const unsigned int lcd1_data16_mux[] = {
2231 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2232 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2233 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2234 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2235 };
2236 static const unsigned int lcd1_data18_pins[] = {
2237 /* D[0:17] */
2238 4, 3, 2, 1, 0, 91, 92, 23,
2239 93, 94, 21, 201, 200, 199, 196, 195,
2240 194, 193,
2241 };
2242 static const unsigned int lcd1_data18_mux[] = {
2243 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2244 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2245 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2246 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2247 LCD1_D16_MARK, LCD1_D17_MARK,
2248 };
2249 static const unsigned int lcd1_data24_pins[] = {
2250 /* D[0:23] */
2251 4, 3, 2, 1, 0, 91, 92, 23,
2252 93, 94, 21, 201, 200, 199, 196, 195,
2253 194, 193, 198, 197, 75, 74, 15, 14,
2254 };
2255 static const unsigned int lcd1_data24_mux[] = {
2256 LCD1_D0_MARK, LCD1_D1_MARK, LCD1_D2_MARK, LCD1_D3_MARK,
2257 LCD1_D4_MARK, LCD1_D5_MARK, LCD1_D6_MARK, LCD1_D7_MARK,
2258 LCD1_D8_MARK, LCD1_D9_MARK, LCD1_D10_MARK, LCD1_D11_MARK,
2259 LCD1_D12_MARK, LCD1_D13_MARK, LCD1_D14_MARK, LCD1_D15_MARK,
2260 LCD1_D16_MARK, LCD1_D17_MARK, LCD1_D18_MARK, LCD1_D19_MARK,
2261 LCD1_D20_MARK, LCD1_D21_MARK, LCD1_D22_MARK, LCD1_D23_MARK,
2262 };
2263 static const unsigned int lcd1_display_pins[] = {
2264 /* DON, VCPWC, VEPWC */
2265 100, 5, 6,
2266 };
2267 static const unsigned int lcd1_display_mux[] = {
2268 LCD1_DON_MARK, LCD1_VCPWC_MARK, LCD1_VEPWC_MARK,
2269 };
2270 static const unsigned int lcd1_lclk_pins[] = {
2271 /* LCLK */
2272 40,
2273 };
2274 static const unsigned int lcd1_lclk_mux[] = {
2275 LCD1_LCLK_MARK,
2276 };
2277 static const unsigned int lcd1_sync_pins[] = {
2278 /* VSYN, HSYN, DCK, DISP */
2279 98, 97, 99, 12,
2280 };
2281 static const unsigned int lcd1_sync_mux[] = {
2282 LCD1_VSYN_MARK, LCD1_HSYN_MARK, LCD1_DCK_MARK, LCD1_DISP_MARK,
2283 };
2284 static const unsigned int lcd1_sys_pins[] = {
2285 /* CS, WR, RD, RS */
2286 97, 99, 13, 12,
2287 };
2288 static const unsigned int lcd1_sys_mux[] = {
2289 LCD1_CS_MARK, LCD1_WR_MARK, LCD1_RD_MARK, LCD1_RS_MARK,
2290 };
2291 /* - MMCIF ------------------------------------------------------------------ */
2292 static const unsigned int mmc0_data1_0_pins[] = {
2293 /* D[0] */
2294 68,
2295 };
2296 static const unsigned int mmc0_data1_0_mux[] = {
2297 MMC0_D0_PORT68_MARK,
2298 };
2299 static const unsigned int mmc0_data4_0_pins[] = {
2300 /* D[0:3] */
2301 68, 69, 70, 71,
2302 };
2303 static const unsigned int mmc0_data4_0_mux[] = {
2304 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
2305 };
2306 static const unsigned int mmc0_data8_0_pins[] = {
2307 /* D[0:7] */
2308 68, 69, 70, 71, 72, 73, 74, 75,
2309 };
2310 static const unsigned int mmc0_data8_0_mux[] = {
2311 MMC0_D0_PORT68_MARK, MMC0_D1_PORT69_MARK, MMC0_D2_PORT70_MARK, MMC0_D3_PORT71_MARK,
2312 MMC0_D4_PORT72_MARK, MMC0_D5_PORT73_MARK, MMC0_D6_PORT74_MARK, MMC0_D7_PORT75_MARK,
2313 };
2314 static const unsigned int mmc0_ctrl_0_pins[] = {
2315 /* CMD, CLK */
2316 67, 66,
2317 };
2318 static const unsigned int mmc0_ctrl_0_mux[] = {
2319 MMC0_CMD_PORT67_MARK, MMC0_CLK_PORT66_MARK,
2320 };
2321
2322 static const unsigned int mmc0_data1_1_pins[] = {
2323 /* D[0] */
2324 149,
2325 };
2326 static const unsigned int mmc0_data1_1_mux[] = {
2327 MMC1_D0_PORT149_MARK,
2328 };
2329 static const unsigned int mmc0_data4_1_pins[] = {
2330 /* D[0:3] */
2331 149, 148, 147, 146,
2332 };
2333 static const unsigned int mmc0_data4_1_mux[] = {
2334 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
2335 };
2336 static const unsigned int mmc0_data8_1_pins[] = {
2337 /* D[0:7] */
2338 149, 148, 147, 146, 145, 144, 143, 142,
2339 };
2340 static const unsigned int mmc0_data8_1_mux[] = {
2341 MMC1_D0_PORT149_MARK, MMC1_D1_PORT148_MARK, MMC1_D2_PORT147_MARK, MMC1_D3_PORT146_MARK,
2342 MMC1_D4_PORT145_MARK, MMC1_D5_PORT144_MARK, MMC1_D6_PORT143_MARK, MMC1_D7_PORT142_MARK,
2343 };
2344 static const unsigned int mmc0_ctrl_1_pins[] = {
2345 /* CMD, CLK */
2346 104, 103,
2347 };
2348 static const unsigned int mmc0_ctrl_1_mux[] = {
2349 MMC1_CMD_PORT104_MARK, MMC1_CLK_PORT103_MARK,
2350 };
2351 /* - SCIFA0 ----------------------------------------------------------------- */
2352 static const unsigned int scifa0_data_pins[] = {
2353 /* RXD, TXD */
2354 197, 198,
2355 };
2356 static const unsigned int scifa0_data_mux[] = {
2357 SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
2358 };
2359 static const unsigned int scifa0_clk_pins[] = {
2360 /* SCK */
2361 188,
2362 };
2363 static const unsigned int scifa0_clk_mux[] = {
2364 SCIFA0_SCK_MARK,
2365 };
2366 static const unsigned int scifa0_ctrl_pins[] = {
2367 /* RTS, CTS */
2368 194, 193,
2369 };
2370 static const unsigned int scifa0_ctrl_mux[] = {
2371 SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
2372 };
2373 /* - SCIFA1 ----------------------------------------------------------------- */
2374 static const unsigned int scifa1_data_pins[] = {
2375 /* RXD, TXD */
2376 195, 196,
2377 };
2378 static const unsigned int scifa1_data_mux[] = {
2379 SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
2380 };
2381 static const unsigned int scifa1_clk_pins[] = {
2382 /* SCK */
2383 185,
2384 };
2385 static const unsigned int scifa1_clk_mux[] = {
2386 SCIFA1_SCK_MARK,
2387 };
2388 static const unsigned int scifa1_ctrl_pins[] = {
2389 /* RTS, CTS */
2390 23, 21,
2391 };
2392 static const unsigned int scifa1_ctrl_mux[] = {
2393 SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
2394 };
2395 /* - SCIFA2 ----------------------------------------------------------------- */
2396 static const unsigned int scifa2_data_pins[] = {
2397 /* RXD, TXD */
2398 200, 201,
2399 };
2400 static const unsigned int scifa2_data_mux[] = {
2401 SCIFA2_RXD_MARK, SCIFA2_TXD_MARK,
2402 };
2403 static const unsigned int scifa2_clk_0_pins[] = {
2404 /* SCK */
2405 22,
2406 };
2407 static const unsigned int scifa2_clk_0_mux[] = {
2408 SCIFA2_SCK_PORT22_MARK,
2409 };
2410 static const unsigned int scifa2_clk_1_pins[] = {
2411 /* SCK */
2412 199,
2413 };
2414 static const unsigned int scifa2_clk_1_mux[] = {
2415 SCIFA2_SCK_PORT199_MARK,
2416 };
2417 static const unsigned int scifa2_ctrl_pins[] = {
2418 /* RTS, CTS */
2419 96, 95,
2420 };
2421 static const unsigned int scifa2_ctrl_mux[] = {
2422 SCIFA2_RTS_MARK, SCIFA2_CTS_MARK,
2423 };
2424 /* - SCIFA3 ----------------------------------------------------------------- */
2425 static const unsigned int scifa3_data_0_pins[] = {
2426 /* RXD, TXD */
2427 174, 175,
2428 };
2429 static const unsigned int scifa3_data_0_mux[] = {
2430 SCIFA3_RXD_PORT174_MARK, SCIFA3_TXD_PORT175_MARK,
2431 };
2432 static const unsigned int scifa3_clk_0_pins[] = {
2433 /* SCK */
2434 116,
2435 };
2436 static const unsigned int scifa3_clk_0_mux[] = {
2437 SCIFA3_SCK_PORT116_MARK,
2438 };
2439 static const unsigned int scifa3_ctrl_0_pins[] = {
2440 /* RTS, CTS */
2441 105, 117,
2442 };
2443 static const unsigned int scifa3_ctrl_0_mux[] = {
2444 SCIFA3_RTS_PORT105_MARK, SCIFA3_CTS_PORT117_MARK,
2445 };
2446 static const unsigned int scifa3_data_1_pins[] = {
2447 /* RXD, TXD */
2448 159, 160,
2449 };
2450 static const unsigned int scifa3_data_1_mux[] = {
2451 SCIFA3_RXD_PORT159_MARK, SCIFA3_TXD_PORT160_MARK,
2452 };
2453 static const unsigned int scifa3_clk_1_pins[] = {
2454 /* SCK */
2455 158,
2456 };
2457 static const unsigned int scifa3_clk_1_mux[] = {
2458 SCIFA3_SCK_PORT158_MARK,
2459 };
2460 static const unsigned int scifa3_ctrl_1_pins[] = {
2461 /* RTS, CTS */
2462 161, 162,
2463 };
2464 static const unsigned int scifa3_ctrl_1_mux[] = {
2465 SCIFA3_RTS_PORT161_MARK, SCIFA3_CTS_PORT162_MARK,
2466 };
2467 /* - SCIFA4 ----------------------------------------------------------------- */
2468 static const unsigned int scifa4_data_0_pins[] = {
2469 /* RXD, TXD */
2470 12, 13,
2471 };
2472 static const unsigned int scifa4_data_0_mux[] = {
2473 SCIFA4_RXD_PORT12_MARK, SCIFA4_TXD_PORT13_MARK,
2474 };
2475 static const unsigned int scifa4_data_1_pins[] = {
2476 /* RXD, TXD */
2477 204, 203,
2478 };
2479 static const unsigned int scifa4_data_1_mux[] = {
2480 SCIFA4_RXD_PORT204_MARK, SCIFA4_TXD_PORT203_MARK,
2481 };
2482 static const unsigned int scifa4_data_2_pins[] = {
2483 /* RXD, TXD */
2484 94, 93,
2485 };
2486 static const unsigned int scifa4_data_2_mux[] = {
2487 SCIFA4_RXD_PORT94_MARK, SCIFA4_TXD_PORT93_MARK,
2488 };
2489 static const unsigned int scifa4_clk_0_pins[] = {
2490 /* SCK */
2491 21,
2492 };
2493 static const unsigned int scifa4_clk_0_mux[] = {
2494 SCIFA4_SCK_PORT21_MARK,
2495 };
2496 static const unsigned int scifa4_clk_1_pins[] = {
2497 /* SCK */
2498 205,
2499 };
2500 static const unsigned int scifa4_clk_1_mux[] = {
2501 SCIFA4_SCK_PORT205_MARK,
2502 };
2503 /* - SCIFA5 ----------------------------------------------------------------- */
2504 static const unsigned int scifa5_data_0_pins[] = {
2505 /* RXD, TXD */
2506 10, 20,
2507 };
2508 static const unsigned int scifa5_data_0_mux[] = {
2509 SCIFA5_RXD_PORT10_MARK, SCIFA5_TXD_PORT20_MARK,
2510 };
2511 static const unsigned int scifa5_data_1_pins[] = {
2512 /* RXD, TXD */
2513 207, 208,
2514 };
2515 static const unsigned int scifa5_data_1_mux[] = {
2516 SCIFA5_RXD_PORT207_MARK, SCIFA5_TXD_PORT208_MARK,
2517 };
2518 static const unsigned int scifa5_data_2_pins[] = {
2519 /* RXD, TXD */
2520 92, 91,
2521 };
2522 static const unsigned int scifa5_data_2_mux[] = {
2523 SCIFA5_RXD_PORT92_MARK, SCIFA5_TXD_PORT91_MARK,
2524 };
2525 static const unsigned int scifa5_clk_0_pins[] = {
2526 /* SCK */
2527 23,
2528 };
2529 static const unsigned int scifa5_clk_0_mux[] = {
2530 SCIFA5_SCK_PORT23_MARK,
2531 };
2532 static const unsigned int scifa5_clk_1_pins[] = {
2533 /* SCK */
2534 206,
2535 };
2536 static const unsigned int scifa5_clk_1_mux[] = {
2537 SCIFA5_SCK_PORT206_MARK,
2538 };
2539 /* - SCIFA6 ----------------------------------------------------------------- */
2540 static const unsigned int scifa6_data_pins[] = {
2541 /* RXD, TXD */
2542 25, 26,
2543 };
2544 static const unsigned int scifa6_data_mux[] = {
2545 SCIFA6_RXD_MARK, SCIFA6_TXD_MARK,
2546 };
2547 static const unsigned int scifa6_clk_pins[] = {
2548 /* SCK */
2549 24,
2550 };
2551 static const unsigned int scifa6_clk_mux[] = {
2552 SCIFA6_SCK_MARK,
2553 };
2554 /* - SCIFA7 ----------------------------------------------------------------- */
2555 static const unsigned int scifa7_data_pins[] = {
2556 /* RXD, TXD */
2557 0, 1,
2558 };
2559 static const unsigned int scifa7_data_mux[] = {
2560 SCIFA7_RXD_MARK, SCIFA7_TXD_MARK,
2561 };
2562 /* - SCIFB ------------------------------------------------------------------ */
2563 static const unsigned int scifb_data_0_pins[] = {
2564 /* RXD, TXD */
2565 191, 192,
2566 };
2567 static const unsigned int scifb_data_0_mux[] = {
2568 SCIFB_RXD_PORT191_MARK, SCIFB_TXD_PORT192_MARK,
2569 };
2570 static const unsigned int scifb_clk_0_pins[] = {
2571 /* SCK */
2572 190,
2573 };
2574 static const unsigned int scifb_clk_0_mux[] = {
2575 SCIFB_SCK_PORT190_MARK,
2576 };
2577 static const unsigned int scifb_ctrl_0_pins[] = {
2578 /* RTS, CTS */
2579 186, 187,
2580 };
2581 static const unsigned int scifb_ctrl_0_mux[] = {
2582 SCIFB_RTS_PORT186_MARK, SCIFB_CTS_PORT187_MARK,
2583 };
2584 static const unsigned int scifb_data_1_pins[] = {
2585 /* RXD, TXD */
2586 3, 4,
2587 };
2588 static const unsigned int scifb_data_1_mux[] = {
2589 SCIFB_RXD_PORT3_MARK, SCIFB_TXD_PORT4_MARK,
2590 };
2591 static const unsigned int scifb_clk_1_pins[] = {
2592 /* SCK */
2593 2,
2594 };
2595 static const unsigned int scifb_clk_1_mux[] = {
2596 SCIFB_SCK_PORT2_MARK,
2597 };
2598 static const unsigned int scifb_ctrl_1_pins[] = {
2599 /* RTS, CTS */
2600 172, 173,
2601 };
2602 static const unsigned int scifb_ctrl_1_mux[] = {
2603 SCIFB_RTS_PORT172_MARK, SCIFB_CTS_PORT173_MARK,
2604 };
2605 /* - SDHI0 ------------------------------------------------------------------ */
2606 static const unsigned int sdhi0_data1_pins[] = {
2607 /* D0 */
2608 77,
2609 };
2610 static const unsigned int sdhi0_data1_mux[] = {
2611 SDHI0_D0_MARK,
2612 };
2613 static const unsigned int sdhi0_data4_pins[] = {
2614 /* D[0:3] */
2615 77, 78, 79, 80,
2616 };
2617 static const unsigned int sdhi0_data4_mux[] = {
2618 SDHI0_D0_MARK, SDHI0_D1_MARK, SDHI0_D2_MARK, SDHI0_D3_MARK,
2619 };
2620 static const unsigned int sdhi0_ctrl_pins[] = {
2621 /* CMD, CLK */
2622 76, 82,
2623 };
2624 static const unsigned int sdhi0_ctrl_mux[] = {
2625 SDHI0_CMD_MARK, SDHI0_CLK_MARK,
2626 };
2627 static const unsigned int sdhi0_cd_pins[] = {
2628 /* CD */
2629 81,
2630 };
2631 static const unsigned int sdhi0_cd_mux[] = {
2632 SDHI0_CD_MARK,
2633 };
2634 static const unsigned int sdhi0_wp_pins[] = {
2635 /* WP */
2636 83,
2637 };
2638 static const unsigned int sdhi0_wp_mux[] = {
2639 SDHI0_WP_MARK,
2640 };
2641 /* - SDHI1 ------------------------------------------------------------------ */
2642 static const unsigned int sdhi1_data1_pins[] = {
2643 /* D0 */
2644 68,
2645 };
2646 static const unsigned int sdhi1_data1_mux[] = {
2647 SDHI1_D0_MARK,
2648 };
2649 static const unsigned int sdhi1_data4_pins[] = {
2650 /* D[0:3] */
2651 68, 69, 70, 71,
2652 };
2653 static const unsigned int sdhi1_data4_mux[] = {
2654 SDHI1_D0_MARK, SDHI1_D1_MARK, SDHI1_D2_MARK, SDHI1_D3_MARK,
2655 };
2656 static const unsigned int sdhi1_ctrl_pins[] = {
2657 /* CMD, CLK */
2658 67, 66,
2659 };
2660 static const unsigned int sdhi1_ctrl_mux[] = {
2661 SDHI1_CMD_MARK, SDHI1_CLK_MARK,
2662 };
2663 static const unsigned int sdhi1_cd_pins[] = {
2664 /* CD */
2665 72,
2666 };
2667 static const unsigned int sdhi1_cd_mux[] = {
2668 SDHI1_CD_MARK,
2669 };
2670 static const unsigned int sdhi1_wp_pins[] = {
2671 /* WP */
2672 73,
2673 };
2674 static const unsigned int sdhi1_wp_mux[] = {
2675 SDHI1_WP_MARK,
2676 };
2677 /* - SDHI2 ------------------------------------------------------------------ */
2678 static const unsigned int sdhi2_data1_pins[] = {
2679 /* D0 */
2680 205,
2681 };
2682 static const unsigned int sdhi2_data1_mux[] = {
2683 SDHI2_D0_MARK,
2684 };
2685 static const unsigned int sdhi2_data4_pins[] = {
2686 /* D[0:3] */
2687 205, 206, 207, 208,
2688 };
2689 static const unsigned int sdhi2_data4_mux[] = {
2690 SDHI2_D0_MARK, SDHI2_D1_MARK, SDHI2_D2_MARK, SDHI2_D3_MARK,
2691 };
2692 static const unsigned int sdhi2_ctrl_pins[] = {
2693 /* CMD, CLK */
2694 204, 203,
2695 };
2696 static const unsigned int sdhi2_ctrl_mux[] = {
2697 SDHI2_CMD_MARK, SDHI2_CLK_MARK,
2698 };
2699 static const unsigned int sdhi2_cd_0_pins[] = {
2700 /* CD */
2701 202,
2702 };
2703 static const unsigned int sdhi2_cd_0_mux[] = {
2704 SDHI2_CD_PORT202_MARK,
2705 };
2706 static const unsigned int sdhi2_wp_0_pins[] = {
2707 /* WP */
2708 177,
2709 };
2710 static const unsigned int sdhi2_wp_0_mux[] = {
2711 SDHI2_WP_PORT177_MARK,
2712 };
2713 static const unsigned int sdhi2_cd_1_pins[] = {
2714 /* CD */
2715 24,
2716 };
2717 static const unsigned int sdhi2_cd_1_mux[] = {
2718 SDHI2_CD_PORT24_MARK,
2719 };
2720 static const unsigned int sdhi2_wp_1_pins[] = {
2721 /* WP */
2722 25,
2723 };
2724 static const unsigned int sdhi2_wp_1_mux[] = {
2725 SDHI2_WP_PORT25_MARK,
2726 };
2727 /* - TPU0 ------------------------------------------------------------------- */
2728 static const unsigned int tpu0_to0_pins[] = {
2729 /* TO */
2730 23,
2731 };
2732 static const unsigned int tpu0_to0_mux[] = {
2733 TPU0TO0_MARK,
2734 };
2735 static const unsigned int tpu0_to1_pins[] = {
2736 /* TO */
2737 21,
2738 };
2739 static const unsigned int tpu0_to1_mux[] = {
2740 TPU0TO1_MARK,
2741 };
2742 static const unsigned int tpu0_to2_0_pins[] = {
2743 /* TO */
2744 66,
2745 };
2746 static const unsigned int tpu0_to2_0_mux[] = {
2747 TPU0TO2_PORT66_MARK,
2748 };
2749 static const unsigned int tpu0_to2_1_pins[] = {
2750 /* TO */
2751 202,
2752 };
2753 static const unsigned int tpu0_to2_1_mux[] = {
2754 TPU0TO2_PORT202_MARK,
2755 };
2756 static const unsigned int tpu0_to3_pins[] = {
2757 /* TO */
2758 180,
2759 };
2760 static const unsigned int tpu0_to3_mux[] = {
2761 TPU0TO3_MARK,
2762 };
2763
2764 static const struct sh_pfc_pin_group pinmux_groups[] = {
2765 SH_PFC_PIN_GROUP(bsc_data8),
2766 SH_PFC_PIN_GROUP(bsc_data16),
2767 SH_PFC_PIN_GROUP(bsc_data32),
2768 SH_PFC_PIN_GROUP(bsc_cs0),
2769 SH_PFC_PIN_GROUP(bsc_cs2),
2770 SH_PFC_PIN_GROUP(bsc_cs4),
2771 SH_PFC_PIN_GROUP(bsc_cs5a_0),
2772 SH_PFC_PIN_GROUP(bsc_cs5a_1),
2773 SH_PFC_PIN_GROUP(bsc_cs5b),
2774 SH_PFC_PIN_GROUP(bsc_cs6a),
2775 SH_PFC_PIN_GROUP(bsc_rd_we8),
2776 SH_PFC_PIN_GROUP(bsc_rd_we16),
2777 SH_PFC_PIN_GROUP(bsc_rd_we32),
2778 SH_PFC_PIN_GROUP(bsc_bs),
2779 SH_PFC_PIN_GROUP(bsc_rdwr),
2780 SH_PFC_PIN_GROUP(ceu0_data_0_7),
2781 SH_PFC_PIN_GROUP(ceu0_data_8_15_0),
2782 SH_PFC_PIN_GROUP(ceu0_data_8_15_1),
2783 SH_PFC_PIN_GROUP(ceu0_clk_0),
2784 SH_PFC_PIN_GROUP(ceu0_clk_1),
2785 SH_PFC_PIN_GROUP(ceu0_clk_2),
2786 SH_PFC_PIN_GROUP(ceu0_sync),
2787 SH_PFC_PIN_GROUP(ceu0_field),
2788 SH_PFC_PIN_GROUP(ceu1_data),
2789 SH_PFC_PIN_GROUP(ceu1_clk),
2790 SH_PFC_PIN_GROUP(ceu1_sync),
2791 SH_PFC_PIN_GROUP(ceu1_field),
2792 SH_PFC_PIN_GROUP(fsia_mclk_in),
2793 SH_PFC_PIN_GROUP(fsia_mclk_out),
2794 SH_PFC_PIN_GROUP(fsia_sclk_in),
2795 SH_PFC_PIN_GROUP(fsia_sclk_out),
2796 SH_PFC_PIN_GROUP(fsia_data_in_0),
2797 SH_PFC_PIN_GROUP(fsia_data_in_1),
2798 SH_PFC_PIN_GROUP(fsia_data_out_0),
2799 SH_PFC_PIN_GROUP(fsia_data_out_1),
2800 SH_PFC_PIN_GROUP(fsia_data_out_2),
2801 SH_PFC_PIN_GROUP(fsia_spdif_0),
2802 SH_PFC_PIN_GROUP(fsia_spdif_1),
2803 SH_PFC_PIN_GROUP(fsib_mclk_in),
2804 SH_PFC_PIN_GROUP(gether_rmii),
2805 SH_PFC_PIN_GROUP(gether_mii),
2806 SH_PFC_PIN_GROUP(gether_gmii),
2807 SH_PFC_PIN_GROUP(gether_int),
2808 SH_PFC_PIN_GROUP(gether_link),
2809 SH_PFC_PIN_GROUP(gether_wol),
2810 SH_PFC_PIN_GROUP(hdmi),
2811 SH_PFC_PIN_GROUP(intc_irq0_0),
2812 SH_PFC_PIN_GROUP(intc_irq0_1),
2813 SH_PFC_PIN_GROUP(intc_irq1),
2814 SH_PFC_PIN_GROUP(intc_irq2_0),
2815 SH_PFC_PIN_GROUP(intc_irq2_1),
2816 SH_PFC_PIN_GROUP(intc_irq3_0),
2817 SH_PFC_PIN_GROUP(intc_irq3_1),
2818 SH_PFC_PIN_GROUP(intc_irq4_0),
2819 SH_PFC_PIN_GROUP(intc_irq4_1),
2820 SH_PFC_PIN_GROUP(intc_irq5_0),
2821 SH_PFC_PIN_GROUP(intc_irq5_1),
2822 SH_PFC_PIN_GROUP(intc_irq6_0),
2823 SH_PFC_PIN_GROUP(intc_irq6_1),
2824 SH_PFC_PIN_GROUP(intc_irq7_0),
2825 SH_PFC_PIN_GROUP(intc_irq7_1),
2826 SH_PFC_PIN_GROUP(intc_irq8),
2827 SH_PFC_PIN_GROUP(intc_irq9_0),
2828 SH_PFC_PIN_GROUP(intc_irq9_1),
2829 SH_PFC_PIN_GROUP(intc_irq10),
2830 SH_PFC_PIN_GROUP(intc_irq11),
2831 SH_PFC_PIN_GROUP(intc_irq12_0),
2832 SH_PFC_PIN_GROUP(intc_irq12_1),
2833 SH_PFC_PIN_GROUP(intc_irq13_0),
2834 SH_PFC_PIN_GROUP(intc_irq13_1),
2835 SH_PFC_PIN_GROUP(intc_irq14_0),
2836 SH_PFC_PIN_GROUP(intc_irq14_1),
2837 SH_PFC_PIN_GROUP(intc_irq15_0),
2838 SH_PFC_PIN_GROUP(intc_irq15_1),
2839 SH_PFC_PIN_GROUP(intc_irq16_0),
2840 SH_PFC_PIN_GROUP(intc_irq16_1),
2841 SH_PFC_PIN_GROUP(intc_irq17),
2842 SH_PFC_PIN_GROUP(intc_irq18),
2843 SH_PFC_PIN_GROUP(intc_irq19),
2844 SH_PFC_PIN_GROUP(intc_irq20),
2845 SH_PFC_PIN_GROUP(intc_irq21),
2846 SH_PFC_PIN_GROUP(intc_irq22),
2847 SH_PFC_PIN_GROUP(intc_irq23),
2848 SH_PFC_PIN_GROUP(intc_irq24),
2849 SH_PFC_PIN_GROUP(intc_irq25),
2850 SH_PFC_PIN_GROUP(intc_irq26_0),
2851 SH_PFC_PIN_GROUP(intc_irq26_1),
2852 SH_PFC_PIN_GROUP(intc_irq27_0),
2853 SH_PFC_PIN_GROUP(intc_irq27_1),
2854 SH_PFC_PIN_GROUP(intc_irq28_0),
2855 SH_PFC_PIN_GROUP(intc_irq28_1),
2856 SH_PFC_PIN_GROUP(intc_irq29_0),
2857 SH_PFC_PIN_GROUP(intc_irq29_1),
2858 SH_PFC_PIN_GROUP(intc_irq30_0),
2859 SH_PFC_PIN_GROUP(intc_irq30_1),
2860 SH_PFC_PIN_GROUP(intc_irq31_0),
2861 SH_PFC_PIN_GROUP(intc_irq31_1),
2862 SH_PFC_PIN_GROUP(lcd0_data8),
2863 SH_PFC_PIN_GROUP(lcd0_data9),
2864 SH_PFC_PIN_GROUP(lcd0_data12),
2865 SH_PFC_PIN_GROUP(lcd0_data16),
2866 SH_PFC_PIN_GROUP(lcd0_data18),
2867 SH_PFC_PIN_GROUP(lcd0_data24_0),
2868 SH_PFC_PIN_GROUP(lcd0_data24_1),
2869 SH_PFC_PIN_GROUP(lcd0_display),
2870 SH_PFC_PIN_GROUP(lcd0_lclk_0),
2871 SH_PFC_PIN_GROUP(lcd0_lclk_1),
2872 SH_PFC_PIN_GROUP(lcd0_sync),
2873 SH_PFC_PIN_GROUP(lcd0_sys),
2874 SH_PFC_PIN_GROUP(lcd1_data8),
2875 SH_PFC_PIN_GROUP(lcd1_data9),
2876 SH_PFC_PIN_GROUP(lcd1_data12),
2877 SH_PFC_PIN_GROUP(lcd1_data16),
2878 SH_PFC_PIN_GROUP(lcd1_data18),
2879 SH_PFC_PIN_GROUP(lcd1_data24),
2880 SH_PFC_PIN_GROUP(lcd1_display),
2881 SH_PFC_PIN_GROUP(lcd1_lclk),
2882 SH_PFC_PIN_GROUP(lcd1_sync),
2883 SH_PFC_PIN_GROUP(lcd1_sys),
2884 SH_PFC_PIN_GROUP(mmc0_data1_0),
2885 SH_PFC_PIN_GROUP(mmc0_data4_0),
2886 SH_PFC_PIN_GROUP(mmc0_data8_0),
2887 SH_PFC_PIN_GROUP(mmc0_ctrl_0),
2888 SH_PFC_PIN_GROUP(mmc0_data1_1),
2889 SH_PFC_PIN_GROUP(mmc0_data4_1),
2890 SH_PFC_PIN_GROUP(mmc0_data8_1),
2891 SH_PFC_PIN_GROUP(mmc0_ctrl_1),
2892 SH_PFC_PIN_GROUP(scifa0_data),
2893 SH_PFC_PIN_GROUP(scifa0_clk),
2894 SH_PFC_PIN_GROUP(scifa0_ctrl),
2895 SH_PFC_PIN_GROUP(scifa1_data),
2896 SH_PFC_PIN_GROUP(scifa1_clk),
2897 SH_PFC_PIN_GROUP(scifa1_ctrl),
2898 SH_PFC_PIN_GROUP(scifa2_data),
2899 SH_PFC_PIN_GROUP(scifa2_clk_0),
2900 SH_PFC_PIN_GROUP(scifa2_clk_1),
2901 SH_PFC_PIN_GROUP(scifa2_ctrl),
2902 SH_PFC_PIN_GROUP(scifa3_data_0),
2903 SH_PFC_PIN_GROUP(scifa3_clk_0),
2904 SH_PFC_PIN_GROUP(scifa3_ctrl_0),
2905 SH_PFC_PIN_GROUP(scifa3_data_1),
2906 SH_PFC_PIN_GROUP(scifa3_clk_1),
2907 SH_PFC_PIN_GROUP(scifa3_ctrl_1),
2908 SH_PFC_PIN_GROUP(scifa4_data_0),
2909 SH_PFC_PIN_GROUP(scifa4_data_1),
2910 SH_PFC_PIN_GROUP(scifa4_data_2),
2911 SH_PFC_PIN_GROUP(scifa4_clk_0),
2912 SH_PFC_PIN_GROUP(scifa4_clk_1),
2913 SH_PFC_PIN_GROUP(scifa5_data_0),
2914 SH_PFC_PIN_GROUP(scifa5_data_1),
2915 SH_PFC_PIN_GROUP(scifa5_data_2),
2916 SH_PFC_PIN_GROUP(scifa5_clk_0),
2917 SH_PFC_PIN_GROUP(scifa5_clk_1),
2918 SH_PFC_PIN_GROUP(scifa6_data),
2919 SH_PFC_PIN_GROUP(scifa6_clk),
2920 SH_PFC_PIN_GROUP(scifa7_data),
2921 SH_PFC_PIN_GROUP(scifb_data_0),
2922 SH_PFC_PIN_GROUP(scifb_clk_0),
2923 SH_PFC_PIN_GROUP(scifb_ctrl_0),
2924 SH_PFC_PIN_GROUP(scifb_data_1),
2925 SH_PFC_PIN_GROUP(scifb_clk_1),
2926 SH_PFC_PIN_GROUP(scifb_ctrl_1),
2927 SH_PFC_PIN_GROUP(sdhi0_data1),
2928 SH_PFC_PIN_GROUP(sdhi0_data4),
2929 SH_PFC_PIN_GROUP(sdhi0_ctrl),
2930 SH_PFC_PIN_GROUP(sdhi0_cd),
2931 SH_PFC_PIN_GROUP(sdhi0_wp),
2932 SH_PFC_PIN_GROUP(sdhi1_data1),
2933 SH_PFC_PIN_GROUP(sdhi1_data4),
2934 SH_PFC_PIN_GROUP(sdhi1_ctrl),
2935 SH_PFC_PIN_GROUP(sdhi1_cd),
2936 SH_PFC_PIN_GROUP(sdhi1_wp),
2937 SH_PFC_PIN_GROUP(sdhi2_data1),
2938 SH_PFC_PIN_GROUP(sdhi2_data4),
2939 SH_PFC_PIN_GROUP(sdhi2_ctrl),
2940 SH_PFC_PIN_GROUP(sdhi2_cd_0),
2941 SH_PFC_PIN_GROUP(sdhi2_wp_0),
2942 SH_PFC_PIN_GROUP(sdhi2_cd_1),
2943 SH_PFC_PIN_GROUP(sdhi2_wp_1),
2944 SH_PFC_PIN_GROUP(tpu0_to0),
2945 SH_PFC_PIN_GROUP(tpu0_to1),
2946 SH_PFC_PIN_GROUP(tpu0_to2_0),
2947 SH_PFC_PIN_GROUP(tpu0_to2_1),
2948 SH_PFC_PIN_GROUP(tpu0_to3),
2949 };
2950
2951 static const char * const bsc_groups[] = {
2952 "bsc_data8",
2953 "bsc_data16",
2954 "bsc_data32",
2955 "bsc_cs0",
2956 "bsc_cs2",
2957 "bsc_cs4",
2958 "bsc_cs5a_0",
2959 "bsc_cs5a_1",
2960 "bsc_cs5b",
2961 "bsc_cs6a",
2962 "bsc_rd_we8",
2963 "bsc_rd_we16",
2964 "bsc_rd_we32",
2965 "bsc_bs",
2966 "bsc_rdwr",
2967 };
2968
2969 static const char * const ceu0_groups[] = {
2970 "ceu0_data_0_7",
2971 "ceu0_data_8_15_0",
2972 "ceu0_data_8_15_1",
2973 "ceu0_clk_0",
2974 "ceu0_clk_1",
2975 "ceu0_clk_2",
2976 "ceu0_sync",
2977 "ceu0_field",
2978 };
2979
2980 static const char * const ceu1_groups[] = {
2981 "ceu1_data",
2982 "ceu1_clk",
2983 "ceu1_sync",
2984 "ceu1_field",
2985 };
2986
2987 static const char * const fsia_groups[] = {
2988 "fsia_mclk_in",
2989 "fsia_mclk_out",
2990 "fsia_sclk_in",
2991 "fsia_sclk_out",
2992 "fsia_data_in_0",
2993 "fsia_data_in_1",
2994 "fsia_data_out_0",
2995 "fsia_data_out_1",
2996 "fsia_data_out_2",
2997 "fsia_spdif_0",
2998 "fsia_spdif_1",
2999 };
3000
3001 static const char * const fsib_groups[] = {
3002 "fsib_mclk_in",
3003 };
3004
3005 static const char * const gether_groups[] = {
3006 "gether_rmii",
3007 "gether_mii",
3008 "gether_gmii",
3009 "gether_int",
3010 "gether_link",
3011 "gether_wol",
3012 };
3013
3014 static const char * const hdmi_groups[] = {
3015 "hdmi",
3016 };
3017
3018 static const char * const intc_groups[] = {
3019 "intc_irq0_0",
3020 "intc_irq0_1",
3021 "intc_irq1",
3022 "intc_irq2_0",
3023 "intc_irq2_1",
3024 "intc_irq3_0",
3025 "intc_irq3_1",
3026 "intc_irq4_0",
3027 "intc_irq4_1",
3028 "intc_irq5_0",
3029 "intc_irq5_1",
3030 "intc_irq6_0",
3031 "intc_irq6_1",
3032 "intc_irq7_0",
3033 "intc_irq7_1",
3034 "intc_irq8",
3035 "intc_irq9_0",
3036 "intc_irq9_1",
3037 "intc_irq10",
3038 "intc_irq11",
3039 "intc_irq12_0",
3040 "intc_irq12_1",
3041 "intc_irq13_0",
3042 "intc_irq13_1",
3043 "intc_irq14_0",
3044 "intc_irq14_1",
3045 "intc_irq15_0",
3046 "intc_irq15_1",
3047 "intc_irq16_0",
3048 "intc_irq16_1",
3049 "intc_irq17",
3050 "intc_irq18",
3051 "intc_irq19",
3052 "intc_irq20",
3053 "intc_irq21",
3054 "intc_irq22",
3055 "intc_irq23",
3056 "intc_irq24",
3057 "intc_irq25",
3058 "intc_irq26_0",
3059 "intc_irq26_1",
3060 "intc_irq27_0",
3061 "intc_irq27_1",
3062 "intc_irq28_0",
3063 "intc_irq28_1",
3064 "intc_irq29_0",
3065 "intc_irq29_1",
3066 "intc_irq30_0",
3067 "intc_irq30_1",
3068 "intc_irq31_0",
3069 "intc_irq31_1",
3070 };
3071
3072 static const char * const lcd0_groups[] = {
3073 "lcd0_data8",
3074 "lcd0_data9",
3075 "lcd0_data12",
3076 "lcd0_data16",
3077 "lcd0_data18",
3078 "lcd0_data24_0",
3079 "lcd0_data24_1",
3080 "lcd0_display",
3081 "lcd0_lclk_0",
3082 "lcd0_lclk_1",
3083 "lcd0_sync",
3084 "lcd0_sys",
3085 };
3086
3087 static const char * const lcd1_groups[] = {
3088 "lcd1_data8",
3089 "lcd1_data9",
3090 "lcd1_data12",
3091 "lcd1_data16",
3092 "lcd1_data18",
3093 "lcd1_data24",
3094 "lcd1_display",
3095 "lcd1_lclk",
3096 "lcd1_sync",
3097 "lcd1_sys",
3098 };
3099
3100 static const char * const mmc0_groups[] = {
3101 "mmc0_data1_0",
3102 "mmc0_data4_0",
3103 "mmc0_data8_0",
3104 "mmc0_ctrl_0",
3105 "mmc0_data1_1",
3106 "mmc0_data4_1",
3107 "mmc0_data8_1",
3108 "mmc0_ctrl_1",
3109 };
3110
3111 static const char * const scifa0_groups[] = {
3112 "scifa0_data",
3113 "scifa0_clk",
3114 "scifa0_ctrl",
3115 };
3116
3117 static const char * const scifa1_groups[] = {
3118 "scifa1_data",
3119 "scifa1_clk",
3120 "scifa1_ctrl",
3121 };
3122
3123 static const char * const scifa2_groups[] = {
3124 "scifa2_data",
3125 "scifa2_clk_0",
3126 "scifa2_clk_1",
3127 "scifa2_ctrl",
3128 };
3129
3130 static const char * const scifa3_groups[] = {
3131 "scifa3_data_0",
3132 "scifa3_clk_0",
3133 "scifa3_ctrl_0",
3134 "scifa3_data_1",
3135 "scifa3_clk_1",
3136 "scifa3_ctrl_1",
3137 };
3138
3139 static const char * const scifa4_groups[] = {
3140 "scifa4_data_0",
3141 "scifa4_data_1",
3142 "scifa4_data_2",
3143 "scifa4_clk_0",
3144 "scifa4_clk_1",
3145 };
3146
3147 static const char * const scifa5_groups[] = {
3148 "scifa5_data_0",
3149 "scifa5_data_1",
3150 "scifa5_data_2",
3151 "scifa5_clk_0",
3152 "scifa5_clk_1",
3153 };
3154
3155 static const char * const scifa6_groups[] = {
3156 "scifa6_data",
3157 "scifa6_clk",
3158 };
3159
3160 static const char * const scifa7_groups[] = {
3161 "scifa7_data",
3162 };
3163
3164 static const char * const scifb_groups[] = {
3165 "scifb_data_0",
3166 "scifb_clk_0",
3167 "scifb_ctrl_0",
3168 "scifb_data_1",
3169 "scifb_clk_1",
3170 "scifb_ctrl_1",
3171 };
3172
3173 static const char * const sdhi0_groups[] = {
3174 "sdhi0_data1",
3175 "sdhi0_data4",
3176 "sdhi0_ctrl",
3177 "sdhi0_cd",
3178 "sdhi0_wp",
3179 };
3180
3181 static const char * const sdhi1_groups[] = {
3182 "sdhi1_data1",
3183 "sdhi1_data4",
3184 "sdhi1_ctrl",
3185 "sdhi1_cd",
3186 "sdhi1_wp",
3187 };
3188
3189 static const char * const sdhi2_groups[] = {
3190 "sdhi2_data1",
3191 "sdhi2_data4",
3192 "sdhi2_ctrl",
3193 "sdhi2_cd_0",
3194 "sdhi2_wp_0",
3195 "sdhi2_cd_1",
3196 "sdhi2_wp_1",
3197 };
3198
3199 static const char * const tpu0_groups[] = {
3200 "tpu0_to0",
3201 "tpu0_to1",
3202 "tpu0_to2_0",
3203 "tpu0_to2_1",
3204 "tpu0_to3",
3205 };
3206
3207 static const struct sh_pfc_function pinmux_functions[] = {
3208 SH_PFC_FUNCTION(bsc),
3209 SH_PFC_FUNCTION(ceu0),
3210 SH_PFC_FUNCTION(ceu1),
3211 SH_PFC_FUNCTION(fsia),
3212 SH_PFC_FUNCTION(fsib),
3213 SH_PFC_FUNCTION(gether),
3214 SH_PFC_FUNCTION(hdmi),
3215 SH_PFC_FUNCTION(intc),
3216 SH_PFC_FUNCTION(lcd0),
3217 SH_PFC_FUNCTION(lcd1),
3218 SH_PFC_FUNCTION(mmc0),
3219 SH_PFC_FUNCTION(scifa0),
3220 SH_PFC_FUNCTION(scifa1),
3221 SH_PFC_FUNCTION(scifa2),
3222 SH_PFC_FUNCTION(scifa3),
3223 SH_PFC_FUNCTION(scifa4),
3224 SH_PFC_FUNCTION(scifa5),
3225 SH_PFC_FUNCTION(scifa6),
3226 SH_PFC_FUNCTION(scifa7),
3227 SH_PFC_FUNCTION(scifb),
3228 SH_PFC_FUNCTION(sdhi0),
3229 SH_PFC_FUNCTION(sdhi1),
3230 SH_PFC_FUNCTION(sdhi2),
3231 SH_PFC_FUNCTION(tpu0),
3232 };
3233
3234 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
3235 PORTCR(0, 0xe6050000), /* PORT0CR */
3236 PORTCR(1, 0xe6050001), /* PORT1CR */
3237 PORTCR(2, 0xe6050002), /* PORT2CR */
3238 PORTCR(3, 0xe6050003), /* PORT3CR */
3239 PORTCR(4, 0xe6050004), /* PORT4CR */
3240 PORTCR(5, 0xe6050005), /* PORT5CR */
3241 PORTCR(6, 0xe6050006), /* PORT6CR */
3242 PORTCR(7, 0xe6050007), /* PORT7CR */
3243 PORTCR(8, 0xe6050008), /* PORT8CR */
3244 PORTCR(9, 0xe6050009), /* PORT9CR */
3245 PORTCR(10, 0xe605000a), /* PORT10CR */
3246 PORTCR(11, 0xe605000b), /* PORT11CR */
3247 PORTCR(12, 0xe605000c), /* PORT12CR */
3248 PORTCR(13, 0xe605000d), /* PORT13CR */
3249 PORTCR(14, 0xe605000e), /* PORT14CR */
3250 PORTCR(15, 0xe605000f), /* PORT15CR */
3251 PORTCR(16, 0xe6050010), /* PORT16CR */
3252 PORTCR(17, 0xe6050011), /* PORT17CR */
3253 PORTCR(18, 0xe6050012), /* PORT18CR */
3254 PORTCR(19, 0xe6050013), /* PORT19CR */
3255 PORTCR(20, 0xe6050014), /* PORT20CR */
3256 PORTCR(21, 0xe6050015), /* PORT21CR */
3257 PORTCR(22, 0xe6050016), /* PORT22CR */
3258 PORTCR(23, 0xe6050017), /* PORT23CR */
3259 PORTCR(24, 0xe6050018), /* PORT24CR */
3260 PORTCR(25, 0xe6050019), /* PORT25CR */
3261 PORTCR(26, 0xe605001a), /* PORT26CR */
3262 PORTCR(27, 0xe605001b), /* PORT27CR */
3263 PORTCR(28, 0xe605001c), /* PORT28CR */
3264 PORTCR(29, 0xe605001d), /* PORT29CR */
3265 PORTCR(30, 0xe605001e), /* PORT30CR */
3266 PORTCR(31, 0xe605001f), /* PORT31CR */
3267 PORTCR(32, 0xe6050020), /* PORT32CR */
3268 PORTCR(33, 0xe6050021), /* PORT33CR */
3269 PORTCR(34, 0xe6050022), /* PORT34CR */
3270 PORTCR(35, 0xe6050023), /* PORT35CR */
3271 PORTCR(36, 0xe6050024), /* PORT36CR */
3272 PORTCR(37, 0xe6050025), /* PORT37CR */
3273 PORTCR(38, 0xe6050026), /* PORT38CR */
3274 PORTCR(39, 0xe6050027), /* PORT39CR */
3275 PORTCR(40, 0xe6050028), /* PORT40CR */
3276 PORTCR(41, 0xe6050029), /* PORT41CR */
3277 PORTCR(42, 0xe605002a), /* PORT42CR */
3278 PORTCR(43, 0xe605002b), /* PORT43CR */
3279 PORTCR(44, 0xe605002c), /* PORT44CR */
3280 PORTCR(45, 0xe605002d), /* PORT45CR */
3281 PORTCR(46, 0xe605002e), /* PORT46CR */
3282 PORTCR(47, 0xe605002f), /* PORT47CR */
3283 PORTCR(48, 0xe6050030), /* PORT48CR */
3284 PORTCR(49, 0xe6050031), /* PORT49CR */
3285 PORTCR(50, 0xe6050032), /* PORT50CR */
3286 PORTCR(51, 0xe6050033), /* PORT51CR */
3287 PORTCR(52, 0xe6050034), /* PORT52CR */
3288 PORTCR(53, 0xe6050035), /* PORT53CR */
3289 PORTCR(54, 0xe6050036), /* PORT54CR */
3290 PORTCR(55, 0xe6050037), /* PORT55CR */
3291 PORTCR(56, 0xe6050038), /* PORT56CR */
3292 PORTCR(57, 0xe6050039), /* PORT57CR */
3293 PORTCR(58, 0xe605003a), /* PORT58CR */
3294 PORTCR(59, 0xe605003b), /* PORT59CR */
3295 PORTCR(60, 0xe605003c), /* PORT60CR */
3296 PORTCR(61, 0xe605003d), /* PORT61CR */
3297 PORTCR(62, 0xe605003e), /* PORT62CR */
3298 PORTCR(63, 0xe605003f), /* PORT63CR */
3299 PORTCR(64, 0xe6050040), /* PORT64CR */
3300 PORTCR(65, 0xe6050041), /* PORT65CR */
3301 PORTCR(66, 0xe6050042), /* PORT66CR */
3302 PORTCR(67, 0xe6050043), /* PORT67CR */
3303 PORTCR(68, 0xe6050044), /* PORT68CR */
3304 PORTCR(69, 0xe6050045), /* PORT69CR */
3305 PORTCR(70, 0xe6050046), /* PORT70CR */
3306 PORTCR(71, 0xe6050047), /* PORT71CR */
3307 PORTCR(72, 0xe6050048), /* PORT72CR */
3308 PORTCR(73, 0xe6050049), /* PORT73CR */
3309 PORTCR(74, 0xe605004a), /* PORT74CR */
3310 PORTCR(75, 0xe605004b), /* PORT75CR */
3311 PORTCR(76, 0xe605004c), /* PORT76CR */
3312 PORTCR(77, 0xe605004d), /* PORT77CR */
3313 PORTCR(78, 0xe605004e), /* PORT78CR */
3314 PORTCR(79, 0xe605004f), /* PORT79CR */
3315 PORTCR(80, 0xe6050050), /* PORT80CR */
3316 PORTCR(81, 0xe6050051), /* PORT81CR */
3317 PORTCR(82, 0xe6050052), /* PORT82CR */
3318 PORTCR(83, 0xe6050053), /* PORT83CR */
3319
3320 PORTCR(84, 0xe6051054), /* PORT84CR */
3321 PORTCR(85, 0xe6051055), /* PORT85CR */
3322 PORTCR(86, 0xe6051056), /* PORT86CR */
3323 PORTCR(87, 0xe6051057), /* PORT87CR */
3324 PORTCR(88, 0xe6051058), /* PORT88CR */
3325 PORTCR(89, 0xe6051059), /* PORT89CR */
3326 PORTCR(90, 0xe605105a), /* PORT90CR */
3327 PORTCR(91, 0xe605105b), /* PORT91CR */
3328 PORTCR(92, 0xe605105c), /* PORT92CR */
3329 PORTCR(93, 0xe605105d), /* PORT93CR */
3330 PORTCR(94, 0xe605105e), /* PORT94CR */
3331 PORTCR(95, 0xe605105f), /* PORT95CR */
3332 PORTCR(96, 0xe6051060), /* PORT96CR */
3333 PORTCR(97, 0xe6051061), /* PORT97CR */
3334 PORTCR(98, 0xe6051062), /* PORT98CR */
3335 PORTCR(99, 0xe6051063), /* PORT99CR */
3336 PORTCR(100, 0xe6051064), /* PORT100CR */
3337 PORTCR(101, 0xe6051065), /* PORT101CR */
3338 PORTCR(102, 0xe6051066), /* PORT102CR */
3339 PORTCR(103, 0xe6051067), /* PORT103CR */
3340 PORTCR(104, 0xe6051068), /* PORT104CR */
3341 PORTCR(105, 0xe6051069), /* PORT105CR */
3342 PORTCR(106, 0xe605106a), /* PORT106CR */
3343 PORTCR(107, 0xe605106b), /* PORT107CR */
3344 PORTCR(108, 0xe605106c), /* PORT108CR */
3345 PORTCR(109, 0xe605106d), /* PORT109CR */
3346 PORTCR(110, 0xe605106e), /* PORT110CR */
3347 PORTCR(111, 0xe605106f), /* PORT111CR */
3348 PORTCR(112, 0xe6051070), /* PORT112CR */
3349 PORTCR(113, 0xe6051071), /* PORT113CR */
3350 PORTCR(114, 0xe6051072), /* PORT114CR */
3351
3352 PORTCR(115, 0xe6052073), /* PORT115CR */
3353 PORTCR(116, 0xe6052074), /* PORT116CR */
3354 PORTCR(117, 0xe6052075), /* PORT117CR */
3355 PORTCR(118, 0xe6052076), /* PORT118CR */
3356 PORTCR(119, 0xe6052077), /* PORT119CR */
3357 PORTCR(120, 0xe6052078), /* PORT120CR */
3358 PORTCR(121, 0xe6052079), /* PORT121CR */
3359 PORTCR(122, 0xe605207a), /* PORT122CR */
3360 PORTCR(123, 0xe605207b), /* PORT123CR */
3361 PORTCR(124, 0xe605207c), /* PORT124CR */
3362 PORTCR(125, 0xe605207d), /* PORT125CR */
3363 PORTCR(126, 0xe605207e), /* PORT126CR */
3364 PORTCR(127, 0xe605207f), /* PORT127CR */
3365 PORTCR(128, 0xe6052080), /* PORT128CR */
3366 PORTCR(129, 0xe6052081), /* PORT129CR */
3367 PORTCR(130, 0xe6052082), /* PORT130CR */
3368 PORTCR(131, 0xe6052083), /* PORT131CR */
3369 PORTCR(132, 0xe6052084), /* PORT132CR */
3370 PORTCR(133, 0xe6052085), /* PORT133CR */
3371 PORTCR(134, 0xe6052086), /* PORT134CR */
3372 PORTCR(135, 0xe6052087), /* PORT135CR */
3373 PORTCR(136, 0xe6052088), /* PORT136CR */
3374 PORTCR(137, 0xe6052089), /* PORT137CR */
3375 PORTCR(138, 0xe605208a), /* PORT138CR */
3376 PORTCR(139, 0xe605208b), /* PORT139CR */
3377 PORTCR(140, 0xe605208c), /* PORT140CR */
3378 PORTCR(141, 0xe605208d), /* PORT141CR */
3379 PORTCR(142, 0xe605208e), /* PORT142CR */
3380 PORTCR(143, 0xe605208f), /* PORT143CR */
3381 PORTCR(144, 0xe6052090), /* PORT144CR */
3382 PORTCR(145, 0xe6052091), /* PORT145CR */
3383 PORTCR(146, 0xe6052092), /* PORT146CR */
3384 PORTCR(147, 0xe6052093), /* PORT147CR */
3385 PORTCR(148, 0xe6052094), /* PORT148CR */
3386 PORTCR(149, 0xe6052095), /* PORT149CR */
3387 PORTCR(150, 0xe6052096), /* PORT150CR */
3388 PORTCR(151, 0xe6052097), /* PORT151CR */
3389 PORTCR(152, 0xe6052098), /* PORT152CR */
3390 PORTCR(153, 0xe6052099), /* PORT153CR */
3391 PORTCR(154, 0xe605209a), /* PORT154CR */
3392 PORTCR(155, 0xe605209b), /* PORT155CR */
3393 PORTCR(156, 0xe605209c), /* PORT156CR */
3394 PORTCR(157, 0xe605209d), /* PORT157CR */
3395 PORTCR(158, 0xe605209e), /* PORT158CR */
3396 PORTCR(159, 0xe605209f), /* PORT159CR */
3397 PORTCR(160, 0xe60520a0), /* PORT160CR */
3398 PORTCR(161, 0xe60520a1), /* PORT161CR */
3399 PORTCR(162, 0xe60520a2), /* PORT162CR */
3400 PORTCR(163, 0xe60520a3), /* PORT163CR */
3401 PORTCR(164, 0xe60520a4), /* PORT164CR */
3402 PORTCR(165, 0xe60520a5), /* PORT165CR */
3403 PORTCR(166, 0xe60520a6), /* PORT166CR */
3404 PORTCR(167, 0xe60520a7), /* PORT167CR */
3405 PORTCR(168, 0xe60520a8), /* PORT168CR */
3406 PORTCR(169, 0xe60520a9), /* PORT169CR */
3407 PORTCR(170, 0xe60520aa), /* PORT170CR */
3408 PORTCR(171, 0xe60520ab), /* PORT171CR */
3409 PORTCR(172, 0xe60520ac), /* PORT172CR */
3410 PORTCR(173, 0xe60520ad), /* PORT173CR */
3411 PORTCR(174, 0xe60520ae), /* PORT174CR */
3412 PORTCR(175, 0xe60520af), /* PORT175CR */
3413 PORTCR(176, 0xe60520b0), /* PORT176CR */
3414 PORTCR(177, 0xe60520b1), /* PORT177CR */
3415 PORTCR(178, 0xe60520b2), /* PORT178CR */
3416 PORTCR(179, 0xe60520b3), /* PORT179CR */
3417 PORTCR(180, 0xe60520b4), /* PORT180CR */
3418 PORTCR(181, 0xe60520b5), /* PORT181CR */
3419 PORTCR(182, 0xe60520b6), /* PORT182CR */
3420 PORTCR(183, 0xe60520b7), /* PORT183CR */
3421 PORTCR(184, 0xe60520b8), /* PORT184CR */
3422 PORTCR(185, 0xe60520b9), /* PORT185CR */
3423 PORTCR(186, 0xe60520ba), /* PORT186CR */
3424 PORTCR(187, 0xe60520bb), /* PORT187CR */
3425 PORTCR(188, 0xe60520bc), /* PORT188CR */
3426 PORTCR(189, 0xe60520bd), /* PORT189CR */
3427 PORTCR(190, 0xe60520be), /* PORT190CR */
3428 PORTCR(191, 0xe60520bf), /* PORT191CR */
3429 PORTCR(192, 0xe60520c0), /* PORT192CR */
3430 PORTCR(193, 0xe60520c1), /* PORT193CR */
3431 PORTCR(194, 0xe60520c2), /* PORT194CR */
3432 PORTCR(195, 0xe60520c3), /* PORT195CR */
3433 PORTCR(196, 0xe60520c4), /* PORT196CR */
3434 PORTCR(197, 0xe60520c5), /* PORT197CR */
3435 PORTCR(198, 0xe60520c6), /* PORT198CR */
3436 PORTCR(199, 0xe60520c7), /* PORT199CR */
3437 PORTCR(200, 0xe60520c8), /* PORT200CR */
3438 PORTCR(201, 0xe60520c9), /* PORT201CR */
3439 PORTCR(202, 0xe60520ca), /* PORT202CR */
3440 PORTCR(203, 0xe60520cb), /* PORT203CR */
3441 PORTCR(204, 0xe60520cc), /* PORT204CR */
3442 PORTCR(205, 0xe60520cd), /* PORT205CR */
3443 PORTCR(206, 0xe60520ce), /* PORT206CR */
3444 PORTCR(207, 0xe60520cf), /* PORT207CR */
3445 PORTCR(208, 0xe60520d0), /* PORT208CR */
3446 PORTCR(209, 0xe60520d1), /* PORT209CR */
3447
3448 PORTCR(210, 0xe60530d2), /* PORT210CR */
3449 PORTCR(211, 0xe60530d3), /* PORT211CR */
3450
3451 { PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
3452 MSEL1CR_31_0, MSEL1CR_31_1,
3453 MSEL1CR_30_0, MSEL1CR_30_1,
3454 MSEL1CR_29_0, MSEL1CR_29_1,
3455 MSEL1CR_28_0, MSEL1CR_28_1,
3456 MSEL1CR_27_0, MSEL1CR_27_1,
3457 MSEL1CR_26_0, MSEL1CR_26_1,
3458 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
3459 0, 0, 0, 0, 0, 0, 0, 0,
3460 MSEL1CR_16_0, MSEL1CR_16_1,
3461 MSEL1CR_15_0, MSEL1CR_15_1,
3462 MSEL1CR_14_0, MSEL1CR_14_1,
3463 MSEL1CR_13_0, MSEL1CR_13_1,
3464 MSEL1CR_12_0, MSEL1CR_12_1,
3465 0, 0, 0, 0,
3466 MSEL1CR_9_0, MSEL1CR_9_1,
3467 0, 0,
3468 MSEL1CR_7_0, MSEL1CR_7_1,
3469 MSEL1CR_6_0, MSEL1CR_6_1,
3470 MSEL1CR_5_0, MSEL1CR_5_1,
3471 MSEL1CR_4_0, MSEL1CR_4_1,
3472 MSEL1CR_3_0, MSEL1CR_3_1,
3473 MSEL1CR_2_0, MSEL1CR_2_1,
3474 0, 0,
3475 MSEL1CR_0_0, MSEL1CR_0_1,
3476 }
3477 },
3478 { PINMUX_CFG_REG("MSEL3CR", 0xE6058020, 32, 1) {
3479 0, 0, 0, 0, 0, 0, 0, 0,
3480 0, 0, 0, 0, 0, 0, 0, 0,
3481 0, 0, 0, 0, 0, 0, 0, 0,
3482 0, 0, 0, 0, 0, 0, 0, 0,
3483 MSEL3CR_15_0, MSEL3CR_15_1,
3484 0, 0, 0, 0, 0, 0, 0, 0,
3485 0, 0, 0, 0, 0, 0, 0, 0,
3486 MSEL3CR_6_0, MSEL3CR_6_1,
3487 0, 0, 0, 0, 0, 0, 0, 0,
3488 0, 0, 0, 0,
3489 }
3490 },
3491 { PINMUX_CFG_REG("MSEL4CR", 0xE6058024, 32, 1) {
3492 0, 0, 0, 0, 0, 0, 0, 0,
3493 0, 0, 0, 0, 0, 0, 0, 0,
3494 0, 0, 0, 0, 0, 0, 0, 0,
3495 MSEL4CR_19_0, MSEL4CR_19_1,
3496 MSEL4CR_18_0, MSEL4CR_18_1,
3497 0, 0, 0, 0,
3498 MSEL4CR_15_0, MSEL4CR_15_1,
3499 0, 0, 0, 0, 0, 0, 0, 0,
3500 MSEL4CR_10_0, MSEL4CR_10_1,
3501 0, 0, 0, 0, 0, 0,
3502 MSEL4CR_6_0, MSEL4CR_6_1,
3503 0, 0,
3504 MSEL4CR_4_0, MSEL4CR_4_1,
3505 0, 0, 0, 0,
3506 MSEL4CR_1_0, MSEL4CR_1_1,
3507 0, 0,
3508 }
3509 },
3510 { PINMUX_CFG_REG("MSEL5CR", 0xE6058028, 32, 1) {
3511 MSEL5CR_31_0, MSEL5CR_31_1,
3512 MSEL5CR_30_0, MSEL5CR_30_1,
3513 MSEL5CR_29_0, MSEL5CR_29_1,
3514 0, 0,
3515 MSEL5CR_27_0, MSEL5CR_27_1,
3516 0, 0,
3517 MSEL5CR_25_0, MSEL5CR_25_1,
3518 0, 0,
3519 MSEL5CR_23_0, MSEL5CR_23_1,
3520 0, 0,
3521 MSEL5CR_21_0, MSEL5CR_21_1,
3522 0, 0,
3523 MSEL5CR_19_0, MSEL5CR_19_1,
3524 0, 0,
3525 MSEL5CR_17_0, MSEL5CR_17_1,
3526 0, 0,
3527 MSEL5CR_15_0, MSEL5CR_15_1,
3528 MSEL5CR_14_0, MSEL5CR_14_1,
3529 MSEL5CR_13_0, MSEL5CR_13_1,
3530 MSEL5CR_12_0, MSEL5CR_12_1,
3531 MSEL5CR_11_0, MSEL5CR_11_1,
3532 MSEL5CR_10_0, MSEL5CR_10_1,
3533 0, 0,
3534 MSEL5CR_8_0, MSEL5CR_8_1,
3535 MSEL5CR_7_0, MSEL5CR_7_1,
3536 MSEL5CR_6_0, MSEL5CR_6_1,
3537 MSEL5CR_5_0, MSEL5CR_5_1,
3538 MSEL5CR_4_0, MSEL5CR_4_1,
3539 MSEL5CR_3_0, MSEL5CR_3_1,
3540 MSEL5CR_2_0, MSEL5CR_2_1,
3541 0, 0,
3542 MSEL5CR_0_0, MSEL5CR_0_1,
3543 }
3544 },
3545 { },
3546 };
3547
3548 static const struct pinmux_data_reg pinmux_data_regs[] = {
3549 { PINMUX_DATA_REG("PORTL031_000DR", 0xe6054800, 32) {
3550 PORT31_DATA, PORT30_DATA, PORT29_DATA, PORT28_DATA,
3551 PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
3552 PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
3553 PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
3554 PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
3555 PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
3556 PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
3557 PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA }
3558 },
3559 { PINMUX_DATA_REG("PORTL063_032DR", 0xe6054804, 32) {
3560 PORT63_DATA, PORT62_DATA, PORT61_DATA, PORT60_DATA,
3561 PORT59_DATA, PORT58_DATA, PORT57_DATA, PORT56_DATA,
3562 PORT55_DATA, PORT54_DATA, PORT53_DATA, PORT52_DATA,
3563 PORT51_DATA, PORT50_DATA, PORT49_DATA, PORT48_DATA,
3564 PORT47_DATA, PORT46_DATA, PORT45_DATA, PORT44_DATA,
3565 PORT43_DATA, PORT42_DATA, PORT41_DATA, PORT40_DATA,
3566 PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
3567 PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA }
3568 },
3569 { PINMUX_DATA_REG("PORTL095_064DR", 0xe6054808, 32) {
3570 0, 0, 0, 0,
3571 0, 0, 0, 0,
3572 0, 0, 0, 0,
3573 PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
3574 PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
3575 PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
3576 PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
3577 PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA }
3578 },
3579 { PINMUX_DATA_REG("PORTD095_064DR", 0xe6055808, 32) {
3580 PORT95_DATA, PORT94_DATA, PORT93_DATA, PORT92_DATA,
3581 PORT91_DATA, PORT90_DATA, PORT89_DATA, PORT88_DATA,
3582 PORT87_DATA, PORT86_DATA, PORT85_DATA, PORT84_DATA,
3583 0, 0, 0, 0,
3584 0, 0, 0, 0,
3585 0, 0, 0, 0,
3586 0, 0, 0, 0,
3587 0, 0, 0, 0 }
3588 },
3589 { PINMUX_DATA_REG("PORTD127_096DR", 0xe605580c, 32) {
3590 0, 0, 0, 0,
3591 0, 0, 0, 0,
3592 0, 0, 0, 0,
3593 0, PORT114_DATA, PORT113_DATA, PORT112_DATA,
3594 PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
3595 PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
3596 PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
3597 PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA }
3598 },
3599 { PINMUX_DATA_REG("PORTR127_096DR", 0xe605680C, 32) {
3600 PORT127_DATA, PORT126_DATA, PORT125_DATA, PORT124_DATA,
3601 PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
3602 PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
3603 PORT115_DATA, 0, 0, 0,
3604 0, 0, 0, 0,
3605 0, 0, 0, 0,
3606 0, 0, 0, 0,
3607 0, 0, 0, 0 }
3608 },
3609 { PINMUX_DATA_REG("PORTR159_128DR", 0xe6056810, 32) {
3610 PORT159_DATA, PORT158_DATA, PORT157_DATA, PORT156_DATA,
3611 PORT155_DATA, PORT154_DATA, PORT153_DATA, PORT152_DATA,
3612 PORT151_DATA, PORT150_DATA, PORT149_DATA, PORT148_DATA,
3613 PORT147_DATA, PORT146_DATA, PORT145_DATA, PORT144_DATA,
3614 PORT143_DATA, PORT142_DATA, PORT141_DATA, PORT140_DATA,
3615 PORT139_DATA, PORT138_DATA, PORT137_DATA, PORT136_DATA,
3616 PORT135_DATA, PORT134_DATA, PORT133_DATA, PORT132_DATA,
3617 PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA }
3618 },
3619 { PINMUX_DATA_REG("PORTR191_160DR", 0xe6056814, 32) {
3620 PORT191_DATA, PORT190_DATA, PORT189_DATA, PORT188_DATA,
3621 PORT187_DATA, PORT186_DATA, PORT185_DATA, PORT184_DATA,
3622 PORT183_DATA, PORT182_DATA, PORT181_DATA, PORT180_DATA,
3623 PORT179_DATA, PORT178_DATA, PORT177_DATA, PORT176_DATA,
3624 PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
3625 PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
3626 PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
3627 PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA }
3628 },
3629 { PINMUX_DATA_REG("PORTR223_192DR", 0xe6056818, 32) {
3630 0, 0, 0, 0,
3631 0, 0, 0, 0,
3632 0, 0, 0, 0,
3633 0, 0, PORT209_DATA, PORT208_DATA,
3634 PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
3635 PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
3636 PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
3637 PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA }
3638 },
3639 { PINMUX_DATA_REG("PORTU223_192DR", 0xe6057818, 32) {
3640 0, 0, 0, 0,
3641 0, 0, 0, 0,
3642 0, 0, 0, 0,
3643 PORT211_DATA, PORT210_DATA, 0, 0,
3644 0, 0, 0, 0,
3645 0, 0, 0, 0,
3646 0, 0, 0, 0,
3647 0, 0, 0, 0 }
3648 },
3649 { },
3650 };
3651
3652 static const struct pinmux_irq pinmux_irqs[] = {
3653 PINMUX_IRQ(2, 13), /* IRQ0A */
3654 PINMUX_IRQ(20), /* IRQ1A */
3655 PINMUX_IRQ(11, 12), /* IRQ2A */
3656 PINMUX_IRQ(10, 14), /* IRQ3A */
3657 PINMUX_IRQ(15, 172), /* IRQ4A */
3658 PINMUX_IRQ(0, 1), /* IRQ5A */
3659 PINMUX_IRQ(121, 173), /* IRQ6A */
3660 PINMUX_IRQ(120, 209), /* IRQ7A */
3661 PINMUX_IRQ(119), /* IRQ8A */
3662 PINMUX_IRQ(118, 210), /* IRQ9A */
3663 PINMUX_IRQ(19), /* IRQ10A */
3664 PINMUX_IRQ(104), /* IRQ11A */
3665 PINMUX_IRQ(42, 97), /* IRQ12A */
3666 PINMUX_IRQ(64, 98), /* IRQ13A */
3667 PINMUX_IRQ(63, 99), /* IRQ14A */
3668 PINMUX_IRQ(62, 100), /* IRQ15A */
3669 PINMUX_IRQ(68, 211), /* IRQ16A */
3670 PINMUX_IRQ(69), /* IRQ17A */
3671 PINMUX_IRQ(70), /* IRQ18A */
3672 PINMUX_IRQ(71), /* IRQ19A */
3673 PINMUX_IRQ(67), /* IRQ20A */
3674 PINMUX_IRQ(202), /* IRQ21A */
3675 PINMUX_IRQ(95), /* IRQ22A */
3676 PINMUX_IRQ(96), /* IRQ23A */
3677 PINMUX_IRQ(180), /* IRQ24A */
3678 PINMUX_IRQ(38), /* IRQ25A */
3679 PINMUX_IRQ(58, 81), /* IRQ26A */
3680 PINMUX_IRQ(57, 168), /* IRQ27A */
3681 PINMUX_IRQ(56, 169), /* IRQ28A */
3682 PINMUX_IRQ(50, 170), /* IRQ29A */
3683 PINMUX_IRQ(49, 171), /* IRQ30A */
3684 PINMUX_IRQ(41, 167), /* IRQ31A */
3685 };
3686
3687 #define PORTnCR_PULMD_OFF (0 << 6)
3688 #define PORTnCR_PULMD_DOWN (2 << 6)
3689 #define PORTnCR_PULMD_UP (3 << 6)
3690 #define PORTnCR_PULMD_MASK (3 << 6)
3691
3692 struct r8a7740_portcr_group {
3693 unsigned int end_pin;
3694 unsigned int offset;
3695 };
3696
3697 static const struct r8a7740_portcr_group r8a7740_portcr_offsets[] = {
3698 { 83, 0x0000 }, { 114, 0x1000 }, { 209, 0x2000 }, { 211, 0x3000 },
3699 };
3700
r8a7740_pinmux_portcr(struct sh_pfc * pfc,unsigned int pin)3701 static void __iomem *r8a7740_pinmux_portcr(struct sh_pfc *pfc, unsigned int pin)
3702 {
3703 unsigned int i;
3704
3705 for (i = 0; i < ARRAY_SIZE(r8a7740_portcr_offsets); ++i) {
3706 const struct r8a7740_portcr_group *group =
3707 &r8a7740_portcr_offsets[i];
3708
3709 if (pin <= group->end_pin)
3710 return pfc->windows->virt + group->offset + pin;
3711 }
3712
3713 return NULL;
3714 }
3715
r8a7740_pinmux_get_bias(struct sh_pfc * pfc,unsigned int pin)3716 static unsigned int r8a7740_pinmux_get_bias(struct sh_pfc *pfc, unsigned int pin)
3717 {
3718 void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
3719 u32 value = ioread8(addr) & PORTnCR_PULMD_MASK;
3720
3721 switch (value) {
3722 case PORTnCR_PULMD_UP:
3723 return PIN_CONFIG_BIAS_PULL_UP;
3724 case PORTnCR_PULMD_DOWN:
3725 return PIN_CONFIG_BIAS_PULL_DOWN;
3726 case PORTnCR_PULMD_OFF:
3727 default:
3728 return PIN_CONFIG_BIAS_DISABLE;
3729 }
3730 }
3731
r8a7740_pinmux_set_bias(struct sh_pfc * pfc,unsigned int pin,unsigned int bias)3732 static void r8a7740_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
3733 unsigned int bias)
3734 {
3735 void __iomem *addr = r8a7740_pinmux_portcr(pfc, pin);
3736 u32 value = ioread8(addr) & ~PORTnCR_PULMD_MASK;
3737
3738 switch (bias) {
3739 case PIN_CONFIG_BIAS_PULL_UP:
3740 value |= PORTnCR_PULMD_UP;
3741 break;
3742 case PIN_CONFIG_BIAS_PULL_DOWN:
3743 value |= PORTnCR_PULMD_DOWN;
3744 break;
3745 }
3746
3747 iowrite8(value, addr);
3748 }
3749
3750 static const struct sh_pfc_soc_operations r8a7740_pfc_ops = {
3751 .get_bias = r8a7740_pinmux_get_bias,
3752 .set_bias = r8a7740_pinmux_set_bias,
3753 };
3754
3755 const struct sh_pfc_soc_info r8a7740_pinmux_info = {
3756 .name = "r8a7740_pfc",
3757 .ops = &r8a7740_pfc_ops,
3758
3759 .input = { PINMUX_INPUT_BEGIN,
3760 PINMUX_INPUT_END },
3761 .output = { PINMUX_OUTPUT_BEGIN,
3762 PINMUX_OUTPUT_END },
3763 .function = { PINMUX_FUNCTION_BEGIN,
3764 PINMUX_FUNCTION_END },
3765
3766 .pins = pinmux_pins,
3767 .nr_pins = ARRAY_SIZE(pinmux_pins),
3768 .groups = pinmux_groups,
3769 .nr_groups = ARRAY_SIZE(pinmux_groups),
3770 .functions = pinmux_functions,
3771 .nr_functions = ARRAY_SIZE(pinmux_functions),
3772
3773 .cfg_regs = pinmux_config_regs,
3774 .data_regs = pinmux_data_regs,
3775
3776 .pinmux_data = pinmux_data,
3777 .pinmux_data_size = ARRAY_SIZE(pinmux_data),
3778
3779 .gpio_irq = pinmux_irqs,
3780 .gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
3781 };
3782
