1 /*
2  * Copyright (C) 2012-2013  Renesas Solutions Corp.
3  * Copyright (C) 2013  Magnus Damm
4  * Copyright (C) 2012  Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
5  *
6  * This program is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU General Public License as
8  * published by the Free Software Foundation; version 2 of the
9  * License.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  *
16  * You should have received a copy of the GNU General Public License
17  * along with this program; if not, write to the Free Software
18  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
19  */
20 #include <linux/io.h>
21 #include <linux/kernel.h>
22 #include <linux/pinctrl/pinconf-generic.h>
23 
24 #include "sh_pfc.h"
25 
26 #define CPU_ALL_PORT(fn, pfx, sfx)					\
27 	/*  Port0 - Port30 */						\
28 	PORT_10(0, fn, pfx, sfx),					\
29 	PORT_10(10, fn, pfx##1, sfx),					\
30 	PORT_10(20, fn, pfx##2, sfx),					\
31 	PORT_1(30, fn, pfx##30, sfx),					\
32 	/* Port32 - Port40 */						\
33 	PORT_1(32, fn, pfx##32, sfx),	PORT_1(33, fn, pfx##33, sfx),	\
34 	PORT_1(34, fn, pfx##34, sfx),	PORT_1(35, fn, pfx##35, sfx),	\
35 	PORT_1(36, fn, pfx##36, sfx),	PORT_1(37, fn, pfx##37, sfx),	\
36 	PORT_1(38, fn, pfx##38, sfx),	PORT_1(39, fn, pfx##39, sfx),	\
37 	PORT_1(40, fn, pfx##40, sfx),					\
38 	/* Port64  - Port85 */						\
39 	PORT_1(64, fn, pfx##64, sfx),	PORT_1(65, fn, pfx##65, sfx),	\
40 	PORT_1(66, fn, pfx##66, sfx),	PORT_1(67, fn, pfx##67, sfx),	\
41 	PORT_1(68, fn, pfx##68, sfx),	PORT_1(69, fn, pfx##69, sfx),	\
42 	PORT_10(70, fn, pfx##7, sfx),					\
43 	PORT_1(80, fn, pfx##80, sfx),	PORT_1(81, fn, pfx##81, sfx),	\
44 	PORT_1(82, fn, pfx##82, sfx),	PORT_1(83, fn, pfx##83, sfx),	\
45 	PORT_1(84, fn, pfx##84, sfx),	PORT_1(85, fn, pfx##85, sfx),	\
46 	/* Port96  - Port126 */						\
47 	PORT_1(96, fn, pfx##96, sfx),	PORT_1(97, fn, pfx##97, sfx),	\
48 	PORT_1(98, fn, pfx##98, sfx),	PORT_1(99, fn, pfx##99, sfx),	\
49 	PORT_10(100, fn, pfx##10, sfx),					\
50 	PORT_10(110, fn, pfx##11, sfx),					\
51 	PORT_1(120, fn, pfx##120, sfx),	PORT_1(121, fn, pfx##121, sfx),	\
52 	PORT_1(122, fn, pfx##122, sfx),	PORT_1(123, fn, pfx##123, sfx),	\
53 	PORT_1(124, fn, pfx##124, sfx),	PORT_1(125, fn, pfx##125, sfx),	\
54 	PORT_1(126, fn, pfx##126, sfx),					\
55 	/* Port128 - Port134 */						\
56 	PORT_1(128, fn, pfx##128, sfx),	PORT_1(129, fn, pfx##129, sfx),	\
57 	PORT_1(130, fn, pfx##130, sfx),	PORT_1(131, fn, pfx##131, sfx),	\
58 	PORT_1(132, fn, pfx##132, sfx),	PORT_1(133, fn, pfx##133, sfx),	\
59 	PORT_1(134, fn, pfx##134, sfx),					\
60 	/* Port160 - Port178 */						\
61 	PORT_10(160, fn, pfx##16, sfx),					\
62 	PORT_1(170, fn, pfx##170, sfx),	PORT_1(171, fn, pfx##171, sfx),	\
63 	PORT_1(172, fn, pfx##172, sfx),	PORT_1(173, fn, pfx##173, sfx),	\
64 	PORT_1(174, fn, pfx##174, sfx),	PORT_1(175, fn, pfx##175, sfx),	\
65 	PORT_1(176, fn, pfx##176, sfx),	PORT_1(177, fn, pfx##177, sfx),	\
66 	PORT_1(178, fn, pfx##178, sfx),					\
67 	/* Port192 - Port222 */						\
68 	PORT_1(192, fn, pfx##192, sfx),	PORT_1(193, fn, pfx##193, sfx),	\
69 	PORT_1(194, fn, pfx##194, sfx),	PORT_1(195, fn, pfx##195, sfx),	\
70 	PORT_1(196, fn, pfx##196, sfx),	PORT_1(197, fn, pfx##197, sfx),	\
71 	PORT_1(198, fn, pfx##198, sfx),	PORT_1(199, fn, pfx##199, sfx),	\
72 	PORT_10(200, fn, pfx##20, sfx),					\
73 	PORT_10(210, fn, pfx##21, sfx),					\
74 	PORT_1(220, fn, pfx##220, sfx),	PORT_1(221, fn, pfx##221, sfx),	\
75 	PORT_1(222, fn, pfx##222, sfx),					\
76 	/* Port224 - Port250 */						\
77 	PORT_1(224, fn, pfx##224, sfx),	PORT_1(225, fn, pfx##225, sfx),	\
78 	PORT_1(226, fn, pfx##226, sfx),	PORT_1(227, fn, pfx##227, sfx),	\
79 	PORT_1(228, fn, pfx##228, sfx),	PORT_1(229, fn, pfx##229, sfx),	\
80 	PORT_10(230, fn, pfx##23, sfx),					\
81 	PORT_10(240, fn, pfx##24, sfx),					\
82 	PORT_1(250, fn, pfx##250, sfx),					\
83 	/* Port256 - Port283 */						\
84 	PORT_1(256, fn, pfx##256, sfx),	PORT_1(257, fn, pfx##257, sfx),	\
85 	PORT_1(258, fn, pfx##258, sfx),	PORT_1(259, fn, pfx##259, sfx),	\
86 	PORT_10(260, fn, pfx##26, sfx),					\
87 	PORT_10(270, fn, pfx##27, sfx),					\
88 	PORT_1(280, fn, pfx##280, sfx),	PORT_1(281, fn, pfx##281, sfx),	\
89 	PORT_1(282, fn, pfx##282, sfx),	PORT_1(283, fn, pfx##283, sfx),	\
90 	/* Port288 - Port308 */						\
91 	PORT_1(288, fn, pfx##288, sfx),	PORT_1(289, fn, pfx##289, sfx),	\
92 	PORT_10(290, fn, pfx##29, sfx),					\
93 	PORT_1(300, fn, pfx##300, sfx),	PORT_1(301, fn, pfx##301, sfx),	\
94 	PORT_1(302, fn, pfx##302, sfx),	PORT_1(303, fn, pfx##303, sfx),	\
95 	PORT_1(304, fn, pfx##304, sfx),	PORT_1(305, fn, pfx##305, sfx),	\
96 	PORT_1(306, fn, pfx##306, sfx),	PORT_1(307, fn, pfx##307, sfx),	\
97 	PORT_1(308, fn, pfx##308, sfx),					\
98 	/* Port320 - Port329 */						\
99 	PORT_10(320, fn, pfx##32, sfx)
100 
101 
102 enum {
103 	PINMUX_RESERVED = 0,
104 
105 	/* PORT0_DATA -> PORT329_DATA */
106 	PINMUX_DATA_BEGIN,
107 	PORT_ALL(DATA),
108 	PINMUX_DATA_END,
109 
110 	/* PORT0_IN -> PORT329_IN */
111 	PINMUX_INPUT_BEGIN,
112 	PORT_ALL(IN),
113 	PINMUX_INPUT_END,
114 
115 	/* PORT0_OUT -> PORT329_OUT */
116 	PINMUX_OUTPUT_BEGIN,
117 	PORT_ALL(OUT),
118 	PINMUX_OUTPUT_END,
119 
120 	PINMUX_FUNCTION_BEGIN,
121 	PORT_ALL(FN_IN), /* PORT0_FN_IN -> PORT329_FN_IN */
122 	PORT_ALL(FN_OUT), /* PORT0_FN_OUT -> PORT329_FN_OUT */
123 	PORT_ALL(FN0), /* PORT0_FN0 -> PORT329_FN0 */
124 	PORT_ALL(FN1), /* PORT0_FN1 -> PORT329_FN1 */
125 	PORT_ALL(FN2), /* PORT0_FN2 -> PORT329_FN2 */
126 	PORT_ALL(FN3), /* PORT0_FN3 -> PORT329_FN3 */
127 	PORT_ALL(FN4), /* PORT0_FN4 -> PORT329_FN4 */
128 	PORT_ALL(FN5), /* PORT0_FN5 -> PORT329_FN5 */
129 	PORT_ALL(FN6), /* PORT0_FN6 -> PORT329_FN6 */
130 	PORT_ALL(FN7), /* PORT0_FN7 -> PORT329_FN7 */
131 
132 	MSEL1CR_31_0, MSEL1CR_31_1,
133 	MSEL1CR_27_0, MSEL1CR_27_1,
134 	MSEL1CR_25_0, MSEL1CR_25_1,
135 	MSEL1CR_24_0, MSEL1CR_24_1,
136 	MSEL1CR_22_0, MSEL1CR_22_1,
137 	MSEL1CR_21_0, MSEL1CR_21_1,
138 	MSEL1CR_20_0, MSEL1CR_20_1,
139 	MSEL1CR_19_0, MSEL1CR_19_1,
140 	MSEL1CR_18_0, MSEL1CR_18_1,
141 	MSEL1CR_17_0, MSEL1CR_17_1,
142 	MSEL1CR_16_0, MSEL1CR_16_1,
143 	MSEL1CR_15_0, MSEL1CR_15_1,
144 	MSEL1CR_14_0, MSEL1CR_14_1,
145 	MSEL1CR_13_0, MSEL1CR_13_1,
146 	MSEL1CR_12_0, MSEL1CR_12_1,
147 	MSEL1CR_11_0, MSEL1CR_11_1,
148 	MSEL1CR_10_0, MSEL1CR_10_1,
149 	MSEL1CR_09_0, MSEL1CR_09_1,
150 	MSEL1CR_08_0, MSEL1CR_08_1,
151 	MSEL1CR_07_0, MSEL1CR_07_1,
152 	MSEL1CR_06_0, MSEL1CR_06_1,
153 	MSEL1CR_05_0, MSEL1CR_05_1,
154 	MSEL1CR_04_0, MSEL1CR_04_1,
155 	MSEL1CR_03_0, MSEL1CR_03_1,
156 	MSEL1CR_02_0, MSEL1CR_02_1,
157 	MSEL1CR_01_0, MSEL1CR_01_1,
158 	MSEL1CR_00_0, MSEL1CR_00_1,
159 
160 	MSEL3CR_31_0, MSEL3CR_31_1,
161 	MSEL3CR_28_0, MSEL3CR_28_1,
162 	MSEL3CR_27_0, MSEL3CR_27_1,
163 	MSEL3CR_26_0, MSEL3CR_26_1,
164 	MSEL3CR_23_0, MSEL3CR_23_1,
165 	MSEL3CR_22_0, MSEL3CR_22_1,
166 	MSEL3CR_21_0, MSEL3CR_21_1,
167 	MSEL3CR_20_0, MSEL3CR_20_1,
168 	MSEL3CR_19_0, MSEL3CR_19_1,
169 	MSEL3CR_18_0, MSEL3CR_18_1,
170 	MSEL3CR_17_0, MSEL3CR_17_1,
171 	MSEL3CR_16_0, MSEL3CR_16_1,
172 	MSEL3CR_15_0, MSEL3CR_15_1,
173 	MSEL3CR_12_0, MSEL3CR_12_1,
174 	MSEL3CR_11_0, MSEL3CR_11_1,
175 	MSEL3CR_10_0, MSEL3CR_10_1,
176 	MSEL3CR_09_0, MSEL3CR_09_1,
177 	MSEL3CR_06_0, MSEL3CR_06_1,
178 	MSEL3CR_03_0, MSEL3CR_03_1,
179 	MSEL3CR_01_0, MSEL3CR_01_1,
180 	MSEL3CR_00_0, MSEL3CR_00_1,
181 
182 	MSEL4CR_30_0, MSEL4CR_30_1,
183 	MSEL4CR_29_0, MSEL4CR_29_1,
184 	MSEL4CR_28_0, MSEL4CR_28_1,
185 	MSEL4CR_27_0, MSEL4CR_27_1,
186 	MSEL4CR_26_0, MSEL4CR_26_1,
187 	MSEL4CR_25_0, MSEL4CR_25_1,
188 	MSEL4CR_24_0, MSEL4CR_24_1,
189 	MSEL4CR_23_0, MSEL4CR_23_1,
190 	MSEL4CR_22_0, MSEL4CR_22_1,
191 	MSEL4CR_21_0, MSEL4CR_21_1,
192 	MSEL4CR_20_0, MSEL4CR_20_1,
193 	MSEL4CR_19_0, MSEL4CR_19_1,
194 	MSEL4CR_18_0, MSEL4CR_18_1,
195 	MSEL4CR_17_0, MSEL4CR_17_1,
196 	MSEL4CR_16_0, MSEL4CR_16_1,
197 	MSEL4CR_15_0, MSEL4CR_15_1,
198 	MSEL4CR_14_0, MSEL4CR_14_1,
199 	MSEL4CR_13_0, MSEL4CR_13_1,
200 	MSEL4CR_12_0, MSEL4CR_12_1,
201 	MSEL4CR_11_0, MSEL4CR_11_1,
202 	MSEL4CR_10_0, MSEL4CR_10_1,
203 	MSEL4CR_09_0, MSEL4CR_09_1,
204 	MSEL4CR_07_0, MSEL4CR_07_1,
205 	MSEL4CR_04_0, MSEL4CR_04_1,
206 	MSEL4CR_01_0, MSEL4CR_01_1,
207 
208 	MSEL5CR_31_0, MSEL5CR_31_1,
209 	MSEL5CR_30_0, MSEL5CR_30_1,
210 	MSEL5CR_29_0, MSEL5CR_29_1,
211 	MSEL5CR_28_0, MSEL5CR_28_1,
212 	MSEL5CR_27_0, MSEL5CR_27_1,
213 	MSEL5CR_26_0, MSEL5CR_26_1,
214 	MSEL5CR_25_0, MSEL5CR_25_1,
215 	MSEL5CR_24_0, MSEL5CR_24_1,
216 	MSEL5CR_23_0, MSEL5CR_23_1,
217 	MSEL5CR_22_0, MSEL5CR_22_1,
218 	MSEL5CR_21_0, MSEL5CR_21_1,
219 	MSEL5CR_20_0, MSEL5CR_20_1,
220 	MSEL5CR_19_0, MSEL5CR_19_1,
221 	MSEL5CR_18_0, MSEL5CR_18_1,
222 	MSEL5CR_17_0, MSEL5CR_17_1,
223 	MSEL5CR_16_0, MSEL5CR_16_1,
224 	MSEL5CR_15_0, MSEL5CR_15_1,
225 	MSEL5CR_14_0, MSEL5CR_14_1,
226 	MSEL5CR_13_0, MSEL5CR_13_1,
227 	MSEL5CR_12_0, MSEL5CR_12_1,
228 	MSEL5CR_11_0, MSEL5CR_11_1,
229 	MSEL5CR_10_0, MSEL5CR_10_1,
230 	MSEL5CR_09_0, MSEL5CR_09_1,
231 	MSEL5CR_08_0, MSEL5CR_08_1,
232 	MSEL5CR_07_0, MSEL5CR_07_1,
233 	MSEL5CR_06_0, MSEL5CR_06_1,
234 
235 	MSEL8CR_16_0, MSEL8CR_16_1,
236 	MSEL8CR_01_0, MSEL8CR_01_1,
237 	MSEL8CR_00_0, MSEL8CR_00_1,
238 
239 	PINMUX_FUNCTION_END,
240 
241 	PINMUX_MARK_BEGIN,
242 
243 
244 #define F1(a)	a##_MARK
245 #define F2(a)	a##_MARK
246 #define F3(a)	a##_MARK
247 #define F4(a)	a##_MARK
248 #define F5(a)	a##_MARK
249 #define F6(a)	a##_MARK
250 #define F7(a)	a##_MARK
251 #define IRQ(a)	IRQ##a##_MARK
252 
253 	F1(LCDD0), F3(PDM2_CLK_0), F7(DU0_DR0), IRQ(0), /* Port0 */
254 	F1(LCDD1), F3(PDM2_DATA_1), F7(DU0_DR19), IRQ(1),
255 	F1(LCDD2), F3(PDM3_CLK_2), F7(DU0_DR2), IRQ(2),
256 	F1(LCDD3), F3(PDM3_DATA_3), F7(DU0_DR3), IRQ(3),
257 	F1(LCDD4), F3(PDM4_CLK_4), F7(DU0_DR4), IRQ(4),
258 	F1(LCDD5), F3(PDM4_DATA_5), F7(DU0_DR5), IRQ(5),
259 	F1(LCDD6), F3(PDM0_OUTCLK_6), F7(DU0_DR6), IRQ(6),
260 	F1(LCDD7), F3(PDM0_OUTDATA_7), F7(DU0_DR7), IRQ(7),
261 	F1(LCDD8), F3(PDM1_OUTCLK_8), F7(DU0_DG0), IRQ(8),
262 	F1(LCDD9), F3(PDM1_OUTDATA_9), F7(DU0_DG1), IRQ(9),
263 	F1(LCDD10), F3(FSICCK), F7(DU0_DG2), IRQ(10), /* Port10 */
264 	F1(LCDD11), F3(FSICISLD), F7(DU0_DG3), IRQ(11),
265 	F1(LCDD12), F3(FSICOMC), F7(DU0_DG4), IRQ(12),
266 	F1(LCDD13), F3(FSICOLR), F4(FSICILR), F7(DU0_DG5), IRQ(13),
267 	F1(LCDD14), F3(FSICOBT), F4(FSICIBT), F7(DU0_DG6), IRQ(14),
268 	F1(LCDD15), F3(FSICOSLD), F7(DU0_DG7), IRQ(15),
269 	F1(LCDD16), F4(TPU1TO1), F7(DU0_DB0),
270 	F1(LCDD17), F4(SF_IRQ_00), F7(DU0_DB1),
271 	F1(LCDD18), F4(SF_IRQ_01), F7(DU0_DB2),
272 	F1(LCDD19), F3(SCIFB3_RTS_19), F7(DU0_DB3),
273 	F1(LCDD20), F3(SCIFB3_CTS_20), F7(DU0_DB4), /* Port20 */
274 	F1(LCDD21), F3(SCIFB3_TXD_21), F7(DU0_DB5),
275 	F1(LCDD22), F3(SCIFB3_RXD_22), F7(DU0_DB6),
276 	F1(LCDD23), F3(SCIFB3_SCK_23), F7(DU0_DB7),
277 	F1(LCDHSYN), F2(LCDCS), F3(SCIFB1_RTS_24),
278 	F7(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N),
279 	F1(LCDVSYN), F3(SCIFB1_CTS_25), F7(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N),
280 	F1(LCDDCK), F2(LCDWR), F3(SCIFB1_TXD_26), F7(DU0_DOTCLKIN),
281 	F1(LCDDISP), F2(LCDRS), F3(SCIFB1_RXD_27), F7(DU0_DOTCLKOUT),
282 	F1(LCDRD_N), F3(SCIFB1_SCK_28), F7(DU0_DOTCLKOUTB),
283 	F1(LCDLCLK), F4(SF_IRQ_02), F7(DU0_DISP_CSYNC_N_DE),
284 	F1(LCDDON), F4(SF_IRQ_03), F7(DU0_ODDF_N_CLAMP), /* Port30 */
285 
286 	F1(SCIFA0_RTS), F5(SIM0_DET), F7(CSCIF0_RTS), /* Port32 */
287 	F1(SCIFA0_CTS), F5(SIM1_DET), F7(CSCIF0_CTS),
288 	F1(SCIFA0_SCK), F5(SIM0_PWRON), F7(CSCIF0_SCK),
289 	F1(SCIFA1_RTS), F7(CSCIF1_RTS),
290 	F1(SCIFA1_CTS), F7(CSCIF1_CTS),
291 	F1(SCIFA1_SCK), F7(CSCIF1_SCK),
292 	F1(SCIFB0_RTS), F3(TPU0TO1), F4(SCIFB3_RTS_38), F7(CHSCIF0_HRTS),
293 	F1(SCIFB0_CTS), F3(TPU0TO2), F4(SCIFB3_CTS_39), F7(CHSCIF0_HCTS),
294 	F1(SCIFB0_SCK), F3(TPU0TO3), F4(SCIFB3_SCK_40),
295 	F7(CHSCIF0_HSCK), /* Port40 */
296 
297 	F1(PDM0_DATA), /* Port64 */
298 	F1(PDM1_DATA),
299 	F1(HSI_RX_WAKE), F2(SCIFB2_CTS_66), F3(MSIOF3_SYNC), F5(GenIO4),
300 	IRQ(40),
301 	F1(HSI_RX_READY), F2(SCIFB1_TXD_67), F5(GIO_OUT3_67), F7(CHSCIF1_HTX),
302 	F1(HSI_RX_FLAG), F2(SCIFB2_TXD_68), F3(MSIOF3_TXD), F5(GIO_OUT4_68),
303 	F1(HSI_RX_DATA), F2(SCIFB2_RXD_69), F3(MSIOF3_RXD), F5(GIO_OUT5_69),
304 	F1(HSI_TX_FLAG), F2(SCIFB1_RTS_70), F5(GIO_OUT1_70), F6(HSIC_TSTCLK0),
305 	F7(CHSCIF1_HRTS), /* Port70 */
306 	F1(HSI_TX_DATA), F2(SCIFB1_CTS_71), F5(GIO_OUT2_71), F6(HSIC_TSTCLK1),
307 	F7(CHSCIF1_HCTS),
308 	F1(HSI_TX_WAKE), F2(SCIFB1_RXD_72), F5(GenIO8), F7(CHSCIF1_HRX),
309 	F1(HSI_TX_READY), F2(SCIFB2_RTS_73), F3(MSIOF3_SCK), F5(GIO_OUT0_73),
310 	F1(IRDA_OUT), F1(IRDA_IN), F1(IRDA_FIRSEL), F1(TPU0TO0),
311 	F1(DIGRFEN), F1(GPS_TIMESTAMP), F1(TXP), /* Port80 */
312 	F1(TXP2), F1(COEX_0), F1(COEX_1), IRQ(19), IRQ(18), /* Port85 */
313 
314 	F1(KEYIN0), /* Port96 */
315 	F1(KEYIN1), F1(KEYIN2), F1(KEYIN3), F1(KEYIN4), /* Port100 */
316 	F1(KEYIN5), F1(KEYIN6), IRQ(41), F1(KEYIN7), IRQ(42),
317 	F2(KEYOUT0), F2(KEYOUT1), F2(KEYOUT2), F2(KEYOUT3),
318 	F2(KEYOUT4), F2(KEYOUT5), IRQ(43), F2(KEYOUT6), IRQ(44), /* Port110 */
319 	F2(KEYOUT7), F5(RFANAEN), IRQ(45),
320 	F1(KEYIN8), F2(KEYOUT8), F4(SF_IRQ_04), IRQ(46),
321 	F1(KEYIN9), F2(KEYOUT9), F4(SF_IRQ_05), IRQ(47),
322 	F1(KEYIN10), F2(KEYOUT10), F4(SF_IRQ_06), IRQ(48),
323 	F1(KEYIN11), F2(KEYOUT11), F4(SF_IRQ_07), IRQ(49),
324 	F1(SCIFA0_TXD), F7(CSCIF0_TX), F1(SCIFA0_RXD), F7(CSCIF0_RX),
325 	F1(SCIFA1_TXD), F7(CSCIF1_TX), F1(SCIFA1_RXD), F7(CSCIF1_RX),
326 	F3(SF_PORT_1_120), F4(SCIFB3_RXD_120), F7(DU0_CDE), /* Port120 */
327 	F3(SF_PORT_0_121), F4(SCIFB3_TXD_121),
328 	F1(SCIFB0_TXD), F7(CHSCIF0_HTX),
329 	F1(SCIFB0_RXD), F7(CHSCIF0_HRX), F3(ISP_STROBE_124),
330 	F1(STP_ISD_0), F2(PDM4_CLK_125), F3(MSIOF2_TXD), F5(SIM0_VOLTSEL0),
331 	F1(TS_SDEN), F2(MSIOF7_SYNC), F3(STP_ISEN_1),
332 	F1(STP_ISEN_0), F2(PDM1_OUTDATA_128), F3(MSIOF2_SYNC),
333 	F5(SIM1_VOLTSEL1), F1(TS_SPSYNC), F2(MSIOF7_RXD), F3(STP_ISSYNC_1),
334 	F1(STP_ISSYNC_0), F2(PDM4_DATA_130), F3(MSIOF2_RXD),
335 	F5(SIM0_VOLTSEL1), /* Port130 */
336 	F1(STP_OPWM_0), F5(SIM1_PWRON), F1(TS_SCK), F2(MSIOF7_SCK),
337 	F3(STP_ISCLK_1), F1(STP_ISCLK_0), F2(PDM1_OUTCLK_133), F3(MSIOF2_SCK),
338 	F5(SIM1_VOLTSEL0), F1(TS_SDAT), F2(MSIOF7_TXD), F3(STP_ISD_1),
339 	IRQ(20), /* Port160 */
340 	IRQ(21), IRQ(22), IRQ(23),
341 	F1(MMCD0_0), F1(MMCD0_1), F1(MMCD0_2), F1(MMCD0_3),
342 	F1(MMCD0_4), F1(MMCD0_5), F1(MMCD0_6), /* Port170 */
343 	F1(MMCD0_7), F1(MMCCMD0), F1(MMCCLK0), F1(MMCRST),
344 	IRQ(24), IRQ(25), IRQ(26), IRQ(27),
345 	F1(A10), F2(MMCD1_7), IRQ(31), /* Port192 */
346 	F1(A9), F2(MMCD1_6), IRQ(32),
347 	F1(A8), F2(MMCD1_5), IRQ(33),
348 	F1(A7), F2(MMCD1_4), IRQ(34),
349 	F1(A6), F2(MMCD1_3), IRQ(35),
350 	F1(A5), F2(MMCD1_2), IRQ(36),
351 	F1(A4), F2(MMCD1_1), IRQ(37),
352 	F1(A3), F2(MMCD1_0), IRQ(38),
353 	F1(A2), F2(MMCCMD1), IRQ(39), /* Port200 */
354 	F1(A1),
355 	F1(A0), F2(BS),
356 	F1(CKO), F2(MMCCLK1),
357 	F1(CS0_N), F5(SIM0_GPO1),
358 	F1(CS2_N), F5(SIM0_GPO2),
359 	F1(CS4_N), F2(VIO_VD), F5(SIM1_GPO0),
360 	F1(D15), F5(GIO_OUT15),
361 	F1(D14), F5(GIO_OUT14),
362 	F1(D13), F5(GIO_OUT13),
363 	F1(D12), F5(GIO_OUT12), /* Port210 */
364 	F1(D11), F5(WGM_TXP2),
365 	F1(D10), F5(WGM_GPS_TIMEM_ASK_RFCLK),
366 	F1(D9), F2(VIO_D9), F5(GIO_OUT9),
367 	F1(D8), F2(VIO_D8), F5(GIO_OUT8),
368 	F1(D7), F2(VIO_D7), F5(GIO_OUT7),
369 	F1(D6), F2(VIO_D6), F5(GIO_OUT6),
370 	F1(D5), F2(VIO_D5), F5(GIO_OUT5_217),
371 	F1(D4), F2(VIO_D4), F5(GIO_OUT4_218),
372 	F1(D3), F2(VIO_D3), F5(GIO_OUT3_219),
373 	F1(D2), F2(VIO_D2), F5(GIO_OUT2_220), /* Port220 */
374 	F1(D1), F2(VIO_D1), F5(GIO_OUT1_221),
375 	F1(D0), F2(VIO_D0), F5(GIO_OUT0_222),
376 	F1(RDWR_224), F2(VIO_HD), F5(SIM1_GPO2),
377 	F1(RD_N), F1(WAIT_N), F2(VIO_CLK), F5(SIM1_GPO1),
378 	F1(WE0_N), F2(RDWR_227),
379 	F1(WE1_N), F5(SIM0_GPO0),
380 	F1(PWMO), F2(VIO_CKO1_229),
381 	F1(SLIM_CLK), F2(VIO_CKO4_230), /* Port230 */
382 	F1(SLIM_DATA), F2(VIO_CKO5_231), F2(VIO_CKO2_232), F4(SF_PORT_0_232),
383 	F2(VIO_CKO3_233), F4(SF_PORT_1_233),
384 	F1(FSIACK), F2(PDM3_CLK_234), F3(ISP_IRIS1_234),
385 	F1(FSIAISLD), F2(PDM3_DATA_235),
386 	F1(FSIAOMC), F2(PDM0_OUTCLK_236), F3(ISP_IRIS0_236),
387 	F1(FSIAOLR), F2(FSIAILR), F1(FSIAOBT), F2(FSIAIBT),
388 	F1(FSIAOSLD), F2(PDM0_OUTDATA_239),
389 	F1(FSIBISLD), /* Port240 */
390 	F1(FSIBOLR), F2(FSIBILR), F1(FSIBOMC), F3(ISP_SHUTTER1_242),
391 	F1(FSIBOBT), F2(FSIBIBT), F1(FSIBOSLD), F2(FSIASPDIF),
392 	F1(FSIBCK), F3(ISP_SHUTTER0_245),
393 	F1(ISP_IRIS1_246), F1(ISP_IRIS0_247), F1(ISP_SHUTTER1_248),
394 	F1(ISP_SHUTTER0_249), F1(ISP_STROBE_250), /* Port250 */
395 	F1(MSIOF0_SYNC), F1(MSIOF0_RXD), F1(MSIOF0_SCK), F1(MSIOF0_SS2),
396 	F3(VIO_CKO3_259), F1(MSIOF0_TXD), /* Port260 */
397 	F2(SCIFB1_SCK_261), F7(CHSCIF1_HSCK), F2(SCIFB2_SCK_262),
398 	F1(MSIOF1_SS2), F4(MSIOF5_SS2), F1(MSIOF1_TXD), F4(MSIOF5_TXD),
399 	F1(MSIOF1_RXD), F4(MSIOF5_RXD), F1(MSIOF1_SS1), F4(MSIOF5_SS1),
400 	F1(MSIOF0_SS1), F1(MSIOF1_SCK), F4(MSIOF5_SCK),
401 	F1(MSIOF1_SYNC), F4(MSIOF5_SYNC),
402 	F1(MSIOF2_SS1), F3(VIO_CKO5_270), /* Port270 */
403 	F1(MSIOF2_SS2), F3(VIO_CKO2_271), F1(MSIOF3_SS2), F3(VIO_CKO1_272),
404 	F1(MSIOF3_SS1), F3(VIO_CKO4_273), F1(MSIOF4_SS2), F4(TPU1TO0),
405 	F1(IC_DP), F1(SIM0_RST), F1(IC_DM), F1(SIM0_BSICOMP),
406 	F1(SIM0_CLK), F1(SIM0_IO), /* Port280 */
407 	F1(SIM1_IO), F2(PDM2_DATA_281), F1(SIM1_CLK), F2(PDM2_CLK_282),
408 	F1(SIM1_RST), F1(SDHID1_0), F3(STMDATA0_2),
409 	F1(SDHID1_1), F3(STMDATA1_2), IRQ(51), /* Port290 */
410 	F1(SDHID1_2), F3(STMDATA2_2), F1(SDHID1_3), F3(STMDATA3_2),
411 	F1(SDHICLK1), F3(STMCLK_2), F1(SDHICMD1), F3(STMSIDI_2),
412 	F1(SDHID2_0), F2(MSIOF4_TXD), F3(SCIFB2_TXD_295), F4(MSIOF6_TXD),
413 	F1(SDHID2_1), F4(MSIOF6_SS2), IRQ(52),
414 	F1(SDHID2_2), F2(MSIOF4_RXD), F3(SCIFB2_RXD_297), F4(MSIOF6_RXD),
415 	F1(SDHID2_3), F2(MSIOF4_SYNC), F3(SCIFB2_CTS_298), F4(MSIOF6_SYNC),
416 	F1(SDHICLK2), F2(MSIOF4_SCK), F3(SCIFB2_SCK_299), F4(MSIOF6_SCK),
417 	F1(SDHICMD2), F2(MSIOF4_SS1), F3(SCIFB2_RTS_300),
418 	F4(MSIOF6_SS1), /* Port300 */
419 	F1(SDHICD0), IRQ(50), F1(SDHID0_0), F3(STMDATA0_1),
420 	F1(SDHID0_1), F3(STMDATA1_1), F1(SDHID0_2), F3(STMDATA2_1),
421 	F1(SDHID0_3), F3(STMDATA3_1), F1(SDHICMD0), F3(STMSIDI_1),
422 	F1(SDHIWP0), F1(SDHICLK0), F3(STMCLK_1), IRQ(16), /* Port320 */
423 	IRQ(17), IRQ(28), IRQ(29), IRQ(30), IRQ(53), IRQ(54),
424 	IRQ(55), IRQ(56), IRQ(57),
425 	PINMUX_MARK_END,
426 };
427 
428 static const u16 pinmux_data[] = {
429 	/* specify valid pin states for each pin in GPIO mode */
430 	PINMUX_DATA_ALL(),
431 
432 	/* Port0 */
433 	PINMUX_DATA(LCDD0_MARK,		PORT0_FN1),
434 	PINMUX_DATA(PDM2_CLK_0_MARK,	PORT0_FN3),
435 	PINMUX_DATA(DU0_DR0_MARK,	PORT0_FN7),
436 	PINMUX_DATA(IRQ0_MARK,		PORT0_FN0),
437 
438 	/* Port1 */
439 	PINMUX_DATA(LCDD1_MARK,		PORT1_FN1),
440 	PINMUX_DATA(PDM2_DATA_1_MARK,	PORT1_FN3,	MSEL3CR_12_0),
441 	PINMUX_DATA(DU0_DR19_MARK,	PORT1_FN7),
442 	PINMUX_DATA(IRQ1_MARK,		PORT1_FN0),
443 
444 	/* Port2 */
445 	PINMUX_DATA(LCDD2_MARK,		PORT2_FN1),
446 	PINMUX_DATA(PDM3_CLK_2_MARK,	PORT2_FN3),
447 	PINMUX_DATA(DU0_DR2_MARK,	PORT2_FN7),
448 	PINMUX_DATA(IRQ2_MARK,		PORT2_FN0),
449 
450 	/* Port3 */
451 	PINMUX_DATA(LCDD3_MARK,		PORT3_FN1),
452 	PINMUX_DATA(PDM3_DATA_3_MARK,	PORT3_FN3,	MSEL3CR_12_0),
453 	PINMUX_DATA(DU0_DR3_MARK,	PORT3_FN7),
454 	PINMUX_DATA(IRQ3_MARK,		PORT3_FN0),
455 
456 	/* Port4 */
457 	PINMUX_DATA(LCDD4_MARK,		PORT4_FN1),
458 	PINMUX_DATA(PDM4_CLK_4_MARK,	PORT4_FN3),
459 	PINMUX_DATA(DU0_DR4_MARK,	PORT4_FN7),
460 	PINMUX_DATA(IRQ4_MARK,		PORT4_FN0),
461 
462 	/* Port5 */
463 	PINMUX_DATA(LCDD5_MARK,		PORT5_FN1),
464 	PINMUX_DATA(PDM4_DATA_5_MARK,	PORT5_FN3,	MSEL3CR_12_0),
465 	PINMUX_DATA(DU0_DR5_MARK,	PORT5_FN7),
466 	PINMUX_DATA(IRQ5_MARK,		PORT5_FN0),
467 
468 	/* Port6 */
469 	PINMUX_DATA(LCDD6_MARK,		PORT6_FN1),
470 	PINMUX_DATA(PDM0_OUTCLK_6_MARK,	PORT6_FN3),
471 	PINMUX_DATA(DU0_DR6_MARK,	PORT6_FN7),
472 	PINMUX_DATA(IRQ6_MARK,		PORT6_FN0),
473 
474 	/* Port7 */
475 	PINMUX_DATA(LCDD7_MARK,			PORT7_FN1),
476 	PINMUX_DATA(PDM0_OUTDATA_7_MARK,	PORT7_FN3),
477 	PINMUX_DATA(DU0_DR7_MARK,		PORT7_FN7),
478 	PINMUX_DATA(IRQ7_MARK,			PORT7_FN0),
479 
480 	/* Port8 */
481 	PINMUX_DATA(LCDD8_MARK,		PORT8_FN1),
482 	PINMUX_DATA(PDM1_OUTCLK_8_MARK,	PORT8_FN3),
483 	PINMUX_DATA(DU0_DG0_MARK,	PORT8_FN7),
484 	PINMUX_DATA(IRQ8_MARK,		PORT8_FN0),
485 
486 	/* Port9 */
487 	PINMUX_DATA(LCDD9_MARK,		PORT9_FN1),
488 	PINMUX_DATA(PDM1_OUTDATA_9_MARK, PORT9_FN3),
489 	PINMUX_DATA(DU0_DG1_MARK,	PORT9_FN7),
490 	PINMUX_DATA(IRQ9_MARK,		PORT9_FN0),
491 
492 	/* Port10 */
493 	PINMUX_DATA(LCDD10_MARK,		PORT10_FN1),
494 	PINMUX_DATA(FSICCK_MARK,		PORT10_FN3),
495 	PINMUX_DATA(DU0_DG2_MARK,		PORT10_FN7),
496 	PINMUX_DATA(IRQ10_MARK,			PORT10_FN0),
497 
498 	/* Port11 */
499 	PINMUX_DATA(LCDD11_MARK,		PORT11_FN1),
500 	PINMUX_DATA(FSICISLD_MARK,		PORT11_FN3),
501 	PINMUX_DATA(DU0_DG3_MARK,		PORT11_FN7),
502 	PINMUX_DATA(IRQ11_MARK,			PORT11_FN0),
503 
504 	/* Port12 */
505 	PINMUX_DATA(LCDD12_MARK,		PORT12_FN1),
506 	PINMUX_DATA(FSICOMC_MARK,		PORT12_FN3),
507 	PINMUX_DATA(DU0_DG4_MARK,		PORT12_FN7),
508 	PINMUX_DATA(IRQ12_MARK,			PORT12_FN0),
509 
510 	/* Port13 */
511 	PINMUX_DATA(LCDD13_MARK,		PORT13_FN1),
512 	PINMUX_DATA(FSICOLR_MARK,		PORT13_FN3),
513 	PINMUX_DATA(FSICILR_MARK,		PORT13_FN4),
514 	PINMUX_DATA(DU0_DG5_MARK,		PORT13_FN7),
515 	PINMUX_DATA(IRQ13_MARK,			PORT13_FN0),
516 
517 	/* Port14 */
518 	PINMUX_DATA(LCDD14_MARK,		PORT14_FN1),
519 	PINMUX_DATA(FSICOBT_MARK,		PORT14_FN3),
520 	PINMUX_DATA(FSICIBT_MARK,		PORT14_FN4),
521 	PINMUX_DATA(DU0_DG6_MARK,		PORT14_FN7),
522 	PINMUX_DATA(IRQ14_MARK,			PORT14_FN0),
523 
524 	/* Port15 */
525 	PINMUX_DATA(LCDD15_MARK,		PORT15_FN1),
526 	PINMUX_DATA(FSICOSLD_MARK,		PORT15_FN3),
527 	PINMUX_DATA(DU0_DG7_MARK,		PORT15_FN7),
528 	PINMUX_DATA(IRQ15_MARK,			PORT15_FN0),
529 
530 	/* Port16 */
531 	PINMUX_DATA(LCDD16_MARK,		PORT16_FN1),
532 	PINMUX_DATA(TPU1TO1_MARK,		PORT16_FN4),
533 	PINMUX_DATA(DU0_DB0_MARK,		PORT16_FN7),
534 
535 	/* Port17 */
536 	PINMUX_DATA(LCDD17_MARK,		PORT17_FN1),
537 	PINMUX_DATA(SF_IRQ_00_MARK,		PORT17_FN4),
538 	PINMUX_DATA(DU0_DB1_MARK,		PORT17_FN7),
539 
540 	/* Port18 */
541 	PINMUX_DATA(LCDD18_MARK,		PORT18_FN1),
542 	PINMUX_DATA(SF_IRQ_01_MARK,		PORT18_FN4),
543 	PINMUX_DATA(DU0_DB2_MARK,		PORT18_FN7),
544 
545 	/* Port19 */
546 	PINMUX_DATA(LCDD19_MARK,		PORT19_FN1),
547 	PINMUX_DATA(SCIFB3_RTS_19_MARK,		PORT19_FN3),
548 	PINMUX_DATA(DU0_DB3_MARK,		PORT19_FN7),
549 
550 	/* Port20 */
551 	PINMUX_DATA(LCDD20_MARK,		PORT20_FN1),
552 	PINMUX_DATA(SCIFB3_CTS_20_MARK,		PORT20_FN3,	MSEL3CR_09_0),
553 	PINMUX_DATA(DU0_DB4_MARK,		PORT20_FN7),
554 
555 	/* Port21 */
556 	PINMUX_DATA(LCDD21_MARK,		PORT21_FN1),
557 	PINMUX_DATA(SCIFB3_TXD_21_MARK,		PORT21_FN3,	MSEL3CR_09_0),
558 	PINMUX_DATA(DU0_DB5_MARK,		PORT21_FN7),
559 
560 	/* Port22 */
561 	PINMUX_DATA(LCDD22_MARK,		PORT22_FN1),
562 	PINMUX_DATA(SCIFB3_RXD_22_MARK,		PORT22_FN3,	MSEL3CR_09_0),
563 	PINMUX_DATA(DU0_DB6_MARK,		PORT22_FN7),
564 
565 	/* Port23 */
566 	PINMUX_DATA(LCDD23_MARK,		PORT23_FN1),
567 	PINMUX_DATA(SCIFB3_SCK_23_MARK,		PORT23_FN3),
568 	PINMUX_DATA(DU0_DB7_MARK,		PORT23_FN7),
569 
570 	/* Port24 */
571 	PINMUX_DATA(LCDHSYN_MARK,			PORT24_FN1),
572 	PINMUX_DATA(LCDCS_MARK,				PORT24_FN2),
573 	PINMUX_DATA(SCIFB1_RTS_24_MARK,			PORT24_FN3),
574 	PINMUX_DATA(DU0_EXHSYNC_N_CSYNC_N_HSYNC_N_MARK,	PORT24_FN7),
575 
576 	/* Port25 */
577 	PINMUX_DATA(LCDVSYN_MARK,			PORT25_FN1),
578 	PINMUX_DATA(SCIFB1_CTS_25_MARK, PORT25_FN3, MSEL3CR_11_0),
579 	PINMUX_DATA(DU0_EXVSYNC_N_VSYNC_N_CSYNC_N_MARK,	PORT25_FN7),
580 
581 	/* Port26 */
582 	PINMUX_DATA(LCDDCK_MARK,		PORT26_FN1),
583 	PINMUX_DATA(LCDWR_MARK,			PORT26_FN2),
584 	PINMUX_DATA(SCIFB1_TXD_26_MARK,		PORT26_FN3,	MSEL3CR_11_0),
585 	PINMUX_DATA(DU0_DOTCLKIN_MARK,		PORT26_FN7),
586 
587 	/* Port27 */
588 	PINMUX_DATA(LCDDISP_MARK,		PORT27_FN1),
589 	PINMUX_DATA(LCDRS_MARK,			PORT27_FN2),
590 	PINMUX_DATA(SCIFB1_RXD_27_MARK,		PORT27_FN3,	MSEL3CR_11_0),
591 	PINMUX_DATA(DU0_DOTCLKOUT_MARK,		PORT27_FN7),
592 
593 	/* Port28 */
594 	PINMUX_DATA(LCDRD_N_MARK,		PORT28_FN1),
595 	PINMUX_DATA(SCIFB1_SCK_28_MARK,		PORT28_FN3),
596 	PINMUX_DATA(DU0_DOTCLKOUTB_MARK,	PORT28_FN7),
597 
598 	/* Port29 */
599 	PINMUX_DATA(LCDLCLK_MARK,		PORT29_FN1),
600 	PINMUX_DATA(SF_IRQ_02_MARK,		PORT29_FN4),
601 	PINMUX_DATA(DU0_DISP_CSYNC_N_DE_MARK,	PORT29_FN7),
602 
603 	/* Port30 */
604 	PINMUX_DATA(LCDDON_MARK,		PORT30_FN1),
605 	PINMUX_DATA(SF_IRQ_03_MARK,		PORT30_FN4),
606 	PINMUX_DATA(DU0_ODDF_N_CLAMP_MARK,	PORT30_FN7),
607 
608 	/* Port32 */
609 	PINMUX_DATA(SCIFA0_RTS_MARK,		PORT32_FN1),
610 	PINMUX_DATA(SIM0_DET_MARK,		PORT32_FN5),
611 	PINMUX_DATA(CSCIF0_RTS_MARK,		PORT32_FN7),
612 
613 	/* Port33 */
614 	PINMUX_DATA(SCIFA0_CTS_MARK,		PORT33_FN1),
615 	PINMUX_DATA(SIM1_DET_MARK,		PORT33_FN5),
616 	PINMUX_DATA(CSCIF0_CTS_MARK,		PORT33_FN7),
617 
618 	/* Port34 */
619 	PINMUX_DATA(SCIFA0_SCK_MARK,		PORT34_FN1),
620 	PINMUX_DATA(SIM0_PWRON_MARK,		PORT34_FN5),
621 	PINMUX_DATA(CSCIF0_SCK_MARK,		PORT34_FN7),
622 
623 	/* Port35 */
624 	PINMUX_DATA(SCIFA1_RTS_MARK,		PORT35_FN1),
625 	PINMUX_DATA(CSCIF1_RTS_MARK,		PORT35_FN7),
626 
627 	/* Port36 */
628 	PINMUX_DATA(SCIFA1_CTS_MARK,		PORT36_FN1),
629 	PINMUX_DATA(CSCIF1_CTS_MARK,		PORT36_FN7),
630 
631 	/* Port37 */
632 	PINMUX_DATA(SCIFA1_SCK_MARK,		PORT37_FN1),
633 	PINMUX_DATA(CSCIF1_SCK_MARK,		PORT37_FN7),
634 
635 	/* Port38 */
636 	PINMUX_DATA(SCIFB0_RTS_MARK,		PORT38_FN1),
637 	PINMUX_DATA(TPU0TO1_MARK,		PORT38_FN3),
638 	PINMUX_DATA(SCIFB3_RTS_38_MARK,		PORT38_FN4),
639 	PINMUX_DATA(CHSCIF0_HRTS_MARK,		PORT38_FN7),
640 
641 	/* Port39 */
642 	PINMUX_DATA(SCIFB0_CTS_MARK,		PORT39_FN1),
643 	PINMUX_DATA(TPU0TO2_MARK,		PORT39_FN3),
644 	PINMUX_DATA(SCIFB3_CTS_39_MARK,		PORT39_FN4,	MSEL3CR_09_1),
645 	PINMUX_DATA(CHSCIF0_HCTS_MARK,		PORT39_FN7),
646 
647 	/* Port40 */
648 	PINMUX_DATA(SCIFB0_SCK_MARK,		PORT40_FN1),
649 	PINMUX_DATA(TPU0TO3_MARK,		PORT40_FN3),
650 	PINMUX_DATA(SCIFB3_SCK_40_MARK,		PORT40_FN4),
651 	PINMUX_DATA(CHSCIF0_HSCK_MARK,		PORT40_FN7),
652 
653 	/* Port64 */
654 	PINMUX_DATA(PDM0_DATA_MARK,		PORT64_FN1),
655 
656 	/* Port65 */
657 	PINMUX_DATA(PDM1_DATA_MARK,		PORT65_FN1),
658 
659 	/* Port66 */
660 	PINMUX_DATA(HSI_RX_WAKE_MARK,		PORT66_FN1),
661 	PINMUX_DATA(SCIFB2_CTS_66_MARK,		PORT66_FN2,	MSEL3CR_10_0),
662 	PINMUX_DATA(MSIOF3_SYNC_MARK,		PORT66_FN3),
663 	PINMUX_DATA(GenIO4_MARK,		PORT66_FN5),
664 	PINMUX_DATA(IRQ40_MARK,			PORT66_FN0),
665 
666 	/* Port67 */
667 	PINMUX_DATA(HSI_RX_READY_MARK,		PORT67_FN1),
668 	PINMUX_DATA(SCIFB1_TXD_67_MARK,		PORT67_FN2,	MSEL3CR_11_1),
669 	PINMUX_DATA(GIO_OUT3_67_MARK,		PORT67_FN5),
670 	PINMUX_DATA(CHSCIF1_HTX_MARK,		PORT67_FN7),
671 
672 	/* Port68 */
673 	PINMUX_DATA(HSI_RX_FLAG_MARK,		PORT68_FN1),
674 	PINMUX_DATA(SCIFB2_TXD_68_MARK,		PORT68_FN2,	MSEL3CR_10_0),
675 	PINMUX_DATA(MSIOF3_TXD_MARK,		PORT68_FN3),
676 	PINMUX_DATA(GIO_OUT4_68_MARK,		PORT68_FN5),
677 
678 	/* Port69 */
679 	PINMUX_DATA(HSI_RX_DATA_MARK,		PORT69_FN1),
680 	PINMUX_DATA(SCIFB2_RXD_69_MARK,		PORT69_FN2,	MSEL3CR_10_0),
681 	PINMUX_DATA(MSIOF3_RXD_MARK,		PORT69_FN3),
682 	PINMUX_DATA(GIO_OUT5_69_MARK,		PORT69_FN5),
683 
684 	/* Port70 */
685 	PINMUX_DATA(HSI_TX_FLAG_MARK,		PORT70_FN1),
686 	PINMUX_DATA(SCIFB1_RTS_70_MARK,		PORT70_FN2),
687 	PINMUX_DATA(GIO_OUT1_70_MARK,		PORT70_FN5),
688 	PINMUX_DATA(HSIC_TSTCLK0_MARK,		PORT70_FN6),
689 	PINMUX_DATA(CHSCIF1_HRTS_MARK,		PORT70_FN7),
690 
691 	/* Port71 */
692 	PINMUX_DATA(HSI_TX_DATA_MARK,		PORT71_FN1),
693 	PINMUX_DATA(SCIFB1_CTS_71_MARK,		PORT71_FN2,	MSEL3CR_11_1),
694 	PINMUX_DATA(GIO_OUT2_71_MARK,		PORT71_FN5),
695 	PINMUX_DATA(HSIC_TSTCLK1_MARK,		PORT71_FN6),
696 	PINMUX_DATA(CHSCIF1_HCTS_MARK,		PORT71_FN7),
697 
698 	/* Port72 */
699 	PINMUX_DATA(HSI_TX_WAKE_MARK,		PORT72_FN1),
700 	PINMUX_DATA(SCIFB1_RXD_72_MARK,		PORT72_FN2,	MSEL3CR_11_1),
701 	PINMUX_DATA(GenIO8_MARK,		PORT72_FN5),
702 	PINMUX_DATA(CHSCIF1_HRX_MARK,		PORT72_FN7),
703 
704 	/* Port73 */
705 	PINMUX_DATA(HSI_TX_READY_MARK,		PORT73_FN1),
706 	PINMUX_DATA(SCIFB2_RTS_73_MARK,		PORT73_FN2),
707 	PINMUX_DATA(MSIOF3_SCK_MARK,		PORT73_FN3),
708 	PINMUX_DATA(GIO_OUT0_73_MARK,		PORT73_FN5),
709 
710 	/* Port74 - Port85 */
711 	PINMUX_DATA(IRDA_OUT_MARK,		PORT74_FN1),
712 	PINMUX_DATA(IRDA_IN_MARK,		PORT75_FN1),
713 	PINMUX_DATA(IRDA_FIRSEL_MARK,		PORT76_FN1),
714 	PINMUX_DATA(TPU0TO0_MARK,		PORT77_FN1),
715 	PINMUX_DATA(DIGRFEN_MARK,		PORT78_FN1),
716 	PINMUX_DATA(GPS_TIMESTAMP_MARK,		PORT79_FN1),
717 	PINMUX_DATA(TXP_MARK,			PORT80_FN1),
718 	PINMUX_DATA(TXP2_MARK,			PORT81_FN1),
719 	PINMUX_DATA(COEX_0_MARK,		PORT82_FN1),
720 	PINMUX_DATA(COEX_1_MARK,		PORT83_FN1),
721 	PINMUX_DATA(IRQ19_MARK,			PORT84_FN0),
722 	PINMUX_DATA(IRQ18_MARK,			PORT85_FN0),
723 
724 	/* Port96 - Port101 */
725 	PINMUX_DATA(KEYIN0_MARK,		PORT96_FN1),
726 	PINMUX_DATA(KEYIN1_MARK,		PORT97_FN1),
727 	PINMUX_DATA(KEYIN2_MARK,		PORT98_FN1),
728 	PINMUX_DATA(KEYIN3_MARK,		PORT99_FN1),
729 	PINMUX_DATA(KEYIN4_MARK,		PORT100_FN1),
730 	PINMUX_DATA(KEYIN5_MARK,		PORT101_FN1),
731 
732 	/* Port102 */
733 	PINMUX_DATA(KEYIN6_MARK,		PORT102_FN1),
734 	PINMUX_DATA(IRQ41_MARK,			PORT102_FN0),
735 
736 	/* Port103 */
737 	PINMUX_DATA(KEYIN7_MARK,		PORT103_FN1),
738 	PINMUX_DATA(IRQ42_MARK,			PORT103_FN0),
739 
740 	/* Port104 - Port108 */
741 	PINMUX_DATA(KEYOUT0_MARK,		PORT104_FN2),
742 	PINMUX_DATA(KEYOUT1_MARK,		PORT105_FN2),
743 	PINMUX_DATA(KEYOUT2_MARK,		PORT106_FN2),
744 	PINMUX_DATA(KEYOUT3_MARK,		PORT107_FN2),
745 	PINMUX_DATA(KEYOUT4_MARK,		PORT108_FN2),
746 
747 	/* Port109 */
748 	PINMUX_DATA(KEYOUT5_MARK,		PORT109_FN2),
749 	PINMUX_DATA(IRQ43_MARK,			PORT109_FN0),
750 
751 	/* Port110 */
752 	PINMUX_DATA(KEYOUT6_MARK,		PORT110_FN2),
753 	PINMUX_DATA(IRQ44_MARK,			PORT110_FN0),
754 
755 	/* Port111 */
756 	PINMUX_DATA(KEYOUT7_MARK,		PORT111_FN2),
757 	PINMUX_DATA(RFANAEN_MARK,		PORT111_FN5),
758 	PINMUX_DATA(IRQ45_MARK,			PORT111_FN0),
759 
760 	/* Port112 */
761 	PINMUX_DATA(KEYIN8_MARK,		PORT112_FN1),
762 	PINMUX_DATA(KEYOUT8_MARK,		PORT112_FN2),
763 	PINMUX_DATA(SF_IRQ_04_MARK,		PORT112_FN4),
764 	PINMUX_DATA(IRQ46_MARK,			PORT112_FN0),
765 
766 	/* Port113 */
767 	PINMUX_DATA(KEYIN9_MARK,		PORT113_FN1),
768 	PINMUX_DATA(KEYOUT9_MARK,		PORT113_FN2),
769 	PINMUX_DATA(SF_IRQ_05_MARK,		PORT113_FN4),
770 	PINMUX_DATA(IRQ47_MARK,			PORT113_FN0),
771 
772 	/* Port114 */
773 	PINMUX_DATA(KEYIN10_MARK,		PORT114_FN1),
774 	PINMUX_DATA(KEYOUT10_MARK,		PORT114_FN2),
775 	PINMUX_DATA(SF_IRQ_06_MARK,		PORT114_FN4),
776 	PINMUX_DATA(IRQ48_MARK,			PORT114_FN0),
777 
778 	/* Port115 */
779 	PINMUX_DATA(KEYIN11_MARK,		PORT115_FN1),
780 	PINMUX_DATA(KEYOUT11_MARK,		PORT115_FN2),
781 	PINMUX_DATA(SF_IRQ_07_MARK,		PORT115_FN4),
782 	PINMUX_DATA(IRQ49_MARK,			PORT115_FN0),
783 
784 	/* Port116 */
785 	PINMUX_DATA(SCIFA0_TXD_MARK,		PORT116_FN1),
786 	PINMUX_DATA(CSCIF0_TX_MARK,		PORT116_FN7),
787 
788 	/* Port117 */
789 	PINMUX_DATA(SCIFA0_RXD_MARK,		PORT117_FN1),
790 	PINMUX_DATA(CSCIF0_RX_MARK,		PORT117_FN7),
791 
792 	/* Port118 */
793 	PINMUX_DATA(SCIFA1_TXD_MARK,		PORT118_FN1),
794 	PINMUX_DATA(CSCIF1_TX_MARK,		PORT118_FN7),
795 
796 	/* Port119 */
797 	PINMUX_DATA(SCIFA1_RXD_MARK,		PORT119_FN1),
798 	PINMUX_DATA(CSCIF1_RX_MARK,		PORT119_FN7),
799 
800 	/* Port120 */
801 	PINMUX_DATA(SF_PORT_1_120_MARK,		PORT120_FN3),
802 	PINMUX_DATA(SCIFB3_RXD_120_MARK,	PORT120_FN4,	MSEL3CR_09_1),
803 	PINMUX_DATA(DU0_CDE_MARK,		PORT120_FN7),
804 
805 	/* Port121 */
806 	PINMUX_DATA(SF_PORT_0_121_MARK,		PORT121_FN3),
807 	PINMUX_DATA(SCIFB3_TXD_121_MARK,	PORT121_FN4,	MSEL3CR_09_1),
808 
809 	/* Port122 */
810 	PINMUX_DATA(SCIFB0_TXD_MARK,		PORT122_FN1),
811 	PINMUX_DATA(CHSCIF0_HTX_MARK,		PORT122_FN7),
812 
813 	/* Port123 */
814 	PINMUX_DATA(SCIFB0_RXD_MARK,		PORT123_FN1),
815 	PINMUX_DATA(CHSCIF0_HRX_MARK,		PORT123_FN7),
816 
817 	/* Port124 */
818 	PINMUX_DATA(ISP_STROBE_124_MARK,	PORT124_FN3),
819 
820 	/* Port125 */
821 	PINMUX_DATA(STP_ISD_0_MARK,		PORT125_FN1),
822 	PINMUX_DATA(PDM4_CLK_125_MARK,		PORT125_FN2),
823 	PINMUX_DATA(MSIOF2_TXD_MARK,		PORT125_FN3),
824 	PINMUX_DATA(SIM0_VOLTSEL0_MARK,		PORT125_FN5),
825 
826 	/* Port126 */
827 	PINMUX_DATA(TS_SDEN_MARK,		PORT126_FN1),
828 	PINMUX_DATA(MSIOF7_SYNC_MARK,		PORT126_FN2),
829 	PINMUX_DATA(STP_ISEN_1_MARK,		PORT126_FN3),
830 
831 	/* Port128 */
832 	PINMUX_DATA(STP_ISEN_0_MARK,		PORT128_FN1),
833 	PINMUX_DATA(PDM1_OUTDATA_128_MARK,	PORT128_FN2),
834 	PINMUX_DATA(MSIOF2_SYNC_MARK,		PORT128_FN3),
835 	PINMUX_DATA(SIM1_VOLTSEL1_MARK,		PORT128_FN5),
836 
837 	/* Port129 */
838 	PINMUX_DATA(TS_SPSYNC_MARK,		PORT129_FN1),
839 	PINMUX_DATA(MSIOF7_RXD_MARK,		PORT129_FN2),
840 	PINMUX_DATA(STP_ISSYNC_1_MARK,		PORT129_FN3),
841 
842 	/* Port130 */
843 	PINMUX_DATA(STP_ISSYNC_0_MARK,		PORT130_FN1),
844 	PINMUX_DATA(PDM4_DATA_130_MARK,		PORT130_FN2,	MSEL3CR_12_1),
845 	PINMUX_DATA(MSIOF2_RXD_MARK,		PORT130_FN3),
846 	PINMUX_DATA(SIM0_VOLTSEL1_MARK,		PORT130_FN5),
847 
848 	/* Port131 */
849 	PINMUX_DATA(STP_OPWM_0_MARK,		PORT131_FN1),
850 	PINMUX_DATA(SIM1_PWRON_MARK,		PORT131_FN5),
851 
852 	/* Port132 */
853 	PINMUX_DATA(TS_SCK_MARK,		PORT132_FN1),
854 	PINMUX_DATA(MSIOF7_SCK_MARK,		PORT132_FN2),
855 	PINMUX_DATA(STP_ISCLK_1_MARK,		PORT132_FN3),
856 
857 	/* Port133 */
858 	PINMUX_DATA(STP_ISCLK_0_MARK,		PORT133_FN1),
859 	PINMUX_DATA(PDM1_OUTCLK_133_MARK,	PORT133_FN2),
860 	PINMUX_DATA(MSIOF2_SCK_MARK,		PORT133_FN3),
861 	PINMUX_DATA(SIM1_VOLTSEL0_MARK,		PORT133_FN5),
862 
863 	/* Port134 */
864 	PINMUX_DATA(TS_SDAT_MARK,		PORT134_FN1),
865 	PINMUX_DATA(MSIOF7_TXD_MARK,		PORT134_FN2),
866 	PINMUX_DATA(STP_ISD_1_MARK,		PORT134_FN3),
867 
868 	/* Port160 - Port178 */
869 	PINMUX_DATA(IRQ20_MARK,			PORT160_FN0),
870 	PINMUX_DATA(IRQ21_MARK,			PORT161_FN0),
871 	PINMUX_DATA(IRQ22_MARK,			PORT162_FN0),
872 	PINMUX_DATA(IRQ23_MARK,			PORT163_FN0),
873 	PINMUX_DATA(MMCD0_0_MARK,		PORT164_FN1),
874 	PINMUX_DATA(MMCD0_1_MARK,		PORT165_FN1),
875 	PINMUX_DATA(MMCD0_2_MARK,		PORT166_FN1),
876 	PINMUX_DATA(MMCD0_3_MARK,		PORT167_FN1),
877 	PINMUX_DATA(MMCD0_4_MARK,		PORT168_FN1),
878 	PINMUX_DATA(MMCD0_5_MARK,		PORT169_FN1),
879 	PINMUX_DATA(MMCD0_6_MARK,		PORT170_FN1),
880 	PINMUX_DATA(MMCD0_7_MARK,		PORT171_FN1),
881 	PINMUX_DATA(MMCCMD0_MARK,		PORT172_FN1),
882 	PINMUX_DATA(MMCCLK0_MARK,		PORT173_FN1),
883 	PINMUX_DATA(MMCRST_MARK,		PORT174_FN1),
884 	PINMUX_DATA(IRQ24_MARK,			PORT175_FN0),
885 	PINMUX_DATA(IRQ25_MARK,			PORT176_FN0),
886 	PINMUX_DATA(IRQ26_MARK,			PORT177_FN0),
887 	PINMUX_DATA(IRQ27_MARK,			PORT178_FN0),
888 
889 	/* Port192 - Port200 FN1 */
890 	PINMUX_DATA(A10_MARK,		PORT192_FN1),
891 	PINMUX_DATA(A9_MARK,		PORT193_FN1),
892 	PINMUX_DATA(A8_MARK,		PORT194_FN1),
893 	PINMUX_DATA(A7_MARK,		PORT195_FN1),
894 	PINMUX_DATA(A6_MARK,		PORT196_FN1),
895 	PINMUX_DATA(A5_MARK,		PORT197_FN1),
896 	PINMUX_DATA(A4_MARK,		PORT198_FN1),
897 	PINMUX_DATA(A3_MARK,		PORT199_FN1),
898 	PINMUX_DATA(A2_MARK,		PORT200_FN1),
899 
900 	/* Port192 - Port200 FN2 */
901 	PINMUX_DATA(MMCD1_7_MARK,		PORT192_FN2),
902 	PINMUX_DATA(MMCD1_6_MARK,		PORT193_FN2),
903 	PINMUX_DATA(MMCD1_5_MARK,		PORT194_FN2),
904 	PINMUX_DATA(MMCD1_4_MARK,		PORT195_FN2),
905 	PINMUX_DATA(MMCD1_3_MARK,		PORT196_FN2),
906 	PINMUX_DATA(MMCD1_2_MARK,		PORT197_FN2),
907 	PINMUX_DATA(MMCD1_1_MARK,		PORT198_FN2),
908 	PINMUX_DATA(MMCD1_0_MARK,		PORT199_FN2),
909 	PINMUX_DATA(MMCCMD1_MARK,		PORT200_FN2),
910 
911 	/* Port192 - Port200 IRQ */
912 	PINMUX_DATA(IRQ31_MARK,			PORT192_FN0),
913 	PINMUX_DATA(IRQ32_MARK,			PORT193_FN0),
914 	PINMUX_DATA(IRQ33_MARK,			PORT194_FN0),
915 	PINMUX_DATA(IRQ34_MARK,			PORT195_FN0),
916 	PINMUX_DATA(IRQ35_MARK,			PORT196_FN0),
917 	PINMUX_DATA(IRQ36_MARK,			PORT197_FN0),
918 	PINMUX_DATA(IRQ37_MARK,			PORT198_FN0),
919 	PINMUX_DATA(IRQ38_MARK,			PORT199_FN0),
920 	PINMUX_DATA(IRQ39_MARK,			PORT200_FN0),
921 
922 	/* Port201 */
923 	PINMUX_DATA(A1_MARK,		PORT201_FN1),
924 
925 	/* Port202 */
926 	PINMUX_DATA(A0_MARK,		PORT202_FN1),
927 	PINMUX_DATA(BS_MARK,		PORT202_FN2),
928 
929 	/* Port203 */
930 	PINMUX_DATA(CKO_MARK,		PORT203_FN1),
931 	PINMUX_DATA(MMCCLK1_MARK,	PORT203_FN2),
932 
933 	/* Port204 */
934 	PINMUX_DATA(CS0_N_MARK,		PORT204_FN1),
935 	PINMUX_DATA(SIM0_GPO1_MARK,	PORT204_FN5),
936 
937 	/* Port205 */
938 	PINMUX_DATA(CS2_N_MARK,		PORT205_FN1),
939 	PINMUX_DATA(SIM0_GPO2_MARK,	PORT205_FN5),
940 
941 	/* Port206 */
942 	PINMUX_DATA(CS4_N_MARK,		PORT206_FN1),
943 	PINMUX_DATA(VIO_VD_MARK,	PORT206_FN2),
944 	PINMUX_DATA(SIM1_GPO0_MARK,	PORT206_FN5),
945 
946 	/* Port207 - Port212 FN1 */
947 	PINMUX_DATA(D15_MARK,		PORT207_FN1),
948 	PINMUX_DATA(D14_MARK,		PORT208_FN1),
949 	PINMUX_DATA(D13_MARK,		PORT209_FN1),
950 	PINMUX_DATA(D12_MARK,		PORT210_FN1),
951 	PINMUX_DATA(D11_MARK,		PORT211_FN1),
952 	PINMUX_DATA(D10_MARK,		PORT212_FN1),
953 
954 	/* Port207 - Port212 FN5 */
955 	PINMUX_DATA(GIO_OUT15_MARK,			PORT207_FN5),
956 	PINMUX_DATA(GIO_OUT14_MARK,			PORT208_FN5),
957 	PINMUX_DATA(GIO_OUT13_MARK,			PORT209_FN5),
958 	PINMUX_DATA(GIO_OUT12_MARK,			PORT210_FN5),
959 	PINMUX_DATA(WGM_TXP2_MARK,			PORT211_FN5),
960 	PINMUX_DATA(WGM_GPS_TIMEM_ASK_RFCLK_MARK,	PORT212_FN5),
961 
962 	/* Port213 - Port222 FN1 */
963 	PINMUX_DATA(D9_MARK,		PORT213_FN1),
964 	PINMUX_DATA(D8_MARK,		PORT214_FN1),
965 	PINMUX_DATA(D7_MARK,		PORT215_FN1),
966 	PINMUX_DATA(D6_MARK,		PORT216_FN1),
967 	PINMUX_DATA(D5_MARK,		PORT217_FN1),
968 	PINMUX_DATA(D4_MARK,		PORT218_FN1),
969 	PINMUX_DATA(D3_MARK,		PORT219_FN1),
970 	PINMUX_DATA(D2_MARK,		PORT220_FN1),
971 	PINMUX_DATA(D1_MARK,		PORT221_FN1),
972 	PINMUX_DATA(D0_MARK,		PORT222_FN1),
973 
974 	/* Port213 - Port222 FN2 */
975 	PINMUX_DATA(VIO_D9_MARK,	PORT213_FN2),
976 	PINMUX_DATA(VIO_D8_MARK,	PORT214_FN2),
977 	PINMUX_DATA(VIO_D7_MARK,	PORT215_FN2),
978 	PINMUX_DATA(VIO_D6_MARK,	PORT216_FN2),
979 	PINMUX_DATA(VIO_D5_MARK,	PORT217_FN2),
980 	PINMUX_DATA(VIO_D4_MARK,	PORT218_FN2),
981 	PINMUX_DATA(VIO_D3_MARK,	PORT219_FN2),
982 	PINMUX_DATA(VIO_D2_MARK,	PORT220_FN2),
983 	PINMUX_DATA(VIO_D1_MARK,	PORT221_FN2),
984 	PINMUX_DATA(VIO_D0_MARK,	PORT222_FN2),
985 
986 	/* Port213 - Port222 FN5 */
987 	PINMUX_DATA(GIO_OUT9_MARK,	PORT213_FN5),
988 	PINMUX_DATA(GIO_OUT8_MARK,	PORT214_FN5),
989 	PINMUX_DATA(GIO_OUT7_MARK,	PORT215_FN5),
990 	PINMUX_DATA(GIO_OUT6_MARK,	PORT216_FN5),
991 	PINMUX_DATA(GIO_OUT5_217_MARK,	PORT217_FN5),
992 	PINMUX_DATA(GIO_OUT4_218_MARK,	PORT218_FN5),
993 	PINMUX_DATA(GIO_OUT3_219_MARK,	PORT219_FN5),
994 	PINMUX_DATA(GIO_OUT2_220_MARK,	PORT220_FN5),
995 	PINMUX_DATA(GIO_OUT1_221_MARK,	PORT221_FN5),
996 	PINMUX_DATA(GIO_OUT0_222_MARK,	PORT222_FN5),
997 
998 	/* Port224 */
999 	PINMUX_DATA(RDWR_224_MARK,	PORT224_FN1),
1000 	PINMUX_DATA(VIO_HD_MARK,	PORT224_FN2),
1001 	PINMUX_DATA(SIM1_GPO2_MARK,	PORT224_FN5),
1002 
1003 	/* Port225 */
1004 	PINMUX_DATA(RD_N_MARK,		PORT225_FN1),
1005 
1006 	/* Port226 */
1007 	PINMUX_DATA(WAIT_N_MARK,	PORT226_FN1),
1008 	PINMUX_DATA(VIO_CLK_MARK,	PORT226_FN2),
1009 	PINMUX_DATA(SIM1_GPO1_MARK,	PORT226_FN5),
1010 
1011 	/* Port227 */
1012 	PINMUX_DATA(WE0_N_MARK,		PORT227_FN1),
1013 	PINMUX_DATA(RDWR_227_MARK,	PORT227_FN2),
1014 
1015 	/* Port228 */
1016 	PINMUX_DATA(WE1_N_MARK,		PORT228_FN1),
1017 	PINMUX_DATA(SIM0_GPO0_MARK,	PORT228_FN5),
1018 
1019 	/* Port229 */
1020 	PINMUX_DATA(PWMO_MARK,		PORT229_FN1),
1021 	PINMUX_DATA(VIO_CKO1_229_MARK,	PORT229_FN2),
1022 
1023 	/* Port230 */
1024 	PINMUX_DATA(SLIM_CLK_MARK,	PORT230_FN1),
1025 	PINMUX_DATA(VIO_CKO4_230_MARK,	PORT230_FN2),
1026 
1027 	/* Port231 */
1028 	PINMUX_DATA(SLIM_DATA_MARK,	PORT231_FN1),
1029 	PINMUX_DATA(VIO_CKO5_231_MARK,	PORT231_FN2),
1030 
1031 	/* Port232 */
1032 	PINMUX_DATA(VIO_CKO2_232_MARK,	PORT232_FN2),
1033 	PINMUX_DATA(SF_PORT_0_232_MARK,	PORT232_FN4),
1034 
1035 	/* Port233 */
1036 	PINMUX_DATA(VIO_CKO3_233_MARK,	PORT233_FN2),
1037 	PINMUX_DATA(SF_PORT_1_233_MARK,	PORT233_FN4),
1038 
1039 	/* Port234 */
1040 	PINMUX_DATA(FSIACK_MARK,	PORT234_FN1),
1041 	PINMUX_DATA(PDM3_CLK_234_MARK,	PORT234_FN2),
1042 	PINMUX_DATA(ISP_IRIS1_234_MARK,	PORT234_FN3),
1043 
1044 	/* Port235 */
1045 	PINMUX_DATA(FSIAISLD_MARK,	PORT235_FN1),
1046 	PINMUX_DATA(PDM3_DATA_235_MARK,	PORT235_FN2,	MSEL3CR_12_1),
1047 
1048 	/* Port236 */
1049 	PINMUX_DATA(FSIAOMC_MARK,		PORT236_FN1),
1050 	PINMUX_DATA(PDM0_OUTCLK_236_MARK,	PORT236_FN2),
1051 	PINMUX_DATA(ISP_IRIS0_236_MARK,		PORT236_FN3),
1052 
1053 	/* Port237 */
1054 	PINMUX_DATA(FSIAOLR_MARK,	PORT237_FN1),
1055 	PINMUX_DATA(FSIAILR_MARK,	PORT237_FN2),
1056 
1057 	/* Port238 */
1058 	PINMUX_DATA(FSIAOBT_MARK,	PORT238_FN1),
1059 	PINMUX_DATA(FSIAIBT_MARK,	PORT238_FN2),
1060 
1061 	/* Port239 */
1062 	PINMUX_DATA(FSIAOSLD_MARK,		PORT239_FN1),
1063 	PINMUX_DATA(PDM0_OUTDATA_239_MARK,	PORT239_FN2),
1064 
1065 	/* Port240 */
1066 	PINMUX_DATA(FSIBISLD_MARK,	PORT240_FN1),
1067 
1068 	/* Port241 */
1069 	PINMUX_DATA(FSIBOLR_MARK,	PORT241_FN1),
1070 	PINMUX_DATA(FSIBILR_MARK,	PORT241_FN2),
1071 
1072 	/* Port242 */
1073 	PINMUX_DATA(FSIBOMC_MARK,		PORT242_FN1),
1074 	PINMUX_DATA(ISP_SHUTTER1_242_MARK,	PORT242_FN3),
1075 
1076 	/* Port243 */
1077 	PINMUX_DATA(FSIBOBT_MARK,	PORT243_FN1),
1078 	PINMUX_DATA(FSIBIBT_MARK,	PORT243_FN2),
1079 
1080 	/* Port244 */
1081 	PINMUX_DATA(FSIBOSLD_MARK,	PORT244_FN1),
1082 	PINMUX_DATA(FSIASPDIF_MARK,	PORT244_FN2),
1083 
1084 	/* Port245 */
1085 	PINMUX_DATA(FSIBCK_MARK,		PORT245_FN1),
1086 	PINMUX_DATA(ISP_SHUTTER0_245_MARK,	PORT245_FN3),
1087 
1088 	/* Port246 - Port250 FN1 */
1089 	PINMUX_DATA(ISP_IRIS1_246_MARK,		PORT246_FN1),
1090 	PINMUX_DATA(ISP_IRIS0_247_MARK,		PORT247_FN1),
1091 	PINMUX_DATA(ISP_SHUTTER1_248_MARK,	PORT248_FN1),
1092 	PINMUX_DATA(ISP_SHUTTER0_249_MARK,	PORT249_FN1),
1093 	PINMUX_DATA(ISP_STROBE_250_MARK,	PORT250_FN1),
1094 
1095 	/* Port256 - Port258 */
1096 	PINMUX_DATA(MSIOF0_SYNC_MARK,		PORT256_FN1),
1097 	PINMUX_DATA(MSIOF0_RXD_MARK,		PORT257_FN1),
1098 	PINMUX_DATA(MSIOF0_SCK_MARK,		PORT258_FN1),
1099 
1100 	/* Port259 */
1101 	PINMUX_DATA(MSIOF0_SS2_MARK,		PORT259_FN1),
1102 	PINMUX_DATA(VIO_CKO3_259_MARK,		PORT259_FN3),
1103 
1104 	/* Port260 */
1105 	PINMUX_DATA(MSIOF0_TXD_MARK,		PORT260_FN1),
1106 
1107 	/* Port261 */
1108 	PINMUX_DATA(SCIFB1_SCK_261_MARK,	PORT261_FN2),
1109 	PINMUX_DATA(CHSCIF1_HSCK_MARK,		PORT261_FN7),
1110 
1111 	/* Port262 */
1112 	PINMUX_DATA(SCIFB2_SCK_262_MARK,	PORT262_FN2),
1113 
1114 	/* Port263 - Port266 FN1 */
1115 	PINMUX_DATA(MSIOF1_SS2_MARK,		PORT263_FN1),
1116 	PINMUX_DATA(MSIOF1_TXD_MARK,		PORT264_FN1),
1117 	PINMUX_DATA(MSIOF1_RXD_MARK,		PORT265_FN1),
1118 	PINMUX_DATA(MSIOF1_SS1_MARK,		PORT266_FN1),
1119 
1120 	/* Port263 - Port266 FN4 */
1121 	PINMUX_DATA(MSIOF5_SS2_MARK,		PORT263_FN4),
1122 	PINMUX_DATA(MSIOF5_TXD_MARK,		PORT264_FN4),
1123 	PINMUX_DATA(MSIOF5_RXD_MARK,		PORT265_FN4),
1124 	PINMUX_DATA(MSIOF5_SS1_MARK,		PORT266_FN4),
1125 
1126 	/* Port267 */
1127 	PINMUX_DATA(MSIOF0_SS1_MARK,		PORT267_FN1),
1128 
1129 	/* Port268 */
1130 	PINMUX_DATA(MSIOF1_SCK_MARK,		PORT268_FN1),
1131 	PINMUX_DATA(MSIOF5_SCK_MARK,		PORT268_FN4),
1132 
1133 	/* Port269 */
1134 	PINMUX_DATA(MSIOF1_SYNC_MARK,		PORT269_FN1),
1135 	PINMUX_DATA(MSIOF5_SYNC_MARK,		PORT269_FN4),
1136 
1137 	/* Port270 - Port273 FN1 */
1138 	PINMUX_DATA(MSIOF2_SS1_MARK,		PORT270_FN1),
1139 	PINMUX_DATA(MSIOF2_SS2_MARK,		PORT271_FN1),
1140 	PINMUX_DATA(MSIOF3_SS2_MARK,		PORT272_FN1),
1141 	PINMUX_DATA(MSIOF3_SS1_MARK,		PORT273_FN1),
1142 
1143 	/* Port270 - Port273 FN3 */
1144 	PINMUX_DATA(VIO_CKO5_270_MARK,		PORT270_FN3),
1145 	PINMUX_DATA(VIO_CKO2_271_MARK,		PORT271_FN3),
1146 	PINMUX_DATA(VIO_CKO1_272_MARK,		PORT272_FN3),
1147 	PINMUX_DATA(VIO_CKO4_273_MARK,		PORT273_FN3),
1148 
1149 	/* Port274 */
1150 	PINMUX_DATA(MSIOF4_SS2_MARK,		PORT274_FN1),
1151 	PINMUX_DATA(TPU1TO0_MARK,		PORT274_FN4),
1152 
1153 	/* Port275 - Port280 */
1154 	PINMUX_DATA(IC_DP_MARK,			PORT275_FN1),
1155 	PINMUX_DATA(SIM0_RST_MARK,		PORT276_FN1),
1156 	PINMUX_DATA(IC_DM_MARK,			PORT277_FN1),
1157 	PINMUX_DATA(SIM0_BSICOMP_MARK,		PORT278_FN1),
1158 	PINMUX_DATA(SIM0_CLK_MARK,		PORT279_FN1),
1159 	PINMUX_DATA(SIM0_IO_MARK,		PORT280_FN1),
1160 
1161 	/* Port281 */
1162 	PINMUX_DATA(SIM1_IO_MARK,		PORT281_FN1),
1163 	PINMUX_DATA(PDM2_DATA_281_MARK,		PORT281_FN2,	MSEL3CR_12_1),
1164 
1165 	/* Port282 */
1166 	PINMUX_DATA(SIM1_CLK_MARK,		PORT282_FN1),
1167 	PINMUX_DATA(PDM2_CLK_282_MARK,		PORT282_FN2),
1168 
1169 	/* Port283 */
1170 	PINMUX_DATA(SIM1_RST_MARK,		PORT283_FN1),
1171 
1172 	/* Port289 */
1173 	PINMUX_DATA(SDHID1_0_MARK,		PORT289_FN1),
1174 	PINMUX_DATA(STMDATA0_2_MARK,		PORT289_FN3),
1175 
1176 	/* Port290 */
1177 	PINMUX_DATA(SDHID1_1_MARK,		PORT290_FN1),
1178 	PINMUX_DATA(STMDATA1_2_MARK,		PORT290_FN3),
1179 	PINMUX_DATA(IRQ51_MARK,			PORT290_FN0),
1180 
1181 	/* Port291 - Port294 FN1 */
1182 	PINMUX_DATA(SDHID1_2_MARK,		PORT291_FN1),
1183 	PINMUX_DATA(SDHID1_3_MARK,		PORT292_FN1),
1184 	PINMUX_DATA(SDHICLK1_MARK,		PORT293_FN1),
1185 	PINMUX_DATA(SDHICMD1_MARK,		PORT294_FN1),
1186 
1187 	/* Port291 - Port294 FN3 */
1188 	PINMUX_DATA(STMDATA2_2_MARK,		PORT291_FN3),
1189 	PINMUX_DATA(STMDATA3_2_MARK,		PORT292_FN3),
1190 	PINMUX_DATA(STMCLK_2_MARK,		PORT293_FN3),
1191 	PINMUX_DATA(STMSIDI_2_MARK,		PORT294_FN3),
1192 
1193 	/* Port295 */
1194 	PINMUX_DATA(SDHID2_0_MARK,		PORT295_FN1),
1195 	PINMUX_DATA(MSIOF4_TXD_MARK,		PORT295_FN2),
1196 	PINMUX_DATA(SCIFB2_TXD_295_MARK,	PORT295_FN3,	MSEL3CR_10_1),
1197 	PINMUX_DATA(MSIOF6_TXD_MARK,		PORT295_FN4),
1198 
1199 	/* Port296 */
1200 	PINMUX_DATA(SDHID2_1_MARK,		PORT296_FN1),
1201 	PINMUX_DATA(MSIOF6_SS2_MARK,		PORT296_FN4),
1202 	PINMUX_DATA(IRQ52_MARK,			PORT296_FN0),
1203 
1204 	/* Port297 - Port300 FN1 */
1205 	PINMUX_DATA(SDHID2_2_MARK,		PORT297_FN1),
1206 	PINMUX_DATA(SDHID2_3_MARK,		PORT298_FN1),
1207 	PINMUX_DATA(SDHICLK2_MARK,		PORT299_FN1),
1208 	PINMUX_DATA(SDHICMD2_MARK,		PORT300_FN1),
1209 
1210 	/* Port297 - Port300 FN2 */
1211 	PINMUX_DATA(MSIOF4_RXD_MARK,		PORT297_FN2),
1212 	PINMUX_DATA(MSIOF4_SYNC_MARK,		PORT298_FN2),
1213 	PINMUX_DATA(MSIOF4_SCK_MARK,		PORT299_FN2),
1214 	PINMUX_DATA(MSIOF4_SS1_MARK,		PORT300_FN2),
1215 
1216 	/* Port297 - Port300 FN3 */
1217 	PINMUX_DATA(SCIFB2_RXD_297_MARK,	PORT297_FN3,	MSEL3CR_10_1),
1218 	PINMUX_DATA(SCIFB2_CTS_298_MARK,	PORT298_FN3,	MSEL3CR_10_1),
1219 	PINMUX_DATA(SCIFB2_SCK_299_MARK,	PORT299_FN3),
1220 	PINMUX_DATA(SCIFB2_RTS_300_MARK,	PORT300_FN3),
1221 
1222 	/* Port297 - Port300 FN4 */
1223 	PINMUX_DATA(MSIOF6_RXD_MARK,		PORT297_FN4),
1224 	PINMUX_DATA(MSIOF6_SYNC_MARK,		PORT298_FN4),
1225 	PINMUX_DATA(MSIOF6_SCK_MARK,		PORT299_FN4),
1226 	PINMUX_DATA(MSIOF6_SS1_MARK,		PORT300_FN4),
1227 
1228 	/* Port301 */
1229 	PINMUX_DATA(SDHICD0_MARK,		PORT301_FN1),
1230 	PINMUX_DATA(IRQ50_MARK,			PORT301_FN0),
1231 
1232 	/* Port302 - Port306 FN1 */
1233 	PINMUX_DATA(SDHID0_0_MARK,		PORT302_FN1),
1234 	PINMUX_DATA(SDHID0_1_MARK,		PORT303_FN1),
1235 	PINMUX_DATA(SDHID0_2_MARK,		PORT304_FN1),
1236 	PINMUX_DATA(SDHID0_3_MARK,		PORT305_FN1),
1237 	PINMUX_DATA(SDHICMD0_MARK,		PORT306_FN1),
1238 
1239 	/* Port302 - Port306 FN3 */
1240 	PINMUX_DATA(STMDATA0_1_MARK,		PORT302_FN3),
1241 	PINMUX_DATA(STMDATA1_1_MARK,		PORT303_FN3),
1242 	PINMUX_DATA(STMDATA2_1_MARK,		PORT304_FN3),
1243 	PINMUX_DATA(STMDATA3_1_MARK,		PORT305_FN3),
1244 	PINMUX_DATA(STMSIDI_1_MARK,		PORT306_FN3),
1245 
1246 	/* Port307 */
1247 	PINMUX_DATA(SDHIWP0_MARK,		PORT307_FN1),
1248 
1249 	/* Port308 */
1250 	PINMUX_DATA(SDHICLK0_MARK,		PORT308_FN1),
1251 	PINMUX_DATA(STMCLK_1_MARK,		PORT308_FN3),
1252 
1253 	/* Port320 - Port329 */
1254 	PINMUX_DATA(IRQ16_MARK,			PORT320_FN0),
1255 	PINMUX_DATA(IRQ17_MARK,			PORT321_FN0),
1256 	PINMUX_DATA(IRQ28_MARK,			PORT322_FN0),
1257 	PINMUX_DATA(IRQ29_MARK,			PORT323_FN0),
1258 	PINMUX_DATA(IRQ30_MARK,			PORT324_FN0),
1259 	PINMUX_DATA(IRQ53_MARK,			PORT325_FN0),
1260 	PINMUX_DATA(IRQ54_MARK,			PORT326_FN0),
1261 	PINMUX_DATA(IRQ55_MARK,			PORT327_FN0),
1262 	PINMUX_DATA(IRQ56_MARK,			PORT328_FN0),
1263 	PINMUX_DATA(IRQ57_MARK,			PORT329_FN0),
1264 };
1265 
1266 #define __O	(SH_PFC_PIN_CFG_OUTPUT)
1267 #define __IO	(SH_PFC_PIN_CFG_INPUT | SH_PFC_PIN_CFG_OUTPUT)
1268 #define __PUD	(SH_PFC_PIN_CFG_PULL_DOWN | SH_PFC_PIN_CFG_PULL_UP)
1269 
1270 #define R8A73A4_PIN_IO_PU_PD(pin)       SH_PFC_PIN_CFG(pin, __IO | __PUD)
1271 #define R8A73A4_PIN_O(pin)              SH_PFC_PIN_CFG(pin, __O)
1272 
1273 static const struct sh_pfc_pin pinmux_pins[] = {
1274 	R8A73A4_PIN_IO_PU_PD(0), R8A73A4_PIN_IO_PU_PD(1),
1275 	R8A73A4_PIN_IO_PU_PD(2), R8A73A4_PIN_IO_PU_PD(3),
1276 	R8A73A4_PIN_IO_PU_PD(4), R8A73A4_PIN_IO_PU_PD(5),
1277 	R8A73A4_PIN_IO_PU_PD(6), R8A73A4_PIN_IO_PU_PD(7),
1278 	R8A73A4_PIN_IO_PU_PD(8), R8A73A4_PIN_IO_PU_PD(9),
1279 	R8A73A4_PIN_IO_PU_PD(10), R8A73A4_PIN_IO_PU_PD(11),
1280 	R8A73A4_PIN_IO_PU_PD(12), R8A73A4_PIN_IO_PU_PD(13),
1281 	R8A73A4_PIN_IO_PU_PD(14), R8A73A4_PIN_IO_PU_PD(15),
1282 	R8A73A4_PIN_IO_PU_PD(16), R8A73A4_PIN_IO_PU_PD(17),
1283 	R8A73A4_PIN_IO_PU_PD(18), R8A73A4_PIN_IO_PU_PD(19),
1284 	R8A73A4_PIN_IO_PU_PD(20), R8A73A4_PIN_IO_PU_PD(21),
1285 	R8A73A4_PIN_IO_PU_PD(22), R8A73A4_PIN_IO_PU_PD(23),
1286 	R8A73A4_PIN_IO_PU_PD(24), R8A73A4_PIN_IO_PU_PD(25),
1287 	R8A73A4_PIN_IO_PU_PD(26), R8A73A4_PIN_IO_PU_PD(27),
1288 	R8A73A4_PIN_IO_PU_PD(28), R8A73A4_PIN_IO_PU_PD(29),
1289 	R8A73A4_PIN_IO_PU_PD(30),
1290 	R8A73A4_PIN_IO_PU_PD(32), R8A73A4_PIN_IO_PU_PD(33),
1291 	R8A73A4_PIN_IO_PU_PD(34), R8A73A4_PIN_IO_PU_PD(35),
1292 	R8A73A4_PIN_IO_PU_PD(36), R8A73A4_PIN_IO_PU_PD(37),
1293 	R8A73A4_PIN_IO_PU_PD(38), R8A73A4_PIN_IO_PU_PD(39),
1294 	R8A73A4_PIN_IO_PU_PD(40),
1295 	R8A73A4_PIN_IO_PU_PD(64), R8A73A4_PIN_IO_PU_PD(65),
1296 	R8A73A4_PIN_IO_PU_PD(66), R8A73A4_PIN_IO_PU_PD(67),
1297 	R8A73A4_PIN_IO_PU_PD(68), R8A73A4_PIN_IO_PU_PD(69),
1298 	R8A73A4_PIN_IO_PU_PD(70), R8A73A4_PIN_IO_PU_PD(71),
1299 	R8A73A4_PIN_IO_PU_PD(72), R8A73A4_PIN_IO_PU_PD(73),
1300 	R8A73A4_PIN_O(74), R8A73A4_PIN_IO_PU_PD(75),
1301 	R8A73A4_PIN_IO_PU_PD(76), R8A73A4_PIN_IO_PU_PD(77),
1302 	R8A73A4_PIN_IO_PU_PD(78), R8A73A4_PIN_IO_PU_PD(79),
1303 	R8A73A4_PIN_IO_PU_PD(80), R8A73A4_PIN_IO_PU_PD(81),
1304 	R8A73A4_PIN_IO_PU_PD(82), R8A73A4_PIN_IO_PU_PD(83),
1305 	R8A73A4_PIN_IO_PU_PD(84), R8A73A4_PIN_IO_PU_PD(85),
1306 	R8A73A4_PIN_IO_PU_PD(96), R8A73A4_PIN_IO_PU_PD(97),
1307 	R8A73A4_PIN_IO_PU_PD(98), R8A73A4_PIN_IO_PU_PD(99),
1308 	R8A73A4_PIN_IO_PU_PD(100), R8A73A4_PIN_IO_PU_PD(101),
1309 	R8A73A4_PIN_IO_PU_PD(102), R8A73A4_PIN_IO_PU_PD(103),
1310 	R8A73A4_PIN_IO_PU_PD(104), R8A73A4_PIN_IO_PU_PD(105),
1311 	R8A73A4_PIN_IO_PU_PD(106), R8A73A4_PIN_IO_PU_PD(107),
1312 	R8A73A4_PIN_IO_PU_PD(108), R8A73A4_PIN_IO_PU_PD(109),
1313 	R8A73A4_PIN_IO_PU_PD(110), R8A73A4_PIN_IO_PU_PD(111),
1314 	R8A73A4_PIN_IO_PU_PD(112), R8A73A4_PIN_IO_PU_PD(113),
1315 	R8A73A4_PIN_IO_PU_PD(114), R8A73A4_PIN_IO_PU_PD(115),
1316 	R8A73A4_PIN_IO_PU_PD(116), R8A73A4_PIN_IO_PU_PD(117),
1317 	R8A73A4_PIN_IO_PU_PD(118), R8A73A4_PIN_IO_PU_PD(119),
1318 	R8A73A4_PIN_IO_PU_PD(120), R8A73A4_PIN_IO_PU_PD(121),
1319 	R8A73A4_PIN_IO_PU_PD(122), R8A73A4_PIN_IO_PU_PD(123),
1320 	R8A73A4_PIN_IO_PU_PD(124), R8A73A4_PIN_IO_PU_PD(125),
1321 	R8A73A4_PIN_IO_PU_PD(126),
1322 	R8A73A4_PIN_IO_PU_PD(128), R8A73A4_PIN_IO_PU_PD(129),
1323 	R8A73A4_PIN_IO_PU_PD(130), R8A73A4_PIN_IO_PU_PD(131),
1324 	R8A73A4_PIN_IO_PU_PD(132), R8A73A4_PIN_IO_PU_PD(133),
1325 	R8A73A4_PIN_IO_PU_PD(134),
1326 	R8A73A4_PIN_IO_PU_PD(160), R8A73A4_PIN_IO_PU_PD(161),
1327 	R8A73A4_PIN_IO_PU_PD(162), R8A73A4_PIN_IO_PU_PD(163),
1328 	R8A73A4_PIN_IO_PU_PD(164), R8A73A4_PIN_IO_PU_PD(165),
1329 	R8A73A4_PIN_IO_PU_PD(166), R8A73A4_PIN_IO_PU_PD(167),
1330 	R8A73A4_PIN_IO_PU_PD(168), R8A73A4_PIN_IO_PU_PD(169),
1331 	R8A73A4_PIN_IO_PU_PD(170), R8A73A4_PIN_IO_PU_PD(171),
1332 	R8A73A4_PIN_IO_PU_PD(172), R8A73A4_PIN_IO_PU_PD(173),
1333 	R8A73A4_PIN_IO_PU_PD(174), R8A73A4_PIN_IO_PU_PD(175),
1334 	R8A73A4_PIN_IO_PU_PD(176), R8A73A4_PIN_IO_PU_PD(177),
1335 	R8A73A4_PIN_IO_PU_PD(178),
1336 	R8A73A4_PIN_IO_PU_PD(192), R8A73A4_PIN_IO_PU_PD(193),
1337 	R8A73A4_PIN_IO_PU_PD(194), R8A73A4_PIN_IO_PU_PD(195),
1338 	R8A73A4_PIN_IO_PU_PD(196), R8A73A4_PIN_IO_PU_PD(197),
1339 	R8A73A4_PIN_IO_PU_PD(198), R8A73A4_PIN_IO_PU_PD(199),
1340 	R8A73A4_PIN_IO_PU_PD(200), R8A73A4_PIN_IO_PU_PD(201),
1341 	R8A73A4_PIN_IO_PU_PD(202), R8A73A4_PIN_IO_PU_PD(203),
1342 	R8A73A4_PIN_IO_PU_PD(204), R8A73A4_PIN_IO_PU_PD(205),
1343 	R8A73A4_PIN_IO_PU_PD(206), R8A73A4_PIN_IO_PU_PD(207),
1344 	R8A73A4_PIN_IO_PU_PD(208), R8A73A4_PIN_IO_PU_PD(209),
1345 	R8A73A4_PIN_IO_PU_PD(210), R8A73A4_PIN_IO_PU_PD(211),
1346 	R8A73A4_PIN_IO_PU_PD(212), R8A73A4_PIN_IO_PU_PD(213),
1347 	R8A73A4_PIN_IO_PU_PD(214), R8A73A4_PIN_IO_PU_PD(215),
1348 	R8A73A4_PIN_IO_PU_PD(216), R8A73A4_PIN_IO_PU_PD(217),
1349 	R8A73A4_PIN_IO_PU_PD(218), R8A73A4_PIN_IO_PU_PD(219),
1350 	R8A73A4_PIN_IO_PU_PD(220), R8A73A4_PIN_IO_PU_PD(221),
1351 	R8A73A4_PIN_IO_PU_PD(222),
1352 	R8A73A4_PIN_IO_PU_PD(224), R8A73A4_PIN_IO_PU_PD(225),
1353 	R8A73A4_PIN_IO_PU_PD(226), R8A73A4_PIN_IO_PU_PD(227),
1354 	R8A73A4_PIN_IO_PU_PD(228), R8A73A4_PIN_IO_PU_PD(229),
1355 	R8A73A4_PIN_IO_PU_PD(230), R8A73A4_PIN_IO_PU_PD(231),
1356 	R8A73A4_PIN_IO_PU_PD(232), R8A73A4_PIN_IO_PU_PD(233),
1357 	R8A73A4_PIN_IO_PU_PD(234), R8A73A4_PIN_IO_PU_PD(235),
1358 	R8A73A4_PIN_IO_PU_PD(236), R8A73A4_PIN_IO_PU_PD(237),
1359 	R8A73A4_PIN_IO_PU_PD(238), R8A73A4_PIN_IO_PU_PD(239),
1360 	R8A73A4_PIN_IO_PU_PD(240), R8A73A4_PIN_IO_PU_PD(241),
1361 	R8A73A4_PIN_IO_PU_PD(242), R8A73A4_PIN_IO_PU_PD(243),
1362 	R8A73A4_PIN_IO_PU_PD(244), R8A73A4_PIN_IO_PU_PD(245),
1363 	R8A73A4_PIN_IO_PU_PD(246), R8A73A4_PIN_IO_PU_PD(247),
1364 	R8A73A4_PIN_IO_PU_PD(248), R8A73A4_PIN_IO_PU_PD(249),
1365 	R8A73A4_PIN_IO_PU_PD(250),
1366 	R8A73A4_PIN_IO_PU_PD(256), R8A73A4_PIN_IO_PU_PD(257),
1367 	R8A73A4_PIN_IO_PU_PD(258), R8A73A4_PIN_IO_PU_PD(259),
1368 	R8A73A4_PIN_IO_PU_PD(260), R8A73A4_PIN_IO_PU_PD(261),
1369 	R8A73A4_PIN_IO_PU_PD(262), R8A73A4_PIN_IO_PU_PD(263),
1370 	R8A73A4_PIN_IO_PU_PD(264), R8A73A4_PIN_IO_PU_PD(265),
1371 	R8A73A4_PIN_IO_PU_PD(266), R8A73A4_PIN_IO_PU_PD(267),
1372 	R8A73A4_PIN_IO_PU_PD(268), R8A73A4_PIN_IO_PU_PD(269),
1373 	R8A73A4_PIN_IO_PU_PD(270), R8A73A4_PIN_IO_PU_PD(271),
1374 	R8A73A4_PIN_IO_PU_PD(272), R8A73A4_PIN_IO_PU_PD(273),
1375 	R8A73A4_PIN_IO_PU_PD(274), R8A73A4_PIN_IO_PU_PD(275),
1376 	R8A73A4_PIN_IO_PU_PD(276), R8A73A4_PIN_IO_PU_PD(277),
1377 	R8A73A4_PIN_IO_PU_PD(278), R8A73A4_PIN_IO_PU_PD(279),
1378 	R8A73A4_PIN_IO_PU_PD(280), R8A73A4_PIN_IO_PU_PD(281),
1379 	R8A73A4_PIN_IO_PU_PD(282), R8A73A4_PIN_IO_PU_PD(283),
1380 	R8A73A4_PIN_O(288), R8A73A4_PIN_IO_PU_PD(289),
1381 	R8A73A4_PIN_IO_PU_PD(290), R8A73A4_PIN_IO_PU_PD(291),
1382 	R8A73A4_PIN_IO_PU_PD(292), R8A73A4_PIN_IO_PU_PD(293),
1383 	R8A73A4_PIN_IO_PU_PD(294), R8A73A4_PIN_IO_PU_PD(295),
1384 	R8A73A4_PIN_IO_PU_PD(296), R8A73A4_PIN_IO_PU_PD(297),
1385 	R8A73A4_PIN_IO_PU_PD(298), R8A73A4_PIN_IO_PU_PD(299),
1386 	R8A73A4_PIN_IO_PU_PD(300), R8A73A4_PIN_IO_PU_PD(301),
1387 	R8A73A4_PIN_IO_PU_PD(302), R8A73A4_PIN_IO_PU_PD(303),
1388 	R8A73A4_PIN_IO_PU_PD(304), R8A73A4_PIN_IO_PU_PD(305),
1389 	R8A73A4_PIN_IO_PU_PD(306), R8A73A4_PIN_IO_PU_PD(307),
1390 	R8A73A4_PIN_IO_PU_PD(308),
1391 	R8A73A4_PIN_IO_PU_PD(320), R8A73A4_PIN_IO_PU_PD(321),
1392 	R8A73A4_PIN_IO_PU_PD(322), R8A73A4_PIN_IO_PU_PD(323),
1393 	R8A73A4_PIN_IO_PU_PD(324), R8A73A4_PIN_IO_PU_PD(325),
1394 	R8A73A4_PIN_IO_PU_PD(326), R8A73A4_PIN_IO_PU_PD(327),
1395 	R8A73A4_PIN_IO_PU_PD(328), R8A73A4_PIN_IO_PU_PD(329),
1396 };
1397 
1398 /* - IRQC ------------------------------------------------------------------- */
1399 #define IRQC_PINS_MUX(pin, irq_mark)				\
1400 static const unsigned int irqc_irq##irq_mark##_pins[] = {	\
1401 	pin,							\
1402 };								\
1403 static const unsigned int irqc_irq##irq_mark##_mux[] = {	\
1404 	IRQ##irq_mark##_MARK,					\
1405 }
1406 IRQC_PINS_MUX(0, 0);
1407 IRQC_PINS_MUX(1, 1);
1408 IRQC_PINS_MUX(2, 2);
1409 IRQC_PINS_MUX(3, 3);
1410 IRQC_PINS_MUX(4, 4);
1411 IRQC_PINS_MUX(5, 5);
1412 IRQC_PINS_MUX(6, 6);
1413 IRQC_PINS_MUX(7, 7);
1414 IRQC_PINS_MUX(8, 8);
1415 IRQC_PINS_MUX(9, 9);
1416 IRQC_PINS_MUX(10, 10);
1417 IRQC_PINS_MUX(11, 11);
1418 IRQC_PINS_MUX(12, 12);
1419 IRQC_PINS_MUX(13, 13);
1420 IRQC_PINS_MUX(14, 14);
1421 IRQC_PINS_MUX(15, 15);
1422 IRQC_PINS_MUX(66, 40);
1423 IRQC_PINS_MUX(84, 19);
1424 IRQC_PINS_MUX(85, 18);
1425 IRQC_PINS_MUX(102, 41);
1426 IRQC_PINS_MUX(103, 42);
1427 IRQC_PINS_MUX(109, 43);
1428 IRQC_PINS_MUX(110, 44);
1429 IRQC_PINS_MUX(111, 45);
1430 IRQC_PINS_MUX(112, 46);
1431 IRQC_PINS_MUX(113, 47);
1432 IRQC_PINS_MUX(114, 48);
1433 IRQC_PINS_MUX(115, 49);
1434 IRQC_PINS_MUX(160, 20);
1435 IRQC_PINS_MUX(161, 21);
1436 IRQC_PINS_MUX(162, 22);
1437 IRQC_PINS_MUX(163, 23);
1438 IRQC_PINS_MUX(175, 24);
1439 IRQC_PINS_MUX(176, 25);
1440 IRQC_PINS_MUX(177, 26);
1441 IRQC_PINS_MUX(178, 27);
1442 IRQC_PINS_MUX(192, 31);
1443 IRQC_PINS_MUX(193, 32);
1444 IRQC_PINS_MUX(194, 33);
1445 IRQC_PINS_MUX(195, 34);
1446 IRQC_PINS_MUX(196, 35);
1447 IRQC_PINS_MUX(197, 36);
1448 IRQC_PINS_MUX(198, 37);
1449 IRQC_PINS_MUX(199, 38);
1450 IRQC_PINS_MUX(200, 39);
1451 IRQC_PINS_MUX(290, 51);
1452 IRQC_PINS_MUX(296, 52);
1453 IRQC_PINS_MUX(301, 50);
1454 IRQC_PINS_MUX(320, 16);
1455 IRQC_PINS_MUX(321, 17);
1456 IRQC_PINS_MUX(322, 28);
1457 IRQC_PINS_MUX(323, 29);
1458 IRQC_PINS_MUX(324, 30);
1459 IRQC_PINS_MUX(325, 53);
1460 IRQC_PINS_MUX(326, 54);
1461 IRQC_PINS_MUX(327, 55);
1462 IRQC_PINS_MUX(328, 56);
1463 IRQC_PINS_MUX(329, 57);
1464 /* - MMCIF0 ----------------------------------------------------------------- */
1465 static const unsigned int mmc0_data1_pins[] = {
1466 	/* D[0] */
1467 	164,
1468 };
1469 static const unsigned int mmc0_data1_mux[] = {
1470 	MMCD0_0_MARK,
1471 };
1472 static const unsigned int mmc0_data4_pins[] = {
1473 	/* D[0:3] */
1474 	164, 165, 166, 167,
1475 };
1476 static const unsigned int mmc0_data4_mux[] = {
1477 	MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
1478 };
1479 static const unsigned int mmc0_data8_pins[] = {
1480 	/* D[0:7] */
1481 	164, 165, 166, 167, 168, 169, 170, 171,
1482 };
1483 static const unsigned int mmc0_data8_mux[] = {
1484 	MMCD0_0_MARK, MMCD0_1_MARK, MMCD0_2_MARK, MMCD0_3_MARK,
1485 	MMCD0_4_MARK, MMCD0_5_MARK, MMCD0_6_MARK, MMCD0_7_MARK,
1486 };
1487 static const unsigned int mmc0_ctrl_pins[] = {
1488 	/* CMD, CLK */
1489 	172, 173,
1490 };
1491 static const unsigned int mmc0_ctrl_mux[] = {
1492 	MMCCMD0_MARK, MMCCLK0_MARK,
1493 };
1494 /* - MMCIF1 ----------------------------------------------------------------- */
1495 static const unsigned int mmc1_data1_pins[] = {
1496 	/* D[0] */
1497 	199,
1498 };
1499 static const unsigned int mmc1_data1_mux[] = {
1500 	MMCD1_0_MARK,
1501 };
1502 static const unsigned int mmc1_data4_pins[] = {
1503 	/* D[0:3] */
1504 	199, 198, 197, 196,
1505 };
1506 static const unsigned int mmc1_data4_mux[] = {
1507 	MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
1508 };
1509 static const unsigned int mmc1_data8_pins[] = {
1510 	/* D[0:7] */
1511 	199, 198, 197, 196, 195, 194, 193, 192,
1512 };
1513 static const unsigned int mmc1_data8_mux[] = {
1514 	MMCD1_0_MARK, MMCD1_1_MARK, MMCD1_2_MARK, MMCD1_3_MARK,
1515 	MMCD1_4_MARK, MMCD1_5_MARK, MMCD1_6_MARK, MMCD1_7_MARK,
1516 };
1517 static const unsigned int mmc1_ctrl_pins[] = {
1518 	/* CMD, CLK */
1519 	200, 203,
1520 };
1521 static const unsigned int mmc1_ctrl_mux[] = {
1522 	MMCCMD1_MARK, MMCCLK1_MARK,
1523 };
1524 /* - SCIFA0 ----------------------------------------------------------------- */
1525 static const unsigned int scifa0_data_pins[] = {
1526 	/* SCIFA0_RXD, SCIFA0_TXD */
1527 	117, 116,
1528 };
1529 static const unsigned int scifa0_data_mux[] = {
1530 	SCIFA0_RXD_MARK, SCIFA0_TXD_MARK,
1531 };
1532 static const unsigned int scifa0_clk_pins[] = {
1533 	/* SCIFA0_SCK */
1534 	34,
1535 };
1536 static const unsigned int scifa0_clk_mux[] = {
1537 	SCIFA0_SCK_MARK,
1538 };
1539 static const unsigned int scifa0_ctrl_pins[] = {
1540 	/* SCIFA0_RTS, SCIFA0_CTS */
1541 	32, 33,
1542 };
1543 static const unsigned int scifa0_ctrl_mux[] = {
1544 	SCIFA0_RTS_MARK, SCIFA0_CTS_MARK,
1545 };
1546 /* - SCIFA1 ----------------------------------------------------------------- */
1547 static const unsigned int scifa1_data_pins[] = {
1548 	/* SCIFA1_RXD, SCIFA1_TXD */
1549 	119, 118,
1550 };
1551 static const unsigned int scifa1_data_mux[] = {
1552 	SCIFA1_RXD_MARK, SCIFA1_TXD_MARK,
1553 };
1554 static const unsigned int scifa1_clk_pins[] = {
1555 	/* SCIFA1_SCK */
1556 	37,
1557 };
1558 static const unsigned int scifa1_clk_mux[] = {
1559 	SCIFA1_SCK_MARK,
1560 };
1561 static const unsigned int scifa1_ctrl_pins[] = {
1562 	/* SCIFA1_RTS, SCIFA1_CTS */
1563 	35, 36,
1564 };
1565 static const unsigned int scifa1_ctrl_mux[] = {
1566 	SCIFA1_RTS_MARK, SCIFA1_CTS_MARK,
1567 };
1568 /* - SCIFB0 ----------------------------------------------------------------- */
1569 static const unsigned int scifb0_data_pins[] = {
1570 	/* SCIFB0_RXD, SCIFB0_TXD */
1571 	123, 122,
1572 };
1573 static const unsigned int scifb0_data_mux[] = {
1574 	SCIFB0_RXD_MARK, SCIFB0_TXD_MARK,
1575 };
1576 static const unsigned int scifb0_clk_pins[] = {
1577 	/* SCIFB0_SCK */
1578 	40,
1579 };
1580 static const unsigned int scifb0_clk_mux[] = {
1581 	SCIFB0_SCK_MARK,
1582 };
1583 static const unsigned int scifb0_ctrl_pins[] = {
1584 	/* SCIFB0_RTS, SCIFB0_CTS */
1585 	38, 39,
1586 };
1587 static const unsigned int scifb0_ctrl_mux[] = {
1588 	SCIFB0_RTS_MARK, SCIFB0_CTS_MARK,
1589 };
1590 /* - SCIFB1 ----------------------------------------------------------------- */
1591 static const unsigned int scifb1_data_pins[] = {
1592 	/* SCIFB1_RXD, SCIFB1_TXD */
1593 	27, 26,
1594 };
1595 static const unsigned int scifb1_data_mux[] = {
1596 	SCIFB1_RXD_27_MARK, SCIFB1_TXD_26_MARK,
1597 };
1598 static const unsigned int scifb1_clk_pins[] = {
1599 	/* SCIFB1_SCK */
1600 	28,
1601 };
1602 static const unsigned int scifb1_clk_mux[] = {
1603 	SCIFB1_SCK_28_MARK,
1604 };
1605 static const unsigned int scifb1_ctrl_pins[] = {
1606 	/* SCIFB1_RTS, SCIFB1_CTS */
1607 	24, 25,
1608 };
1609 static const unsigned int scifb1_ctrl_mux[] = {
1610 	SCIFB1_RTS_24_MARK, SCIFB1_CTS_25_MARK,
1611 };
1612 static const unsigned int scifb1_data_b_pins[] = {
1613 	/* SCIFB1_RXD, SCIFB1_TXD */
1614 	72, 67,
1615 };
1616 static const unsigned int scifb1_data_b_mux[] = {
1617 	SCIFB1_RXD_72_MARK, SCIFB1_TXD_67_MARK,
1618 };
1619 static const unsigned int scifb1_clk_b_pins[] = {
1620 	/* SCIFB1_SCK */
1621 	261,
1622 };
1623 static const unsigned int scifb1_clk_b_mux[] = {
1624 	SCIFB1_SCK_261_MARK,
1625 };
1626 static const unsigned int scifb1_ctrl_b_pins[] = {
1627 	/* SCIFB1_RTS, SCIFB1_CTS */
1628 	70, 71,
1629 };
1630 static const unsigned int scifb1_ctrl_b_mux[] = {
1631 	SCIFB1_RTS_70_MARK, SCIFB1_CTS_71_MARK,
1632 };
1633 /* - SCIFB2 ----------------------------------------------------------------- */
1634 static const unsigned int scifb2_data_pins[] = {
1635 	/* SCIFB2_RXD, SCIFB2_TXD */
1636 	69, 68,
1637 };
1638 static const unsigned int scifb2_data_mux[] = {
1639 	SCIFB2_RXD_69_MARK, SCIFB2_TXD_68_MARK,
1640 };
1641 static const unsigned int scifb2_clk_pins[] = {
1642 	/* SCIFB2_SCK */
1643 	262,
1644 };
1645 static const unsigned int scifb2_clk_mux[] = {
1646 	SCIFB2_SCK_262_MARK,
1647 };
1648 static const unsigned int scifb2_ctrl_pins[] = {
1649 	/* SCIFB2_RTS, SCIFB2_CTS */
1650 	73, 66,
1651 };
1652 static const unsigned int scifb2_ctrl_mux[] = {
1653 	SCIFB2_RTS_73_MARK, SCIFB2_CTS_66_MARK,
1654 };
1655 static const unsigned int scifb2_data_b_pins[] = {
1656 	/* SCIFB2_RXD, SCIFB2_TXD */
1657 	297, 295,
1658 };
1659 static const unsigned int scifb2_data_b_mux[] = {
1660 	SCIFB2_RXD_297_MARK, SCIFB2_TXD_295_MARK,
1661 };
1662 static const unsigned int scifb2_clk_b_pins[] = {
1663 	/* SCIFB2_SCK */
1664 	299,
1665 };
1666 static const unsigned int scifb2_clk_b_mux[] = {
1667 	SCIFB2_SCK_299_MARK,
1668 };
1669 static const unsigned int scifb2_ctrl_b_pins[] = {
1670 	/* SCIFB2_RTS, SCIFB2_CTS */
1671 	300, 298,
1672 };
1673 static const unsigned int scifb2_ctrl_b_mux[] = {
1674 	SCIFB2_RTS_300_MARK, SCIFB2_CTS_298_MARK,
1675 };
1676 /* - SCIFB3 ----------------------------------------------------------------- */
1677 static const unsigned int scifb3_data_pins[] = {
1678 	/* SCIFB3_RXD, SCIFB3_TXD */
1679 	22, 21,
1680 };
1681 static const unsigned int scifb3_data_mux[] = {
1682 	SCIFB3_RXD_22_MARK, SCIFB3_TXD_21_MARK,
1683 };
1684 static const unsigned int scifb3_clk_pins[] = {
1685 	/* SCIFB3_SCK */
1686 	23,
1687 };
1688 static const unsigned int scifb3_clk_mux[] = {
1689 	SCIFB3_SCK_23_MARK,
1690 };
1691 static const unsigned int scifb3_ctrl_pins[] = {
1692 	/* SCIFB3_RTS, SCIFB3_CTS */
1693 	19, 20,
1694 };
1695 static const unsigned int scifb3_ctrl_mux[] = {
1696 	SCIFB3_RTS_19_MARK, SCIFB3_CTS_20_MARK,
1697 };
1698 static const unsigned int scifb3_data_b_pins[] = {
1699 	/* SCIFB3_RXD, SCIFB3_TXD */
1700 	120, 121,
1701 };
1702 static const unsigned int scifb3_data_b_mux[] = {
1703 	SCIFB3_RXD_120_MARK, SCIFB3_TXD_121_MARK,
1704 };
1705 static const unsigned int scifb3_clk_b_pins[] = {
1706 	/* SCIFB3_SCK */
1707 	40,
1708 };
1709 static const unsigned int scifb3_clk_b_mux[] = {
1710 	SCIFB3_SCK_40_MARK,
1711 };
1712 static const unsigned int scifb3_ctrl_b_pins[] = {
1713 	/* SCIFB3_RTS, SCIFB3_CTS */
1714 	38, 39,
1715 };
1716 static const unsigned int scifb3_ctrl_b_mux[] = {
1717 	SCIFB3_RTS_38_MARK, SCIFB3_CTS_39_MARK,
1718 };
1719 /* - SDHI0 ------------------------------------------------------------------ */
1720 static const unsigned int sdhi0_data1_pins[] = {
1721 	/* D0 */
1722 	302,
1723 };
1724 static const unsigned int sdhi0_data1_mux[] = {
1725 	SDHID0_0_MARK,
1726 };
1727 static const unsigned int sdhi0_data4_pins[] = {
1728 	/* D[0:3] */
1729 	302, 303, 304, 305,
1730 };
1731 static const unsigned int sdhi0_data4_mux[] = {
1732 	SDHID0_0_MARK, SDHID0_1_MARK, SDHID0_2_MARK, SDHID0_3_MARK,
1733 };
1734 static const unsigned int sdhi0_ctrl_pins[] = {
1735 	/* CLK, CMD */
1736 	308, 306,
1737 };
1738 static const unsigned int sdhi0_ctrl_mux[] = {
1739 	SDHICLK0_MARK, SDHICMD0_MARK,
1740 };
1741 static const unsigned int sdhi0_cd_pins[] = {
1742 	/* CD */
1743 	301,
1744 };
1745 static const unsigned int sdhi0_cd_mux[] = {
1746 	SDHICD0_MARK,
1747 };
1748 static const unsigned int sdhi0_wp_pins[] = {
1749 	/* WP */
1750 	307,
1751 };
1752 static const unsigned int sdhi0_wp_mux[] = {
1753 	SDHIWP0_MARK,
1754 };
1755 /* - SDHI1 ------------------------------------------------------------------ */
1756 static const unsigned int sdhi1_data1_pins[] = {
1757 	/* D0 */
1758 	289,
1759 };
1760 static const unsigned int sdhi1_data1_mux[] = {
1761 	SDHID1_0_MARK,
1762 };
1763 static const unsigned int sdhi1_data4_pins[] = {
1764 	/* D[0:3] */
1765 	289, 290, 291, 292,
1766 };
1767 static const unsigned int sdhi1_data4_mux[] = {
1768 	SDHID1_0_MARK, SDHID1_1_MARK, SDHID1_2_MARK, SDHID1_3_MARK,
1769 };
1770 static const unsigned int sdhi1_ctrl_pins[] = {
1771 	/* CLK, CMD */
1772 	293, 294,
1773 };
1774 static const unsigned int sdhi1_ctrl_mux[] = {
1775 	SDHICLK1_MARK, SDHICMD1_MARK,
1776 };
1777 /* - SDHI2 ------------------------------------------------------------------ */
1778 static const unsigned int sdhi2_data1_pins[] = {
1779 	/* D0 */
1780 	295,
1781 };
1782 static const unsigned int sdhi2_data1_mux[] = {
1783 	SDHID2_0_MARK,
1784 };
1785 static const unsigned int sdhi2_data4_pins[] = {
1786 	/* D[0:3] */
1787 	295, 296, 297, 298,
1788 };
1789 static const unsigned int sdhi2_data4_mux[] = {
1790 	SDHID2_0_MARK, SDHID2_1_MARK, SDHID2_2_MARK, SDHID2_3_MARK,
1791 };
1792 static const unsigned int sdhi2_ctrl_pins[] = {
1793 	/* CLK, CMD */
1794 	299, 300,
1795 };
1796 static const unsigned int sdhi2_ctrl_mux[] = {
1797 	SDHICLK2_MARK, SDHICMD2_MARK,
1798 };
1799 
1800 static const struct sh_pfc_pin_group pinmux_groups[] = {
1801 	SH_PFC_PIN_GROUP(irqc_irq0),
1802 	SH_PFC_PIN_GROUP(irqc_irq1),
1803 	SH_PFC_PIN_GROUP(irqc_irq2),
1804 	SH_PFC_PIN_GROUP(irqc_irq3),
1805 	SH_PFC_PIN_GROUP(irqc_irq4),
1806 	SH_PFC_PIN_GROUP(irqc_irq5),
1807 	SH_PFC_PIN_GROUP(irqc_irq6),
1808 	SH_PFC_PIN_GROUP(irqc_irq7),
1809 	SH_PFC_PIN_GROUP(irqc_irq8),
1810 	SH_PFC_PIN_GROUP(irqc_irq9),
1811 	SH_PFC_PIN_GROUP(irqc_irq10),
1812 	SH_PFC_PIN_GROUP(irqc_irq11),
1813 	SH_PFC_PIN_GROUP(irqc_irq12),
1814 	SH_PFC_PIN_GROUP(irqc_irq13),
1815 	SH_PFC_PIN_GROUP(irqc_irq14),
1816 	SH_PFC_PIN_GROUP(irqc_irq15),
1817 	SH_PFC_PIN_GROUP(irqc_irq16),
1818 	SH_PFC_PIN_GROUP(irqc_irq17),
1819 	SH_PFC_PIN_GROUP(irqc_irq18),
1820 	SH_PFC_PIN_GROUP(irqc_irq19),
1821 	SH_PFC_PIN_GROUP(irqc_irq20),
1822 	SH_PFC_PIN_GROUP(irqc_irq21),
1823 	SH_PFC_PIN_GROUP(irqc_irq22),
1824 	SH_PFC_PIN_GROUP(irqc_irq23),
1825 	SH_PFC_PIN_GROUP(irqc_irq24),
1826 	SH_PFC_PIN_GROUP(irqc_irq25),
1827 	SH_PFC_PIN_GROUP(irqc_irq26),
1828 	SH_PFC_PIN_GROUP(irqc_irq27),
1829 	SH_PFC_PIN_GROUP(irqc_irq28),
1830 	SH_PFC_PIN_GROUP(irqc_irq29),
1831 	SH_PFC_PIN_GROUP(irqc_irq30),
1832 	SH_PFC_PIN_GROUP(irqc_irq31),
1833 	SH_PFC_PIN_GROUP(irqc_irq32),
1834 	SH_PFC_PIN_GROUP(irqc_irq33),
1835 	SH_PFC_PIN_GROUP(irqc_irq34),
1836 	SH_PFC_PIN_GROUP(irqc_irq35),
1837 	SH_PFC_PIN_GROUP(irqc_irq36),
1838 	SH_PFC_PIN_GROUP(irqc_irq37),
1839 	SH_PFC_PIN_GROUP(irqc_irq38),
1840 	SH_PFC_PIN_GROUP(irqc_irq39),
1841 	SH_PFC_PIN_GROUP(irqc_irq40),
1842 	SH_PFC_PIN_GROUP(irqc_irq41),
1843 	SH_PFC_PIN_GROUP(irqc_irq42),
1844 	SH_PFC_PIN_GROUP(irqc_irq43),
1845 	SH_PFC_PIN_GROUP(irqc_irq44),
1846 	SH_PFC_PIN_GROUP(irqc_irq45),
1847 	SH_PFC_PIN_GROUP(irqc_irq46),
1848 	SH_PFC_PIN_GROUP(irqc_irq47),
1849 	SH_PFC_PIN_GROUP(irqc_irq48),
1850 	SH_PFC_PIN_GROUP(irqc_irq49),
1851 	SH_PFC_PIN_GROUP(irqc_irq50),
1852 	SH_PFC_PIN_GROUP(irqc_irq51),
1853 	SH_PFC_PIN_GROUP(irqc_irq52),
1854 	SH_PFC_PIN_GROUP(irqc_irq53),
1855 	SH_PFC_PIN_GROUP(irqc_irq54),
1856 	SH_PFC_PIN_GROUP(irqc_irq55),
1857 	SH_PFC_PIN_GROUP(irqc_irq56),
1858 	SH_PFC_PIN_GROUP(irqc_irq57),
1859 	SH_PFC_PIN_GROUP(mmc0_data1),
1860 	SH_PFC_PIN_GROUP(mmc0_data4),
1861 	SH_PFC_PIN_GROUP(mmc0_data8),
1862 	SH_PFC_PIN_GROUP(mmc0_ctrl),
1863 	SH_PFC_PIN_GROUP(mmc1_data1),
1864 	SH_PFC_PIN_GROUP(mmc1_data4),
1865 	SH_PFC_PIN_GROUP(mmc1_data8),
1866 	SH_PFC_PIN_GROUP(mmc1_ctrl),
1867 	SH_PFC_PIN_GROUP(scifa0_data),
1868 	SH_PFC_PIN_GROUP(scifa0_clk),
1869 	SH_PFC_PIN_GROUP(scifa0_ctrl),
1870 	SH_PFC_PIN_GROUP(scifa1_data),
1871 	SH_PFC_PIN_GROUP(scifa1_clk),
1872 	SH_PFC_PIN_GROUP(scifa1_ctrl),
1873 	SH_PFC_PIN_GROUP(scifb0_data),
1874 	SH_PFC_PIN_GROUP(scifb0_clk),
1875 	SH_PFC_PIN_GROUP(scifb0_ctrl),
1876 	SH_PFC_PIN_GROUP(scifb1_data),
1877 	SH_PFC_PIN_GROUP(scifb1_clk),
1878 	SH_PFC_PIN_GROUP(scifb1_ctrl),
1879 	SH_PFC_PIN_GROUP(scifb1_data_b),
1880 	SH_PFC_PIN_GROUP(scifb1_clk_b),
1881 	SH_PFC_PIN_GROUP(scifb1_ctrl_b),
1882 	SH_PFC_PIN_GROUP(scifb2_data),
1883 	SH_PFC_PIN_GROUP(scifb2_clk),
1884 	SH_PFC_PIN_GROUP(scifb2_ctrl),
1885 	SH_PFC_PIN_GROUP(scifb2_data_b),
1886 	SH_PFC_PIN_GROUP(scifb2_clk_b),
1887 	SH_PFC_PIN_GROUP(scifb2_ctrl_b),
1888 	SH_PFC_PIN_GROUP(scifb3_data),
1889 	SH_PFC_PIN_GROUP(scifb3_clk),
1890 	SH_PFC_PIN_GROUP(scifb3_ctrl),
1891 	SH_PFC_PIN_GROUP(scifb3_data_b),
1892 	SH_PFC_PIN_GROUP(scifb3_clk_b),
1893 	SH_PFC_PIN_GROUP(scifb3_ctrl_b),
1894 	SH_PFC_PIN_GROUP(sdhi0_data1),
1895 	SH_PFC_PIN_GROUP(sdhi0_data4),
1896 	SH_PFC_PIN_GROUP(sdhi0_ctrl),
1897 	SH_PFC_PIN_GROUP(sdhi0_cd),
1898 	SH_PFC_PIN_GROUP(sdhi0_wp),
1899 	SH_PFC_PIN_GROUP(sdhi1_data1),
1900 	SH_PFC_PIN_GROUP(sdhi1_data4),
1901 	SH_PFC_PIN_GROUP(sdhi1_ctrl),
1902 	SH_PFC_PIN_GROUP(sdhi2_data1),
1903 	SH_PFC_PIN_GROUP(sdhi2_data4),
1904 	SH_PFC_PIN_GROUP(sdhi2_ctrl),
1905 };
1906 
1907 static const char * const irqc_groups[] = {
1908 	"irqc_irq0",
1909 	"irqc_irq1",
1910 	"irqc_irq2",
1911 	"irqc_irq3",
1912 	"irqc_irq4",
1913 	"irqc_irq5",
1914 	"irqc_irq6",
1915 	"irqc_irq7",
1916 	"irqc_irq8",
1917 	"irqc_irq9",
1918 	"irqc_irq10",
1919 	"irqc_irq11",
1920 	"irqc_irq12",
1921 	"irqc_irq13",
1922 	"irqc_irq14",
1923 	"irqc_irq15",
1924 	"irqc_irq16",
1925 	"irqc_irq17",
1926 	"irqc_irq18",
1927 	"irqc_irq19",
1928 	"irqc_irq20",
1929 	"irqc_irq21",
1930 	"irqc_irq22",
1931 	"irqc_irq23",
1932 	"irqc_irq24",
1933 	"irqc_irq25",
1934 	"irqc_irq26",
1935 	"irqc_irq27",
1936 	"irqc_irq28",
1937 	"irqc_irq29",
1938 	"irqc_irq30",
1939 	"irqc_irq31",
1940 	"irqc_irq32",
1941 	"irqc_irq33",
1942 	"irqc_irq34",
1943 	"irqc_irq35",
1944 	"irqc_irq36",
1945 	"irqc_irq37",
1946 	"irqc_irq38",
1947 	"irqc_irq39",
1948 	"irqc_irq40",
1949 	"irqc_irq41",
1950 	"irqc_irq42",
1951 	"irqc_irq43",
1952 	"irqc_irq44",
1953 	"irqc_irq45",
1954 	"irqc_irq46",
1955 	"irqc_irq47",
1956 	"irqc_irq48",
1957 	"irqc_irq49",
1958 	"irqc_irq50",
1959 	"irqc_irq51",
1960 	"irqc_irq52",
1961 	"irqc_irq53",
1962 	"irqc_irq54",
1963 	"irqc_irq55",
1964 	"irqc_irq56",
1965 	"irqc_irq57",
1966 };
1967 
1968 static const char * const mmc0_groups[] = {
1969 	"mmc0_data1",
1970 	"mmc0_data4",
1971 	"mmc0_data8",
1972 	"mmc0_ctrl",
1973 };
1974 
1975 static const char * const mmc1_groups[] = {
1976 	"mmc1_data1",
1977 	"mmc1_data4",
1978 	"mmc1_data8",
1979 	"mmc1_ctrl",
1980 };
1981 
1982 static const char * const scifa0_groups[] = {
1983 	"scifa0_data",
1984 	"scifa0_clk",
1985 	"scifa0_ctrl",
1986 };
1987 
1988 static const char * const scifa1_groups[] = {
1989 	"scifa1_data",
1990 	"scifa1_clk",
1991 	"scifa1_ctrl",
1992 };
1993 
1994 static const char * const scifb0_groups[] = {
1995 	"scifb0_data",
1996 	"scifb0_clk",
1997 	"scifb0_ctrl",
1998 };
1999 
2000 static const char * const scifb1_groups[] = {
2001 	"scifb1_data",
2002 	"scifb1_clk",
2003 	"scifb1_ctrl",
2004 	"scifb1_data_b",
2005 	"scifb1_clk_b",
2006 	"scifb1_ctrl_b",
2007 };
2008 
2009 static const char * const scifb2_groups[] = {
2010 	"scifb2_data",
2011 	"scifb2_clk",
2012 	"scifb2_ctrl",
2013 	"scifb2_data_b",
2014 	"scifb2_clk_b",
2015 	"scifb2_ctrl_b",
2016 };
2017 
2018 static const char * const scifb3_groups[] = {
2019 	"scifb3_data",
2020 	"scifb3_clk",
2021 	"scifb3_ctrl",
2022 	"scifb3_data_b",
2023 	"scifb3_clk_b",
2024 	"scifb3_ctrl_b",
2025 };
2026 
2027 static const char * const sdhi0_groups[] = {
2028 	"sdhi0_data1",
2029 	"sdhi0_data4",
2030 	"sdhi0_ctrl",
2031 	"sdhi0_cd",
2032 	"sdhi0_wp",
2033 };
2034 
2035 static const char * const sdhi1_groups[] = {
2036 	"sdhi1_data1",
2037 	"sdhi1_data4",
2038 	"sdhi1_ctrl",
2039 };
2040 
2041 static const char * const sdhi2_groups[] = {
2042 	"sdhi2_data1",
2043 	"sdhi2_data4",
2044 	"sdhi2_ctrl",
2045 };
2046 
2047 static const struct sh_pfc_function pinmux_functions[] = {
2048 	SH_PFC_FUNCTION(irqc),
2049 	SH_PFC_FUNCTION(mmc0),
2050 	SH_PFC_FUNCTION(mmc1),
2051 	SH_PFC_FUNCTION(scifa0),
2052 	SH_PFC_FUNCTION(scifa1),
2053 	SH_PFC_FUNCTION(scifb0),
2054 	SH_PFC_FUNCTION(scifb1),
2055 	SH_PFC_FUNCTION(scifb2),
2056 	SH_PFC_FUNCTION(scifb3),
2057 	SH_PFC_FUNCTION(sdhi0),
2058 	SH_PFC_FUNCTION(sdhi1),
2059 	SH_PFC_FUNCTION(sdhi2),
2060 };
2061 
2062 static const struct pinmux_cfg_reg pinmux_config_regs[] = {
2063 	PORTCR(0, 0xe6050000),
2064 	PORTCR(1, 0xe6050001),
2065 	PORTCR(2, 0xe6050002),
2066 	PORTCR(3, 0xe6050003),
2067 	PORTCR(4, 0xe6050004),
2068 	PORTCR(5, 0xe6050005),
2069 	PORTCR(6, 0xe6050006),
2070 	PORTCR(7, 0xe6050007),
2071 	PORTCR(8, 0xe6050008),
2072 	PORTCR(9, 0xe6050009),
2073 	PORTCR(10, 0xe605000A),
2074 	PORTCR(11, 0xe605000B),
2075 	PORTCR(12, 0xe605000C),
2076 	PORTCR(13, 0xe605000D),
2077 	PORTCR(14, 0xe605000E),
2078 	PORTCR(15, 0xe605000F),
2079 	PORTCR(16, 0xe6050010),
2080 	PORTCR(17, 0xe6050011),
2081 	PORTCR(18, 0xe6050012),
2082 	PORTCR(19, 0xe6050013),
2083 	PORTCR(20, 0xe6050014),
2084 	PORTCR(21, 0xe6050015),
2085 	PORTCR(22, 0xe6050016),
2086 	PORTCR(23, 0xe6050017),
2087 	PORTCR(24, 0xe6050018),
2088 	PORTCR(25, 0xe6050019),
2089 	PORTCR(26, 0xe605001A),
2090 	PORTCR(27, 0xe605001B),
2091 	PORTCR(28, 0xe605001C),
2092 	PORTCR(29, 0xe605001D),
2093 	PORTCR(30, 0xe605001E),
2094 	PORTCR(32, 0xe6051020),
2095 	PORTCR(33, 0xe6051021),
2096 	PORTCR(34, 0xe6051022),
2097 	PORTCR(35, 0xe6051023),
2098 	PORTCR(36, 0xe6051024),
2099 	PORTCR(37, 0xe6051025),
2100 	PORTCR(38, 0xe6051026),
2101 	PORTCR(39, 0xe6051027),
2102 	PORTCR(40, 0xe6051028),
2103 	PORTCR(64, 0xe6050040),
2104 	PORTCR(65, 0xe6050041),
2105 	PORTCR(66, 0xe6050042),
2106 	PORTCR(67, 0xe6050043),
2107 	PORTCR(68, 0xe6050044),
2108 	PORTCR(69, 0xe6050045),
2109 	PORTCR(70, 0xe6050046),
2110 	PORTCR(71, 0xe6050047),
2111 	PORTCR(72, 0xe6050048),
2112 	PORTCR(73, 0xe6050049),
2113 	PORTCR(74, 0xe605004A),
2114 	PORTCR(75, 0xe605004B),
2115 	PORTCR(76, 0xe605004C),
2116 	PORTCR(77, 0xe605004D),
2117 	PORTCR(78, 0xe605004E),
2118 	PORTCR(79, 0xe605004F),
2119 	PORTCR(80, 0xe6050050),
2120 	PORTCR(81, 0xe6050051),
2121 	PORTCR(82, 0xe6050052),
2122 	PORTCR(83, 0xe6050053),
2123 	PORTCR(84, 0xe6050054),
2124 	PORTCR(85, 0xe6050055),
2125 	PORTCR(96, 0xe6051060),
2126 	PORTCR(97, 0xe6051061),
2127 	PORTCR(98, 0xe6051062),
2128 	PORTCR(99, 0xe6051063),
2129 	PORTCR(100, 0xe6051064),
2130 	PORTCR(101, 0xe6051065),
2131 	PORTCR(102, 0xe6051066),
2132 	PORTCR(103, 0xe6051067),
2133 	PORTCR(104, 0xe6051068),
2134 	PORTCR(105, 0xe6051069),
2135 	PORTCR(106, 0xe605106A),
2136 	PORTCR(107, 0xe605106B),
2137 	PORTCR(108, 0xe605106C),
2138 	PORTCR(109, 0xe605106D),
2139 	PORTCR(110, 0xe605106E),
2140 	PORTCR(111, 0xe605106F),
2141 	PORTCR(112, 0xe6051070),
2142 	PORTCR(113, 0xe6051071),
2143 	PORTCR(114, 0xe6051072),
2144 	PORTCR(115, 0xe6051073),
2145 	PORTCR(116, 0xe6051074),
2146 	PORTCR(117, 0xe6051075),
2147 	PORTCR(118, 0xe6051076),
2148 	PORTCR(119, 0xe6051077),
2149 	PORTCR(120, 0xe6051078),
2150 	PORTCR(121, 0xe6051079),
2151 	PORTCR(122, 0xe605107A),
2152 	PORTCR(123, 0xe605107B),
2153 	PORTCR(124, 0xe605107C),
2154 	PORTCR(125, 0xe605107D),
2155 	PORTCR(126, 0xe605107E),
2156 	PORTCR(128, 0xe6051080),
2157 	PORTCR(129, 0xe6051081),
2158 	PORTCR(130, 0xe6051082),
2159 	PORTCR(131, 0xe6051083),
2160 	PORTCR(132, 0xe6051084),
2161 	PORTCR(133, 0xe6051085),
2162 	PORTCR(134, 0xe6051086),
2163 	PORTCR(160, 0xe60520A0),
2164 	PORTCR(161, 0xe60520A1),
2165 	PORTCR(162, 0xe60520A2),
2166 	PORTCR(163, 0xe60520A3),
2167 	PORTCR(164, 0xe60520A4),
2168 	PORTCR(165, 0xe60520A5),
2169 	PORTCR(166, 0xe60520A6),
2170 	PORTCR(167, 0xe60520A7),
2171 	PORTCR(168, 0xe60520A8),
2172 	PORTCR(169, 0xe60520A9),
2173 	PORTCR(170, 0xe60520AA),
2174 	PORTCR(171, 0xe60520AB),
2175 	PORTCR(172, 0xe60520AC),
2176 	PORTCR(173, 0xe60520AD),
2177 	PORTCR(174, 0xe60520AE),
2178 	PORTCR(175, 0xe60520AF),
2179 	PORTCR(176, 0xe60520B0),
2180 	PORTCR(177, 0xe60520B1),
2181 	PORTCR(178, 0xe60520B2),
2182 	PORTCR(192, 0xe60520C0),
2183 	PORTCR(193, 0xe60520C1),
2184 	PORTCR(194, 0xe60520C2),
2185 	PORTCR(195, 0xe60520C3),
2186 	PORTCR(196, 0xe60520C4),
2187 	PORTCR(197, 0xe60520C5),
2188 	PORTCR(198, 0xe60520C6),
2189 	PORTCR(199, 0xe60520C7),
2190 	PORTCR(200, 0xe60520C8),
2191 	PORTCR(201, 0xe60520C9),
2192 	PORTCR(202, 0xe60520CA),
2193 	PORTCR(203, 0xe60520CB),
2194 	PORTCR(204, 0xe60520CC),
2195 	PORTCR(205, 0xe60520CD),
2196 	PORTCR(206, 0xe60520CE),
2197 	PORTCR(207, 0xe60520CF),
2198 	PORTCR(208, 0xe60520D0),
2199 	PORTCR(209, 0xe60520D1),
2200 	PORTCR(210, 0xe60520D2),
2201 	PORTCR(211, 0xe60520D3),
2202 	PORTCR(212, 0xe60520D4),
2203 	PORTCR(213, 0xe60520D5),
2204 	PORTCR(214, 0xe60520D6),
2205 	PORTCR(215, 0xe60520D7),
2206 	PORTCR(216, 0xe60520D8),
2207 	PORTCR(217, 0xe60520D9),
2208 	PORTCR(218, 0xe60520DA),
2209 	PORTCR(219, 0xe60520DB),
2210 	PORTCR(220, 0xe60520DC),
2211 	PORTCR(221, 0xe60520DD),
2212 	PORTCR(222, 0xe60520DE),
2213 	PORTCR(224, 0xe60520E0),
2214 	PORTCR(225, 0xe60520E1),
2215 	PORTCR(226, 0xe60520E2),
2216 	PORTCR(227, 0xe60520E3),
2217 	PORTCR(228, 0xe60520E4),
2218 	PORTCR(229, 0xe60520E5),
2219 	PORTCR(230, 0xe60520e6),
2220 	PORTCR(231, 0xe60520E7),
2221 	PORTCR(232, 0xe60520E8),
2222 	PORTCR(233, 0xe60520E9),
2223 	PORTCR(234, 0xe60520EA),
2224 	PORTCR(235, 0xe60520EB),
2225 	PORTCR(236, 0xe60520EC),
2226 	PORTCR(237, 0xe60520ED),
2227 	PORTCR(238, 0xe60520EE),
2228 	PORTCR(239, 0xe60520EF),
2229 	PORTCR(240, 0xe60520F0),
2230 	PORTCR(241, 0xe60520F1),
2231 	PORTCR(242, 0xe60520F2),
2232 	PORTCR(243, 0xe60520F3),
2233 	PORTCR(244, 0xe60520F4),
2234 	PORTCR(245, 0xe60520F5),
2235 	PORTCR(246, 0xe60520F6),
2236 	PORTCR(247, 0xe60520F7),
2237 	PORTCR(248, 0xe60520F8),
2238 	PORTCR(249, 0xe60520F9),
2239 	PORTCR(250, 0xe60520FA),
2240 	PORTCR(256, 0xe6052100),
2241 	PORTCR(257, 0xe6052101),
2242 	PORTCR(258, 0xe6052102),
2243 	PORTCR(259, 0xe6052103),
2244 	PORTCR(260, 0xe6052104),
2245 	PORTCR(261, 0xe6052105),
2246 	PORTCR(262, 0xe6052106),
2247 	PORTCR(263, 0xe6052107),
2248 	PORTCR(264, 0xe6052108),
2249 	PORTCR(265, 0xe6052109),
2250 	PORTCR(266, 0xe605210A),
2251 	PORTCR(267, 0xe605210B),
2252 	PORTCR(268, 0xe605210C),
2253 	PORTCR(269, 0xe605210D),
2254 	PORTCR(270, 0xe605210E),
2255 	PORTCR(271, 0xe605210F),
2256 	PORTCR(272, 0xe6052110),
2257 	PORTCR(273, 0xe6052111),
2258 	PORTCR(274, 0xe6052112),
2259 	PORTCR(275, 0xe6052113),
2260 	PORTCR(276, 0xe6052114),
2261 	PORTCR(277, 0xe6052115),
2262 	PORTCR(278, 0xe6052116),
2263 	PORTCR(279, 0xe6052117),
2264 	PORTCR(280, 0xe6052118),
2265 	PORTCR(281, 0xe6052119),
2266 	PORTCR(282, 0xe605211A),
2267 	PORTCR(283, 0xe605211B),
2268 	PORTCR(288, 0xe6053120),
2269 	PORTCR(289, 0xe6053121),
2270 	PORTCR(290, 0xe6053122),
2271 	PORTCR(291, 0xe6053123),
2272 	PORTCR(292, 0xe6053124),
2273 	PORTCR(293, 0xe6053125),
2274 	PORTCR(294, 0xe6053126),
2275 	PORTCR(295, 0xe6053127),
2276 	PORTCR(296, 0xe6053128),
2277 	PORTCR(297, 0xe6053129),
2278 	PORTCR(298, 0xe605312A),
2279 	PORTCR(299, 0xe605312B),
2280 	PORTCR(300, 0xe605312C),
2281 	PORTCR(301, 0xe605312D),
2282 	PORTCR(302, 0xe605312E),
2283 	PORTCR(303, 0xe605312F),
2284 	PORTCR(304, 0xe6053130),
2285 	PORTCR(305, 0xe6053131),
2286 	PORTCR(306, 0xe6053132),
2287 	PORTCR(307, 0xe6053133),
2288 	PORTCR(308, 0xe6053134),
2289 	PORTCR(320, 0xe6053140),
2290 	PORTCR(321, 0xe6053141),
2291 	PORTCR(322, 0xe6053142),
2292 	PORTCR(323, 0xe6053143),
2293 	PORTCR(324, 0xe6053144),
2294 	PORTCR(325, 0xe6053145),
2295 	PORTCR(326, 0xe6053146),
2296 	PORTCR(327, 0xe6053147),
2297 	PORTCR(328, 0xe6053148),
2298 	PORTCR(329, 0xe6053149),
2299 
2300 	{ PINMUX_CFG_REG("MSEL1CR", 0xe605800c, 32, 1) {
2301 			MSEL1CR_31_0, MSEL1CR_31_1,
2302 			0, 0,
2303 			0, 0,
2304 			0, 0,
2305 			MSEL1CR_27_0, MSEL1CR_27_1,
2306 			0, 0,
2307 			MSEL1CR_25_0, MSEL1CR_25_1,
2308 			MSEL1CR_24_0, MSEL1CR_24_1,
2309 			0, 0,
2310 			MSEL1CR_22_0, MSEL1CR_22_1,
2311 			MSEL1CR_21_0, MSEL1CR_21_1,
2312 			MSEL1CR_20_0, MSEL1CR_20_1,
2313 			MSEL1CR_19_0, MSEL1CR_19_1,
2314 			MSEL1CR_18_0, MSEL1CR_18_1,
2315 			MSEL1CR_17_0, MSEL1CR_17_1,
2316 			MSEL1CR_16_0, MSEL1CR_16_1,
2317 			MSEL1CR_15_0, MSEL1CR_15_1,
2318 			MSEL1CR_14_0, MSEL1CR_14_1,
2319 			MSEL1CR_13_0, MSEL1CR_13_1,
2320 			MSEL1CR_12_0, MSEL1CR_12_1,
2321 			MSEL1CR_11_0, MSEL1CR_11_1,
2322 			MSEL1CR_10_0, MSEL1CR_10_1,
2323 			MSEL1CR_09_0, MSEL1CR_09_1,
2324 			MSEL1CR_08_0, MSEL1CR_08_1,
2325 			MSEL1CR_07_0, MSEL1CR_07_1,
2326 			MSEL1CR_06_0, MSEL1CR_06_1,
2327 			MSEL1CR_05_0, MSEL1CR_05_1,
2328 			MSEL1CR_04_0, MSEL1CR_04_1,
2329 			MSEL1CR_03_0, MSEL1CR_03_1,
2330 			MSEL1CR_02_0, MSEL1CR_02_1,
2331 			MSEL1CR_01_0, MSEL1CR_01_1,
2332 			MSEL1CR_00_0, MSEL1CR_00_1,
2333 		}
2334 	},
2335 	{ PINMUX_CFG_REG("MSEL3CR", 0xe6058020, 32, 1) {
2336 			MSEL3CR_31_0, MSEL3CR_31_1,
2337 			0, 0,
2338 			0, 0,
2339 			MSEL3CR_28_0, MSEL3CR_28_1,
2340 			MSEL3CR_27_0, MSEL3CR_27_1,
2341 			MSEL3CR_26_0, MSEL3CR_26_1,
2342 			0, 0,
2343 			0, 0,
2344 			MSEL3CR_23_0, MSEL3CR_23_1,
2345 			MSEL3CR_22_0, MSEL3CR_22_1,
2346 			MSEL3CR_21_0, MSEL3CR_21_1,
2347 			MSEL3CR_20_0, MSEL3CR_20_1,
2348 			MSEL3CR_19_0, MSEL3CR_19_1,
2349 			MSEL3CR_18_0, MSEL3CR_18_1,
2350 			MSEL3CR_17_0, MSEL3CR_17_1,
2351 			MSEL3CR_16_0, MSEL3CR_16_1,
2352 			MSEL3CR_15_0, MSEL3CR_15_1,
2353 			0, 0,
2354 			0, 0,
2355 			MSEL3CR_12_0, MSEL3CR_12_1,
2356 			MSEL3CR_11_0, MSEL3CR_11_1,
2357 			MSEL3CR_10_0, MSEL3CR_10_1,
2358 			MSEL3CR_09_0, MSEL3CR_09_1,
2359 			0, 0,
2360 			0, 0,
2361 			MSEL3CR_06_0, MSEL3CR_06_1,
2362 			0, 0,
2363 			0, 0,
2364 			MSEL3CR_03_0, MSEL3CR_03_1,
2365 			0, 0,
2366 			MSEL3CR_01_0, MSEL3CR_01_1,
2367 			MSEL3CR_00_0, MSEL3CR_00_1,
2368 			}
2369 	},
2370 	{ PINMUX_CFG_REG("MSEL4CR", 0xe6058024, 32, 1) {
2371 			0, 0,
2372 			MSEL4CR_30_0, MSEL4CR_30_1,
2373 			MSEL4CR_29_0, MSEL4CR_29_1,
2374 			MSEL4CR_28_0, MSEL4CR_28_1,
2375 			MSEL4CR_27_0, MSEL4CR_27_1,
2376 			MSEL4CR_26_0, MSEL4CR_26_1,
2377 			MSEL4CR_25_0, MSEL4CR_25_1,
2378 			MSEL4CR_24_0, MSEL4CR_24_1,
2379 			MSEL4CR_23_0, MSEL4CR_23_1,
2380 			MSEL4CR_22_0, MSEL4CR_22_1,
2381 			MSEL4CR_21_0, MSEL4CR_21_1,
2382 			MSEL4CR_20_0, MSEL4CR_20_1,
2383 			MSEL4CR_19_0, MSEL4CR_19_1,
2384 			MSEL4CR_18_0, MSEL4CR_18_1,
2385 			MSEL4CR_17_0, MSEL4CR_17_1,
2386 			MSEL4CR_16_0, MSEL4CR_16_1,
2387 			MSEL4CR_15_0, MSEL4CR_15_1,
2388 			MSEL4CR_14_0, MSEL4CR_14_1,
2389 			MSEL4CR_13_0, MSEL4CR_13_1,
2390 			MSEL4CR_12_0, MSEL4CR_12_1,
2391 			MSEL4CR_11_0, MSEL4CR_11_1,
2392 			MSEL4CR_10_0, MSEL4CR_10_1,
2393 			MSEL4CR_09_0, MSEL4CR_09_1,
2394 			0, 0,
2395 			MSEL4CR_07_0, MSEL4CR_07_1,
2396 			0, 0,
2397 			0, 0,
2398 			MSEL4CR_04_0, MSEL4CR_04_1,
2399 			0, 0,
2400 			0, 0,
2401 			MSEL4CR_01_0, MSEL4CR_01_1,
2402 			0, 0,
2403 		}
2404 	},
2405 	{ PINMUX_CFG_REG("MSEL5CR", 0xe6058028, 32, 1) {
2406 			MSEL5CR_31_0, MSEL5CR_31_1,
2407 			MSEL5CR_30_0, MSEL5CR_30_1,
2408 			MSEL5CR_29_0, MSEL5CR_29_1,
2409 			MSEL5CR_28_0, MSEL5CR_28_1,
2410 			MSEL5CR_27_0, MSEL5CR_27_1,
2411 			MSEL5CR_26_0, MSEL5CR_26_1,
2412 			MSEL5CR_25_0, MSEL5CR_25_1,
2413 			MSEL5CR_24_0, MSEL5CR_24_1,
2414 			MSEL5CR_23_0, MSEL5CR_23_1,
2415 			MSEL5CR_22_0, MSEL5CR_22_1,
2416 			MSEL5CR_21_0, MSEL5CR_21_1,
2417 			MSEL5CR_20_0, MSEL5CR_20_1,
2418 			MSEL5CR_19_0, MSEL5CR_19_1,
2419 			MSEL5CR_18_0, MSEL5CR_18_1,
2420 			MSEL5CR_17_0, MSEL5CR_17_1,
2421 			MSEL5CR_16_0, MSEL5CR_16_1,
2422 			MSEL5CR_15_0, MSEL5CR_15_1,
2423 			MSEL5CR_14_0, MSEL5CR_14_1,
2424 			MSEL5CR_13_0, MSEL5CR_13_1,
2425 			MSEL5CR_12_0, MSEL5CR_12_1,
2426 			MSEL5CR_11_0, MSEL5CR_11_1,
2427 			MSEL5CR_10_0, MSEL5CR_10_1,
2428 			MSEL5CR_09_0, MSEL5CR_09_1,
2429 			MSEL5CR_08_0, MSEL5CR_08_1,
2430 			MSEL5CR_07_0, MSEL5CR_07_1,
2431 			MSEL5CR_06_0, MSEL5CR_06_1,
2432 			0, 0,
2433 			0, 0,
2434 			0, 0,
2435 			0, 0,
2436 			0, 0,
2437 			0, 0,
2438 		}
2439 	},
2440 	{ PINMUX_CFG_REG("MSEL8CR", 0xe6058034, 32, 1) {
2441 			0, 0,
2442 			0, 0,
2443 			0, 0,
2444 			0, 0,
2445 			0, 0,
2446 			0, 0,
2447 			0, 0,
2448 			0, 0,
2449 			0, 0,
2450 			0, 0,
2451 			0, 0,
2452 			0, 0,
2453 			0, 0,
2454 			0, 0,
2455 			0, 0,
2456 			MSEL8CR_16_0, MSEL8CR_16_1,
2457 			0, 0,
2458 			0, 0,
2459 			0, 0,
2460 			0, 0,
2461 			0, 0,
2462 			0, 0,
2463 			0, 0,
2464 			0, 0,
2465 			0, 0,
2466 			0, 0,
2467 			0, 0,
2468 			0, 0,
2469 			0, 0,
2470 			0, 0,
2471 			MSEL8CR_01_0, MSEL8CR_01_1,
2472 			MSEL8CR_00_0, MSEL8CR_00_1,
2473 		}
2474 	},
2475 	{ },
2476 };
2477 
2478 static const struct pinmux_data_reg pinmux_data_regs[] = {
2479 
2480 	{ PINMUX_DATA_REG("PORTL031_000DR", 0xe6054000, 32) {
2481 			0, PORT30_DATA, PORT29_DATA, PORT28_DATA,
2482 			PORT27_DATA, PORT26_DATA, PORT25_DATA, PORT24_DATA,
2483 			PORT23_DATA, PORT22_DATA, PORT21_DATA, PORT20_DATA,
2484 			PORT19_DATA, PORT18_DATA, PORT17_DATA, PORT16_DATA,
2485 			PORT15_DATA, PORT14_DATA, PORT13_DATA, PORT12_DATA,
2486 			PORT11_DATA, PORT10_DATA, PORT9_DATA, PORT8_DATA,
2487 			PORT7_DATA, PORT6_DATA, PORT5_DATA, PORT4_DATA,
2488 			PORT3_DATA, PORT2_DATA, PORT1_DATA, PORT0_DATA,
2489 		}
2490 	},
2491 	{ PINMUX_DATA_REG("PORTD063_032DR", 0xe6055000, 32) {
2492 			0, 0, 0, 0,
2493 			0, 0, 0, 0,
2494 			0, 0, 0, 0,
2495 			0, 0, 0, 0,
2496 			0, 0, 0, 0,
2497 			0, 0, 0, PORT40_DATA,
2498 			PORT39_DATA, PORT38_DATA, PORT37_DATA, PORT36_DATA,
2499 			PORT35_DATA, PORT34_DATA, PORT33_DATA, PORT32_DATA,
2500 		}
2501 	},
2502 	{ PINMUX_DATA_REG("PORTL095_064DR", 0xe6054004, 32) {
2503 			0, 0, 0, 0,
2504 			0, 0, 0, 0,
2505 			0, 0, PORT85_DATA, PORT84_DATA,
2506 			PORT83_DATA, PORT82_DATA, PORT81_DATA, PORT80_DATA,
2507 			PORT79_DATA, PORT78_DATA, PORT77_DATA, PORT76_DATA,
2508 			PORT75_DATA, PORT74_DATA, PORT73_DATA, PORT72_DATA,
2509 			PORT71_DATA, PORT70_DATA, PORT69_DATA, PORT68_DATA,
2510 			PORT67_DATA, PORT66_DATA, PORT65_DATA, PORT64_DATA,
2511 		}
2512 	},
2513 	{ PINMUX_DATA_REG("PORTD127_096DR", 0xe6055004, 32) {
2514 			0, PORT126_DATA, PORT125_DATA, PORT124_DATA,
2515 			PORT123_DATA, PORT122_DATA, PORT121_DATA, PORT120_DATA,
2516 			PORT119_DATA, PORT118_DATA, PORT117_DATA, PORT116_DATA,
2517 			PORT115_DATA, PORT114_DATA, PORT113_DATA, PORT112_DATA,
2518 			PORT111_DATA, PORT110_DATA, PORT109_DATA, PORT108_DATA,
2519 			PORT107_DATA, PORT106_DATA, PORT105_DATA, PORT104_DATA,
2520 			PORT103_DATA, PORT102_DATA, PORT101_DATA, PORT100_DATA,
2521 			PORT99_DATA, PORT98_DATA, PORT97_DATA, PORT96_DATA,
2522 		}
2523 	},
2524 	{ PINMUX_DATA_REG("PORTD159_128DR", 0xe6055008, 32) {
2525 			0, 0, 0, 0,
2526 			0, 0, 0, 0,
2527 			0, 0, 0, 0,
2528 			0, 0, 0, 0,
2529 			0, 0, 0, 0,
2530 			0, 0, 0, 0,
2531 			0, PORT134_DATA, PORT133_DATA, PORT132_DATA,
2532 			PORT131_DATA, PORT130_DATA, PORT129_DATA, PORT128_DATA,
2533 		}
2534 	},
2535 	{ PINMUX_DATA_REG("PORTR191_160DR", 0xe6056000, 32) {
2536 			0, 0, 0, 0,
2537 			0, 0, 0, 0,
2538 			0, 0, 0, 0,
2539 			0, PORT178_DATA, PORT177_DATA, PORT176_DATA,
2540 			PORT175_DATA, PORT174_DATA, PORT173_DATA, PORT172_DATA,
2541 			PORT171_DATA, PORT170_DATA, PORT169_DATA, PORT168_DATA,
2542 			PORT167_DATA, PORT166_DATA, PORT165_DATA, PORT164_DATA,
2543 			PORT163_DATA, PORT162_DATA, PORT161_DATA, PORT160_DATA,
2544 		}
2545 	},
2546 	{ PINMUX_DATA_REG("PORTR223_192DR", 0xe6056004, 32) {
2547 			0, PORT222_DATA, PORT221_DATA, PORT220_DATA,
2548 			PORT219_DATA, PORT218_DATA, PORT217_DATA, PORT216_DATA,
2549 			PORT215_DATA, PORT214_DATA, PORT213_DATA, PORT212_DATA,
2550 			PORT211_DATA, PORT210_DATA, PORT209_DATA, PORT208_DATA,
2551 			PORT207_DATA, PORT206_DATA, PORT205_DATA, PORT204_DATA,
2552 			PORT203_DATA, PORT202_DATA, PORT201_DATA, PORT200_DATA,
2553 			PORT199_DATA, PORT198_DATA, PORT197_DATA, PORT196_DATA,
2554 			PORT195_DATA, PORT194_DATA, PORT193_DATA, PORT192_DATA,
2555 		}
2556 	},
2557 	{ PINMUX_DATA_REG("PORTR255_224DR", 0xe6056008, 32) {
2558 			0, 0, 0, 0,
2559 			0, PORT250_DATA, PORT249_DATA, PORT248_DATA,
2560 			PORT247_DATA, PORT246_DATA, PORT245_DATA, PORT244_DATA,
2561 			PORT243_DATA, PORT242_DATA, PORT241_DATA, PORT240_DATA,
2562 			PORT239_DATA, PORT238_DATA, PORT237_DATA, PORT236_DATA,
2563 			PORT235_DATA, PORT234_DATA, PORT233_DATA, PORT232_DATA,
2564 			PORT231_DATA, PORT230_DATA, PORT229_DATA, PORT228_DATA,
2565 			PORT227_DATA, PORT226_DATA, PORT225_DATA, PORT224_DATA,
2566 		}
2567 	},
2568 	{ PINMUX_DATA_REG("PORTR287_256DR", 0xe605600C, 32) {
2569 			0, 0, 0, 0,
2570 			PORT283_DATA, PORT282_DATA, PORT281_DATA, PORT280_DATA,
2571 			PORT279_DATA, PORT278_DATA, PORT277_DATA, PORT276_DATA,
2572 			PORT275_DATA, PORT274_DATA, PORT273_DATA, PORT272_DATA,
2573 			PORT271_DATA, PORT270_DATA, PORT269_DATA, PORT268_DATA,
2574 			PORT267_DATA, PORT266_DATA, PORT265_DATA, PORT264_DATA,
2575 			PORT263_DATA, PORT262_DATA, PORT261_DATA, PORT260_DATA,
2576 			PORT259_DATA, PORT258_DATA, PORT257_DATA, PORT256_DATA,
2577 		}
2578 	},
2579 	{ PINMUX_DATA_REG("PORTU319_288DR", 0xe6057000, 32) {
2580 			0, 0, 0, 0,
2581 			0, 0, 0, 0,
2582 			0, 0, 0, PORT308_DATA,
2583 			PORT307_DATA, PORT306_DATA, PORT305_DATA, PORT304_DATA,
2584 			PORT303_DATA, PORT302_DATA, PORT301_DATA, PORT300_DATA,
2585 			PORT299_DATA, PORT298_DATA, PORT297_DATA, PORT296_DATA,
2586 			PORT295_DATA, PORT294_DATA, PORT293_DATA, PORT292_DATA,
2587 			PORT291_DATA, PORT290_DATA, PORT289_DATA, PORT288_DATA,
2588 		}
2589 	},
2590 	{ PINMUX_DATA_REG("PORTU351_320DR", 0xe6057004, 32) {
2591 			0, 0, 0, 0,
2592 			0, 0, 0, 0,
2593 			0, 0, 0, 0,
2594 			0, 0, 0, 0,
2595 			0, 0, 0, 0,
2596 			0, 0, PORT329_DATA, PORT328_DATA,
2597 			PORT327_DATA, PORT326_DATA, PORT325_DATA, PORT324_DATA,
2598 			PORT323_DATA, PORT322_DATA, PORT321_DATA, PORT320_DATA,
2599 		}
2600 	},
2601 	{ },
2602 };
2603 
2604 static const struct pinmux_irq pinmux_irqs[] = {
2605 	PINMUX_IRQ(0),		/* IRQ0 */
2606 	PINMUX_IRQ(1),		/* IRQ1 */
2607 	PINMUX_IRQ(2),		/* IRQ2 */
2608 	PINMUX_IRQ(3),		/* IRQ3 */
2609 	PINMUX_IRQ(4),		/* IRQ4 */
2610 	PINMUX_IRQ(5),		/* IRQ5 */
2611 	PINMUX_IRQ(6),		/* IRQ6 */
2612 	PINMUX_IRQ(7),		/* IRQ7 */
2613 	PINMUX_IRQ(8),		/* IRQ8 */
2614 	PINMUX_IRQ(9),		/* IRQ9 */
2615 	PINMUX_IRQ(10),		/* IRQ10 */
2616 	PINMUX_IRQ(11),		/* IRQ11 */
2617 	PINMUX_IRQ(12),		/* IRQ12 */
2618 	PINMUX_IRQ(13),		/* IRQ13 */
2619 	PINMUX_IRQ(14),		/* IRQ14 */
2620 	PINMUX_IRQ(15),		/* IRQ15 */
2621 	PINMUX_IRQ(320),	/* IRQ16 */
2622 	PINMUX_IRQ(321),	/* IRQ17 */
2623 	PINMUX_IRQ(85),		/* IRQ18 */
2624 	PINMUX_IRQ(84),		/* IRQ19 */
2625 	PINMUX_IRQ(160),	/* IRQ20 */
2626 	PINMUX_IRQ(161),	/* IRQ21 */
2627 	PINMUX_IRQ(162),	/* IRQ22 */
2628 	PINMUX_IRQ(163),	/* IRQ23 */
2629 	PINMUX_IRQ(175),	/* IRQ24 */
2630 	PINMUX_IRQ(176),	/* IRQ25 */
2631 	PINMUX_IRQ(177),	/* IRQ26 */
2632 	PINMUX_IRQ(178),	/* IRQ27 */
2633 	PINMUX_IRQ(322),	/* IRQ28 */
2634 	PINMUX_IRQ(323),	/* IRQ29 */
2635 	PINMUX_IRQ(324),	/* IRQ30 */
2636 	PINMUX_IRQ(192),	/* IRQ31 */
2637 	PINMUX_IRQ(193),	/* IRQ32 */
2638 	PINMUX_IRQ(194),	/* IRQ33 */
2639 	PINMUX_IRQ(195),	/* IRQ34 */
2640 	PINMUX_IRQ(196),	/* IRQ35 */
2641 	PINMUX_IRQ(197),	/* IRQ36 */
2642 	PINMUX_IRQ(198),	/* IRQ37 */
2643 	PINMUX_IRQ(199),	/* IRQ38 */
2644 	PINMUX_IRQ(200),	/* IRQ39 */
2645 	PINMUX_IRQ(66),		/* IRQ40 */
2646 	PINMUX_IRQ(102),	/* IRQ41 */
2647 	PINMUX_IRQ(103),	/* IRQ42 */
2648 	PINMUX_IRQ(109),	/* IRQ43 */
2649 	PINMUX_IRQ(110),	/* IRQ44 */
2650 	PINMUX_IRQ(111),	/* IRQ45 */
2651 	PINMUX_IRQ(112),	/* IRQ46 */
2652 	PINMUX_IRQ(113),	/* IRQ47 */
2653 	PINMUX_IRQ(114),	/* IRQ48 */
2654 	PINMUX_IRQ(115),	/* IRQ49 */
2655 	PINMUX_IRQ(301),	/* IRQ50 */
2656 	PINMUX_IRQ(290),	/* IRQ51 */
2657 	PINMUX_IRQ(296),	/* IRQ52 */
2658 	PINMUX_IRQ(325),	/* IRQ53 */
2659 	PINMUX_IRQ(326),	/* IRQ54 */
2660 	PINMUX_IRQ(327),	/* IRQ55 */
2661 	PINMUX_IRQ(328),	/* IRQ56 */
2662 	PINMUX_IRQ(329),	/* IRQ57 */
2663 };
2664 
2665 #define PORTCR_PULMD_OFF (0 << 6)
2666 #define PORTCR_PULMD_DOWN (2 << 6)
2667 #define PORTCR_PULMD_UP (3 << 6)
2668 #define PORTCR_PULMD_MASK (3 << 6)
2669 
2670 static const unsigned int r8a73a4_portcr_offsets[] = {
2671 	0x00000000, 0x00001000, 0x00000000, 0x00001000,
2672 	0x00001000, 0x00002000, 0x00002000, 0x00002000,
2673 	0x00002000, 0x00003000, 0x00003000,
2674 };
2675 
r8a73a4_pinmux_get_bias(struct sh_pfc * pfc,unsigned int pin)2676 static unsigned int r8a73a4_pinmux_get_bias(struct sh_pfc *pfc,
2677 					    unsigned int pin)
2678 {
2679 	void __iomem *addr;
2680 
2681 	addr = pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
2682 
2683 	switch (ioread8(addr) & PORTCR_PULMD_MASK) {
2684 	case PORTCR_PULMD_UP:
2685 		return PIN_CONFIG_BIAS_PULL_UP;
2686 	case PORTCR_PULMD_DOWN:
2687 		return PIN_CONFIG_BIAS_PULL_DOWN;
2688 	case PORTCR_PULMD_OFF:
2689 	default:
2690 		return PIN_CONFIG_BIAS_DISABLE;
2691 	}
2692 }
2693 
r8a73a4_pinmux_set_bias(struct sh_pfc * pfc,unsigned int pin,unsigned int bias)2694 static void r8a73a4_pinmux_set_bias(struct sh_pfc *pfc, unsigned int pin,
2695 				   unsigned int bias)
2696 {
2697 	void __iomem *addr;
2698 	u32 value;
2699 
2700 	addr = pfc->windows->virt + r8a73a4_portcr_offsets[pin >> 5] + pin;
2701 	value = ioread8(addr) & ~PORTCR_PULMD_MASK;
2702 
2703 	switch (bias) {
2704 	case PIN_CONFIG_BIAS_PULL_UP:
2705 		value |= PORTCR_PULMD_UP;
2706 		break;
2707 	case PIN_CONFIG_BIAS_PULL_DOWN:
2708 		value |= PORTCR_PULMD_DOWN;
2709 		break;
2710 	}
2711 
2712 	iowrite8(value, addr);
2713 }
2714 
2715 static const struct sh_pfc_soc_operations r8a73a4_pfc_ops = {
2716 	.get_bias = r8a73a4_pinmux_get_bias,
2717 	.set_bias = r8a73a4_pinmux_set_bias,
2718 };
2719 
2720 const struct sh_pfc_soc_info r8a73a4_pinmux_info = {
2721 	.name		= "r8a73a4_pfc",
2722 	.ops		= &r8a73a4_pfc_ops,
2723 
2724 	.input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
2725 	.output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
2726 	.function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
2727 
2728 	.pins = pinmux_pins,
2729 	.nr_pins = ARRAY_SIZE(pinmux_pins),
2730 
2731 	.groups = pinmux_groups,
2732 	.nr_groups = ARRAY_SIZE(pinmux_groups),
2733 	.functions = pinmux_functions,
2734 	.nr_functions = ARRAY_SIZE(pinmux_functions),
2735 
2736 	.cfg_regs = pinmux_config_regs,
2737 	.data_regs = pinmux_data_regs,
2738 
2739 	.pinmux_data = pinmux_data,
2740 	.pinmux_data_size = ARRAY_SIZE(pinmux_data),
2741 
2742 	.gpio_irq = pinmux_irqs,
2743 	.gpio_irq_size = ARRAY_SIZE(pinmux_irqs),
2744 };
2745