1 // SPDX-License-Identifier: GPL-2.0+
2 //
3 // Exynos specific support for Samsung pinctrl/gpiolib driver with eint support.
4 //
5 // Copyright (c) 2012 Samsung Electronics Co., Ltd.
6 // http://www.samsung.com
7 // Copyright (c) 2012 Linaro Ltd
8 // http://www.linaro.org
9 //
10 // Author: Thomas Abraham <thomas.ab@samsung.com>
11 //
12 // This file contains the Samsung Exynos specific information required by the
13 // the Samsung pinctrl/gpiolib driver. It also includes the implementation of
14 // external gpio and wakeup interrupt support.
15
16 #include <linux/device.h>
17 #include <linux/of_address.h>
18 #include <linux/slab.h>
19 #include <linux/err.h>
20 #include <linux/soc/samsung/exynos-regs-pmu.h>
21
22 #include "pinctrl-samsung.h"
23 #include "pinctrl-exynos.h"
24
25 static const struct samsung_pin_bank_type bank_type_off = {
26 .fld_width = { 4, 1, 2, 2, 2, 2, },
27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
28 };
29
30 static const struct samsung_pin_bank_type bank_type_alive = {
31 .fld_width = { 4, 1, 2, 2, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
33 };
34
35 /* Retention control for S5PV210 are located at the end of clock controller */
36 #define S5P_OTHERS 0xE000
37
38 #define S5P_OTHERS_RET_IO (1 << 31)
39 #define S5P_OTHERS_RET_CF (1 << 30)
40 #define S5P_OTHERS_RET_MMC (1 << 29)
41 #define S5P_OTHERS_RET_UART (1 << 28)
42
s5pv210_retention_disable(struct samsung_pinctrl_drv_data * drvdata)43 static void s5pv210_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
44 {
45 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv;
46 u32 tmp;
47
48 tmp = __raw_readl(clk_base + S5P_OTHERS);
49 tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF | S5P_OTHERS_RET_MMC |
50 S5P_OTHERS_RET_UART);
51 __raw_writel(tmp, clk_base + S5P_OTHERS);
52 }
53
54 static struct samsung_retention_ctrl *
s5pv210_retention_init(struct samsung_pinctrl_drv_data * drvdata,const struct samsung_retention_data * data)55 s5pv210_retention_init(struct samsung_pinctrl_drv_data *drvdata,
56 const struct samsung_retention_data *data)
57 {
58 struct samsung_retention_ctrl *ctrl;
59 struct device_node *np;
60 void __iomem *clk_base;
61
62 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL);
63 if (!ctrl)
64 return ERR_PTR(-ENOMEM);
65
66 np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock");
67 if (!np) {
68 pr_err("%s: failed to find clock controller DT node\n",
69 __func__);
70 return ERR_PTR(-ENODEV);
71 }
72
73 clk_base = of_iomap(np, 0);
74 if (!clk_base) {
75 pr_err("%s: failed to map clock registers\n", __func__);
76 return ERR_PTR(-EINVAL);
77 }
78
79 ctrl->priv = (void __force *)clk_base;
80 ctrl->disable = s5pv210_retention_disable;
81
82 return ctrl;
83 }
84
85 static const struct samsung_retention_data s5pv210_retention_data __initconst = {
86 .init = s5pv210_retention_init,
87 };
88
89 /* pin banks of s5pv210 pin-controller */
90 static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = {
91 /* Must start with EINTG banks, ordered by EINT group number. */
92 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
93 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
94 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
95 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
96 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
97 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
98 EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
99 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c),
100 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20),
101 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24),
102 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28),
103 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c),
104 EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30),
105 EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34),
106 EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38),
107 EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c),
108 EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40),
109 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44),
110 EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48),
111 EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c),
112 EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50),
113 EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54),
114 EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"),
115 EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"),
116 EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"),
117 EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"),
118 EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"),
119 EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"),
120 EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"),
121 EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"),
122 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00),
123 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04),
124 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08),
125 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c),
126 };
127
128 static const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = {
129 {
130 /* pin-controller instance 0 data */
131 .pin_banks = s5pv210_pin_bank,
132 .nr_banks = ARRAY_SIZE(s5pv210_pin_bank),
133 .eint_gpio_init = exynos_eint_gpio_init,
134 .eint_wkup_init = exynos_eint_wkup_init,
135 .suspend = exynos_pinctrl_suspend,
136 .resume = exynos_pinctrl_resume,
137 .retention_data = &s5pv210_retention_data,
138 },
139 };
140
141 const struct samsung_pinctrl_of_match_data s5pv210_of_data __initconst = {
142 .ctrl = s5pv210_pin_ctrl,
143 .num_ctrl = ARRAY_SIZE(s5pv210_pin_ctrl),
144 };
145
146 /* Pad retention control code for accessing PMU regmap */
147 static atomic_t exynos_shared_retention_refcnt;
148
149 /* pin banks of exynos3250 pin-controller 0 */
150 static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = {
151 /* Must start with EINTG banks, ordered by EINT group number. */
152 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
153 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
154 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
155 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
156 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
157 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
158 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18),
159 };
160
161 /* pin banks of exynos3250 pin-controller 1 */
162 static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = {
163 /* Must start with EINTG banks, ordered by EINT group number. */
164 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"),
165 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"),
166 EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"),
167 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08),
168 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
169 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
170 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18),
171 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
172 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
173 EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c),
174 EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30),
175 EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34),
176 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
177 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
178 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
179 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
180 };
181
182 /*
183 * PMU pad retention groups for Exynos3250 doesn't match pin banks, so handle
184 * them all together
185 */
186 static const u32 exynos3250_retention_regs[] = {
187 S5P_PAD_RET_MAUDIO_OPTION,
188 S5P_PAD_RET_GPIO_OPTION,
189 S5P_PAD_RET_UART_OPTION,
190 S5P_PAD_RET_MMCA_OPTION,
191 S5P_PAD_RET_MMCB_OPTION,
192 S5P_PAD_RET_EBIA_OPTION,
193 S5P_PAD_RET_EBIB_OPTION,
194 S5P_PAD_RET_MMC2_OPTION,
195 S5P_PAD_RET_SPI_OPTION,
196 };
197
198 static const struct samsung_retention_data exynos3250_retention_data __initconst = {
199 .regs = exynos3250_retention_regs,
200 .nr_regs = ARRAY_SIZE(exynos3250_retention_regs),
201 .value = EXYNOS_WAKEUP_FROM_LOWPWR,
202 .refcnt = &exynos_shared_retention_refcnt,
203 .init = exynos_retention_init,
204 };
205
206 /*
207 * Samsung pinctrl driver data for Exynos3250 SoC. Exynos3250 SoC includes
208 * two gpio/pin-mux/pinconfig controllers.
209 */
210 static const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = {
211 {
212 /* pin-controller instance 0 data */
213 .pin_banks = exynos3250_pin_banks0,
214 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0),
215 .eint_gpio_init = exynos_eint_gpio_init,
216 .suspend = exynos_pinctrl_suspend,
217 .resume = exynos_pinctrl_resume,
218 .retention_data = &exynos3250_retention_data,
219 }, {
220 /* pin-controller instance 1 data */
221 .pin_banks = exynos3250_pin_banks1,
222 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1),
223 .eint_gpio_init = exynos_eint_gpio_init,
224 .eint_wkup_init = exynos_eint_wkup_init,
225 .suspend = exynos_pinctrl_suspend,
226 .resume = exynos_pinctrl_resume,
227 .retention_data = &exynos3250_retention_data,
228 },
229 };
230
231 const struct samsung_pinctrl_of_match_data exynos3250_of_data __initconst = {
232 .ctrl = exynos3250_pin_ctrl,
233 .num_ctrl = ARRAY_SIZE(exynos3250_pin_ctrl),
234 };
235
236 /* pin banks of exynos4210 pin-controller 0 */
237 static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = {
238 /* Must start with EINTG banks, ordered by EINT group number. */
239 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
240 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
241 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
242 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
243 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
244 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
245 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
246 EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c),
247 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),
248 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24),
249 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28),
250 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c),
251 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
252 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
253 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
254 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
255 };
256
257 /* pin banks of exynos4210 pin-controller 1 */
258 static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst = {
259 /* Must start with EINTG banks, ordered by EINT group number. */
260 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00),
261 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04),
262 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
263 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
264 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
265 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
266 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18),
267 EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c),
268 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
269 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
270 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
271 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
272 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
273 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
274 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
275 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
276 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
277 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
278 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
279 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
280 };
281
282 /* pin banks of exynos4210 pin-controller 2 */
283 static const struct samsung_pin_bank_data exynos4210_pin_banks2[] __initconst = {
284 /* Must start with EINTG banks, ordered by EINT group number. */
285 EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
286 };
287
288 /* PMU pad retention groups registers for Exynos4 (without audio) */
289 static const u32 exynos4_retention_regs[] = {
290 S5P_PAD_RET_GPIO_OPTION,
291 S5P_PAD_RET_UART_OPTION,
292 S5P_PAD_RET_MMCA_OPTION,
293 S5P_PAD_RET_MMCB_OPTION,
294 S5P_PAD_RET_EBIA_OPTION,
295 S5P_PAD_RET_EBIB_OPTION,
296 };
297
298 static const struct samsung_retention_data exynos4_retention_data __initconst = {
299 .regs = exynos4_retention_regs,
300 .nr_regs = ARRAY_SIZE(exynos4_retention_regs),
301 .value = EXYNOS_WAKEUP_FROM_LOWPWR,
302 .refcnt = &exynos_shared_retention_refcnt,
303 .init = exynos_retention_init,
304 };
305
306 /* PMU retention control for audio pins can be tied to audio pin bank */
307 static const u32 exynos4_audio_retention_regs[] = {
308 S5P_PAD_RET_MAUDIO_OPTION,
309 };
310
311 static const struct samsung_retention_data exynos4_audio_retention_data __initconst = {
312 .regs = exynos4_audio_retention_regs,
313 .nr_regs = ARRAY_SIZE(exynos4_audio_retention_regs),
314 .value = EXYNOS_WAKEUP_FROM_LOWPWR,
315 .init = exynos_retention_init,
316 };
317
318 /*
319 * Samsung pinctrl driver data for Exynos4210 SoC. Exynos4210 SoC includes
320 * three gpio/pin-mux/pinconfig controllers.
321 */
322 static const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = {
323 {
324 /* pin-controller instance 0 data */
325 .pin_banks = exynos4210_pin_banks0,
326 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0),
327 .eint_gpio_init = exynos_eint_gpio_init,
328 .suspend = exynos_pinctrl_suspend,
329 .resume = exynos_pinctrl_resume,
330 .retention_data = &exynos4_retention_data,
331 }, {
332 /* pin-controller instance 1 data */
333 .pin_banks = exynos4210_pin_banks1,
334 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1),
335 .eint_gpio_init = exynos_eint_gpio_init,
336 .eint_wkup_init = exynos_eint_wkup_init,
337 .suspend = exynos_pinctrl_suspend,
338 .resume = exynos_pinctrl_resume,
339 .retention_data = &exynos4_retention_data,
340 }, {
341 /* pin-controller instance 2 data */
342 .pin_banks = exynos4210_pin_banks2,
343 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2),
344 .retention_data = &exynos4_audio_retention_data,
345 },
346 };
347
348 const struct samsung_pinctrl_of_match_data exynos4210_of_data __initconst = {
349 .ctrl = exynos4210_pin_ctrl,
350 .num_ctrl = ARRAY_SIZE(exynos4210_pin_ctrl),
351 };
352
353 /* pin banks of exynos4x12 pin-controller 0 */
354 static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = {
355 /* Must start with EINTG banks, ordered by EINT group number. */
356 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
357 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
358 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
359 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
360 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
361 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
362 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
363 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
364 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
365 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
366 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
367 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40),
368 EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44),
369 };
370
371 /* pin banks of exynos4x12 pin-controller 1 */
372 static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst = {
373 /* Must start with EINTG banks, ordered by EINT group number. */
374 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
375 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
376 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
377 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
378 EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18),
379 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c),
380 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
381 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
382 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
383 EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
384 EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
385 EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
386 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
387 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
388 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
389 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
390 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
391 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
392 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
393 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
394 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
395 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
396 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
397 };
398
399 /* pin banks of exynos4x12 pin-controller 2 */
400 static const struct samsung_pin_bank_data exynos4x12_pin_banks2[] __initconst = {
401 /* Must start with EINTG banks, ordered by EINT group number. */
402 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
403 };
404
405 /* pin banks of exynos4x12 pin-controller 3 */
406 static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = {
407 /* Must start with EINTG banks, ordered by EINT group number. */
408 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
409 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
410 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),
411 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c),
412 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10),
413 };
414
415 /*
416 * Samsung pinctrl driver data for Exynos4x12 SoC. Exynos4x12 SoC includes
417 * four gpio/pin-mux/pinconfig controllers.
418 */
419 static const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = {
420 {
421 /* pin-controller instance 0 data */
422 .pin_banks = exynos4x12_pin_banks0,
423 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0),
424 .eint_gpio_init = exynos_eint_gpio_init,
425 .suspend = exynos_pinctrl_suspend,
426 .resume = exynos_pinctrl_resume,
427 .retention_data = &exynos4_retention_data,
428 }, {
429 /* pin-controller instance 1 data */
430 .pin_banks = exynos4x12_pin_banks1,
431 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1),
432 .eint_gpio_init = exynos_eint_gpio_init,
433 .eint_wkup_init = exynos_eint_wkup_init,
434 .suspend = exynos_pinctrl_suspend,
435 .resume = exynos_pinctrl_resume,
436 .retention_data = &exynos4_retention_data,
437 }, {
438 /* pin-controller instance 2 data */
439 .pin_banks = exynos4x12_pin_banks2,
440 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2),
441 .eint_gpio_init = exynos_eint_gpio_init,
442 .suspend = exynos_pinctrl_suspend,
443 .resume = exynos_pinctrl_resume,
444 .retention_data = &exynos4_audio_retention_data,
445 }, {
446 /* pin-controller instance 3 data */
447 .pin_banks = exynos4x12_pin_banks3,
448 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3),
449 .eint_gpio_init = exynos_eint_gpio_init,
450 .suspend = exynos_pinctrl_suspend,
451 .resume = exynos_pinctrl_resume,
452 },
453 };
454
455 const struct samsung_pinctrl_of_match_data exynos4x12_of_data __initconst = {
456 .ctrl = exynos4x12_pin_ctrl,
457 .num_ctrl = ARRAY_SIZE(exynos4x12_pin_ctrl),
458 };
459
460 /* pin banks of exynos5250 pin-controller 0 */
461 static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = {
462 /* Must start with EINTG banks, ordered by EINT group number. */
463 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
464 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
465 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
466 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
467 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
468 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
469 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
470 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
471 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20),
472 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24),
473 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28),
474 EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c),
475 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30),
476 EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34),
477 EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"),
478 EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"),
479 EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"),
480 EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"),
481 EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"),
482 EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"),
483 EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"),
484 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
485 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
486 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
487 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
488 };
489
490 /* pin banks of exynos5250 pin-controller 1 */
491 static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst = {
492 /* Must start with EINTG banks, ordered by EINT group number. */
493 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
494 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
495 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
496 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c),
497 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
498 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
499 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
500 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c),
501 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20),
502 };
503
504 /* pin banks of exynos5250 pin-controller 2 */
505 static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst = {
506 /* Must start with EINTG banks, ordered by EINT group number. */
507 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
508 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
509 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
510 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
511 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
512 };
513
514 /* pin banks of exynos5250 pin-controller 3 */
515 static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = {
516 /* Must start with EINTG banks, ordered by EINT group number. */
517 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
518 };
519
520 /*
521 * Samsung pinctrl driver data for Exynos5250 SoC. Exynos5250 SoC includes
522 * four gpio/pin-mux/pinconfig controllers.
523 */
524 static const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = {
525 {
526 /* pin-controller instance 0 data */
527 .pin_banks = exynos5250_pin_banks0,
528 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0),
529 .eint_gpio_init = exynos_eint_gpio_init,
530 .eint_wkup_init = exynos_eint_wkup_init,
531 .suspend = exynos_pinctrl_suspend,
532 .resume = exynos_pinctrl_resume,
533 .retention_data = &exynos4_retention_data,
534 }, {
535 /* pin-controller instance 1 data */
536 .pin_banks = exynos5250_pin_banks1,
537 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1),
538 .eint_gpio_init = exynos_eint_gpio_init,
539 .suspend = exynos_pinctrl_suspend,
540 .resume = exynos_pinctrl_resume,
541 .retention_data = &exynos4_retention_data,
542 }, {
543 /* pin-controller instance 2 data */
544 .pin_banks = exynos5250_pin_banks2,
545 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2),
546 .eint_gpio_init = exynos_eint_gpio_init,
547 .suspend = exynos_pinctrl_suspend,
548 .resume = exynos_pinctrl_resume,
549 }, {
550 /* pin-controller instance 3 data */
551 .pin_banks = exynos5250_pin_banks3,
552 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3),
553 .eint_gpio_init = exynos_eint_gpio_init,
554 .suspend = exynos_pinctrl_suspend,
555 .resume = exynos_pinctrl_resume,
556 .retention_data = &exynos4_audio_retention_data,
557 },
558 };
559
560 const struct samsung_pinctrl_of_match_data exynos5250_of_data __initconst = {
561 .ctrl = exynos5250_pin_ctrl,
562 .num_ctrl = ARRAY_SIZE(exynos5250_pin_ctrl),
563 };
564
565 /* pin banks of exynos5260 pin-controller 0 */
566 static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = {
567 /* Must start with EINTG banks, ordered by EINT group number. */
568 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),
569 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04),
570 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
571 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
572 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10),
573 EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14),
574 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18),
575 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c),
576 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20),
577 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24),
578 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28),
579 EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
580 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30),
581 EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34),
582 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38),
583 EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c),
584 EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40),
585 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
586 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
587 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
588 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
589 };
590
591 /* pin banks of exynos5260 pin-controller 1 */
592 static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst = {
593 /* Must start with EINTG banks, ordered by EINT group number. */
594 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00),
595 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04),
596 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
597 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
598 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10),
599 };
600
601 /* pin banks of exynos5260 pin-controller 2 */
602 static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = {
603 /* Must start with EINTG banks, ordered by EINT group number. */
604 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
605 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
606 };
607
608 /*
609 * Samsung pinctrl driver data for Exynos5260 SoC. Exynos5260 SoC includes
610 * three gpio/pin-mux/pinconfig controllers.
611 */
612 static const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = {
613 {
614 /* pin-controller instance 0 data */
615 .pin_banks = exynos5260_pin_banks0,
616 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0),
617 .eint_gpio_init = exynos_eint_gpio_init,
618 .eint_wkup_init = exynos_eint_wkup_init,
619 .suspend = exynos_pinctrl_suspend,
620 .resume = exynos_pinctrl_resume,
621 }, {
622 /* pin-controller instance 1 data */
623 .pin_banks = exynos5260_pin_banks1,
624 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1),
625 .eint_gpio_init = exynos_eint_gpio_init,
626 .suspend = exynos_pinctrl_suspend,
627 .resume = exynos_pinctrl_resume,
628 }, {
629 /* pin-controller instance 2 data */
630 .pin_banks = exynos5260_pin_banks2,
631 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2),
632 .eint_gpio_init = exynos_eint_gpio_init,
633 .suspend = exynos_pinctrl_suspend,
634 .resume = exynos_pinctrl_resume,
635 },
636 };
637
638 const struct samsung_pinctrl_of_match_data exynos5260_of_data __initconst = {
639 .ctrl = exynos5260_pin_ctrl,
640 .num_ctrl = ARRAY_SIZE(exynos5260_pin_ctrl),
641 };
642
643 /* pin banks of exynos5410 pin-controller 0 */
644 static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = {
645 /* Must start with EINTG banks, ordered by EINT group number. */
646 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
647 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
648 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
649 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
650 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
651 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
652 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
653 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
654 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20),
655 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24),
656 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28),
657 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c),
658 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30),
659 EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34),
660 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf0", 0x38),
661 EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpf1", 0x3c),
662 EXYNOS_PIN_BANK_EINTG(8, 0x220, "gpg0", 0x40),
663 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpg1", 0x44),
664 EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48),
665 EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c),
666 EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50),
667 EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"),
668 EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"),
669 EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"),
670 EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"),
671 EXYNOS_PIN_BANK_EINTN(6, 0x320, "gpy2"),
672 EXYNOS_PIN_BANK_EINTN(8, 0x340, "gpy3"),
673 EXYNOS_PIN_BANK_EINTN(8, 0x360, "gpy4"),
674 EXYNOS_PIN_BANK_EINTN(8, 0x380, "gpy5"),
675 EXYNOS_PIN_BANK_EINTN(8, 0x3A0, "gpy6"),
676 EXYNOS_PIN_BANK_EINTN(8, 0x3C0, "gpy7"),
677 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
678 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
679 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
680 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
681 };
682
683 /* pin banks of exynos5410 pin-controller 1 */
684 static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst = {
685 /* Must start with EINTG banks, ordered by EINT group number. */
686 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00),
687 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04),
688 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpj2", 0x08),
689 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpj3", 0x0c),
690 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpj4", 0x10),
691 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpk0", 0x14),
692 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpk1", 0x18),
693 EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpk2", 0x1c),
694 EXYNOS_PIN_BANK_EINTG(7, 0x100, "gpk3", 0x20),
695 };
696
697 /* pin banks of exynos5410 pin-controller 2 */
698 static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst = {
699 /* Must start with EINTG banks, ordered by EINT group number. */
700 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
701 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
702 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
703 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
704 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
705 };
706
707 /* pin banks of exynos5410 pin-controller 3 */
708 static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = {
709 /* Must start with EINTG banks, ordered by EINT group number. */
710 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
711 };
712
713 /*
714 * Samsung pinctrl driver data for Exynos5410 SoC. Exynos5410 SoC includes
715 * four gpio/pin-mux/pinconfig controllers.
716 */
717 static const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = {
718 {
719 /* pin-controller instance 0 data */
720 .pin_banks = exynos5410_pin_banks0,
721 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks0),
722 .eint_gpio_init = exynos_eint_gpio_init,
723 .eint_wkup_init = exynos_eint_wkup_init,
724 .suspend = exynos_pinctrl_suspend,
725 .resume = exynos_pinctrl_resume,
726 }, {
727 /* pin-controller instance 1 data */
728 .pin_banks = exynos5410_pin_banks1,
729 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks1),
730 .eint_gpio_init = exynos_eint_gpio_init,
731 .suspend = exynos_pinctrl_suspend,
732 .resume = exynos_pinctrl_resume,
733 }, {
734 /* pin-controller instance 2 data */
735 .pin_banks = exynos5410_pin_banks2,
736 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks2),
737 .eint_gpio_init = exynos_eint_gpio_init,
738 .suspend = exynos_pinctrl_suspend,
739 .resume = exynos_pinctrl_resume,
740 }, {
741 /* pin-controller instance 3 data */
742 .pin_banks = exynos5410_pin_banks3,
743 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks3),
744 .eint_gpio_init = exynos_eint_gpio_init,
745 .suspend = exynos_pinctrl_suspend,
746 .resume = exynos_pinctrl_resume,
747 },
748 };
749
750 const struct samsung_pinctrl_of_match_data exynos5410_of_data __initconst = {
751 .ctrl = exynos5410_pin_ctrl,
752 .num_ctrl = ARRAY_SIZE(exynos5410_pin_ctrl),
753 };
754
755 /* pin banks of exynos5420 pin-controller 0 */
756 static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = {
757 /* Must start with EINTG banks, ordered by EINT group number. */
758 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
759 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
760 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
761 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
762 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
763 };
764
765 /* pin banks of exynos5420 pin-controller 1 */
766 static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst = {
767 /* Must start with EINTG banks, ordered by EINT group number. */
768 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00),
769 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04),
770 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
771 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
772 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10),
773 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14),
774 EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"),
775 EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"),
776 EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"),
777 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"),
778 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"),
779 EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"),
780 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"),
781 };
782
783 /* pin banks of exynos5420 pin-controller 2 */
784 static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst = {
785 /* Must start with EINTG banks, ordered by EINT group number. */
786 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
787 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
788 EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08),
789 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c),
790 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
791 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
792 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
793 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c),
794 };
795
796 /* pin banks of exynos5420 pin-controller 3 */
797 static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst = {
798 /* Must start with EINTG banks, ordered by EINT group number. */
799 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
800 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
801 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
802 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
803 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
804 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
805 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18),
806 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c),
807 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20),
808 };
809
810 /* pin banks of exynos5420 pin-controller 4 */
811 static const struct samsung_pin_bank_data exynos5420_pin_banks4[] __initconst = {
812 /* Must start with EINTG banks, ordered by EINT group number. */
813 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
814 };
815
816 /* PMU pad retention groups registers for Exynos5420 (without audio) */
817 static const u32 exynos5420_retention_regs[] = {
818 EXYNOS_PAD_RET_DRAM_OPTION,
819 EXYNOS_PAD_RET_JTAG_OPTION,
820 EXYNOS5420_PAD_RET_GPIO_OPTION,
821 EXYNOS5420_PAD_RET_UART_OPTION,
822 EXYNOS5420_PAD_RET_MMCA_OPTION,
823 EXYNOS5420_PAD_RET_MMCB_OPTION,
824 EXYNOS5420_PAD_RET_MMCC_OPTION,
825 EXYNOS5420_PAD_RET_HSI_OPTION,
826 EXYNOS_PAD_RET_EBIA_OPTION,
827 EXYNOS_PAD_RET_EBIB_OPTION,
828 EXYNOS5420_PAD_RET_SPI_OPTION,
829 EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION,
830 };
831
832 static const struct samsung_retention_data exynos5420_retention_data __initconst = {
833 .regs = exynos5420_retention_regs,
834 .nr_regs = ARRAY_SIZE(exynos5420_retention_regs),
835 .value = EXYNOS_WAKEUP_FROM_LOWPWR,
836 .refcnt = &exynos_shared_retention_refcnt,
837 .init = exynos_retention_init,
838 };
839
840 /*
841 * Samsung pinctrl driver data for Exynos5420 SoC. Exynos5420 SoC includes
842 * four gpio/pin-mux/pinconfig controllers.
843 */
844 static const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = {
845 {
846 /* pin-controller instance 0 data */
847 .pin_banks = exynos5420_pin_banks0,
848 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0),
849 .eint_gpio_init = exynos_eint_gpio_init,
850 .eint_wkup_init = exynos_eint_wkup_init,
851 .suspend = exynos_pinctrl_suspend,
852 .resume = exynos_pinctrl_resume,
853 .retention_data = &exynos5420_retention_data,
854 }, {
855 /* pin-controller instance 1 data */
856 .pin_banks = exynos5420_pin_banks1,
857 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1),
858 .eint_gpio_init = exynos_eint_gpio_init,
859 .suspend = exynos_pinctrl_suspend,
860 .resume = exynos_pinctrl_resume,
861 .retention_data = &exynos5420_retention_data,
862 }, {
863 /* pin-controller instance 2 data */
864 .pin_banks = exynos5420_pin_banks2,
865 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2),
866 .eint_gpio_init = exynos_eint_gpio_init,
867 .suspend = exynos_pinctrl_suspend,
868 .resume = exynos_pinctrl_resume,
869 .retention_data = &exynos5420_retention_data,
870 }, {
871 /* pin-controller instance 3 data */
872 .pin_banks = exynos5420_pin_banks3,
873 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3),
874 .eint_gpio_init = exynos_eint_gpio_init,
875 .suspend = exynos_pinctrl_suspend,
876 .resume = exynos_pinctrl_resume,
877 .retention_data = &exynos5420_retention_data,
878 }, {
879 /* pin-controller instance 4 data */
880 .pin_banks = exynos5420_pin_banks4,
881 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4),
882 .eint_gpio_init = exynos_eint_gpio_init,
883 .suspend = exynos_pinctrl_suspend,
884 .resume = exynos_pinctrl_resume,
885 .retention_data = &exynos4_audio_retention_data,
886 },
887 };
888
889 const struct samsung_pinctrl_of_match_data exynos5420_of_data __initconst = {
890 .ctrl = exynos5420_pin_ctrl,
891 .num_ctrl = ARRAY_SIZE(exynos5420_pin_ctrl),
892 };
893
