1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Pinctrl GPIO driver for Intel Baytrail
4 *
5 * Copyright (c) 2012-2013, Intel Corporation
6 * Author: Mathias Nyman <mathias.nyman@linux.intel.com>
7 */
8
9 #include <linux/kernel.h>
10 #include <linux/init.h>
11 #include <linux/types.h>
12 #include <linux/bitops.h>
13 #include <linux/interrupt.h>
14 #include <linux/gpio.h>
15 #include <linux/gpio/driver.h>
16 #include <linux/acpi.h>
17 #include <linux/platform_device.h>
18 #include <linux/seq_file.h>
19 #include <linux/io.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/pinctrl/pinctrl.h>
22 #include <linux/pinctrl/pinmux.h>
23 #include <linux/pinctrl/pinconf.h>
24 #include <linux/pinctrl/pinconf-generic.h>
25
26 /* memory mapped register offsets */
27 #define BYT_CONF0_REG 0x000
28 #define BYT_CONF1_REG 0x004
29 #define BYT_VAL_REG 0x008
30 #define BYT_DFT_REG 0x00c
31 #define BYT_INT_STAT_REG 0x800
32 #define BYT_DEBOUNCE_REG 0x9d0
33
34 /* BYT_CONF0_REG register bits */
35 #define BYT_IODEN BIT(31)
36 #define BYT_DIRECT_IRQ_EN BIT(27)
37 #define BYT_TRIG_NEG BIT(26)
38 #define BYT_TRIG_POS BIT(25)
39 #define BYT_TRIG_LVL BIT(24)
40 #define BYT_DEBOUNCE_EN BIT(20)
41 #define BYT_GLITCH_FILTER_EN BIT(19)
42 #define BYT_GLITCH_F_SLOW_CLK BIT(17)
43 #define BYT_GLITCH_F_FAST_CLK BIT(16)
44 #define BYT_PULL_STR_SHIFT 9
45 #define BYT_PULL_STR_MASK (3 << BYT_PULL_STR_SHIFT)
46 #define BYT_PULL_STR_2K (0 << BYT_PULL_STR_SHIFT)
47 #define BYT_PULL_STR_10K (1 << BYT_PULL_STR_SHIFT)
48 #define BYT_PULL_STR_20K (2 << BYT_PULL_STR_SHIFT)
49 #define BYT_PULL_STR_40K (3 << BYT_PULL_STR_SHIFT)
50 #define BYT_PULL_ASSIGN_SHIFT 7
51 #define BYT_PULL_ASSIGN_MASK (3 << BYT_PULL_ASSIGN_SHIFT)
52 #define BYT_PULL_ASSIGN_UP (1 << BYT_PULL_ASSIGN_SHIFT)
53 #define BYT_PULL_ASSIGN_DOWN (2 << BYT_PULL_ASSIGN_SHIFT)
54 #define BYT_PIN_MUX 0x07
55
56 /* BYT_VAL_REG register bits */
57 #define BYT_INPUT_EN BIT(2) /* 0: input enabled (active low)*/
58 #define BYT_OUTPUT_EN BIT(1) /* 0: output enabled (active low)*/
59 #define BYT_LEVEL BIT(0)
60
61 #define BYT_DIR_MASK (BIT(1) | BIT(2))
62 #define BYT_TRIG_MASK (BIT(26) | BIT(25) | BIT(24))
63
64 #define BYT_CONF0_RESTORE_MASK (BYT_DIRECT_IRQ_EN | BYT_TRIG_MASK | \
65 BYT_PIN_MUX)
66 #define BYT_VAL_RESTORE_MASK (BYT_DIR_MASK | BYT_LEVEL)
67
68 /* BYT_DEBOUNCE_REG bits */
69 #define BYT_DEBOUNCE_PULSE_MASK 0x7
70 #define BYT_DEBOUNCE_PULSE_375US 1
71 #define BYT_DEBOUNCE_PULSE_750US 2
72 #define BYT_DEBOUNCE_PULSE_1500US 3
73 #define BYT_DEBOUNCE_PULSE_3MS 4
74 #define BYT_DEBOUNCE_PULSE_6MS 5
75 #define BYT_DEBOUNCE_PULSE_12MS 6
76 #define BYT_DEBOUNCE_PULSE_24MS 7
77
78 #define BYT_NGPIO_SCORE 102
79 #define BYT_NGPIO_NCORE 28
80 #define BYT_NGPIO_SUS 44
81
82 #define BYT_SCORE_ACPI_UID "1"
83 #define BYT_NCORE_ACPI_UID "2"
84 #define BYT_SUS_ACPI_UID "3"
85
86 /*
87 * This is the function value most pins have for GPIO muxing. If the value
88 * differs from the default one, it must be explicitly mentioned. Otherwise, the
89 * pin control implementation will set the muxing value to default GPIO if it
90 * does not find a match for the requested function.
91 */
92 #define BYT_DEFAULT_GPIO_MUX 0
93
94 struct byt_gpio_pin_context {
95 u32 conf0;
96 u32 val;
97 };
98
99 struct byt_simple_func_mux {
100 const char *name;
101 unsigned short func;
102 };
103
104 struct byt_mixed_func_mux {
105 const char *name;
106 const unsigned short *func_values;
107 };
108
109 struct byt_pingroup {
110 const char *name;
111 const unsigned int *pins;
112 size_t npins;
113 unsigned short has_simple_funcs;
114 union {
115 const struct byt_simple_func_mux *simple_funcs;
116 const struct byt_mixed_func_mux *mixed_funcs;
117 };
118 size_t nfuncs;
119 };
120
121 struct byt_function {
122 const char *name;
123 const char * const *groups;
124 size_t ngroups;
125 };
126
127 struct byt_community {
128 unsigned int pin_base;
129 size_t npins;
130 const unsigned int *pad_map;
131 void __iomem *reg_base;
132 };
133
134 #define SIMPLE_FUNC(n, f) \
135 { \
136 .name = (n), \
137 .func = (f), \
138 }
139 #define MIXED_FUNC(n, f) \
140 { \
141 .name = (n), \
142 .func_values = (f), \
143 }
144
145 #define PIN_GROUP_SIMPLE(n, p, f) \
146 { \
147 .name = (n), \
148 .pins = (p), \
149 .npins = ARRAY_SIZE((p)), \
150 .has_simple_funcs = 1, \
151 { \
152 .simple_funcs = (f), \
153 }, \
154 .nfuncs = ARRAY_SIZE((f)), \
155 }
156 #define PIN_GROUP_MIXED(n, p, f) \
157 { \
158 .name = (n), \
159 .pins = (p), \
160 .npins = ARRAY_SIZE((p)), \
161 .has_simple_funcs = 0, \
162 { \
163 .mixed_funcs = (f), \
164 }, \
165 .nfuncs = ARRAY_SIZE((f)), \
166 }
167
168 #define FUNCTION(n, g) \
169 { \
170 .name = (n), \
171 .groups = (g), \
172 .ngroups = ARRAY_SIZE((g)), \
173 }
174
175 #define COMMUNITY(p, n, map) \
176 { \
177 .pin_base = (p), \
178 .npins = (n), \
179 .pad_map = (map),\
180 }
181
182 struct byt_pinctrl_soc_data {
183 const char *uid;
184 const struct pinctrl_pin_desc *pins;
185 size_t npins;
186 const struct byt_pingroup *groups;
187 size_t ngroups;
188 const struct byt_function *functions;
189 size_t nfunctions;
190 const struct byt_community *communities;
191 size_t ncommunities;
192 };
193
194 struct byt_gpio {
195 struct gpio_chip chip;
196 struct platform_device *pdev;
197 struct pinctrl_dev *pctl_dev;
198 struct pinctrl_desc pctl_desc;
199 raw_spinlock_t lock;
200 const struct byt_pinctrl_soc_data *soc_data;
201 struct byt_community *communities_copy;
202 struct byt_gpio_pin_context *saved_context;
203 };
204
205 /* SCORE pins, aka GPIOC_<pin_no> or GPIO_S0_SC[<pin_no>] */
206 static const struct pinctrl_pin_desc byt_score_pins[] = {
207 PINCTRL_PIN(0, "SATA_GP0"),
208 PINCTRL_PIN(1, "SATA_GP1"),
209 PINCTRL_PIN(2, "SATA_LED#"),
210 PINCTRL_PIN(3, "PCIE_CLKREQ0"),
211 PINCTRL_PIN(4, "PCIE_CLKREQ1"),
212 PINCTRL_PIN(5, "PCIE_CLKREQ2"),
213 PINCTRL_PIN(6, "PCIE_CLKREQ3"),
214 PINCTRL_PIN(7, "SD3_WP"),
215 PINCTRL_PIN(8, "HDA_RST"),
216 PINCTRL_PIN(9, "HDA_SYNC"),
217 PINCTRL_PIN(10, "HDA_CLK"),
218 PINCTRL_PIN(11, "HDA_SDO"),
219 PINCTRL_PIN(12, "HDA_SDI0"),
220 PINCTRL_PIN(13, "HDA_SDI1"),
221 PINCTRL_PIN(14, "GPIO_S0_SC14"),
222 PINCTRL_PIN(15, "GPIO_S0_SC15"),
223 PINCTRL_PIN(16, "MMC1_CLK"),
224 PINCTRL_PIN(17, "MMC1_D0"),
225 PINCTRL_PIN(18, "MMC1_D1"),
226 PINCTRL_PIN(19, "MMC1_D2"),
227 PINCTRL_PIN(20, "MMC1_D3"),
228 PINCTRL_PIN(21, "MMC1_D4"),
229 PINCTRL_PIN(22, "MMC1_D5"),
230 PINCTRL_PIN(23, "MMC1_D6"),
231 PINCTRL_PIN(24, "MMC1_D7"),
232 PINCTRL_PIN(25, "MMC1_CMD"),
233 PINCTRL_PIN(26, "MMC1_RST"),
234 PINCTRL_PIN(27, "SD2_CLK"),
235 PINCTRL_PIN(28, "SD2_D0"),
236 PINCTRL_PIN(29, "SD2_D1"),
237 PINCTRL_PIN(30, "SD2_D2"),
238 PINCTRL_PIN(31, "SD2_D3_CD"),
239 PINCTRL_PIN(32, "SD2_CMD"),
240 PINCTRL_PIN(33, "SD3_CLK"),
241 PINCTRL_PIN(34, "SD3_D0"),
242 PINCTRL_PIN(35, "SD3_D1"),
243 PINCTRL_PIN(36, "SD3_D2"),
244 PINCTRL_PIN(37, "SD3_D3"),
245 PINCTRL_PIN(38, "SD3_CD"),
246 PINCTRL_PIN(39, "SD3_CMD"),
247 PINCTRL_PIN(40, "SD3_1P8EN"),
248 PINCTRL_PIN(41, "SD3_PWREN#"),
249 PINCTRL_PIN(42, "ILB_LPC_AD0"),
250 PINCTRL_PIN(43, "ILB_LPC_AD1"),
251 PINCTRL_PIN(44, "ILB_LPC_AD2"),
252 PINCTRL_PIN(45, "ILB_LPC_AD3"),
253 PINCTRL_PIN(46, "ILB_LPC_FRAME"),
254 PINCTRL_PIN(47, "ILB_LPC_CLK0"),
255 PINCTRL_PIN(48, "ILB_LPC_CLK1"),
256 PINCTRL_PIN(49, "ILB_LPC_CLKRUN"),
257 PINCTRL_PIN(50, "ILB_LPC_SERIRQ"),
258 PINCTRL_PIN(51, "PCU_SMB_DATA"),
259 PINCTRL_PIN(52, "PCU_SMB_CLK"),
260 PINCTRL_PIN(53, "PCU_SMB_ALERT"),
261 PINCTRL_PIN(54, "ILB_8254_SPKR"),
262 PINCTRL_PIN(55, "GPIO_S0_SC55"),
263 PINCTRL_PIN(56, "GPIO_S0_SC56"),
264 PINCTRL_PIN(57, "GPIO_S0_SC57"),
265 PINCTRL_PIN(58, "GPIO_S0_SC58"),
266 PINCTRL_PIN(59, "GPIO_S0_SC59"),
267 PINCTRL_PIN(60, "GPIO_S0_SC60"),
268 PINCTRL_PIN(61, "GPIO_S0_SC61"),
269 PINCTRL_PIN(62, "LPE_I2S2_CLK"),
270 PINCTRL_PIN(63, "LPE_I2S2_FRM"),
271 PINCTRL_PIN(64, "LPE_I2S2_DATAIN"),
272 PINCTRL_PIN(65, "LPE_I2S2_DATAOUT"),
273 PINCTRL_PIN(66, "SIO_SPI_CS"),
274 PINCTRL_PIN(67, "SIO_SPI_MISO"),
275 PINCTRL_PIN(68, "SIO_SPI_MOSI"),
276 PINCTRL_PIN(69, "SIO_SPI_CLK"),
277 PINCTRL_PIN(70, "SIO_UART1_RXD"),
278 PINCTRL_PIN(71, "SIO_UART1_TXD"),
279 PINCTRL_PIN(72, "SIO_UART1_RTS"),
280 PINCTRL_PIN(73, "SIO_UART1_CTS"),
281 PINCTRL_PIN(74, "SIO_UART2_RXD"),
282 PINCTRL_PIN(75, "SIO_UART2_TXD"),
283 PINCTRL_PIN(76, "SIO_UART2_RTS"),
284 PINCTRL_PIN(77, "SIO_UART2_CTS"),
285 PINCTRL_PIN(78, "SIO_I2C0_DATA"),
286 PINCTRL_PIN(79, "SIO_I2C0_CLK"),
287 PINCTRL_PIN(80, "SIO_I2C1_DATA"),
288 PINCTRL_PIN(81, "SIO_I2C1_CLK"),
289 PINCTRL_PIN(82, "SIO_I2C2_DATA"),
290 PINCTRL_PIN(83, "SIO_I2C2_CLK"),
291 PINCTRL_PIN(84, "SIO_I2C3_DATA"),
292 PINCTRL_PIN(85, "SIO_I2C3_CLK"),
293 PINCTRL_PIN(86, "SIO_I2C4_DATA"),
294 PINCTRL_PIN(87, "SIO_I2C4_CLK"),
295 PINCTRL_PIN(88, "SIO_I2C5_DATA"),
296 PINCTRL_PIN(89, "SIO_I2C5_CLK"),
297 PINCTRL_PIN(90, "SIO_I2C6_DATA"),
298 PINCTRL_PIN(91, "SIO_I2C6_CLK"),
299 PINCTRL_PIN(92, "GPIO_S0_SC92"),
300 PINCTRL_PIN(93, "GPIO_S0_SC93"),
301 PINCTRL_PIN(94, "SIO_PWM0"),
302 PINCTRL_PIN(95, "SIO_PWM1"),
303 PINCTRL_PIN(96, "PMC_PLT_CLK0"),
304 PINCTRL_PIN(97, "PMC_PLT_CLK1"),
305 PINCTRL_PIN(98, "PMC_PLT_CLK2"),
306 PINCTRL_PIN(99, "PMC_PLT_CLK3"),
307 PINCTRL_PIN(100, "PMC_PLT_CLK4"),
308 PINCTRL_PIN(101, "PMC_PLT_CLK5"),
309 };
310
311 static const unsigned int byt_score_pins_map[BYT_NGPIO_SCORE] = {
312 85, 89, 93, 96, 99, 102, 98, 101, 34, 37,
313 36, 38, 39, 35, 40, 84, 62, 61, 64, 59,
314 54, 56, 60, 55, 63, 57, 51, 50, 53, 47,
315 52, 49, 48, 43, 46, 41, 45, 42, 58, 44,
316 95, 105, 70, 68, 67, 66, 69, 71, 65, 72,
317 86, 90, 88, 92, 103, 77, 79, 83, 78, 81,
318 80, 82, 13, 12, 15, 14, 17, 18, 19, 16,
319 2, 1, 0, 4, 6, 7, 9, 8, 33, 32,
320 31, 30, 29, 27, 25, 28, 26, 23, 21, 20,
321 24, 22, 5, 3, 10, 11, 106, 87, 91, 104,
322 97, 100,
323 };
324
325 /* SCORE groups */
326 static const unsigned int byt_score_uart1_pins[] = { 70, 71, 72, 73 };
327 static const unsigned int byt_score_uart2_pins[] = { 74, 75, 76, 77 };
328 static const struct byt_simple_func_mux byt_score_uart_mux[] = {
329 SIMPLE_FUNC("uart", 1),
330 };
331
332 static const unsigned int byt_score_pwm0_pins[] = { 94 };
333 static const unsigned int byt_score_pwm1_pins[] = { 95 };
334 static const struct byt_simple_func_mux byt_score_pwm_mux[] = {
335 SIMPLE_FUNC("pwm", 1),
336 };
337
338 static const unsigned int byt_score_sio_spi_pins[] = { 66, 67, 68, 69 };
339 static const struct byt_simple_func_mux byt_score_spi_mux[] = {
340 SIMPLE_FUNC("spi", 1),
341 };
342
343 static const unsigned int byt_score_i2c5_pins[] = { 88, 89 };
344 static const unsigned int byt_score_i2c6_pins[] = { 90, 91 };
345 static const unsigned int byt_score_i2c4_pins[] = { 86, 87 };
346 static const unsigned int byt_score_i2c3_pins[] = { 84, 85 };
347 static const unsigned int byt_score_i2c2_pins[] = { 82, 83 };
348 static const unsigned int byt_score_i2c1_pins[] = { 80, 81 };
349 static const unsigned int byt_score_i2c0_pins[] = { 78, 79 };
350 static const struct byt_simple_func_mux byt_score_i2c_mux[] = {
351 SIMPLE_FUNC("i2c", 1),
352 };
353
354 static const unsigned int byt_score_ssp0_pins[] = { 8, 9, 10, 11 };
355 static const unsigned int byt_score_ssp1_pins[] = { 12, 13, 14, 15 };
356 static const unsigned int byt_score_ssp2_pins[] = { 62, 63, 64, 65 };
357 static const struct byt_simple_func_mux byt_score_ssp_mux[] = {
358 SIMPLE_FUNC("ssp", 1),
359 };
360
361 static const unsigned int byt_score_sdcard_pins[] = {
362 7, 33, 34, 35, 36, 37, 38, 39, 40, 41,
363 };
364 static const unsigned short byt_score_sdcard_mux_values[] = {
365 2, 1, 1, 1, 1, 1, 1, 1, 1, 1,
366 };
367 static const struct byt_mixed_func_mux byt_score_sdcard_mux[] = {
368 MIXED_FUNC("sdcard", byt_score_sdcard_mux_values),
369 };
370
371 static const unsigned int byt_score_sdio_pins[] = { 27, 28, 29, 30, 31, 32 };
372 static const struct byt_simple_func_mux byt_score_sdio_mux[] = {
373 SIMPLE_FUNC("sdio", 1),
374 };
375
376 static const unsigned int byt_score_emmc_pins[] = {
377 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26,
378 };
379 static const struct byt_simple_func_mux byt_score_emmc_mux[] = {
380 SIMPLE_FUNC("emmc", 1),
381 };
382
383 static const unsigned int byt_score_ilb_lpc_pins[] = {
384 42, 43, 44, 45, 46, 47, 48, 49, 50,
385 };
386 static const struct byt_simple_func_mux byt_score_lpc_mux[] = {
387 SIMPLE_FUNC("lpc", 1),
388 };
389
390 static const unsigned int byt_score_sata_pins[] = { 0, 1, 2 };
391 static const struct byt_simple_func_mux byt_score_sata_mux[] = {
392 SIMPLE_FUNC("sata", 1),
393 };
394
395 static const unsigned int byt_score_plt_clk0_pins[] = { 96 };
396 static const unsigned int byt_score_plt_clk1_pins[] = { 97 };
397 static const unsigned int byt_score_plt_clk2_pins[] = { 98 };
398 static const unsigned int byt_score_plt_clk3_pins[] = { 99 };
399 static const unsigned int byt_score_plt_clk4_pins[] = { 100 };
400 static const unsigned int byt_score_plt_clk5_pins[] = { 101 };
401 static const struct byt_simple_func_mux byt_score_plt_clk_mux[] = {
402 SIMPLE_FUNC("plt_clk", 1),
403 };
404
405 static const unsigned int byt_score_smbus_pins[] = { 51, 52, 53 };
406 static const struct byt_simple_func_mux byt_score_smbus_mux[] = {
407 SIMPLE_FUNC("smbus", 1),
408 };
409
410 static const struct byt_pingroup byt_score_groups[] = {
411 PIN_GROUP_SIMPLE("uart1_grp",
412 byt_score_uart1_pins, byt_score_uart_mux),
413 PIN_GROUP_SIMPLE("uart2_grp",
414 byt_score_uart2_pins, byt_score_uart_mux),
415 PIN_GROUP_SIMPLE("pwm0_grp",
416 byt_score_pwm0_pins, byt_score_pwm_mux),
417 PIN_GROUP_SIMPLE("pwm1_grp",
418 byt_score_pwm1_pins, byt_score_pwm_mux),
419 PIN_GROUP_SIMPLE("ssp2_grp",
420 byt_score_ssp2_pins, byt_score_pwm_mux),
421 PIN_GROUP_SIMPLE("sio_spi_grp",
422 byt_score_sio_spi_pins, byt_score_spi_mux),
423 PIN_GROUP_SIMPLE("i2c5_grp",
424 byt_score_i2c5_pins, byt_score_i2c_mux),
425 PIN_GROUP_SIMPLE("i2c6_grp",
426 byt_score_i2c6_pins, byt_score_i2c_mux),
427 PIN_GROUP_SIMPLE("i2c4_grp",
428 byt_score_i2c4_pins, byt_score_i2c_mux),
429 PIN_GROUP_SIMPLE("i2c3_grp",
430 byt_score_i2c3_pins, byt_score_i2c_mux),
431 PIN_GROUP_SIMPLE("i2c2_grp",
432 byt_score_i2c2_pins, byt_score_i2c_mux),
433 PIN_GROUP_SIMPLE("i2c1_grp",
434 byt_score_i2c1_pins, byt_score_i2c_mux),
435 PIN_GROUP_SIMPLE("i2c0_grp",
436 byt_score_i2c0_pins, byt_score_i2c_mux),
437 PIN_GROUP_SIMPLE("ssp0_grp",
438 byt_score_ssp0_pins, byt_score_ssp_mux),
439 PIN_GROUP_SIMPLE("ssp1_grp",
440 byt_score_ssp1_pins, byt_score_ssp_mux),
441 PIN_GROUP_MIXED("sdcard_grp",
442 byt_score_sdcard_pins, byt_score_sdcard_mux),
443 PIN_GROUP_SIMPLE("sdio_grp",
444 byt_score_sdio_pins, byt_score_sdio_mux),
445 PIN_GROUP_SIMPLE("emmc_grp",
446 byt_score_emmc_pins, byt_score_emmc_mux),
447 PIN_GROUP_SIMPLE("lpc_grp",
448 byt_score_ilb_lpc_pins, byt_score_lpc_mux),
449 PIN_GROUP_SIMPLE("sata_grp",
450 byt_score_sata_pins, byt_score_sata_mux),
451 PIN_GROUP_SIMPLE("plt_clk0_grp",
452 byt_score_plt_clk0_pins, byt_score_plt_clk_mux),
453 PIN_GROUP_SIMPLE("plt_clk1_grp",
454 byt_score_plt_clk1_pins, byt_score_plt_clk_mux),
455 PIN_GROUP_SIMPLE("plt_clk2_grp",
456 byt_score_plt_clk2_pins, byt_score_plt_clk_mux),
457 PIN_GROUP_SIMPLE("plt_clk3_grp",
458 byt_score_plt_clk3_pins, byt_score_plt_clk_mux),
459 PIN_GROUP_SIMPLE("plt_clk4_grp",
460 byt_score_plt_clk4_pins, byt_score_plt_clk_mux),
461 PIN_GROUP_SIMPLE("plt_clk5_grp",
462 byt_score_plt_clk5_pins, byt_score_plt_clk_mux),
463 PIN_GROUP_SIMPLE("smbus_grp",
464 byt_score_smbus_pins, byt_score_smbus_mux),
465 };
466
467 static const char * const byt_score_uart_groups[] = {
468 "uart1_grp", "uart2_grp",
469 };
470 static const char * const byt_score_pwm_groups[] = {
471 "pwm0_grp", "pwm1_grp",
472 };
473 static const char * const byt_score_ssp_groups[] = {
474 "ssp0_grp", "ssp1_grp", "ssp2_grp",
475 };
476 static const char * const byt_score_spi_groups[] = { "sio_spi_grp" };
477 static const char * const byt_score_i2c_groups[] = {
478 "i2c0_grp", "i2c1_grp", "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp",
479 "i2c6_grp",
480 };
481 static const char * const byt_score_sdcard_groups[] = { "sdcard_grp" };
482 static const char * const byt_score_sdio_groups[] = { "sdio_grp" };
483 static const char * const byt_score_emmc_groups[] = { "emmc_grp" };
484 static const char * const byt_score_lpc_groups[] = { "lpc_grp" };
485 static const char * const byt_score_sata_groups[] = { "sata_grp" };
486 static const char * const byt_score_plt_clk_groups[] = {
487 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
488 "plt_clk4_grp", "plt_clk5_grp",
489 };
490 static const char * const byt_score_smbus_groups[] = { "smbus_grp" };
491 static const char * const byt_score_gpio_groups[] = {
492 "uart1_grp", "uart2_grp", "pwm0_grp", "pwm1_grp", "ssp0_grp",
493 "ssp1_grp", "ssp2_grp", "sio_spi_grp", "i2c0_grp", "i2c1_grp",
494 "i2c2_grp", "i2c3_grp", "i2c4_grp", "i2c5_grp", "i2c6_grp",
495 "sdcard_grp", "sdio_grp", "emmc_grp", "lpc_grp", "sata_grp",
496 "plt_clk0_grp", "plt_clk1_grp", "plt_clk2_grp", "plt_clk3_grp",
497 "plt_clk4_grp", "plt_clk5_grp", "smbus_grp",
498
499 };
500
501 static const struct byt_function byt_score_functions[] = {
502 FUNCTION("uart", byt_score_uart_groups),
503 FUNCTION("pwm", byt_score_pwm_groups),
504 FUNCTION("ssp", byt_score_ssp_groups),
505 FUNCTION("spi", byt_score_spi_groups),
506 FUNCTION("i2c", byt_score_i2c_groups),
507 FUNCTION("sdcard", byt_score_sdcard_groups),
508 FUNCTION("sdio", byt_score_sdio_groups),
509 FUNCTION("emmc", byt_score_emmc_groups),
510 FUNCTION("lpc", byt_score_lpc_groups),
511 FUNCTION("sata", byt_score_sata_groups),
512 FUNCTION("plt_clk", byt_score_plt_clk_groups),
513 FUNCTION("smbus", byt_score_smbus_groups),
514 FUNCTION("gpio", byt_score_gpio_groups),
515 };
516
517 static const struct byt_community byt_score_communities[] = {
518 COMMUNITY(0, BYT_NGPIO_SCORE, byt_score_pins_map),
519 };
520
521 static const struct byt_pinctrl_soc_data byt_score_soc_data = {
522 .uid = BYT_SCORE_ACPI_UID,
523 .pins = byt_score_pins,
524 .npins = ARRAY_SIZE(byt_score_pins),
525 .groups = byt_score_groups,
526 .ngroups = ARRAY_SIZE(byt_score_groups),
527 .functions = byt_score_functions,
528 .nfunctions = ARRAY_SIZE(byt_score_functions),
529 .communities = byt_score_communities,
530 .ncommunities = ARRAY_SIZE(byt_score_communities),
531 };
532
533 /* SUS pins, aka GPIOS_<pin_no> or GPIO_S5[<pin_no>] */
534 static const struct pinctrl_pin_desc byt_sus_pins[] = {
535 PINCTRL_PIN(0, "GPIO_S50"),
536 PINCTRL_PIN(1, "GPIO_S51"),
537 PINCTRL_PIN(2, "GPIO_S52"),
538 PINCTRL_PIN(3, "GPIO_S53"),
539 PINCTRL_PIN(4, "GPIO_S54"),
540 PINCTRL_PIN(5, "GPIO_S55"),
541 PINCTRL_PIN(6, "GPIO_S56"),
542 PINCTRL_PIN(7, "GPIO_S57"),
543 PINCTRL_PIN(8, "GPIO_S58"),
544 PINCTRL_PIN(9, "GPIO_S59"),
545 PINCTRL_PIN(10, "GPIO_S510"),
546 PINCTRL_PIN(11, "PMC_SUSPWRDNACK"),
547 PINCTRL_PIN(12, "PMC_SUSCLK0"),
548 PINCTRL_PIN(13, "GPIO_S513"),
549 PINCTRL_PIN(14, "USB_ULPI_RST"),
550 PINCTRL_PIN(15, "PMC_WAKE_PCIE0#"),
551 PINCTRL_PIN(16, "PMC_PWRBTN"),
552 PINCTRL_PIN(17, "GPIO_S517"),
553 PINCTRL_PIN(18, "PMC_SUS_STAT"),
554 PINCTRL_PIN(19, "USB_OC0"),
555 PINCTRL_PIN(20, "USB_OC1"),
556 PINCTRL_PIN(21, "PCU_SPI_CS1"),
557 PINCTRL_PIN(22, "GPIO_S522"),
558 PINCTRL_PIN(23, "GPIO_S523"),
559 PINCTRL_PIN(24, "GPIO_S524"),
560 PINCTRL_PIN(25, "GPIO_S525"),
561 PINCTRL_PIN(26, "GPIO_S526"),
562 PINCTRL_PIN(27, "GPIO_S527"),
563 PINCTRL_PIN(28, "GPIO_S528"),
564 PINCTRL_PIN(29, "GPIO_S529"),
565 PINCTRL_PIN(30, "GPIO_S530"),
566 PINCTRL_PIN(31, "USB_ULPI_CLK"),
567 PINCTRL_PIN(32, "USB_ULPI_DATA0"),
568 PINCTRL_PIN(33, "USB_ULPI_DATA1"),
569 PINCTRL_PIN(34, "USB_ULPI_DATA2"),
570 PINCTRL_PIN(35, "USB_ULPI_DATA3"),
571 PINCTRL_PIN(36, "USB_ULPI_DATA4"),
572 PINCTRL_PIN(37, "USB_ULPI_DATA5"),
573 PINCTRL_PIN(38, "USB_ULPI_DATA6"),
574 PINCTRL_PIN(39, "USB_ULPI_DATA7"),
575 PINCTRL_PIN(40, "USB_ULPI_DIR"),
576 PINCTRL_PIN(41, "USB_ULPI_NXT"),
577 PINCTRL_PIN(42, "USB_ULPI_STP"),
578 PINCTRL_PIN(43, "USB_ULPI_REFCLK"),
579 };
580
581 static const unsigned int byt_sus_pins_map[BYT_NGPIO_SUS] = {
582 29, 33, 30, 31, 32, 34, 36, 35, 38, 37,
583 18, 7, 11, 20, 17, 1, 8, 10, 19, 12,
584 0, 2, 23, 39, 28, 27, 22, 21, 24, 25,
585 26, 51, 56, 54, 49, 55, 48, 57, 50, 58,
586 52, 53, 59, 40,
587 };
588
589 static const unsigned int byt_sus_usb_over_current_pins[] = { 19, 20 };
590 static const struct byt_simple_func_mux byt_sus_usb_oc_mux[] = {
591 SIMPLE_FUNC("usb", 0),
592 SIMPLE_FUNC("gpio", 1),
593 };
594
595 static const unsigned int byt_sus_usb_ulpi_pins[] = {
596 14, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
597 };
598 static const unsigned short byt_sus_usb_ulpi_mode_values[] = {
599 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1,
600 };
601 static const unsigned short byt_sus_usb_ulpi_gpio_mode_values[] = {
602 1, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
603 };
604 static const struct byt_mixed_func_mux byt_sus_usb_ulpi_mux[] = {
605 MIXED_FUNC("usb", byt_sus_usb_ulpi_mode_values),
606 MIXED_FUNC("gpio", byt_sus_usb_ulpi_gpio_mode_values),
607 };
608
609 static const unsigned int byt_sus_pcu_spi_pins[] = { 21 };
610 static const struct byt_simple_func_mux byt_sus_pcu_spi_mux[] = {
611 SIMPLE_FUNC("spi", 0),
612 SIMPLE_FUNC("gpio", 1),
613 };
614
615 static const struct byt_pingroup byt_sus_groups[] = {
616 PIN_GROUP_SIMPLE("usb_oc_grp",
617 byt_sus_usb_over_current_pins, byt_sus_usb_oc_mux),
618 PIN_GROUP_MIXED("usb_ulpi_grp",
619 byt_sus_usb_ulpi_pins, byt_sus_usb_ulpi_mux),
620 PIN_GROUP_SIMPLE("pcu_spi_grp",
621 byt_sus_pcu_spi_pins, byt_sus_pcu_spi_mux),
622 };
623
624 static const char * const byt_sus_usb_groups[] = {
625 "usb_oc_grp", "usb_ulpi_grp",
626 };
627 static const char * const byt_sus_spi_groups[] = { "pcu_spi_grp" };
628 static const char * const byt_sus_gpio_groups[] = {
629 "usb_oc_grp", "usb_ulpi_grp", "pcu_spi_grp",
630 };
631
632 static const struct byt_function byt_sus_functions[] = {
633 FUNCTION("usb", byt_sus_usb_groups),
634 FUNCTION("spi", byt_sus_spi_groups),
635 FUNCTION("gpio", byt_sus_gpio_groups),
636 };
637
638 static const struct byt_community byt_sus_communities[] = {
639 COMMUNITY(0, BYT_NGPIO_SUS, byt_sus_pins_map),
640 };
641
642 static const struct byt_pinctrl_soc_data byt_sus_soc_data = {
643 .uid = BYT_SUS_ACPI_UID,
644 .pins = byt_sus_pins,
645 .npins = ARRAY_SIZE(byt_sus_pins),
646 .groups = byt_sus_groups,
647 .ngroups = ARRAY_SIZE(byt_sus_groups),
648 .functions = byt_sus_functions,
649 .nfunctions = ARRAY_SIZE(byt_sus_functions),
650 .communities = byt_sus_communities,
651 .ncommunities = ARRAY_SIZE(byt_sus_communities),
652 };
653
654 static const struct pinctrl_pin_desc byt_ncore_pins[] = {
655 PINCTRL_PIN(0, "GPIO_NCORE0"),
656 PINCTRL_PIN(1, "GPIO_NCORE1"),
657 PINCTRL_PIN(2, "GPIO_NCORE2"),
658 PINCTRL_PIN(3, "GPIO_NCORE3"),
659 PINCTRL_PIN(4, "GPIO_NCORE4"),
660 PINCTRL_PIN(5, "GPIO_NCORE5"),
661 PINCTRL_PIN(6, "GPIO_NCORE6"),
662 PINCTRL_PIN(7, "GPIO_NCORE7"),
663 PINCTRL_PIN(8, "GPIO_NCORE8"),
664 PINCTRL_PIN(9, "GPIO_NCORE9"),
665 PINCTRL_PIN(10, "GPIO_NCORE10"),
666 PINCTRL_PIN(11, "GPIO_NCORE11"),
667 PINCTRL_PIN(12, "GPIO_NCORE12"),
668 PINCTRL_PIN(13, "GPIO_NCORE13"),
669 PINCTRL_PIN(14, "GPIO_NCORE14"),
670 PINCTRL_PIN(15, "GPIO_NCORE15"),
671 PINCTRL_PIN(16, "GPIO_NCORE16"),
672 PINCTRL_PIN(17, "GPIO_NCORE17"),
673 PINCTRL_PIN(18, "GPIO_NCORE18"),
674 PINCTRL_PIN(19, "GPIO_NCORE19"),
675 PINCTRL_PIN(20, "GPIO_NCORE20"),
676 PINCTRL_PIN(21, "GPIO_NCORE21"),
677 PINCTRL_PIN(22, "GPIO_NCORE22"),
678 PINCTRL_PIN(23, "GPIO_NCORE23"),
679 PINCTRL_PIN(24, "GPIO_NCORE24"),
680 PINCTRL_PIN(25, "GPIO_NCORE25"),
681 PINCTRL_PIN(26, "GPIO_NCORE26"),
682 PINCTRL_PIN(27, "GPIO_NCORE27"),
683 };
684
685 static unsigned const byt_ncore_pins_map[BYT_NGPIO_NCORE] = {
686 19, 18, 17, 20, 21, 22, 24, 25, 23, 16,
687 14, 15, 12, 26, 27, 1, 4, 8, 11, 0,
688 3, 6, 10, 13, 2, 5, 9, 7,
689 };
690
691 static const struct byt_community byt_ncore_communities[] = {
692 COMMUNITY(0, BYT_NGPIO_NCORE, byt_ncore_pins_map),
693 };
694
695 static const struct byt_pinctrl_soc_data byt_ncore_soc_data = {
696 .uid = BYT_NCORE_ACPI_UID,
697 .pins = byt_ncore_pins,
698 .npins = ARRAY_SIZE(byt_ncore_pins),
699 .communities = byt_ncore_communities,
700 .ncommunities = ARRAY_SIZE(byt_ncore_communities),
701 };
702
703 static const struct byt_pinctrl_soc_data *byt_soc_data[] = {
704 &byt_score_soc_data,
705 &byt_sus_soc_data,
706 &byt_ncore_soc_data,
707 NULL,
708 };
709
byt_get_community(struct byt_gpio * vg,unsigned int pin)710 static struct byt_community *byt_get_community(struct byt_gpio *vg,
711 unsigned int pin)
712 {
713 struct byt_community *comm;
714 int i;
715
716 for (i = 0; i < vg->soc_data->ncommunities; i++) {
717 comm = vg->communities_copy + i;
718 if (pin < comm->pin_base + comm->npins && pin >= comm->pin_base)
719 return comm;
720 }
721
722 return NULL;
723 }
724
byt_gpio_reg(struct byt_gpio * vg,unsigned int offset,int reg)725 static void __iomem *byt_gpio_reg(struct byt_gpio *vg, unsigned int offset,
726 int reg)
727 {
728 struct byt_community *comm = byt_get_community(vg, offset);
729 u32 reg_offset;
730
731 if (!comm)
732 return NULL;
733
734 offset -= comm->pin_base;
735 switch (reg) {
736 case BYT_INT_STAT_REG:
737 reg_offset = (offset / 32) * 4;
738 break;
739 case BYT_DEBOUNCE_REG:
740 reg_offset = 0;
741 break;
742 default:
743 reg_offset = comm->pad_map[offset] * 16;
744 break;
745 }
746
747 return comm->reg_base + reg_offset + reg;
748 }
749
byt_get_groups_count(struct pinctrl_dev * pctldev)750 static int byt_get_groups_count(struct pinctrl_dev *pctldev)
751 {
752 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
753
754 return vg->soc_data->ngroups;
755 }
756
byt_get_group_name(struct pinctrl_dev * pctldev,unsigned int selector)757 static const char *byt_get_group_name(struct pinctrl_dev *pctldev,
758 unsigned int selector)
759 {
760 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
761
762 return vg->soc_data->groups[selector].name;
763 }
764
byt_get_group_pins(struct pinctrl_dev * pctldev,unsigned int selector,const unsigned int ** pins,unsigned int * num_pins)765 static int byt_get_group_pins(struct pinctrl_dev *pctldev,
766 unsigned int selector,
767 const unsigned int **pins,
768 unsigned int *num_pins)
769 {
770 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
771
772 *pins = vg->soc_data->groups[selector].pins;
773 *num_pins = vg->soc_data->groups[selector].npins;
774
775 return 0;
776 }
777
778 static const struct pinctrl_ops byt_pinctrl_ops = {
779 .get_groups_count = byt_get_groups_count,
780 .get_group_name = byt_get_group_name,
781 .get_group_pins = byt_get_group_pins,
782 };
783
byt_get_functions_count(struct pinctrl_dev * pctldev)784 static int byt_get_functions_count(struct pinctrl_dev *pctldev)
785 {
786 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
787
788 return vg->soc_data->nfunctions;
789 }
790
byt_get_function_name(struct pinctrl_dev * pctldev,unsigned int selector)791 static const char *byt_get_function_name(struct pinctrl_dev *pctldev,
792 unsigned int selector)
793 {
794 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
795
796 return vg->soc_data->functions[selector].name;
797 }
798
byt_get_function_groups(struct pinctrl_dev * pctldev,unsigned int selector,const char * const ** groups,unsigned int * num_groups)799 static int byt_get_function_groups(struct pinctrl_dev *pctldev,
800 unsigned int selector,
801 const char * const **groups,
802 unsigned int *num_groups)
803 {
804 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
805
806 *groups = vg->soc_data->functions[selector].groups;
807 *num_groups = vg->soc_data->functions[selector].ngroups;
808
809 return 0;
810 }
811
byt_get_group_simple_mux(const struct byt_pingroup group,const char * func_name,unsigned short * func)812 static int byt_get_group_simple_mux(const struct byt_pingroup group,
813 const char *func_name,
814 unsigned short *func)
815 {
816 int i;
817
818 for (i = 0; i < group.nfuncs; i++) {
819 if (!strcmp(group.simple_funcs[i].name, func_name)) {
820 *func = group.simple_funcs[i].func;
821 return 0;
822 }
823 }
824
825 return 1;
826 }
827
byt_get_group_mixed_mux(const struct byt_pingroup group,const char * func_name,const unsigned short ** func)828 static int byt_get_group_mixed_mux(const struct byt_pingroup group,
829 const char *func_name,
830 const unsigned short **func)
831 {
832 int i;
833
834 for (i = 0; i < group.nfuncs; i++) {
835 if (!strcmp(group.mixed_funcs[i].name, func_name)) {
836 *func = group.mixed_funcs[i].func_values;
837 return 0;
838 }
839 }
840
841 return 1;
842 }
843
byt_set_group_simple_mux(struct byt_gpio * vg,const struct byt_pingroup group,unsigned short func)844 static void byt_set_group_simple_mux(struct byt_gpio *vg,
845 const struct byt_pingroup group,
846 unsigned short func)
847 {
848 unsigned long flags;
849 int i;
850
851 raw_spin_lock_irqsave(&vg->lock, flags);
852
853 for (i = 0; i < group.npins; i++) {
854 void __iomem *padcfg0;
855 u32 value;
856
857 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
858 if (!padcfg0) {
859 dev_warn(&vg->pdev->dev,
860 "Group %s, pin %i not muxed (no padcfg0)\n",
861 group.name, i);
862 continue;
863 }
864
865 value = readl(padcfg0);
866 value &= ~BYT_PIN_MUX;
867 value |= func;
868 writel(value, padcfg0);
869 }
870
871 raw_spin_unlock_irqrestore(&vg->lock, flags);
872 }
873
byt_set_group_mixed_mux(struct byt_gpio * vg,const struct byt_pingroup group,const unsigned short * func)874 static void byt_set_group_mixed_mux(struct byt_gpio *vg,
875 const struct byt_pingroup group,
876 const unsigned short *func)
877 {
878 unsigned long flags;
879 int i;
880
881 raw_spin_lock_irqsave(&vg->lock, flags);
882
883 for (i = 0; i < group.npins; i++) {
884 void __iomem *padcfg0;
885 u32 value;
886
887 padcfg0 = byt_gpio_reg(vg, group.pins[i], BYT_CONF0_REG);
888 if (!padcfg0) {
889 dev_warn(&vg->pdev->dev,
890 "Group %s, pin %i not muxed (no padcfg0)\n",
891 group.name, i);
892 continue;
893 }
894
895 value = readl(padcfg0);
896 value &= ~BYT_PIN_MUX;
897 value |= func[i];
898 writel(value, padcfg0);
899 }
900
901 raw_spin_unlock_irqrestore(&vg->lock, flags);
902 }
903
byt_set_mux(struct pinctrl_dev * pctldev,unsigned int func_selector,unsigned int group_selector)904 static int byt_set_mux(struct pinctrl_dev *pctldev, unsigned int func_selector,
905 unsigned int group_selector)
906 {
907 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctldev);
908 const struct byt_function func = vg->soc_data->functions[func_selector];
909 const struct byt_pingroup group = vg->soc_data->groups[group_selector];
910 const unsigned short *mixed_func;
911 unsigned short simple_func;
912 int ret = 1;
913
914 if (group.has_simple_funcs)
915 ret = byt_get_group_simple_mux(group, func.name, &simple_func);
916 else
917 ret = byt_get_group_mixed_mux(group, func.name, &mixed_func);
918
919 if (ret)
920 byt_set_group_simple_mux(vg, group, BYT_DEFAULT_GPIO_MUX);
921 else if (group.has_simple_funcs)
922 byt_set_group_simple_mux(vg, group, simple_func);
923 else
924 byt_set_group_mixed_mux(vg, group, mixed_func);
925
926 return 0;
927 }
928
byt_get_gpio_mux(struct byt_gpio * vg,unsigned offset)929 static u32 byt_get_gpio_mux(struct byt_gpio *vg, unsigned offset)
930 {
931 /* SCORE pin 92-93 */
932 if (!strcmp(vg->soc_data->uid, BYT_SCORE_ACPI_UID) &&
933 offset >= 92 && offset <= 93)
934 return 1;
935
936 /* SUS pin 11-21 */
937 if (!strcmp(vg->soc_data->uid, BYT_SUS_ACPI_UID) &&
938 offset >= 11 && offset <= 21)
939 return 1;
940
941 return 0;
942 }
943
byt_gpio_clear_triggering(struct byt_gpio * vg,unsigned int offset)944 static void byt_gpio_clear_triggering(struct byt_gpio *vg, unsigned int offset)
945 {
946 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
947 unsigned long flags;
948 u32 value;
949
950 raw_spin_lock_irqsave(&vg->lock, flags);
951 value = readl(reg);
952 value &= ~(BYT_TRIG_POS | BYT_TRIG_NEG | BYT_TRIG_LVL);
953 writel(value, reg);
954 raw_spin_unlock_irqrestore(&vg->lock, flags);
955 }
956
byt_gpio_request_enable(struct pinctrl_dev * pctl_dev,struct pinctrl_gpio_range * range,unsigned int offset)957 static int byt_gpio_request_enable(struct pinctrl_dev *pctl_dev,
958 struct pinctrl_gpio_range *range,
959 unsigned int offset)
960 {
961 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
962 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
963 u32 value, gpio_mux;
964 unsigned long flags;
965
966 raw_spin_lock_irqsave(&vg->lock, flags);
967
968 /*
969 * In most cases, func pin mux 000 means GPIO function.
970 * But, some pins may have func pin mux 001 represents
971 * GPIO function.
972 *
973 * Because there are devices out there where some pins were not
974 * configured correctly we allow changing the mux value from
975 * request (but print out warning about that).
976 */
977 value = readl(reg) & BYT_PIN_MUX;
978 gpio_mux = byt_get_gpio_mux(vg, offset);
979 if (gpio_mux != value) {
980 value = readl(reg) & ~BYT_PIN_MUX;
981 value |= gpio_mux;
982 writel(value, reg);
983
984 dev_warn(&vg->pdev->dev, FW_BUG
985 "pin %u forcibly re-configured as GPIO\n", offset);
986 }
987
988 raw_spin_unlock_irqrestore(&vg->lock, flags);
989
990 pm_runtime_get(&vg->pdev->dev);
991
992 return 0;
993 }
994
byt_gpio_disable_free(struct pinctrl_dev * pctl_dev,struct pinctrl_gpio_range * range,unsigned int offset)995 static void byt_gpio_disable_free(struct pinctrl_dev *pctl_dev,
996 struct pinctrl_gpio_range *range,
997 unsigned int offset)
998 {
999 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1000
1001 byt_gpio_clear_triggering(vg, offset);
1002 pm_runtime_put(&vg->pdev->dev);
1003 }
1004
byt_gpio_set_direction(struct pinctrl_dev * pctl_dev,struct pinctrl_gpio_range * range,unsigned int offset,bool input)1005 static int byt_gpio_set_direction(struct pinctrl_dev *pctl_dev,
1006 struct pinctrl_gpio_range *range,
1007 unsigned int offset,
1008 bool input)
1009 {
1010 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1011 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1012 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1013 unsigned long flags;
1014 u32 value;
1015
1016 raw_spin_lock_irqsave(&vg->lock, flags);
1017
1018 value = readl(val_reg);
1019 value &= ~BYT_DIR_MASK;
1020 if (input)
1021 value |= BYT_OUTPUT_EN;
1022 else
1023 /*
1024 * Before making any direction modifications, do a check if gpio
1025 * is set for direct IRQ. On baytrail, setting GPIO to output
1026 * does not make sense, so let's at least warn the caller before
1027 * they shoot themselves in the foot.
1028 */
1029 WARN(readl(conf_reg) & BYT_DIRECT_IRQ_EN,
1030 "Potential Error: Setting GPIO with direct_irq_en to output");
1031 writel(value, val_reg);
1032
1033 raw_spin_unlock_irqrestore(&vg->lock, flags);
1034
1035 return 0;
1036 }
1037
1038 static const struct pinmux_ops byt_pinmux_ops = {
1039 .get_functions_count = byt_get_functions_count,
1040 .get_function_name = byt_get_function_name,
1041 .get_function_groups = byt_get_function_groups,
1042 .set_mux = byt_set_mux,
1043 .gpio_request_enable = byt_gpio_request_enable,
1044 .gpio_disable_free = byt_gpio_disable_free,
1045 .gpio_set_direction = byt_gpio_set_direction,
1046 };
1047
byt_get_pull_strength(u32 reg,u16 * strength)1048 static void byt_get_pull_strength(u32 reg, u16 *strength)
1049 {
1050 switch (reg & BYT_PULL_STR_MASK) {
1051 case BYT_PULL_STR_2K:
1052 *strength = 2000;
1053 break;
1054 case BYT_PULL_STR_10K:
1055 *strength = 10000;
1056 break;
1057 case BYT_PULL_STR_20K:
1058 *strength = 20000;
1059 break;
1060 case BYT_PULL_STR_40K:
1061 *strength = 40000;
1062 break;
1063 }
1064 }
1065
byt_set_pull_strength(u32 * reg,u16 strength)1066 static int byt_set_pull_strength(u32 *reg, u16 strength)
1067 {
1068 *reg &= ~BYT_PULL_STR_MASK;
1069
1070 switch (strength) {
1071 case 2000:
1072 *reg |= BYT_PULL_STR_2K;
1073 break;
1074 case 10000:
1075 *reg |= BYT_PULL_STR_10K;
1076 break;
1077 case 20000:
1078 *reg |= BYT_PULL_STR_20K;
1079 break;
1080 case 40000:
1081 *reg |= BYT_PULL_STR_40K;
1082 break;
1083 default:
1084 return -EINVAL;
1085 }
1086
1087 return 0;
1088 }
1089
byt_pin_config_get(struct pinctrl_dev * pctl_dev,unsigned int offset,unsigned long * config)1090 static int byt_pin_config_get(struct pinctrl_dev *pctl_dev, unsigned int offset,
1091 unsigned long *config)
1092 {
1093 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1094 enum pin_config_param param = pinconf_to_config_param(*config);
1095 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1096 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1097 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
1098 unsigned long flags;
1099 u32 conf, pull, val, debounce;
1100 u16 arg = 0;
1101
1102 raw_spin_lock_irqsave(&vg->lock, flags);
1103 conf = readl(conf_reg);
1104 pull = conf & BYT_PULL_ASSIGN_MASK;
1105 val = readl(val_reg);
1106 raw_spin_unlock_irqrestore(&vg->lock, flags);
1107
1108 switch (param) {
1109 case PIN_CONFIG_BIAS_DISABLE:
1110 if (pull)
1111 return -EINVAL;
1112 break;
1113 case PIN_CONFIG_BIAS_PULL_DOWN:
1114 /* Pull assignment is only applicable in input mode */
1115 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_DOWN)
1116 return -EINVAL;
1117
1118 byt_get_pull_strength(conf, &arg);
1119
1120 break;
1121 case PIN_CONFIG_BIAS_PULL_UP:
1122 /* Pull assignment is only applicable in input mode */
1123 if ((val & BYT_INPUT_EN) || pull != BYT_PULL_ASSIGN_UP)
1124 return -EINVAL;
1125
1126 byt_get_pull_strength(conf, &arg);
1127
1128 break;
1129 case PIN_CONFIG_INPUT_DEBOUNCE:
1130 if (!(conf & BYT_DEBOUNCE_EN))
1131 return -EINVAL;
1132
1133 raw_spin_lock_irqsave(&vg->lock, flags);
1134 debounce = readl(db_reg);
1135 raw_spin_unlock_irqrestore(&vg->lock, flags);
1136
1137 switch (debounce & BYT_DEBOUNCE_PULSE_MASK) {
1138 case BYT_DEBOUNCE_PULSE_375US:
1139 arg = 375;
1140 break;
1141 case BYT_DEBOUNCE_PULSE_750US:
1142 arg = 750;
1143 break;
1144 case BYT_DEBOUNCE_PULSE_1500US:
1145 arg = 1500;
1146 break;
1147 case BYT_DEBOUNCE_PULSE_3MS:
1148 arg = 3000;
1149 break;
1150 case BYT_DEBOUNCE_PULSE_6MS:
1151 arg = 6000;
1152 break;
1153 case BYT_DEBOUNCE_PULSE_12MS:
1154 arg = 12000;
1155 break;
1156 case BYT_DEBOUNCE_PULSE_24MS:
1157 arg = 24000;
1158 break;
1159 default:
1160 return -EINVAL;
1161 }
1162
1163 break;
1164 default:
1165 return -ENOTSUPP;
1166 }
1167
1168 *config = pinconf_to_config_packed(param, arg);
1169
1170 return 0;
1171 }
1172
byt_pin_config_set(struct pinctrl_dev * pctl_dev,unsigned int offset,unsigned long * configs,unsigned int num_configs)1173 static int byt_pin_config_set(struct pinctrl_dev *pctl_dev,
1174 unsigned int offset,
1175 unsigned long *configs,
1176 unsigned int num_configs)
1177 {
1178 struct byt_gpio *vg = pinctrl_dev_get_drvdata(pctl_dev);
1179 unsigned int param, arg;
1180 void __iomem *conf_reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1181 void __iomem *val_reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1182 void __iomem *db_reg = byt_gpio_reg(vg, offset, BYT_DEBOUNCE_REG);
1183 unsigned long flags;
1184 u32 conf, val, debounce;
1185 int i, ret = 0;
1186
1187 raw_spin_lock_irqsave(&vg->lock, flags);
1188
1189 conf = readl(conf_reg);
1190 val = readl(val_reg);
1191
1192 for (i = 0; i < num_configs; i++) {
1193 param = pinconf_to_config_param(configs[i]);
1194 arg = pinconf_to_config_argument(configs[i]);
1195
1196 switch (param) {
1197 case PIN_CONFIG_BIAS_DISABLE:
1198 conf &= ~BYT_PULL_ASSIGN_MASK;
1199 break;
1200 case PIN_CONFIG_BIAS_PULL_DOWN:
1201 /* Set default strength value in case none is given */
1202 if (arg == 1)
1203 arg = 2000;
1204
1205 /*
1206 * Pull assignment is only applicable in input mode. If
1207 * chip is not in input mode, set it and warn about it.
1208 */
1209 if (val & BYT_INPUT_EN) {
1210 val &= ~BYT_INPUT_EN;
1211 writel(val, val_reg);
1212 dev_warn(&vg->pdev->dev,
1213 "pin %u forcibly set to input mode\n",
1214 offset);
1215 }
1216
1217 conf &= ~BYT_PULL_ASSIGN_MASK;
1218 conf |= BYT_PULL_ASSIGN_DOWN;
1219 ret = byt_set_pull_strength(&conf, arg);
1220
1221 break;
1222 case PIN_CONFIG_BIAS_PULL_UP:
1223 /* Set default strength value in case none is given */
1224 if (arg == 1)
1225 arg = 2000;
1226
1227 /*
1228 * Pull assignment is only applicable in input mode. If
1229 * chip is not in input mode, set it and warn about it.
1230 */
1231 if (val & BYT_INPUT_EN) {
1232 val &= ~BYT_INPUT_EN;
1233 writel(val, val_reg);
1234 dev_warn(&vg->pdev->dev,
1235 "pin %u forcibly set to input mode\n",
1236 offset);
1237 }
1238
1239 conf &= ~BYT_PULL_ASSIGN_MASK;
1240 conf |= BYT_PULL_ASSIGN_UP;
1241 ret = byt_set_pull_strength(&conf, arg);
1242
1243 break;
1244 case PIN_CONFIG_INPUT_DEBOUNCE:
1245 debounce = readl(db_reg);
1246 debounce &= ~BYT_DEBOUNCE_PULSE_MASK;
1247
1248 if (arg)
1249 conf |= BYT_DEBOUNCE_EN;
1250 else
1251 conf &= ~BYT_DEBOUNCE_EN;
1252
1253 switch (arg) {
1254 case 375:
1255 debounce |= BYT_DEBOUNCE_PULSE_375US;
1256 break;
1257 case 750:
1258 debounce |= BYT_DEBOUNCE_PULSE_750US;
1259 break;
1260 case 1500:
1261 debounce |= BYT_DEBOUNCE_PULSE_1500US;
1262 break;
1263 case 3000:
1264 debounce |= BYT_DEBOUNCE_PULSE_3MS;
1265 break;
1266 case 6000:
1267 debounce |= BYT_DEBOUNCE_PULSE_6MS;
1268 break;
1269 case 12000:
1270 debounce |= BYT_DEBOUNCE_PULSE_12MS;
1271 break;
1272 case 24000:
1273 debounce |= BYT_DEBOUNCE_PULSE_24MS;
1274 break;
1275 default:
1276 if (arg)
1277 ret = -EINVAL;
1278 break;
1279 }
1280
1281 if (!ret)
1282 writel(debounce, db_reg);
1283 break;
1284 default:
1285 ret = -ENOTSUPP;
1286 }
1287
1288 if (ret)
1289 break;
1290 }
1291
1292 if (!ret)
1293 writel(conf, conf_reg);
1294
1295 raw_spin_unlock_irqrestore(&vg->lock, flags);
1296
1297 return ret;
1298 }
1299
1300 static const struct pinconf_ops byt_pinconf_ops = {
1301 .is_generic = true,
1302 .pin_config_get = byt_pin_config_get,
1303 .pin_config_set = byt_pin_config_set,
1304 };
1305
1306 static const struct pinctrl_desc byt_pinctrl_desc = {
1307 .pctlops = &byt_pinctrl_ops,
1308 .pmxops = &byt_pinmux_ops,
1309 .confops = &byt_pinconf_ops,
1310 .owner = THIS_MODULE,
1311 };
1312
byt_gpio_get(struct gpio_chip * chip,unsigned offset)1313 static int byt_gpio_get(struct gpio_chip *chip, unsigned offset)
1314 {
1315 struct byt_gpio *vg = gpiochip_get_data(chip);
1316 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1317 unsigned long flags;
1318 u32 val;
1319
1320 raw_spin_lock_irqsave(&vg->lock, flags);
1321 val = readl(reg);
1322 raw_spin_unlock_irqrestore(&vg->lock, flags);
1323
1324 return !!(val & BYT_LEVEL);
1325 }
1326
byt_gpio_set(struct gpio_chip * chip,unsigned offset,int value)1327 static void byt_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
1328 {
1329 struct byt_gpio *vg = gpiochip_get_data(chip);
1330 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1331 unsigned long flags;
1332 u32 old_val;
1333
1334 if (!reg)
1335 return;
1336
1337 raw_spin_lock_irqsave(&vg->lock, flags);
1338 old_val = readl(reg);
1339 if (value)
1340 writel(old_val | BYT_LEVEL, reg);
1341 else
1342 writel(old_val & ~BYT_LEVEL, reg);
1343 raw_spin_unlock_irqrestore(&vg->lock, flags);
1344 }
1345
byt_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)1346 static int byt_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
1347 {
1348 struct byt_gpio *vg = gpiochip_get_data(chip);
1349 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_VAL_REG);
1350 unsigned long flags;
1351 u32 value;
1352
1353 if (!reg)
1354 return -EINVAL;
1355
1356 raw_spin_lock_irqsave(&vg->lock, flags);
1357 value = readl(reg);
1358 raw_spin_unlock_irqrestore(&vg->lock, flags);
1359
1360 if (!(value & BYT_OUTPUT_EN))
1361 return GPIOF_DIR_OUT;
1362 if (!(value & BYT_INPUT_EN))
1363 return GPIOF_DIR_IN;
1364
1365 return -EINVAL;
1366 }
1367
byt_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)1368 static int byt_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
1369 {
1370 return pinctrl_gpio_direction_input(chip->base + offset);
1371 }
1372
byt_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)1373 static int byt_gpio_direction_output(struct gpio_chip *chip,
1374 unsigned int offset, int value)
1375 {
1376 int ret = pinctrl_gpio_direction_output(chip->base + offset);
1377
1378 if (ret)
1379 return ret;
1380
1381 byt_gpio_set(chip, offset, value);
1382
1383 return 0;
1384 }
1385
byt_gpio_dbg_show(struct seq_file * s,struct gpio_chip * chip)1386 static void byt_gpio_dbg_show(struct seq_file *s, struct gpio_chip *chip)
1387 {
1388 struct byt_gpio *vg = gpiochip_get_data(chip);
1389 int i;
1390 u32 conf0, val;
1391
1392 for (i = 0; i < vg->soc_data->npins; i++) {
1393 const struct byt_community *comm;
1394 const char *pull_str = NULL;
1395 const char *pull = NULL;
1396 void __iomem *reg;
1397 unsigned long flags;
1398 const char *label;
1399 unsigned int pin;
1400
1401 raw_spin_lock_irqsave(&vg->lock, flags);
1402 pin = vg->soc_data->pins[i].number;
1403 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1404 if (!reg) {
1405 seq_printf(s,
1406 "Could not retrieve pin %i conf0 reg\n",
1407 pin);
1408 raw_spin_unlock_irqrestore(&vg->lock, flags);
1409 continue;
1410 }
1411 conf0 = readl(reg);
1412
1413 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1414 if (!reg) {
1415 seq_printf(s,
1416 "Could not retrieve pin %i val reg\n", pin);
1417 raw_spin_unlock_irqrestore(&vg->lock, flags);
1418 continue;
1419 }
1420 val = readl(reg);
1421 raw_spin_unlock_irqrestore(&vg->lock, flags);
1422
1423 comm = byt_get_community(vg, pin);
1424 if (!comm) {
1425 seq_printf(s,
1426 "Could not get community for pin %i\n", pin);
1427 continue;
1428 }
1429 label = gpiochip_is_requested(chip, i);
1430 if (!label)
1431 label = "Unrequested";
1432
1433 switch (conf0 & BYT_PULL_ASSIGN_MASK) {
1434 case BYT_PULL_ASSIGN_UP:
1435 pull = "up";
1436 break;
1437 case BYT_PULL_ASSIGN_DOWN:
1438 pull = "down";
1439 break;
1440 }
1441
1442 switch (conf0 & BYT_PULL_STR_MASK) {
1443 case BYT_PULL_STR_2K:
1444 pull_str = "2k";
1445 break;
1446 case BYT_PULL_STR_10K:
1447 pull_str = "10k";
1448 break;
1449 case BYT_PULL_STR_20K:
1450 pull_str = "20k";
1451 break;
1452 case BYT_PULL_STR_40K:
1453 pull_str = "40k";
1454 break;
1455 }
1456
1457 seq_printf(s,
1458 " gpio-%-3d (%-20.20s) %s %s %s pad-%-3d offset:0x%03x mux:%d %s%s%s",
1459 pin,
1460 label,
1461 val & BYT_INPUT_EN ? " " : "in",
1462 val & BYT_OUTPUT_EN ? " " : "out",
1463 val & BYT_LEVEL ? "hi" : "lo",
1464 comm->pad_map[i], comm->pad_map[i] * 16,
1465 conf0 & 0x7,
1466 conf0 & BYT_TRIG_NEG ? " fall" : " ",
1467 conf0 & BYT_TRIG_POS ? " rise" : " ",
1468 conf0 & BYT_TRIG_LVL ? " level" : " ");
1469
1470 if (pull && pull_str)
1471 seq_printf(s, " %-4s %-3s", pull, pull_str);
1472 else
1473 seq_puts(s, " ");
1474
1475 if (conf0 & BYT_IODEN)
1476 seq_puts(s, " open-drain");
1477
1478 seq_puts(s, "\n");
1479 }
1480 }
1481
1482 static const struct gpio_chip byt_gpio_chip = {
1483 .owner = THIS_MODULE,
1484 .request = gpiochip_generic_request,
1485 .free = gpiochip_generic_free,
1486 .get_direction = byt_gpio_get_direction,
1487 .direction_input = byt_gpio_direction_input,
1488 .direction_output = byt_gpio_direction_output,
1489 .get = byt_gpio_get,
1490 .set = byt_gpio_set,
1491 .dbg_show = byt_gpio_dbg_show,
1492 };
1493
byt_irq_ack(struct irq_data * d)1494 static void byt_irq_ack(struct irq_data *d)
1495 {
1496 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1497 struct byt_gpio *vg = gpiochip_get_data(gc);
1498 unsigned offset = irqd_to_hwirq(d);
1499 void __iomem *reg;
1500
1501 reg = byt_gpio_reg(vg, offset, BYT_INT_STAT_REG);
1502 if (!reg)
1503 return;
1504
1505 raw_spin_lock(&vg->lock);
1506 writel(BIT(offset % 32), reg);
1507 raw_spin_unlock(&vg->lock);
1508 }
1509
byt_irq_mask(struct irq_data * d)1510 static void byt_irq_mask(struct irq_data *d)
1511 {
1512 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1513 struct byt_gpio *vg = gpiochip_get_data(gc);
1514
1515 byt_gpio_clear_triggering(vg, irqd_to_hwirq(d));
1516 }
1517
byt_irq_unmask(struct irq_data * d)1518 static void byt_irq_unmask(struct irq_data *d)
1519 {
1520 struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
1521 struct byt_gpio *vg = gpiochip_get_data(gc);
1522 unsigned offset = irqd_to_hwirq(d);
1523 unsigned long flags;
1524 void __iomem *reg;
1525 u32 value;
1526
1527 reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1528 if (!reg)
1529 return;
1530
1531 raw_spin_lock_irqsave(&vg->lock, flags);
1532 value = readl(reg);
1533
1534 switch (irqd_get_trigger_type(d)) {
1535 case IRQ_TYPE_LEVEL_HIGH:
1536 value |= BYT_TRIG_LVL;
1537 /* fall through */
1538 case IRQ_TYPE_EDGE_RISING:
1539 value |= BYT_TRIG_POS;
1540 break;
1541 case IRQ_TYPE_LEVEL_LOW:
1542 value |= BYT_TRIG_LVL;
1543 /* fall through */
1544 case IRQ_TYPE_EDGE_FALLING:
1545 value |= BYT_TRIG_NEG;
1546 break;
1547 case IRQ_TYPE_EDGE_BOTH:
1548 value |= (BYT_TRIG_NEG | BYT_TRIG_POS);
1549 break;
1550 }
1551
1552 writel(value, reg);
1553
1554 raw_spin_unlock_irqrestore(&vg->lock, flags);
1555 }
1556
byt_irq_type(struct irq_data * d,unsigned int type)1557 static int byt_irq_type(struct irq_data *d, unsigned int type)
1558 {
1559 struct byt_gpio *vg = gpiochip_get_data(irq_data_get_irq_chip_data(d));
1560 u32 offset = irqd_to_hwirq(d);
1561 u32 value;
1562 unsigned long flags;
1563 void __iomem *reg = byt_gpio_reg(vg, offset, BYT_CONF0_REG);
1564
1565 if (!reg || offset >= vg->chip.ngpio)
1566 return -EINVAL;
1567
1568 raw_spin_lock_irqsave(&vg->lock, flags);
1569 value = readl(reg);
1570
1571 WARN(value & BYT_DIRECT_IRQ_EN,
1572 "Bad pad config for io mode, force direct_irq_en bit clearing");
1573
1574 /* For level trigges the BYT_TRIG_POS and BYT_TRIG_NEG bits
1575 * are used to indicate high and low level triggering
1576 */
1577 value &= ~(BYT_DIRECT_IRQ_EN | BYT_TRIG_POS | BYT_TRIG_NEG |
1578 BYT_TRIG_LVL);
1579 /* Enable glitch filtering */
1580 value |= BYT_GLITCH_FILTER_EN | BYT_GLITCH_F_SLOW_CLK |
1581 BYT_GLITCH_F_FAST_CLK;
1582
1583 writel(value, reg);
1584
1585 if (type & IRQ_TYPE_EDGE_BOTH)
1586 irq_set_handler_locked(d, handle_edge_irq);
1587 else if (type & IRQ_TYPE_LEVEL_MASK)
1588 irq_set_handler_locked(d, handle_level_irq);
1589
1590 raw_spin_unlock_irqrestore(&vg->lock, flags);
1591
1592 return 0;
1593 }
1594
1595 static struct irq_chip byt_irqchip = {
1596 .name = "BYT-GPIO",
1597 .irq_ack = byt_irq_ack,
1598 .irq_mask = byt_irq_mask,
1599 .irq_unmask = byt_irq_unmask,
1600 .irq_set_type = byt_irq_type,
1601 .flags = IRQCHIP_SKIP_SET_WAKE,
1602 };
1603
byt_gpio_irq_handler(struct irq_desc * desc)1604 static void byt_gpio_irq_handler(struct irq_desc *desc)
1605 {
1606 struct irq_data *data = irq_desc_get_irq_data(desc);
1607 struct byt_gpio *vg = gpiochip_get_data(
1608 irq_desc_get_handler_data(desc));
1609 struct irq_chip *chip = irq_data_get_irq_chip(data);
1610 u32 base, pin;
1611 void __iomem *reg;
1612 unsigned long pending;
1613 unsigned int virq;
1614
1615 /* check from GPIO controller which pin triggered the interrupt */
1616 for (base = 0; base < vg->chip.ngpio; base += 32) {
1617 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1618
1619 if (!reg) {
1620 dev_warn(&vg->pdev->dev,
1621 "Pin %i: could not retrieve interrupt status register\n",
1622 base);
1623 continue;
1624 }
1625
1626 raw_spin_lock(&vg->lock);
1627 pending = readl(reg);
1628 raw_spin_unlock(&vg->lock);
1629 for_each_set_bit(pin, &pending, 32) {
1630 virq = irq_find_mapping(vg->chip.irq.domain, base + pin);
1631 generic_handle_irq(virq);
1632 }
1633 }
1634 chip->irq_eoi(data);
1635 }
1636
byt_gpio_irq_init_hw(struct byt_gpio * vg)1637 static void byt_gpio_irq_init_hw(struct byt_gpio *vg)
1638 {
1639 struct gpio_chip *gc = &vg->chip;
1640 struct device *dev = &vg->pdev->dev;
1641 void __iomem *reg;
1642 u32 base, value;
1643 int i;
1644
1645 /*
1646 * Clear interrupt triggers for all pins that are GPIOs and
1647 * do not use direct IRQ mode. This will prevent spurious
1648 * interrupts from misconfigured pins.
1649 */
1650 for (i = 0; i < vg->soc_data->npins; i++) {
1651 unsigned int pin = vg->soc_data->pins[i].number;
1652
1653 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1654 if (!reg) {
1655 dev_warn(&vg->pdev->dev,
1656 "Pin %i: could not retrieve conf0 register\n",
1657 i);
1658 continue;
1659 }
1660
1661 value = readl(reg);
1662 if (value & BYT_DIRECT_IRQ_EN) {
1663 clear_bit(i, gc->irq.valid_mask);
1664 dev_dbg(dev, "excluding GPIO %d from IRQ domain\n", i);
1665 } else if ((value & BYT_PIN_MUX) == byt_get_gpio_mux(vg, i)) {
1666 byt_gpio_clear_triggering(vg, i);
1667 dev_dbg(dev, "disabling GPIO %d\n", i);
1668 }
1669 }
1670
1671 /* clear interrupt status trigger registers */
1672 for (base = 0; base < vg->soc_data->npins; base += 32) {
1673 reg = byt_gpio_reg(vg, base, BYT_INT_STAT_REG);
1674
1675 if (!reg) {
1676 dev_warn(&vg->pdev->dev,
1677 "Pin %i: could not retrieve irq status reg\n",
1678 base);
1679 continue;
1680 }
1681
1682 writel(0xffffffff, reg);
1683 /* make sure trigger bits are cleared, if not then a pin
1684 might be misconfigured in bios */
1685 value = readl(reg);
1686 if (value)
1687 dev_err(&vg->pdev->dev,
1688 "GPIO interrupt error, pins misconfigured. INT_STAT%u: 0x%08x\n",
1689 base / 32, value);
1690 }
1691 }
1692
byt_gpio_probe(struct byt_gpio * vg)1693 static int byt_gpio_probe(struct byt_gpio *vg)
1694 {
1695 struct gpio_chip *gc;
1696 struct resource *irq_rc;
1697 int ret;
1698
1699 /* Set up gpio chip */
1700 vg->chip = byt_gpio_chip;
1701 gc = &vg->chip;
1702 gc->label = dev_name(&vg->pdev->dev);
1703 gc->base = -1;
1704 gc->can_sleep = false;
1705 gc->parent = &vg->pdev->dev;
1706 gc->ngpio = vg->soc_data->npins;
1707 gc->irq.need_valid_mask = true;
1708
1709 #ifdef CONFIG_PM_SLEEP
1710 vg->saved_context = devm_kcalloc(&vg->pdev->dev, gc->ngpio,
1711 sizeof(*vg->saved_context), GFP_KERNEL);
1712 #endif
1713 ret = devm_gpiochip_add_data(&vg->pdev->dev, gc, vg);
1714 if (ret) {
1715 dev_err(&vg->pdev->dev, "failed adding byt-gpio chip\n");
1716 return ret;
1717 }
1718
1719 ret = gpiochip_add_pin_range(&vg->chip, dev_name(&vg->pdev->dev),
1720 0, 0, vg->soc_data->npins);
1721 if (ret) {
1722 dev_err(&vg->pdev->dev, "failed to add GPIO pin range\n");
1723 return ret;
1724 }
1725
1726 /* set up interrupts */
1727 irq_rc = platform_get_resource(vg->pdev, IORESOURCE_IRQ, 0);
1728 if (irq_rc && irq_rc->start) {
1729 byt_gpio_irq_init_hw(vg);
1730 ret = gpiochip_irqchip_add(gc, &byt_irqchip, 0,
1731 handle_bad_irq, IRQ_TYPE_NONE);
1732 if (ret) {
1733 dev_err(&vg->pdev->dev, "failed to add irqchip\n");
1734 return ret;
1735 }
1736
1737 gpiochip_set_chained_irqchip(gc, &byt_irqchip,
1738 (unsigned)irq_rc->start,
1739 byt_gpio_irq_handler);
1740 }
1741
1742 return ret;
1743 }
1744
byt_set_soc_data(struct byt_gpio * vg,const struct byt_pinctrl_soc_data * soc_data)1745 static int byt_set_soc_data(struct byt_gpio *vg,
1746 const struct byt_pinctrl_soc_data *soc_data)
1747 {
1748 int i;
1749
1750 vg->soc_data = soc_data;
1751 vg->communities_copy = devm_kcalloc(&vg->pdev->dev,
1752 soc_data->ncommunities,
1753 sizeof(*vg->communities_copy),
1754 GFP_KERNEL);
1755 if (!vg->communities_copy)
1756 return -ENOMEM;
1757
1758 for (i = 0; i < soc_data->ncommunities; i++) {
1759 struct byt_community *comm = vg->communities_copy + i;
1760 struct resource *mem_rc;
1761
1762 *comm = vg->soc_data->communities[i];
1763
1764 mem_rc = platform_get_resource(vg->pdev, IORESOURCE_MEM, 0);
1765 comm->reg_base = devm_ioremap_resource(&vg->pdev->dev, mem_rc);
1766 if (IS_ERR(comm->reg_base))
1767 return PTR_ERR(comm->reg_base);
1768 }
1769
1770 return 0;
1771 }
1772
1773 static const struct acpi_device_id byt_gpio_acpi_match[] = {
1774 { "INT33B2", (kernel_ulong_t)byt_soc_data },
1775 { "INT33FC", (kernel_ulong_t)byt_soc_data },
1776 { }
1777 };
1778 MODULE_DEVICE_TABLE(acpi, byt_gpio_acpi_match);
1779
byt_pinctrl_probe(struct platform_device * pdev)1780 static int byt_pinctrl_probe(struct platform_device *pdev)
1781 {
1782 const struct byt_pinctrl_soc_data *soc_data = NULL;
1783 const struct byt_pinctrl_soc_data **soc_table;
1784 const struct acpi_device_id *acpi_id;
1785 struct acpi_device *acpi_dev;
1786 struct byt_gpio *vg;
1787 int i, ret;
1788
1789 acpi_dev = ACPI_COMPANION(&pdev->dev);
1790 if (!acpi_dev)
1791 return -ENODEV;
1792
1793 acpi_id = acpi_match_device(byt_gpio_acpi_match, &pdev->dev);
1794 if (!acpi_id)
1795 return -ENODEV;
1796
1797 soc_table = (const struct byt_pinctrl_soc_data **)acpi_id->driver_data;
1798
1799 for (i = 0; soc_table[i]; i++) {
1800 if (!strcmp(acpi_dev->pnp.unique_id, soc_table[i]->uid)) {
1801 soc_data = soc_table[i];
1802 break;
1803 }
1804 }
1805
1806 if (!soc_data)
1807 return -ENODEV;
1808
1809 vg = devm_kzalloc(&pdev->dev, sizeof(*vg), GFP_KERNEL);
1810 if (!vg)
1811 return -ENOMEM;
1812
1813 vg->pdev = pdev;
1814 ret = byt_set_soc_data(vg, soc_data);
1815 if (ret) {
1816 dev_err(&pdev->dev, "failed to set soc data\n");
1817 return ret;
1818 }
1819
1820 vg->pctl_desc = byt_pinctrl_desc;
1821 vg->pctl_desc.name = dev_name(&pdev->dev);
1822 vg->pctl_desc.pins = vg->soc_data->pins;
1823 vg->pctl_desc.npins = vg->soc_data->npins;
1824
1825 vg->pctl_dev = devm_pinctrl_register(&pdev->dev, &vg->pctl_desc, vg);
1826 if (IS_ERR(vg->pctl_dev)) {
1827 dev_err(&pdev->dev, "failed to register pinctrl driver\n");
1828 return PTR_ERR(vg->pctl_dev);
1829 }
1830
1831 raw_spin_lock_init(&vg->lock);
1832
1833 ret = byt_gpio_probe(vg);
1834 if (ret)
1835 return ret;
1836
1837 platform_set_drvdata(pdev, vg);
1838 pm_runtime_enable(&pdev->dev);
1839
1840 return 0;
1841 }
1842
1843 #ifdef CONFIG_PM_SLEEP
byt_gpio_suspend(struct device * dev)1844 static int byt_gpio_suspend(struct device *dev)
1845 {
1846 struct platform_device *pdev = to_platform_device(dev);
1847 struct byt_gpio *vg = platform_get_drvdata(pdev);
1848 int i;
1849
1850 for (i = 0; i < vg->soc_data->npins; i++) {
1851 void __iomem *reg;
1852 u32 value;
1853 unsigned int pin = vg->soc_data->pins[i].number;
1854
1855 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1856 if (!reg) {
1857 dev_warn(&vg->pdev->dev,
1858 "Pin %i: could not retrieve conf0 register\n",
1859 i);
1860 continue;
1861 }
1862 value = readl(reg) & BYT_CONF0_RESTORE_MASK;
1863 vg->saved_context[i].conf0 = value;
1864
1865 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1866 value = readl(reg) & BYT_VAL_RESTORE_MASK;
1867 vg->saved_context[i].val = value;
1868 }
1869
1870 return 0;
1871 }
1872
byt_gpio_resume(struct device * dev)1873 static int byt_gpio_resume(struct device *dev)
1874 {
1875 struct platform_device *pdev = to_platform_device(dev);
1876 struct byt_gpio *vg = platform_get_drvdata(pdev);
1877 int i;
1878
1879 for (i = 0; i < vg->soc_data->npins; i++) {
1880 void __iomem *reg;
1881 u32 value;
1882 unsigned int pin = vg->soc_data->pins[i].number;
1883
1884 reg = byt_gpio_reg(vg, pin, BYT_CONF0_REG);
1885 if (!reg) {
1886 dev_warn(&vg->pdev->dev,
1887 "Pin %i: could not retrieve conf0 register\n",
1888 i);
1889 continue;
1890 }
1891 value = readl(reg);
1892 if ((value & BYT_CONF0_RESTORE_MASK) !=
1893 vg->saved_context[i].conf0) {
1894 value &= ~BYT_CONF0_RESTORE_MASK;
1895 value |= vg->saved_context[i].conf0;
1896 writel(value, reg);
1897 dev_info(dev, "restored pin %d conf0 %#08x", i, value);
1898 }
1899
1900 reg = byt_gpio_reg(vg, pin, BYT_VAL_REG);
1901 value = readl(reg);
1902 if ((value & BYT_VAL_RESTORE_MASK) !=
1903 vg->saved_context[i].val) {
1904 u32 v;
1905
1906 v = value & ~BYT_VAL_RESTORE_MASK;
1907 v |= vg->saved_context[i].val;
1908 if (v != value) {
1909 writel(v, reg);
1910 dev_dbg(dev, "restored pin %d val %#08x\n",
1911 i, v);
1912 }
1913 }
1914 }
1915
1916 return 0;
1917 }
1918 #endif
1919
1920 #ifdef CONFIG_PM
byt_gpio_runtime_suspend(struct device * dev)1921 static int byt_gpio_runtime_suspend(struct device *dev)
1922 {
1923 return 0;
1924 }
1925
byt_gpio_runtime_resume(struct device * dev)1926 static int byt_gpio_runtime_resume(struct device *dev)
1927 {
1928 return 0;
1929 }
1930 #endif
1931
1932 static const struct dev_pm_ops byt_gpio_pm_ops = {
1933 SET_LATE_SYSTEM_SLEEP_PM_OPS(byt_gpio_suspend, byt_gpio_resume)
1934 SET_RUNTIME_PM_OPS(byt_gpio_runtime_suspend, byt_gpio_runtime_resume,
1935 NULL)
1936 };
1937
1938 static struct platform_driver byt_gpio_driver = {
1939 .probe = byt_pinctrl_probe,
1940 .driver = {
1941 .name = "byt_gpio",
1942 .pm = &byt_gpio_pm_ops,
1943 .suppress_bind_attrs = true,
1944
1945 .acpi_match_table = ACPI_PTR(byt_gpio_acpi_match),
1946 },
1947 };
1948
byt_gpio_init(void)1949 static int __init byt_gpio_init(void)
1950 {
1951 return platform_driver_register(&byt_gpio_driver);
1952 }
1953 subsys_initcall(byt_gpio_init);
1954
