1 /*
2 * Driver for Broadcom BCM2835 GPIO unit (pinctrl + GPIO)
3 *
4 * Copyright (C) 2012 Chris Boot, Simon Arlott, Stephen Warren
5 *
6 * This driver is inspired by:
7 * pinctrl-nomadik.c, please see original file for copyright information
8 * pinctrl-tegra.c, please see original file for copyright information
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 */
20
21 #include <linux/bitmap.h>
22 #include <linux/bug.h>
23 #include <linux/delay.h>
24 #include <linux/device.h>
25 #include <linux/err.h>
26 #include <linux/gpio/driver.h>
27 #include <linux/io.h>
28 #include <linux/irq.h>
29 #include <linux/irqdesc.h>
30 #include <linux/init.h>
31 #include <linux/of_address.h>
32 #include <linux/of.h>
33 #include <linux/of_irq.h>
34 #include <linux/pinctrl/consumer.h>
35 #include <linux/pinctrl/machine.h>
36 #include <linux/pinctrl/pinconf.h>
37 #include <linux/pinctrl/pinctrl.h>
38 #include <linux/pinctrl/pinmux.h>
39 #include <linux/pinctrl/pinconf-generic.h>
40 #include <linux/platform_device.h>
41 #include <linux/seq_file.h>
42 #include <linux/slab.h>
43 #include <linux/spinlock.h>
44 #include <linux/types.h>
45 #include <dt-bindings/pinctrl/bcm2835.h>
46
47 #define MODULE_NAME "pinctrl-bcm2835"
48 #define BCM2835_NUM_GPIOS 54
49 #define BCM2835_NUM_BANKS 2
50 #define BCM2835_NUM_IRQS 3
51
52 #define BCM2835_PIN_BITMAP_SZ \
53 DIV_ROUND_UP(BCM2835_NUM_GPIOS, sizeof(unsigned long) * 8)
54
55 /* GPIO register offsets */
56 #define GPFSEL0 0x0 /* Function Select */
57 #define GPSET0 0x1c /* Pin Output Set */
58 #define GPCLR0 0x28 /* Pin Output Clear */
59 #define GPLEV0 0x34 /* Pin Level */
60 #define GPEDS0 0x40 /* Pin Event Detect Status */
61 #define GPREN0 0x4c /* Pin Rising Edge Detect Enable */
62 #define GPFEN0 0x58 /* Pin Falling Edge Detect Enable */
63 #define GPHEN0 0x64 /* Pin High Detect Enable */
64 #define GPLEN0 0x70 /* Pin Low Detect Enable */
65 #define GPAREN0 0x7c /* Pin Async Rising Edge Detect */
66 #define GPAFEN0 0x88 /* Pin Async Falling Edge Detect */
67 #define GPPUD 0x94 /* Pin Pull-up/down Enable */
68 #define GPPUDCLK0 0x98 /* Pin Pull-up/down Enable Clock */
69
70 #define FSEL_REG(p) (GPFSEL0 + (((p) / 10) * 4))
71 #define FSEL_SHIFT(p) (((p) % 10) * 3)
72 #define GPIO_REG_OFFSET(p) ((p) / 32)
73 #define GPIO_REG_SHIFT(p) ((p) % 32)
74
75 enum bcm2835_pinconf_param {
76 /* argument: bcm2835_pinconf_pull */
77 BCM2835_PINCONF_PARAM_PULL = (PIN_CONFIG_END + 1),
78 };
79
80 struct bcm2835_pinctrl {
81 struct device *dev;
82 void __iomem *base;
83 int irq[BCM2835_NUM_IRQS];
84
85 /* note: locking assumes each bank will have its own unsigned long */
86 unsigned long enabled_irq_map[BCM2835_NUM_BANKS];
87 unsigned int irq_type[BCM2835_NUM_GPIOS];
88
89 struct pinctrl_dev *pctl_dev;
90 struct gpio_chip gpio_chip;
91 struct pinctrl_gpio_range gpio_range;
92
93 spinlock_t irq_lock[BCM2835_NUM_BANKS];
94 };
95
96 /* pins are just named GPIO0..GPIO53 */
97 #define BCM2835_GPIO_PIN(a) PINCTRL_PIN(a, "gpio" #a)
98 static struct pinctrl_pin_desc bcm2835_gpio_pins[] = {
99 BCM2835_GPIO_PIN(0),
100 BCM2835_GPIO_PIN(1),
101 BCM2835_GPIO_PIN(2),
102 BCM2835_GPIO_PIN(3),
103 BCM2835_GPIO_PIN(4),
104 BCM2835_GPIO_PIN(5),
105 BCM2835_GPIO_PIN(6),
106 BCM2835_GPIO_PIN(7),
107 BCM2835_GPIO_PIN(8),
108 BCM2835_GPIO_PIN(9),
109 BCM2835_GPIO_PIN(10),
110 BCM2835_GPIO_PIN(11),
111 BCM2835_GPIO_PIN(12),
112 BCM2835_GPIO_PIN(13),
113 BCM2835_GPIO_PIN(14),
114 BCM2835_GPIO_PIN(15),
115 BCM2835_GPIO_PIN(16),
116 BCM2835_GPIO_PIN(17),
117 BCM2835_GPIO_PIN(18),
118 BCM2835_GPIO_PIN(19),
119 BCM2835_GPIO_PIN(20),
120 BCM2835_GPIO_PIN(21),
121 BCM2835_GPIO_PIN(22),
122 BCM2835_GPIO_PIN(23),
123 BCM2835_GPIO_PIN(24),
124 BCM2835_GPIO_PIN(25),
125 BCM2835_GPIO_PIN(26),
126 BCM2835_GPIO_PIN(27),
127 BCM2835_GPIO_PIN(28),
128 BCM2835_GPIO_PIN(29),
129 BCM2835_GPIO_PIN(30),
130 BCM2835_GPIO_PIN(31),
131 BCM2835_GPIO_PIN(32),
132 BCM2835_GPIO_PIN(33),
133 BCM2835_GPIO_PIN(34),
134 BCM2835_GPIO_PIN(35),
135 BCM2835_GPIO_PIN(36),
136 BCM2835_GPIO_PIN(37),
137 BCM2835_GPIO_PIN(38),
138 BCM2835_GPIO_PIN(39),
139 BCM2835_GPIO_PIN(40),
140 BCM2835_GPIO_PIN(41),
141 BCM2835_GPIO_PIN(42),
142 BCM2835_GPIO_PIN(43),
143 BCM2835_GPIO_PIN(44),
144 BCM2835_GPIO_PIN(45),
145 BCM2835_GPIO_PIN(46),
146 BCM2835_GPIO_PIN(47),
147 BCM2835_GPIO_PIN(48),
148 BCM2835_GPIO_PIN(49),
149 BCM2835_GPIO_PIN(50),
150 BCM2835_GPIO_PIN(51),
151 BCM2835_GPIO_PIN(52),
152 BCM2835_GPIO_PIN(53),
153 };
154
155 /* one pin per group */
156 static const char * const bcm2835_gpio_groups[] = {
157 "gpio0",
158 "gpio1",
159 "gpio2",
160 "gpio3",
161 "gpio4",
162 "gpio5",
163 "gpio6",
164 "gpio7",
165 "gpio8",
166 "gpio9",
167 "gpio10",
168 "gpio11",
169 "gpio12",
170 "gpio13",
171 "gpio14",
172 "gpio15",
173 "gpio16",
174 "gpio17",
175 "gpio18",
176 "gpio19",
177 "gpio20",
178 "gpio21",
179 "gpio22",
180 "gpio23",
181 "gpio24",
182 "gpio25",
183 "gpio26",
184 "gpio27",
185 "gpio28",
186 "gpio29",
187 "gpio30",
188 "gpio31",
189 "gpio32",
190 "gpio33",
191 "gpio34",
192 "gpio35",
193 "gpio36",
194 "gpio37",
195 "gpio38",
196 "gpio39",
197 "gpio40",
198 "gpio41",
199 "gpio42",
200 "gpio43",
201 "gpio44",
202 "gpio45",
203 "gpio46",
204 "gpio47",
205 "gpio48",
206 "gpio49",
207 "gpio50",
208 "gpio51",
209 "gpio52",
210 "gpio53",
211 };
212
213 enum bcm2835_fsel {
214 BCM2835_FSEL_COUNT = 8,
215 BCM2835_FSEL_MASK = 0x7,
216 };
217
218 static const char * const bcm2835_functions[BCM2835_FSEL_COUNT] = {
219 [BCM2835_FSEL_GPIO_IN] = "gpio_in",
220 [BCM2835_FSEL_GPIO_OUT] = "gpio_out",
221 [BCM2835_FSEL_ALT0] = "alt0",
222 [BCM2835_FSEL_ALT1] = "alt1",
223 [BCM2835_FSEL_ALT2] = "alt2",
224 [BCM2835_FSEL_ALT3] = "alt3",
225 [BCM2835_FSEL_ALT4] = "alt4",
226 [BCM2835_FSEL_ALT5] = "alt5",
227 };
228
229 static const char * const irq_type_names[] = {
230 [IRQ_TYPE_NONE] = "none",
231 [IRQ_TYPE_EDGE_RISING] = "edge-rising",
232 [IRQ_TYPE_EDGE_FALLING] = "edge-falling",
233 [IRQ_TYPE_EDGE_BOTH] = "edge-both",
234 [IRQ_TYPE_LEVEL_HIGH] = "level-high",
235 [IRQ_TYPE_LEVEL_LOW] = "level-low",
236 };
237
bcm2835_gpio_rd(struct bcm2835_pinctrl * pc,unsigned reg)238 static inline u32 bcm2835_gpio_rd(struct bcm2835_pinctrl *pc, unsigned reg)
239 {
240 return readl(pc->base + reg);
241 }
242
bcm2835_gpio_wr(struct bcm2835_pinctrl * pc,unsigned reg,u32 val)243 static inline void bcm2835_gpio_wr(struct bcm2835_pinctrl *pc, unsigned reg,
244 u32 val)
245 {
246 writel(val, pc->base + reg);
247 }
248
bcm2835_gpio_get_bit(struct bcm2835_pinctrl * pc,unsigned reg,unsigned bit)249 static inline int bcm2835_gpio_get_bit(struct bcm2835_pinctrl *pc, unsigned reg,
250 unsigned bit)
251 {
252 reg += GPIO_REG_OFFSET(bit) * 4;
253 return (bcm2835_gpio_rd(pc, reg) >> GPIO_REG_SHIFT(bit)) & 1;
254 }
255
256 /* note NOT a read/modify/write cycle */
bcm2835_gpio_set_bit(struct bcm2835_pinctrl * pc,unsigned reg,unsigned bit)257 static inline void bcm2835_gpio_set_bit(struct bcm2835_pinctrl *pc,
258 unsigned reg, unsigned bit)
259 {
260 reg += GPIO_REG_OFFSET(bit) * 4;
261 bcm2835_gpio_wr(pc, reg, BIT(GPIO_REG_SHIFT(bit)));
262 }
263
bcm2835_pinctrl_fsel_get(struct bcm2835_pinctrl * pc,unsigned pin)264 static inline enum bcm2835_fsel bcm2835_pinctrl_fsel_get(
265 struct bcm2835_pinctrl *pc, unsigned pin)
266 {
267 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
268 enum bcm2835_fsel status = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
269
270 dev_dbg(pc->dev, "get %08x (%u => %s)\n", val, pin,
271 bcm2835_functions[status]);
272
273 return status;
274 }
275
bcm2835_pinctrl_fsel_set(struct bcm2835_pinctrl * pc,unsigned pin,enum bcm2835_fsel fsel)276 static inline void bcm2835_pinctrl_fsel_set(
277 struct bcm2835_pinctrl *pc, unsigned pin,
278 enum bcm2835_fsel fsel)
279 {
280 u32 val = bcm2835_gpio_rd(pc, FSEL_REG(pin));
281 enum bcm2835_fsel cur = (val >> FSEL_SHIFT(pin)) & BCM2835_FSEL_MASK;
282
283 dev_dbg(pc->dev, "read %08x (%u => %s)\n", val, pin,
284 bcm2835_functions[cur]);
285
286 if (cur == fsel)
287 return;
288
289 if (cur != BCM2835_FSEL_GPIO_IN && fsel != BCM2835_FSEL_GPIO_IN) {
290 /* always transition through GPIO_IN */
291 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
292 val |= BCM2835_FSEL_GPIO_IN << FSEL_SHIFT(pin);
293
294 dev_dbg(pc->dev, "trans %08x (%u <= %s)\n", val, pin,
295 bcm2835_functions[BCM2835_FSEL_GPIO_IN]);
296 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
297 }
298
299 val &= ~(BCM2835_FSEL_MASK << FSEL_SHIFT(pin));
300 val |= fsel << FSEL_SHIFT(pin);
301
302 dev_dbg(pc->dev, "write %08x (%u <= %s)\n", val, pin,
303 bcm2835_functions[fsel]);
304 bcm2835_gpio_wr(pc, FSEL_REG(pin), val);
305 }
306
bcm2835_gpio_direction_input(struct gpio_chip * chip,unsigned offset)307 static int bcm2835_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
308 {
309 return pinctrl_gpio_direction_input(chip->base + offset);
310 }
311
bcm2835_gpio_get(struct gpio_chip * chip,unsigned offset)312 static int bcm2835_gpio_get(struct gpio_chip *chip, unsigned offset)
313 {
314 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
315
316 return bcm2835_gpio_get_bit(pc, GPLEV0, offset);
317 }
318
bcm2835_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)319 static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
320 {
321 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
322 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
323
324 /* Alternative function doesn't clearly provide a direction */
325 if (fsel > BCM2835_FSEL_GPIO_OUT)
326 return -EINVAL;
327
328 return (fsel == BCM2835_FSEL_GPIO_IN);
329 }
330
bcm2835_gpio_set(struct gpio_chip * chip,unsigned offset,int value)331 static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
332 {
333 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
334
335 bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
336 }
337
bcm2835_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int value)338 static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
339 unsigned offset, int value)
340 {
341 bcm2835_gpio_set(chip, offset, value);
342 return pinctrl_gpio_direction_output(chip->base + offset);
343 }
344
345 static const struct gpio_chip bcm2835_gpio_chip = {
346 .label = MODULE_NAME,
347 .owner = THIS_MODULE,
348 .request = gpiochip_generic_request,
349 .free = gpiochip_generic_free,
350 .direction_input = bcm2835_gpio_direction_input,
351 .direction_output = bcm2835_gpio_direction_output,
352 .get_direction = bcm2835_gpio_get_direction,
353 .get = bcm2835_gpio_get,
354 .set = bcm2835_gpio_set,
355 .base = -1,
356 .ngpio = BCM2835_NUM_GPIOS,
357 .can_sleep = false,
358 };
359
bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl * pc,unsigned int bank,u32 mask)360 static void bcm2835_gpio_irq_handle_bank(struct bcm2835_pinctrl *pc,
361 unsigned int bank, u32 mask)
362 {
363 unsigned long events;
364 unsigned offset;
365 unsigned gpio;
366
367 events = bcm2835_gpio_rd(pc, GPEDS0 + bank * 4);
368 events &= mask;
369 events &= pc->enabled_irq_map[bank];
370 for_each_set_bit(offset, &events, 32) {
371 gpio = (32 * bank) + offset;
372 generic_handle_irq(irq_linear_revmap(pc->gpio_chip.irq.domain,
373 gpio));
374 }
375 }
376
bcm2835_gpio_irq_handler(struct irq_desc * desc)377 static void bcm2835_gpio_irq_handler(struct irq_desc *desc)
378 {
379 struct gpio_chip *chip = irq_desc_get_handler_data(desc);
380 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
381 struct irq_chip *host_chip = irq_desc_get_chip(desc);
382 int irq = irq_desc_get_irq(desc);
383 int group;
384 int i;
385
386 for (i = 0; i < ARRAY_SIZE(pc->irq); i++) {
387 if (pc->irq[i] == irq) {
388 group = i;
389 break;
390 }
391 }
392 /* This should not happen, every IRQ has a bank */
393 if (i == ARRAY_SIZE(pc->irq))
394 BUG();
395
396 chained_irq_enter(host_chip, desc);
397
398 switch (group) {
399 case 0: /* IRQ0 covers GPIOs 0-27 */
400 bcm2835_gpio_irq_handle_bank(pc, 0, 0x0fffffff);
401 break;
402 case 1: /* IRQ1 covers GPIOs 28-45 */
403 bcm2835_gpio_irq_handle_bank(pc, 0, 0xf0000000);
404 bcm2835_gpio_irq_handle_bank(pc, 1, 0x00003fff);
405 break;
406 case 2: /* IRQ2 covers GPIOs 46-53 */
407 bcm2835_gpio_irq_handle_bank(pc, 1, 0x003fc000);
408 break;
409 }
410
411 chained_irq_exit(host_chip, desc);
412 }
413
__bcm2835_gpio_irq_config(struct bcm2835_pinctrl * pc,unsigned reg,unsigned offset,bool enable)414 static inline void __bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
415 unsigned reg, unsigned offset, bool enable)
416 {
417 u32 value;
418 reg += GPIO_REG_OFFSET(offset) * 4;
419 value = bcm2835_gpio_rd(pc, reg);
420 if (enable)
421 value |= BIT(GPIO_REG_SHIFT(offset));
422 else
423 value &= ~(BIT(GPIO_REG_SHIFT(offset)));
424 bcm2835_gpio_wr(pc, reg, value);
425 }
426
427 /* fast path for IRQ handler */
bcm2835_gpio_irq_config(struct bcm2835_pinctrl * pc,unsigned offset,bool enable)428 static void bcm2835_gpio_irq_config(struct bcm2835_pinctrl *pc,
429 unsigned offset, bool enable)
430 {
431 switch (pc->irq_type[offset]) {
432 case IRQ_TYPE_EDGE_RISING:
433 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
434 break;
435
436 case IRQ_TYPE_EDGE_FALLING:
437 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
438 break;
439
440 case IRQ_TYPE_EDGE_BOTH:
441 __bcm2835_gpio_irq_config(pc, GPREN0, offset, enable);
442 __bcm2835_gpio_irq_config(pc, GPFEN0, offset, enable);
443 break;
444
445 case IRQ_TYPE_LEVEL_HIGH:
446 __bcm2835_gpio_irq_config(pc, GPHEN0, offset, enable);
447 break;
448
449 case IRQ_TYPE_LEVEL_LOW:
450 __bcm2835_gpio_irq_config(pc, GPLEN0, offset, enable);
451 break;
452 }
453 }
454
bcm2835_gpio_irq_enable(struct irq_data * data)455 static void bcm2835_gpio_irq_enable(struct irq_data *data)
456 {
457 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
458 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
459 unsigned gpio = irqd_to_hwirq(data);
460 unsigned offset = GPIO_REG_SHIFT(gpio);
461 unsigned bank = GPIO_REG_OFFSET(gpio);
462 unsigned long flags;
463
464 spin_lock_irqsave(&pc->irq_lock[bank], flags);
465 set_bit(offset, &pc->enabled_irq_map[bank]);
466 bcm2835_gpio_irq_config(pc, gpio, true);
467 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
468 }
469
bcm2835_gpio_irq_disable(struct irq_data * data)470 static void bcm2835_gpio_irq_disable(struct irq_data *data)
471 {
472 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
473 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
474 unsigned gpio = irqd_to_hwirq(data);
475 unsigned offset = GPIO_REG_SHIFT(gpio);
476 unsigned bank = GPIO_REG_OFFSET(gpio);
477 unsigned long flags;
478
479 spin_lock_irqsave(&pc->irq_lock[bank], flags);
480 bcm2835_gpio_irq_config(pc, gpio, false);
481 /* Clear events that were latched prior to clearing event sources */
482 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
483 clear_bit(offset, &pc->enabled_irq_map[bank]);
484 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
485 }
486
__bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl * pc,unsigned offset,unsigned int type)487 static int __bcm2835_gpio_irq_set_type_disabled(struct bcm2835_pinctrl *pc,
488 unsigned offset, unsigned int type)
489 {
490 switch (type) {
491 case IRQ_TYPE_NONE:
492 case IRQ_TYPE_EDGE_RISING:
493 case IRQ_TYPE_EDGE_FALLING:
494 case IRQ_TYPE_EDGE_BOTH:
495 case IRQ_TYPE_LEVEL_HIGH:
496 case IRQ_TYPE_LEVEL_LOW:
497 pc->irq_type[offset] = type;
498 break;
499
500 default:
501 return -EINVAL;
502 }
503 return 0;
504 }
505
506 /* slower path for reconfiguring IRQ type */
__bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl * pc,unsigned offset,unsigned int type)507 static int __bcm2835_gpio_irq_set_type_enabled(struct bcm2835_pinctrl *pc,
508 unsigned offset, unsigned int type)
509 {
510 switch (type) {
511 case IRQ_TYPE_NONE:
512 if (pc->irq_type[offset] != type) {
513 bcm2835_gpio_irq_config(pc, offset, false);
514 pc->irq_type[offset] = type;
515 }
516 break;
517
518 case IRQ_TYPE_EDGE_RISING:
519 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
520 /* RISING already enabled, disable FALLING */
521 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
522 bcm2835_gpio_irq_config(pc, offset, false);
523 pc->irq_type[offset] = type;
524 } else if (pc->irq_type[offset] != type) {
525 bcm2835_gpio_irq_config(pc, offset, false);
526 pc->irq_type[offset] = type;
527 bcm2835_gpio_irq_config(pc, offset, true);
528 }
529 break;
530
531 case IRQ_TYPE_EDGE_FALLING:
532 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_BOTH) {
533 /* FALLING already enabled, disable RISING */
534 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
535 bcm2835_gpio_irq_config(pc, offset, false);
536 pc->irq_type[offset] = type;
537 } else if (pc->irq_type[offset] != type) {
538 bcm2835_gpio_irq_config(pc, offset, false);
539 pc->irq_type[offset] = type;
540 bcm2835_gpio_irq_config(pc, offset, true);
541 }
542 break;
543
544 case IRQ_TYPE_EDGE_BOTH:
545 if (pc->irq_type[offset] == IRQ_TYPE_EDGE_RISING) {
546 /* RISING already enabled, enable FALLING too */
547 pc->irq_type[offset] = IRQ_TYPE_EDGE_FALLING;
548 bcm2835_gpio_irq_config(pc, offset, true);
549 pc->irq_type[offset] = type;
550 } else if (pc->irq_type[offset] == IRQ_TYPE_EDGE_FALLING) {
551 /* FALLING already enabled, enable RISING too */
552 pc->irq_type[offset] = IRQ_TYPE_EDGE_RISING;
553 bcm2835_gpio_irq_config(pc, offset, true);
554 pc->irq_type[offset] = type;
555 } else if (pc->irq_type[offset] != type) {
556 bcm2835_gpio_irq_config(pc, offset, false);
557 pc->irq_type[offset] = type;
558 bcm2835_gpio_irq_config(pc, offset, true);
559 }
560 break;
561
562 case IRQ_TYPE_LEVEL_HIGH:
563 case IRQ_TYPE_LEVEL_LOW:
564 if (pc->irq_type[offset] != type) {
565 bcm2835_gpio_irq_config(pc, offset, false);
566 pc->irq_type[offset] = type;
567 bcm2835_gpio_irq_config(pc, offset, true);
568 }
569 break;
570
571 default:
572 return -EINVAL;
573 }
574 return 0;
575 }
576
bcm2835_gpio_irq_set_type(struct irq_data * data,unsigned int type)577 static int bcm2835_gpio_irq_set_type(struct irq_data *data, unsigned int type)
578 {
579 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
580 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
581 unsigned gpio = irqd_to_hwirq(data);
582 unsigned offset = GPIO_REG_SHIFT(gpio);
583 unsigned bank = GPIO_REG_OFFSET(gpio);
584 unsigned long flags;
585 int ret;
586
587 spin_lock_irqsave(&pc->irq_lock[bank], flags);
588
589 if (test_bit(offset, &pc->enabled_irq_map[bank]))
590 ret = __bcm2835_gpio_irq_set_type_enabled(pc, gpio, type);
591 else
592 ret = __bcm2835_gpio_irq_set_type_disabled(pc, gpio, type);
593
594 if (type & IRQ_TYPE_EDGE_BOTH)
595 irq_set_handler_locked(data, handle_edge_irq);
596 else
597 irq_set_handler_locked(data, handle_level_irq);
598
599 spin_unlock_irqrestore(&pc->irq_lock[bank], flags);
600
601 return ret;
602 }
603
bcm2835_gpio_irq_ack(struct irq_data * data)604 static void bcm2835_gpio_irq_ack(struct irq_data *data)
605 {
606 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
607 struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
608 unsigned gpio = irqd_to_hwirq(data);
609
610 bcm2835_gpio_set_bit(pc, GPEDS0, gpio);
611 }
612
613 static struct irq_chip bcm2835_gpio_irq_chip = {
614 .name = MODULE_NAME,
615 .irq_enable = bcm2835_gpio_irq_enable,
616 .irq_disable = bcm2835_gpio_irq_disable,
617 .irq_set_type = bcm2835_gpio_irq_set_type,
618 .irq_ack = bcm2835_gpio_irq_ack,
619 .irq_mask = bcm2835_gpio_irq_disable,
620 .irq_unmask = bcm2835_gpio_irq_enable,
621 };
622
bcm2835_pctl_get_groups_count(struct pinctrl_dev * pctldev)623 static int bcm2835_pctl_get_groups_count(struct pinctrl_dev *pctldev)
624 {
625 return ARRAY_SIZE(bcm2835_gpio_groups);
626 }
627
bcm2835_pctl_get_group_name(struct pinctrl_dev * pctldev,unsigned selector)628 static const char *bcm2835_pctl_get_group_name(struct pinctrl_dev *pctldev,
629 unsigned selector)
630 {
631 return bcm2835_gpio_groups[selector];
632 }
633
bcm2835_pctl_get_group_pins(struct pinctrl_dev * pctldev,unsigned selector,const unsigned ** pins,unsigned * num_pins)634 static int bcm2835_pctl_get_group_pins(struct pinctrl_dev *pctldev,
635 unsigned selector,
636 const unsigned **pins,
637 unsigned *num_pins)
638 {
639 *pins = &bcm2835_gpio_pins[selector].number;
640 *num_pins = 1;
641
642 return 0;
643 }
644
bcm2835_pctl_pin_dbg_show(struct pinctrl_dev * pctldev,struct seq_file * s,unsigned offset)645 static void bcm2835_pctl_pin_dbg_show(struct pinctrl_dev *pctldev,
646 struct seq_file *s,
647 unsigned offset)
648 {
649 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
650 struct gpio_chip *chip = &pc->gpio_chip;
651 enum bcm2835_fsel fsel = bcm2835_pinctrl_fsel_get(pc, offset);
652 const char *fname = bcm2835_functions[fsel];
653 int value = bcm2835_gpio_get_bit(pc, GPLEV0, offset);
654 int irq = irq_find_mapping(chip->irq.domain, offset);
655
656 seq_printf(s, "function %s in %s; irq %d (%s)",
657 fname, value ? "hi" : "lo",
658 irq, irq_type_names[pc->irq_type[offset]]);
659 }
660
bcm2835_pctl_dt_free_map(struct pinctrl_dev * pctldev,struct pinctrl_map * maps,unsigned num_maps)661 static void bcm2835_pctl_dt_free_map(struct pinctrl_dev *pctldev,
662 struct pinctrl_map *maps, unsigned num_maps)
663 {
664 int i;
665
666 for (i = 0; i < num_maps; i++)
667 if (maps[i].type == PIN_MAP_TYPE_CONFIGS_PIN)
668 kfree(maps[i].data.configs.configs);
669
670 kfree(maps);
671 }
672
bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl * pc,struct device_node * np,u32 pin,u32 fnum,struct pinctrl_map ** maps)673 static int bcm2835_pctl_dt_node_to_map_func(struct bcm2835_pinctrl *pc,
674 struct device_node *np, u32 pin, u32 fnum,
675 struct pinctrl_map **maps)
676 {
677 struct pinctrl_map *map = *maps;
678
679 if (fnum >= ARRAY_SIZE(bcm2835_functions)) {
680 dev_err(pc->dev, "%pOF: invalid brcm,function %d\n", np, fnum);
681 return -EINVAL;
682 }
683
684 map->type = PIN_MAP_TYPE_MUX_GROUP;
685 map->data.mux.group = bcm2835_gpio_groups[pin];
686 map->data.mux.function = bcm2835_functions[fnum];
687 (*maps)++;
688
689 return 0;
690 }
691
bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl * pc,struct device_node * np,u32 pin,u32 pull,struct pinctrl_map ** maps)692 static int bcm2835_pctl_dt_node_to_map_pull(struct bcm2835_pinctrl *pc,
693 struct device_node *np, u32 pin, u32 pull,
694 struct pinctrl_map **maps)
695 {
696 struct pinctrl_map *map = *maps;
697 unsigned long *configs;
698
699 if (pull > 2) {
700 dev_err(pc->dev, "%pOF: invalid brcm,pull %d\n", np, pull);
701 return -EINVAL;
702 }
703
704 configs = kzalloc(sizeof(*configs), GFP_KERNEL);
705 if (!configs)
706 return -ENOMEM;
707 configs[0] = pinconf_to_config_packed(BCM2835_PINCONF_PARAM_PULL, pull);
708
709 map->type = PIN_MAP_TYPE_CONFIGS_PIN;
710 map->data.configs.group_or_pin = bcm2835_gpio_pins[pin].name;
711 map->data.configs.configs = configs;
712 map->data.configs.num_configs = 1;
713 (*maps)++;
714
715 return 0;
716 }
717
bcm2835_pctl_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * np,struct pinctrl_map ** map,unsigned int * num_maps)718 static int bcm2835_pctl_dt_node_to_map(struct pinctrl_dev *pctldev,
719 struct device_node *np,
720 struct pinctrl_map **map, unsigned int *num_maps)
721 {
722 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
723 struct property *pins, *funcs, *pulls;
724 int num_pins, num_funcs, num_pulls, maps_per_pin;
725 struct pinctrl_map *maps, *cur_map;
726 int i, err;
727 u32 pin, func, pull;
728
729 /* Check for generic binding in this node */
730 err = pinconf_generic_dt_node_to_map_all(pctldev, np, map, num_maps);
731 if (err || *num_maps)
732 return err;
733
734 /* Generic binding did not find anything continue with legacy parse */
735 pins = of_find_property(np, "brcm,pins", NULL);
736 if (!pins) {
737 dev_err(pc->dev, "%pOF: missing brcm,pins property\n", np);
738 return -EINVAL;
739 }
740
741 funcs = of_find_property(np, "brcm,function", NULL);
742 pulls = of_find_property(np, "brcm,pull", NULL);
743
744 if (!funcs && !pulls) {
745 dev_err(pc->dev,
746 "%pOF: neither brcm,function nor brcm,pull specified\n",
747 np);
748 return -EINVAL;
749 }
750
751 num_pins = pins->length / 4;
752 num_funcs = funcs ? (funcs->length / 4) : 0;
753 num_pulls = pulls ? (pulls->length / 4) : 0;
754
755 if (num_funcs > 1 && num_funcs != num_pins) {
756 dev_err(pc->dev,
757 "%pOF: brcm,function must have 1 or %d entries\n",
758 np, num_pins);
759 return -EINVAL;
760 }
761
762 if (num_pulls > 1 && num_pulls != num_pins) {
763 dev_err(pc->dev,
764 "%pOF: brcm,pull must have 1 or %d entries\n",
765 np, num_pins);
766 return -EINVAL;
767 }
768
769 maps_per_pin = 0;
770 if (num_funcs)
771 maps_per_pin++;
772 if (num_pulls)
773 maps_per_pin++;
774 cur_map = maps = kcalloc(num_pins * maps_per_pin, sizeof(*maps),
775 GFP_KERNEL);
776 if (!maps)
777 return -ENOMEM;
778
779 for (i = 0; i < num_pins; i++) {
780 err = of_property_read_u32_index(np, "brcm,pins", i, &pin);
781 if (err)
782 goto out;
783 if (pin >= ARRAY_SIZE(bcm2835_gpio_pins)) {
784 dev_err(pc->dev, "%pOF: invalid brcm,pins value %d\n",
785 np, pin);
786 err = -EINVAL;
787 goto out;
788 }
789
790 if (num_funcs) {
791 err = of_property_read_u32_index(np, "brcm,function",
792 (num_funcs > 1) ? i : 0, &func);
793 if (err)
794 goto out;
795 err = bcm2835_pctl_dt_node_to_map_func(pc, np, pin,
796 func, &cur_map);
797 if (err)
798 goto out;
799 }
800 if (num_pulls) {
801 err = of_property_read_u32_index(np, "brcm,pull",
802 (num_pulls > 1) ? i : 0, &pull);
803 if (err)
804 goto out;
805 err = bcm2835_pctl_dt_node_to_map_pull(pc, np, pin,
806 pull, &cur_map);
807 if (err)
808 goto out;
809 }
810 }
811
812 *map = maps;
813 *num_maps = num_pins * maps_per_pin;
814
815 return 0;
816
817 out:
818 bcm2835_pctl_dt_free_map(pctldev, maps, num_pins * maps_per_pin);
819 return err;
820 }
821
822 static const struct pinctrl_ops bcm2835_pctl_ops = {
823 .get_groups_count = bcm2835_pctl_get_groups_count,
824 .get_group_name = bcm2835_pctl_get_group_name,
825 .get_group_pins = bcm2835_pctl_get_group_pins,
826 .pin_dbg_show = bcm2835_pctl_pin_dbg_show,
827 .dt_node_to_map = bcm2835_pctl_dt_node_to_map,
828 .dt_free_map = bcm2835_pctl_dt_free_map,
829 };
830
bcm2835_pmx_free(struct pinctrl_dev * pctldev,unsigned offset)831 static int bcm2835_pmx_free(struct pinctrl_dev *pctldev,
832 unsigned offset)
833 {
834 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
835
836 /* disable by setting to GPIO_IN */
837 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
838 return 0;
839 }
840
bcm2835_pmx_get_functions_count(struct pinctrl_dev * pctldev)841 static int bcm2835_pmx_get_functions_count(struct pinctrl_dev *pctldev)
842 {
843 return BCM2835_FSEL_COUNT;
844 }
845
bcm2835_pmx_get_function_name(struct pinctrl_dev * pctldev,unsigned selector)846 static const char *bcm2835_pmx_get_function_name(struct pinctrl_dev *pctldev,
847 unsigned selector)
848 {
849 return bcm2835_functions[selector];
850 }
851
bcm2835_pmx_get_function_groups(struct pinctrl_dev * pctldev,unsigned selector,const char * const ** groups,unsigned * const num_groups)852 static int bcm2835_pmx_get_function_groups(struct pinctrl_dev *pctldev,
853 unsigned selector,
854 const char * const **groups,
855 unsigned * const num_groups)
856 {
857 /* every pin can do every function */
858 *groups = bcm2835_gpio_groups;
859 *num_groups = ARRAY_SIZE(bcm2835_gpio_groups);
860
861 return 0;
862 }
863
bcm2835_pmx_set(struct pinctrl_dev * pctldev,unsigned func_selector,unsigned group_selector)864 static int bcm2835_pmx_set(struct pinctrl_dev *pctldev,
865 unsigned func_selector,
866 unsigned group_selector)
867 {
868 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
869
870 bcm2835_pinctrl_fsel_set(pc, group_selector, func_selector);
871
872 return 0;
873 }
874
bcm2835_pmx_gpio_disable_free(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned offset)875 static void bcm2835_pmx_gpio_disable_free(struct pinctrl_dev *pctldev,
876 struct pinctrl_gpio_range *range,
877 unsigned offset)
878 {
879 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
880
881 /* disable by setting to GPIO_IN */
882 bcm2835_pinctrl_fsel_set(pc, offset, BCM2835_FSEL_GPIO_IN);
883 }
884
bcm2835_pmx_gpio_set_direction(struct pinctrl_dev * pctldev,struct pinctrl_gpio_range * range,unsigned offset,bool input)885 static int bcm2835_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
886 struct pinctrl_gpio_range *range,
887 unsigned offset,
888 bool input)
889 {
890 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
891 enum bcm2835_fsel fsel = input ?
892 BCM2835_FSEL_GPIO_IN : BCM2835_FSEL_GPIO_OUT;
893
894 bcm2835_pinctrl_fsel_set(pc, offset, fsel);
895
896 return 0;
897 }
898
899 static const struct pinmux_ops bcm2835_pmx_ops = {
900 .free = bcm2835_pmx_free,
901 .get_functions_count = bcm2835_pmx_get_functions_count,
902 .get_function_name = bcm2835_pmx_get_function_name,
903 .get_function_groups = bcm2835_pmx_get_function_groups,
904 .set_mux = bcm2835_pmx_set,
905 .gpio_disable_free = bcm2835_pmx_gpio_disable_free,
906 .gpio_set_direction = bcm2835_pmx_gpio_set_direction,
907 };
908
bcm2835_pinconf_get(struct pinctrl_dev * pctldev,unsigned pin,unsigned long * config)909 static int bcm2835_pinconf_get(struct pinctrl_dev *pctldev,
910 unsigned pin, unsigned long *config)
911 {
912 /* No way to read back config in HW */
913 return -ENOTSUPP;
914 }
915
bcm2835_pull_config_set(struct bcm2835_pinctrl * pc,unsigned int pin,unsigned int arg)916 static void bcm2835_pull_config_set(struct bcm2835_pinctrl *pc,
917 unsigned int pin, unsigned int arg)
918 {
919 u32 off, bit;
920
921 off = GPIO_REG_OFFSET(pin);
922 bit = GPIO_REG_SHIFT(pin);
923
924 bcm2835_gpio_wr(pc, GPPUD, arg & 3);
925 /*
926 * BCM2835 datasheet say to wait 150 cycles, but not of what.
927 * But the VideoCore firmware delay for this operation
928 * based nearly on the same amount of VPU cycles and this clock
929 * runs at 250 MHz.
930 */
931 udelay(1);
932 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), BIT(bit));
933 udelay(1);
934 bcm2835_gpio_wr(pc, GPPUDCLK0 + (off * 4), 0);
935 }
936
bcm2835_pinconf_set(struct pinctrl_dev * pctldev,unsigned int pin,unsigned long * configs,unsigned int num_configs)937 static int bcm2835_pinconf_set(struct pinctrl_dev *pctldev,
938 unsigned int pin, unsigned long *configs,
939 unsigned int num_configs)
940 {
941 struct bcm2835_pinctrl *pc = pinctrl_dev_get_drvdata(pctldev);
942 u32 param, arg;
943 int i;
944
945 for (i = 0; i < num_configs; i++) {
946 param = pinconf_to_config_param(configs[i]);
947 arg = pinconf_to_config_argument(configs[i]);
948
949 switch (param) {
950 /* Set legacy brcm,pull */
951 case BCM2835_PINCONF_PARAM_PULL:
952 bcm2835_pull_config_set(pc, pin, arg);
953 break;
954
955 /* Set pull generic bindings */
956 case PIN_CONFIG_BIAS_DISABLE:
957 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_OFF);
958 break;
959
960 case PIN_CONFIG_BIAS_PULL_DOWN:
961 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_DOWN);
962 break;
963
964 case PIN_CONFIG_BIAS_PULL_UP:
965 bcm2835_pull_config_set(pc, pin, BCM2835_PUD_UP);
966 break;
967
968 /* Set output-high or output-low */
969 case PIN_CONFIG_OUTPUT:
970 bcm2835_gpio_set_bit(pc, arg ? GPSET0 : GPCLR0, pin);
971 break;
972
973 default:
974 return -EINVAL;
975
976 } /* switch param type */
977 } /* for each config */
978
979 return 0;
980 }
981
982 static const struct pinconf_ops bcm2835_pinconf_ops = {
983 .pin_config_get = bcm2835_pinconf_get,
984 .pin_config_set = bcm2835_pinconf_set,
985 };
986
987 static struct pinctrl_desc bcm2835_pinctrl_desc = {
988 .name = MODULE_NAME,
989 .pins = bcm2835_gpio_pins,
990 .npins = ARRAY_SIZE(bcm2835_gpio_pins),
991 .pctlops = &bcm2835_pctl_ops,
992 .pmxops = &bcm2835_pmx_ops,
993 .confops = &bcm2835_pinconf_ops,
994 .owner = THIS_MODULE,
995 };
996
997 static struct pinctrl_gpio_range bcm2835_pinctrl_gpio_range = {
998 .name = MODULE_NAME,
999 .npins = BCM2835_NUM_GPIOS,
1000 };
1001
bcm2835_pinctrl_probe(struct platform_device * pdev)1002 static int bcm2835_pinctrl_probe(struct platform_device *pdev)
1003 {
1004 struct device *dev = &pdev->dev;
1005 struct device_node *np = dev->of_node;
1006 struct bcm2835_pinctrl *pc;
1007 struct resource iomem;
1008 int err, i;
1009 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_pins) != BCM2835_NUM_GPIOS);
1010 BUILD_BUG_ON(ARRAY_SIZE(bcm2835_gpio_groups) != BCM2835_NUM_GPIOS);
1011
1012 pc = devm_kzalloc(dev, sizeof(*pc), GFP_KERNEL);
1013 if (!pc)
1014 return -ENOMEM;
1015
1016 platform_set_drvdata(pdev, pc);
1017 pc->dev = dev;
1018
1019 err = of_address_to_resource(np, 0, &iomem);
1020 if (err) {
1021 dev_err(dev, "could not get IO memory\n");
1022 return err;
1023 }
1024
1025 pc->base = devm_ioremap_resource(dev, &iomem);
1026 if (IS_ERR(pc->base))
1027 return PTR_ERR(pc->base);
1028
1029 pc->gpio_chip = bcm2835_gpio_chip;
1030 pc->gpio_chip.parent = dev;
1031 pc->gpio_chip.of_node = np;
1032
1033 for (i = 0; i < BCM2835_NUM_BANKS; i++) {
1034 unsigned long events;
1035 unsigned offset;
1036
1037 /* clear event detection flags */
1038 bcm2835_gpio_wr(pc, GPREN0 + i * 4, 0);
1039 bcm2835_gpio_wr(pc, GPFEN0 + i * 4, 0);
1040 bcm2835_gpio_wr(pc, GPHEN0 + i * 4, 0);
1041 bcm2835_gpio_wr(pc, GPLEN0 + i * 4, 0);
1042 bcm2835_gpio_wr(pc, GPAREN0 + i * 4, 0);
1043 bcm2835_gpio_wr(pc, GPAFEN0 + i * 4, 0);
1044
1045 /* clear all the events */
1046 events = bcm2835_gpio_rd(pc, GPEDS0 + i * 4);
1047 for_each_set_bit(offset, &events, 32)
1048 bcm2835_gpio_wr(pc, GPEDS0 + i * 4, BIT(offset));
1049
1050 spin_lock_init(&pc->irq_lock[i]);
1051 }
1052
1053 err = gpiochip_add_data(&pc->gpio_chip, pc);
1054 if (err) {
1055 dev_err(dev, "could not add GPIO chip\n");
1056 return err;
1057 }
1058
1059 err = gpiochip_irqchip_add(&pc->gpio_chip, &bcm2835_gpio_irq_chip,
1060 0, handle_level_irq, IRQ_TYPE_NONE);
1061 if (err) {
1062 dev_info(dev, "could not add irqchip\n");
1063 return err;
1064 }
1065
1066 for (i = 0; i < BCM2835_NUM_IRQS; i++) {
1067 pc->irq[i] = irq_of_parse_and_map(np, i);
1068
1069 if (pc->irq[i] == 0)
1070 continue;
1071
1072 /*
1073 * Use the same handler for all groups: this is necessary
1074 * since we use one gpiochip to cover all lines - the
1075 * irq handler then needs to figure out which group and
1076 * bank that was firing the IRQ and look up the per-group
1077 * and bank data.
1078 */
1079 gpiochip_set_chained_irqchip(&pc->gpio_chip,
1080 &bcm2835_gpio_irq_chip,
1081 pc->irq[i],
1082 bcm2835_gpio_irq_handler);
1083 }
1084
1085 pc->pctl_dev = devm_pinctrl_register(dev, &bcm2835_pinctrl_desc, pc);
1086 if (IS_ERR(pc->pctl_dev)) {
1087 gpiochip_remove(&pc->gpio_chip);
1088 return PTR_ERR(pc->pctl_dev);
1089 }
1090
1091 pc->gpio_range = bcm2835_pinctrl_gpio_range;
1092 pc->gpio_range.base = pc->gpio_chip.base;
1093 pc->gpio_range.gc = &pc->gpio_chip;
1094 pinctrl_add_gpio_range(pc->pctl_dev, &pc->gpio_range);
1095
1096 return 0;
1097 }
1098
1099 static const struct of_device_id bcm2835_pinctrl_match[] = {
1100 { .compatible = "brcm,bcm2835-gpio" },
1101 {}
1102 };
1103
1104 static struct platform_driver bcm2835_pinctrl_driver = {
1105 .probe = bcm2835_pinctrl_probe,
1106 .driver = {
1107 .name = MODULE_NAME,
1108 .of_match_table = bcm2835_pinctrl_match,
1109 .suppress_bind_attrs = true,
1110 },
1111 };
1112 builtin_platform_driver(bcm2835_pinctrl_driver);
1113
