1 // SPDX-License-Identifier: GPL-2.0
2 // Copyright (c) 2017 Cadence
3 // Cadence PCIe endpoint controller driver.
4 // Author: Cyrille Pitchen <cyrille.pitchen@free-electrons.com>
5
6 #include <linux/delay.h>
7 #include <linux/kernel.h>
8 #include <linux/of.h>
9 #include <linux/pci-epc.h>
10 #include <linux/platform_device.h>
11 #include <linux/pm_runtime.h>
12 #include <linux/sizes.h>
13
14 #include "pcie-cadence.h"
15
16 #define CDNS_PCIE_EP_MIN_APERTURE 128 /* 128 bytes */
17 #define CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE 0x1
18 #define CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY 0x3
19
20 /**
21 * struct cdns_pcie_ep - private data for this PCIe endpoint controller driver
22 * @pcie: Cadence PCIe controller
23 * @max_regions: maximum number of regions supported by hardware
24 * @ob_region_map: bitmask of mapped outbound regions
25 * @ob_addr: base addresses in the AXI bus where the outbound regions start
26 * @irq_phys_addr: base address on the AXI bus where the MSI/legacy IRQ
27 * dedicated outbound regions is mapped.
28 * @irq_cpu_addr: base address in the CPU space where a write access triggers
29 * the sending of a memory write (MSI) / normal message (legacy
30 * IRQ) TLP through the PCIe bus.
31 * @irq_pci_addr: used to save the current mapping of the MSI/legacy IRQ
32 * dedicated outbound region.
33 * @irq_pci_fn: the latest PCI function that has updated the mapping of
34 * the MSI/legacy IRQ dedicated outbound region.
35 * @irq_pending: bitmask of asserted legacy IRQs.
36 */
37 struct cdns_pcie_ep {
38 struct cdns_pcie pcie;
39 u32 max_regions;
40 unsigned long ob_region_map;
41 phys_addr_t *ob_addr;
42 phys_addr_t irq_phys_addr;
43 void __iomem *irq_cpu_addr;
44 u64 irq_pci_addr;
45 u8 irq_pci_fn;
46 u8 irq_pending;
47 };
48
cdns_pcie_ep_write_header(struct pci_epc * epc,u8 fn,struct pci_epf_header * hdr)49 static int cdns_pcie_ep_write_header(struct pci_epc *epc, u8 fn,
50 struct pci_epf_header *hdr)
51 {
52 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
53 struct cdns_pcie *pcie = &ep->pcie;
54
55 cdns_pcie_ep_fn_writew(pcie, fn, PCI_DEVICE_ID, hdr->deviceid);
56 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_REVISION_ID, hdr->revid);
57 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CLASS_PROG, hdr->progif_code);
58 cdns_pcie_ep_fn_writew(pcie, fn, PCI_CLASS_DEVICE,
59 hdr->subclass_code | hdr->baseclass_code << 8);
60 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_CACHE_LINE_SIZE,
61 hdr->cache_line_size);
62 cdns_pcie_ep_fn_writew(pcie, fn, PCI_SUBSYSTEM_ID, hdr->subsys_id);
63 cdns_pcie_ep_fn_writeb(pcie, fn, PCI_INTERRUPT_PIN, hdr->interrupt_pin);
64
65 /*
66 * Vendor ID can only be modified from function 0, all other functions
67 * use the same vendor ID as function 0.
68 */
69 if (fn == 0) {
70 /* Update the vendor IDs. */
71 u32 id = CDNS_PCIE_LM_ID_VENDOR(hdr->vendorid) |
72 CDNS_PCIE_LM_ID_SUBSYS(hdr->subsys_vendor_id);
73
74 cdns_pcie_writel(pcie, CDNS_PCIE_LM_ID, id);
75 }
76
77 return 0;
78 }
79
cdns_pcie_ep_set_bar(struct pci_epc * epc,u8 fn,struct pci_epf_bar * epf_bar)80 static int cdns_pcie_ep_set_bar(struct pci_epc *epc, u8 fn,
81 struct pci_epf_bar *epf_bar)
82 {
83 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
84 struct cdns_pcie *pcie = &ep->pcie;
85 dma_addr_t bar_phys = epf_bar->phys_addr;
86 enum pci_barno bar = epf_bar->barno;
87 int flags = epf_bar->flags;
88 u32 addr0, addr1, reg, cfg, b, aperture, ctrl;
89 u64 sz;
90
91 /* BAR size is 2^(aperture + 7) */
92 sz = max_t(size_t, epf_bar->size, CDNS_PCIE_EP_MIN_APERTURE);
93 /*
94 * roundup_pow_of_two() returns an unsigned long, which is not suited
95 * for 64bit values.
96 */
97 sz = 1ULL << fls64(sz - 1);
98 aperture = ilog2(sz) - 7; /* 128B -> 0, 256B -> 1, 512B -> 2, ... */
99
100 if ((flags & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
101 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_IO_32BITS;
102 } else {
103 bool is_prefetch = !!(flags & PCI_BASE_ADDRESS_MEM_PREFETCH);
104 bool is_64bits = sz > SZ_2G;
105
106 if (is_64bits && (bar & 1))
107 return -EINVAL;
108
109 if (is_64bits && !(flags & PCI_BASE_ADDRESS_MEM_TYPE_64))
110 epf_bar->flags |= PCI_BASE_ADDRESS_MEM_TYPE_64;
111
112 if (is_64bits && is_prefetch)
113 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_64BITS;
114 else if (is_prefetch)
115 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_PREFETCH_MEM_32BITS;
116 else if (is_64bits)
117 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_64BITS;
118 else
119 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_MEM_32BITS;
120 }
121
122 addr0 = lower_32_bits(bar_phys);
123 addr1 = upper_32_bits(bar_phys);
124 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar),
125 addr0);
126 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar),
127 addr1);
128
129 if (bar < BAR_4) {
130 reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
131 b = bar;
132 } else {
133 reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
134 b = bar - BAR_4;
135 }
136
137 cfg = cdns_pcie_readl(pcie, reg);
138 cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
139 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
140 cfg |= (CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE(b, aperture) |
141 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl));
142 cdns_pcie_writel(pcie, reg, cfg);
143
144 return 0;
145 }
146
cdns_pcie_ep_clear_bar(struct pci_epc * epc,u8 fn,struct pci_epf_bar * epf_bar)147 static void cdns_pcie_ep_clear_bar(struct pci_epc *epc, u8 fn,
148 struct pci_epf_bar *epf_bar)
149 {
150 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
151 struct cdns_pcie *pcie = &ep->pcie;
152 enum pci_barno bar = epf_bar->barno;
153 u32 reg, cfg, b, ctrl;
154
155 if (bar < BAR_4) {
156 reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG0(fn);
157 b = bar;
158 } else {
159 reg = CDNS_PCIE_LM_EP_FUNC_BAR_CFG1(fn);
160 b = bar - BAR_4;
161 }
162
163 ctrl = CDNS_PCIE_LM_BAR_CFG_CTRL_DISABLED;
164 cfg = cdns_pcie_readl(pcie, reg);
165 cfg &= ~(CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_APERTURE_MASK(b) |
166 CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL_MASK(b));
167 cfg |= CDNS_PCIE_LM_EP_FUNC_BAR_CFG_BAR_CTRL(b, ctrl);
168 cdns_pcie_writel(pcie, reg, cfg);
169
170 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR0(fn, bar), 0);
171 cdns_pcie_writel(pcie, CDNS_PCIE_AT_IB_EP_FUNC_BAR_ADDR1(fn, bar), 0);
172 }
173
cdns_pcie_ep_map_addr(struct pci_epc * epc,u8 fn,phys_addr_t addr,u64 pci_addr,size_t size)174 static int cdns_pcie_ep_map_addr(struct pci_epc *epc, u8 fn, phys_addr_t addr,
175 u64 pci_addr, size_t size)
176 {
177 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
178 struct cdns_pcie *pcie = &ep->pcie;
179 u32 r;
180
181 r = find_first_zero_bit(&ep->ob_region_map,
182 sizeof(ep->ob_region_map) * BITS_PER_LONG);
183 if (r >= ep->max_regions - 1) {
184 dev_err(&epc->dev, "no free outbound region\n");
185 return -EINVAL;
186 }
187
188 cdns_pcie_set_outbound_region(pcie, fn, r, false, addr, pci_addr, size);
189
190 set_bit(r, &ep->ob_region_map);
191 ep->ob_addr[r] = addr;
192
193 return 0;
194 }
195
cdns_pcie_ep_unmap_addr(struct pci_epc * epc,u8 fn,phys_addr_t addr)196 static void cdns_pcie_ep_unmap_addr(struct pci_epc *epc, u8 fn,
197 phys_addr_t addr)
198 {
199 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
200 struct cdns_pcie *pcie = &ep->pcie;
201 u32 r;
202
203 for (r = 0; r < ep->max_regions - 1; r++)
204 if (ep->ob_addr[r] == addr)
205 break;
206
207 if (r == ep->max_regions - 1)
208 return;
209
210 cdns_pcie_reset_outbound_region(pcie, r);
211
212 ep->ob_addr[r] = 0;
213 clear_bit(r, &ep->ob_region_map);
214 }
215
cdns_pcie_ep_set_msi(struct pci_epc * epc,u8 fn,u8 mmc)216 static int cdns_pcie_ep_set_msi(struct pci_epc *epc, u8 fn, u8 mmc)
217 {
218 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
219 struct cdns_pcie *pcie = &ep->pcie;
220 u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
221 u16 flags;
222
223 /*
224 * Set the Multiple Message Capable bitfield into the Message Control
225 * register.
226 */
227 flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
228 flags = (flags & ~PCI_MSI_FLAGS_QMASK) | (mmc << 1);
229 flags |= PCI_MSI_FLAGS_64BIT;
230 flags &= ~PCI_MSI_FLAGS_MASKBIT;
231 cdns_pcie_ep_fn_writew(pcie, fn, cap + PCI_MSI_FLAGS, flags);
232
233 return 0;
234 }
235
cdns_pcie_ep_get_msi(struct pci_epc * epc,u8 fn)236 static int cdns_pcie_ep_get_msi(struct pci_epc *epc, u8 fn)
237 {
238 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
239 struct cdns_pcie *pcie = &ep->pcie;
240 u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
241 u16 flags, mme;
242
243 /* Validate that the MSI feature is actually enabled. */
244 flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
245 if (!(flags & PCI_MSI_FLAGS_ENABLE))
246 return -EINVAL;
247
248 /*
249 * Get the Multiple Message Enable bitfield from the Message Control
250 * register.
251 */
252 mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4;
253
254 return mme;
255 }
256
cdns_pcie_ep_assert_intx(struct cdns_pcie_ep * ep,u8 fn,u8 intx,bool is_asserted)257 static void cdns_pcie_ep_assert_intx(struct cdns_pcie_ep *ep, u8 fn,
258 u8 intx, bool is_asserted)
259 {
260 struct cdns_pcie *pcie = &ep->pcie;
261 u32 r = ep->max_regions - 1;
262 u32 offset;
263 u16 status;
264 u8 msg_code;
265
266 intx &= 3;
267
268 /* Set the outbound region if needed. */
269 if (unlikely(ep->irq_pci_addr != CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY ||
270 ep->irq_pci_fn != fn)) {
271 /* Last region was reserved for IRQ writes. */
272 cdns_pcie_set_outbound_region_for_normal_msg(pcie, fn, r,
273 ep->irq_phys_addr);
274 ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_LEGACY;
275 ep->irq_pci_fn = fn;
276 }
277
278 if (is_asserted) {
279 ep->irq_pending |= BIT(intx);
280 msg_code = MSG_CODE_ASSERT_INTA + intx;
281 } else {
282 ep->irq_pending &= ~BIT(intx);
283 msg_code = MSG_CODE_DEASSERT_INTA + intx;
284 }
285
286 status = cdns_pcie_ep_fn_readw(pcie, fn, PCI_STATUS);
287 if (((status & PCI_STATUS_INTERRUPT) != 0) ^ (ep->irq_pending != 0)) {
288 status ^= PCI_STATUS_INTERRUPT;
289 cdns_pcie_ep_fn_writew(pcie, fn, PCI_STATUS, status);
290 }
291
292 offset = CDNS_PCIE_NORMAL_MSG_ROUTING(MSG_ROUTING_LOCAL) |
293 CDNS_PCIE_NORMAL_MSG_CODE(msg_code) |
294 CDNS_PCIE_MSG_NO_DATA;
295 writel(0, ep->irq_cpu_addr + offset);
296 }
297
cdns_pcie_ep_send_legacy_irq(struct cdns_pcie_ep * ep,u8 fn,u8 intx)298 static int cdns_pcie_ep_send_legacy_irq(struct cdns_pcie_ep *ep, u8 fn, u8 intx)
299 {
300 u16 cmd;
301
302 cmd = cdns_pcie_ep_fn_readw(&ep->pcie, fn, PCI_COMMAND);
303 if (cmd & PCI_COMMAND_INTX_DISABLE)
304 return -EINVAL;
305
306 cdns_pcie_ep_assert_intx(ep, fn, intx, true);
307 /*
308 * The mdelay() value was taken from dra7xx_pcie_raise_legacy_irq()
309 * from drivers/pci/dwc/pci-dra7xx.c
310 */
311 mdelay(1);
312 cdns_pcie_ep_assert_intx(ep, fn, intx, false);
313 return 0;
314 }
315
cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep * ep,u8 fn,u8 interrupt_num)316 static int cdns_pcie_ep_send_msi_irq(struct cdns_pcie_ep *ep, u8 fn,
317 u8 interrupt_num)
318 {
319 struct cdns_pcie *pcie = &ep->pcie;
320 u32 cap = CDNS_PCIE_EP_FUNC_MSI_CAP_OFFSET;
321 u16 flags, mme, data, data_mask;
322 u8 msi_count;
323 u64 pci_addr, pci_addr_mask = 0xff;
324
325 /* Check whether the MSI feature has been enabled by the PCI host. */
326 flags = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_FLAGS);
327 if (!(flags & PCI_MSI_FLAGS_ENABLE))
328 return -EINVAL;
329
330 /* Get the number of enabled MSIs */
331 mme = (flags & PCI_MSI_FLAGS_QSIZE) >> 4;
332 msi_count = 1 << mme;
333 if (!interrupt_num || interrupt_num > msi_count)
334 return -EINVAL;
335
336 /* Compute the data value to be written. */
337 data_mask = msi_count - 1;
338 data = cdns_pcie_ep_fn_readw(pcie, fn, cap + PCI_MSI_DATA_64);
339 data = (data & ~data_mask) | ((interrupt_num - 1) & data_mask);
340
341 /* Get the PCI address where to write the data into. */
342 pci_addr = cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_HI);
343 pci_addr <<= 32;
344 pci_addr |= cdns_pcie_ep_fn_readl(pcie, fn, cap + PCI_MSI_ADDRESS_LO);
345 pci_addr &= GENMASK_ULL(63, 2);
346
347 /* Set the outbound region if needed. */
348 if (unlikely(ep->irq_pci_addr != (pci_addr & ~pci_addr_mask) ||
349 ep->irq_pci_fn != fn)) {
350 /* Last region was reserved for IRQ writes. */
351 cdns_pcie_set_outbound_region(pcie, fn, ep->max_regions - 1,
352 false,
353 ep->irq_phys_addr,
354 pci_addr & ~pci_addr_mask,
355 pci_addr_mask + 1);
356 ep->irq_pci_addr = (pci_addr & ~pci_addr_mask);
357 ep->irq_pci_fn = fn;
358 }
359 writew(data, ep->irq_cpu_addr + (pci_addr & pci_addr_mask));
360
361 return 0;
362 }
363
cdns_pcie_ep_raise_irq(struct pci_epc * epc,u8 fn,enum pci_epc_irq_type type,u16 interrupt_num)364 static int cdns_pcie_ep_raise_irq(struct pci_epc *epc, u8 fn,
365 enum pci_epc_irq_type type,
366 u16 interrupt_num)
367 {
368 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
369
370 switch (type) {
371 case PCI_EPC_IRQ_LEGACY:
372 return cdns_pcie_ep_send_legacy_irq(ep, fn, 0);
373
374 case PCI_EPC_IRQ_MSI:
375 return cdns_pcie_ep_send_msi_irq(ep, fn, interrupt_num);
376
377 default:
378 break;
379 }
380
381 return -EINVAL;
382 }
383
cdns_pcie_ep_start(struct pci_epc * epc)384 static int cdns_pcie_ep_start(struct pci_epc *epc)
385 {
386 struct cdns_pcie_ep *ep = epc_get_drvdata(epc);
387 struct cdns_pcie *pcie = &ep->pcie;
388 struct pci_epf *epf;
389 u32 cfg;
390
391 /*
392 * BIT(0) is hardwired to 1, hence function 0 is always enabled
393 * and can't be disabled anyway.
394 */
395 cfg = BIT(0);
396 list_for_each_entry(epf, &epc->pci_epf, list)
397 cfg |= BIT(epf->func_no);
398 cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, cfg);
399
400 /*
401 * The PCIe links are automatically established by the controller
402 * once for all at powerup: the software can neither start nor stop
403 * those links later at runtime.
404 *
405 * Then we only have to notify the EP core that our links are already
406 * established. However we don't call directly pci_epc_linkup() because
407 * we've already locked the epc->lock.
408 */
409 list_for_each_entry(epf, &epc->pci_epf, list)
410 pci_epf_linkup(epf);
411
412 return 0;
413 }
414
415 static const struct pci_epc_ops cdns_pcie_epc_ops = {
416 .write_header = cdns_pcie_ep_write_header,
417 .set_bar = cdns_pcie_ep_set_bar,
418 .clear_bar = cdns_pcie_ep_clear_bar,
419 .map_addr = cdns_pcie_ep_map_addr,
420 .unmap_addr = cdns_pcie_ep_unmap_addr,
421 .set_msi = cdns_pcie_ep_set_msi,
422 .get_msi = cdns_pcie_ep_get_msi,
423 .raise_irq = cdns_pcie_ep_raise_irq,
424 .start = cdns_pcie_ep_start,
425 };
426
427 static const struct of_device_id cdns_pcie_ep_of_match[] = {
428 { .compatible = "cdns,cdns-pcie-ep" },
429
430 { },
431 };
432
cdns_pcie_ep_probe(struct platform_device * pdev)433 static int cdns_pcie_ep_probe(struct platform_device *pdev)
434 {
435 struct device *dev = &pdev->dev;
436 struct device_node *np = dev->of_node;
437 struct cdns_pcie_ep *ep;
438 struct cdns_pcie *pcie;
439 struct pci_epc *epc;
440 struct resource *res;
441 int ret;
442 int phy_count;
443
444 ep = devm_kzalloc(dev, sizeof(*ep), GFP_KERNEL);
445 if (!ep)
446 return -ENOMEM;
447
448 pcie = &ep->pcie;
449 pcie->is_rc = false;
450
451 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "reg");
452 pcie->reg_base = devm_ioremap_resource(dev, res);
453 if (IS_ERR(pcie->reg_base)) {
454 dev_err(dev, "missing \"reg\"\n");
455 return PTR_ERR(pcie->reg_base);
456 }
457
458 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mem");
459 if (!res) {
460 dev_err(dev, "missing \"mem\"\n");
461 return -EINVAL;
462 }
463 pcie->mem_res = res;
464
465 ret = of_property_read_u32(np, "cdns,max-outbound-regions",
466 &ep->max_regions);
467 if (ret < 0) {
468 dev_err(dev, "missing \"cdns,max-outbound-regions\"\n");
469 return ret;
470 }
471 ep->ob_addr = devm_kcalloc(dev,
472 ep->max_regions, sizeof(*ep->ob_addr),
473 GFP_KERNEL);
474 if (!ep->ob_addr)
475 return -ENOMEM;
476
477 ret = cdns_pcie_init_phy(dev, pcie);
478 if (ret) {
479 dev_err(dev, "failed to init phy\n");
480 return ret;
481 }
482 platform_set_drvdata(pdev, pcie);
483 pm_runtime_enable(dev);
484 ret = pm_runtime_get_sync(dev);
485 if (ret < 0) {
486 dev_err(dev, "pm_runtime_get_sync() failed\n");
487 goto err_get_sync;
488 }
489
490 /* Disable all but function 0 (anyway BIT(0) is hardwired to 1). */
491 cdns_pcie_writel(pcie, CDNS_PCIE_LM_EP_FUNC_CFG, BIT(0));
492
493 epc = devm_pci_epc_create(dev, &cdns_pcie_epc_ops);
494 if (IS_ERR(epc)) {
495 dev_err(dev, "failed to create epc device\n");
496 ret = PTR_ERR(epc);
497 goto err_init;
498 }
499
500 epc_set_drvdata(epc, ep);
501
502 if (of_property_read_u8(np, "max-functions", &epc->max_functions) < 0)
503 epc->max_functions = 1;
504
505 ret = pci_epc_mem_init(epc, pcie->mem_res->start,
506 resource_size(pcie->mem_res));
507 if (ret < 0) {
508 dev_err(dev, "failed to initialize the memory space\n");
509 goto err_init;
510 }
511
512 ep->irq_cpu_addr = pci_epc_mem_alloc_addr(epc, &ep->irq_phys_addr,
513 SZ_128K);
514 if (!ep->irq_cpu_addr) {
515 dev_err(dev, "failed to reserve memory space for MSI\n");
516 ret = -ENOMEM;
517 goto free_epc_mem;
518 }
519 ep->irq_pci_addr = CDNS_PCIE_EP_IRQ_PCI_ADDR_NONE;
520
521 return 0;
522
523 free_epc_mem:
524 pci_epc_mem_exit(epc);
525
526 err_init:
527 pm_runtime_put_sync(dev);
528
529 err_get_sync:
530 pm_runtime_disable(dev);
531 cdns_pcie_disable_phy(pcie);
532 phy_count = pcie->phy_count;
533 while (phy_count--)
534 device_link_del(pcie->link[phy_count]);
535
536 return ret;
537 }
538
cdns_pcie_ep_shutdown(struct platform_device * pdev)539 static void cdns_pcie_ep_shutdown(struct platform_device *pdev)
540 {
541 struct device *dev = &pdev->dev;
542 struct cdns_pcie *pcie = dev_get_drvdata(dev);
543 int ret;
544
545 ret = pm_runtime_put_sync(dev);
546 if (ret < 0)
547 dev_dbg(dev, "pm_runtime_put_sync failed\n");
548
549 pm_runtime_disable(dev);
550
551 cdns_pcie_disable_phy(pcie);
552 }
553
554 static struct platform_driver cdns_pcie_ep_driver = {
555 .driver = {
556 .name = "cdns-pcie-ep",
557 .of_match_table = cdns_pcie_ep_of_match,
558 .pm = &cdns_pcie_pm_ops,
559 },
560 .probe = cdns_pcie_ep_probe,
561 .shutdown = cdns_pcie_ep_shutdown,
562 };
563 builtin_platform_driver(cdns_pcie_ep_driver);
564
