1 /******************************************************************************
2 *
3 * Copyright(c) 2009-2012 Realtek Corporation.
4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * The full GNU General Public License is included in this distribution in the
15 * file called LICENSE.
16 *
17 * Contact Information:
18 * wlanfae <wlanfae@realtek.com>
19 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
20 * Hsinchu 300, Taiwan.
21 *
22 * Larry Finger <Larry.Finger@lwfinger.net>
23 *
24 *****************************************************************************/
25
26 #ifndef __RTL92D_PHY_H__
27 #define __RTL92D_PHY_H__
28
29 #define MAX_PRECMD_CNT 16
30 #define MAX_RFDEPENDCMD_CNT 16
31 #define MAX_POSTCMD_CNT 16
32
33 #define MAX_DOZE_WAITING_TIMES_9x 64
34
35 #define RT_CANNOT_IO(hw) false
36 #define HIGHPOWER_RADIOA_ARRAYLEN 22
37
38 #define MAX_TOLERANCE 5
39
40 #define APK_BB_REG_NUM 5
41 #define APK_AFE_REG_NUM 16
42 #define APK_CURVE_REG_NUM 4
43 #define PATH_NUM 2
44
45 #define LOOP_LIMIT 5
46 #define MAX_STALL_TIME 50
47 #define ANTENNA_DIVERSITY_VALUE 0x80
48 #define MAX_TXPWR_IDX_NMODE_92S 63
49 #define RESET_CNT_LIMIT 3
50
51 #define IQK_ADDA_REG_NUM 16
52 #define IQK_BB_REG_NUM 10
53 #define IQK_BB_REG_NUM_test 6
54 #define IQK_MAC_REG_NUM 4
55 #define RX_INDEX_MAPPING_NUM 15
56
57 #define IQK_DELAY_TIME 1
58
59 #define CT_OFFSET_MAC_ADDR 0X16
60
61 #define CT_OFFSET_CCK_TX_PWR_IDX 0x5A
62 #define CT_OFFSET_HT401S_TX_PWR_IDX 0x60
63 #define CT_OFFSET_HT402S_TX_PWR_IDX_DIFF 0x66
64 #define CT_OFFSET_HT20_TX_PWR_IDX_DIFF 0x69
65 #define CT_OFFSET_OFDM_TX_PWR_IDX_DIFF 0x6C
66
67 #define CT_OFFSET_HT40_MAX_PWR_OFFSET 0x6F
68 #define CT_OFFSET_HT20_MAX_PWR_OFFSET 0x72
69
70 #define CT_OFFSET_CHANNEL_PLAH 0x75
71 #define CT_OFFSET_THERMAL_METER 0x78
72 #define CT_OFFSET_RF_OPTION 0x79
73 #define CT_OFFSET_VERSION 0x7E
74 #define CT_OFFSET_CUSTOMER_ID 0x7F
75
76 enum swchnlcmd_id {
77 CMDID_END,
78 CMDID_SET_TXPOWEROWER_LEVEL,
79 CMDID_BBREGWRITE10,
80 CMDID_WRITEPORT_ULONG,
81 CMDID_WRITEPORT_USHORT,
82 CMDID_WRITEPORT_UCHAR,
83 CMDID_RF_WRITEREG,
84 };
85
86 struct swchnlcmd {
87 enum swchnlcmd_id cmdid;
88 u32 para1;
89 u32 para2;
90 u32 msdelay;
91 };
92
93 enum baseband_config_type {
94 BASEBAND_CONFIG_PHY_REG = 0,
95 BASEBAND_CONFIG_AGC_TAB = 1,
96 };
97
98 enum rf_content {
99 radioa_txt = 0,
100 radiob_txt = 1,
101 radioc_txt = 2,
102 radiod_txt = 3
103 };
104
rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw * hw,unsigned long * flag)105 static inline void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
106 unsigned long *flag)
107 {
108 struct rtl_priv *rtlpriv = rtl_priv(hw);
109
110 if (rtlpriv->rtlhal.interfaceindex == 1)
111 spin_lock_irqsave(&rtlpriv->locks.cck_and_rw_pagea_lock, *flag);
112 }
113
rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw * hw,unsigned long * flag)114 static inline void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
115 unsigned long *flag)
116 {
117 struct rtl_priv *rtlpriv = rtl_priv(hw);
118
119 if (rtlpriv->rtlhal.interfaceindex == 1)
120 spin_unlock_irqrestore(&rtlpriv->locks.cck_and_rw_pagea_lock,
121 *flag);
122 }
123
124 u32 rtl92d_phy_query_bb_reg(struct ieee80211_hw *hw,
125 u32 regaddr, u32 bitmask);
126 void rtl92d_phy_set_bb_reg(struct ieee80211_hw *hw,
127 u32 regaddr, u32 bitmask, u32 data);
128 u32 rtl92d_phy_query_rf_reg(struct ieee80211_hw *hw,
129 enum radio_path rfpath, u32 regaddr,
130 u32 bitmask);
131 void rtl92d_phy_set_rf_reg(struct ieee80211_hw *hw,
132 enum radio_path rfpath, u32 regaddr,
133 u32 bitmask, u32 data);
134 bool rtl92d_phy_mac_config(struct ieee80211_hw *hw);
135 bool rtl92d_phy_bb_config(struct ieee80211_hw *hw);
136 bool rtl92d_phy_rf_config(struct ieee80211_hw *hw);
137 bool rtl92c_phy_config_rf_with_feaderfile(struct ieee80211_hw *hw,
138 enum radio_path rfpath);
139 void rtl92d_phy_get_hw_reg_originalvalue(struct ieee80211_hw *hw);
140 void rtl92d_phy_set_txpower_level(struct ieee80211_hw *hw, u8 channel);
141 void rtl92d_phy_set_bw_mode(struct ieee80211_hw *hw,
142 enum nl80211_channel_type ch_type);
143 u8 rtl92d_phy_sw_chnl(struct ieee80211_hw *hw);
144 bool rtl92d_phy_config_rf_with_headerfile(struct ieee80211_hw *hw,
145 enum rf_content content,
146 enum radio_path rfpath);
147 bool rtl92d_phy_set_io_cmd(struct ieee80211_hw *hw, enum io_type iotype);
148 bool rtl92d_phy_set_rf_power_state(struct ieee80211_hw *hw,
149 enum rf_pwrstate rfpwr_state);
150
151 void rtl92d_phy_config_macphymode(struct ieee80211_hw *hw);
152 void rtl92d_phy_config_macphymode_info(struct ieee80211_hw *hw);
153 u8 rtl92d_get_chnlgroup_fromarray(u8 chnl);
154 void rtl92d_phy_set_poweron(struct ieee80211_hw *hw);
155 void rtl92d_phy_config_maccoexist_rfpage(struct ieee80211_hw *hw);
156 bool rtl92d_phy_check_poweroff(struct ieee80211_hw *hw);
157 void rtl92d_phy_lc_calibrate(struct ieee80211_hw *hw);
158 void rtl92d_update_bbrf_configuration(struct ieee80211_hw *hw);
159 void rtl92d_phy_ap_calibrate(struct ieee80211_hw *hw, s8 delta);
160 void rtl92d_phy_iq_calibrate(struct ieee80211_hw *hw);
161 void rtl92d_phy_reset_iqk_result(struct ieee80211_hw *hw);
162 void rtl92d_release_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
163 unsigned long *flag);
164 void rtl92d_acquire_cckandrw_pagea_ctl(struct ieee80211_hw *hw,
165 unsigned long *flag);
166 u8 rtl92d_get_rightchnlplace_for_iqk(u8 chnl);
167 void rtl92d_phy_reload_iqk_setting(struct ieee80211_hw *hw, u8 channel);
168
169 #endif
170
