1 /* 2 * Copyright (c) 2015-2016 Quantenna Communications, Inc. 3 * All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License 7 * as published by the Free Software Foundation; either version 2 8 * of the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 */ 16 17 #ifndef _QTN_FMAC_PCIE_IPC_H_ 18 #define _QTN_FMAC_PCIE_IPC_H_ 19 20 #include <linux/types.h> 21 22 #include "shm_ipc_defs.h" 23 24 /* bitmap for EP status and flags: updated by EP, read by RC */ 25 #define QTN_EP_HAS_UBOOT BIT(0) 26 #define QTN_EP_HAS_FIRMWARE BIT(1) 27 #define QTN_EP_REQ_UBOOT BIT(2) 28 #define QTN_EP_REQ_FIRMWARE BIT(3) 29 #define QTN_EP_ERROR_UBOOT BIT(4) 30 #define QTN_EP_ERROR_FIRMWARE BIT(5) 31 32 #define QTN_EP_FW_LOADRDY BIT(8) 33 #define QTN_EP_FW_SYNC BIT(9) 34 #define QTN_EP_FW_RETRY BIT(10) 35 #define QTN_EP_FW_QLINK_DONE BIT(15) 36 #define QTN_EP_FW_DONE BIT(16) 37 38 /* bitmap for RC status and flags: updated by RC, read by EP */ 39 #define QTN_RC_PCIE_LINK BIT(0) 40 #define QTN_RC_NET_LINK BIT(1) 41 #define QTN_RC_FW_FLASHBOOT BIT(5) 42 #define QTN_RC_FW_QLINK BIT(7) 43 #define QTN_RC_FW_LOADRDY BIT(8) 44 #define QTN_RC_FW_SYNC BIT(9) 45 46 /* state transition timeouts */ 47 #define QTN_FW_DL_TIMEOUT_MS 3000 48 #define QTN_FW_QLINK_TIMEOUT_MS 30000 49 #define QTN_EP_RESET_WAIT_MS 1000 50 51 #define PCIE_HDP_INT_RX_BITS (0 \ 52 | PCIE_HDP_INT_EP_TXDMA \ 53 | PCIE_HDP_INT_EP_TXEMPTY \ 54 | PCIE_HDP_INT_HHBM_UF \ 55 ) 56 57 #define PCIE_HDP_INT_TX_BITS (0 \ 58 | PCIE_HDP_INT_EP_RXDMA \ 59 ) 60 61 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 62 #define QTN_HOST_HI32(a) ((u32)(((u64)a) >> 32)) 63 #define QTN_HOST_LO32(a) ((u32)(((u64)a) & 0xffffffffUL)) 64 #define QTN_HOST_ADDR(h, l) ((((u64)h) << 32) | ((u64)l)) 65 #else 66 #define QTN_HOST_HI32(a) 0 67 #define QTN_HOST_LO32(a) ((u32)(((u32)a) & 0xffffffffUL)) 68 #define QTN_HOST_ADDR(h, l) ((u32)l) 69 #endif 70 71 #define QTN_SYSCTL_BAR 0 72 #define QTN_SHMEM_BAR 2 73 #define QTN_DMA_BAR 3 74 75 #define QTN_PCIE_BDA_VERSION 0x1002 76 77 #define PCIE_BDA_NAMELEN 32 78 #define PCIE_HHBM_MAX_SIZE 2048 79 80 #define SKB_BUF_SIZE 2048 81 82 #define QTN_PCIE_BOARDFLG "PCIEQTN" 83 #define QTN_PCIE_FW_DLMASK 0xF 84 #define QTN_PCIE_FW_BUFSZ 2048 85 86 #define QTN_ENET_ADDR_LENGTH 6 87 88 #define QTN_TXDONE_MASK ((u32)0x80000000) 89 #define QTN_GET_LEN(x) ((x) & 0xFFFF) 90 91 #define QTN_PCIE_TX_DESC_LEN_MASK 0xFFFF 92 #define QTN_PCIE_TX_DESC_LEN_SHIFT 0 93 #define QTN_PCIE_TX_DESC_PORT_MASK 0xF 94 #define QTN_PCIE_TX_DESC_PORT_SHIFT 16 95 #define QTN_PCIE_TX_DESC_TQE_BIT BIT(24) 96 97 #define QTN_EP_LHOST_TQE_PORT 4 98 99 enum qtnf_pcie_bda_ipc_flags { 100 QTN_PCIE_IPC_FLAG_HBM_MAGIC = BIT(0), 101 QTN_PCIE_IPC_FLAG_SHM_PIO = BIT(1), 102 }; 103 104 struct qtnf_pcie_bda { 105 __le16 bda_len; 106 __le16 bda_version; 107 __le32 bda_pci_endian; 108 __le32 bda_ep_state; 109 __le32 bda_rc_state; 110 __le32 bda_dma_mask; 111 __le32 bda_msi_addr; 112 __le32 bda_flashsz; 113 u8 bda_boardname[PCIE_BDA_NAMELEN]; 114 __le32 bda_rc_msi_enabled; 115 u8 bda_hhbm_list[PCIE_HHBM_MAX_SIZE]; 116 __le32 bda_dsbw_start_index; 117 __le32 bda_dsbw_end_index; 118 __le32 bda_dsbw_total_bytes; 119 __le32 bda_rc_tx_bd_base; 120 __le32 bda_rc_tx_bd_num; 121 u8 bda_pcie_mac[QTN_ENET_ADDR_LENGTH]; 122 struct qtnf_shm_ipc_region bda_shm_reg1 __aligned(4096); /* host TX */ 123 struct qtnf_shm_ipc_region bda_shm_reg2 __aligned(4096); /* host RX */ 124 } __packed; 125 126 struct qtnf_tx_bd { 127 __le32 addr; 128 __le32 addr_h; 129 __le32 info; 130 __le32 info_h; 131 } __packed; 132 133 struct qtnf_rx_bd { 134 __le32 addr; 135 __le32 addr_h; 136 __le32 info; 137 __le32 info_h; 138 __le32 next_ptr; 139 __le32 next_ptr_h; 140 } __packed; 141 142 enum qtnf_fw_loadtype { 143 QTN_FW_DBEGIN, 144 QTN_FW_DSUB, 145 QTN_FW_DEND, 146 QTN_FW_CTRL 147 }; 148 149 struct qtnf_pcie_fw_hdr { 150 u8 boardflg[8]; 151 __le32 fwsize; 152 __le32 seqnum; 153 __le32 type; 154 __le32 pktlen; 155 __le32 crc; 156 } __packed; 157 158 #endif /* _QTN_FMAC_PCIE_IPC_H_ */ 159
