1 /*
2  * Copyright (C) 2014 Felix Fietkau <nbd@openwrt.org>
3  * Copyright (C) 2015 Jakub Kicinski <kubakici@wp.pl>
4  * Copyright (C) 2018 Stanislaw Gruszka <stf_xl@wp.pl>
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2
8  * as published by the Free Software Foundation
9  *
10  * This program is distributed in the hope that it will be useful,
11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
13  * GNU General Public License for more details.
14  */
15 
16 #include <linux/of.h>
17 #include <linux/mtd/mtd.h>
18 #include <linux/mtd/partitions.h>
19 #include <linux/etherdevice.h>
20 #include <asm/unaligned.h>
21 #include "mt76x0.h"
22 #include "eeprom.h"
23 
24 static bool
field_valid(u8 val)25 field_valid(u8 val)
26 {
27 	return val != 0xff;
28 }
29 
30 static s8
field_validate(u8 val)31 field_validate(u8 val)
32 {
33 	if (!field_valid(val))
34 		return 0;
35 
36 	return val;
37 }
38 
39 static inline int
sign_extend(u32 val,unsigned int size)40 sign_extend(u32 val, unsigned int size)
41 {
42 	bool sign = val & BIT(size - 1);
43 
44 	val &= BIT(size - 1) - 1;
45 
46 	return sign ? val : -val;
47 }
48 
49 static int
mt76x0_efuse_read(struct mt76x0_dev * dev,u16 addr,u8 * data,enum mt76x0_eeprom_access_modes mode)50 mt76x0_efuse_read(struct mt76x0_dev *dev, u16 addr, u8 *data,
51 		   enum mt76x0_eeprom_access_modes mode)
52 {
53 	u32 val;
54 	int i;
55 
56 	val = mt76_rr(dev, MT_EFUSE_CTRL);
57 	val &= ~(MT_EFUSE_CTRL_AIN |
58 		 MT_EFUSE_CTRL_MODE);
59 	val |= FIELD_PREP(MT_EFUSE_CTRL_AIN, addr & ~0xf) |
60 	       FIELD_PREP(MT_EFUSE_CTRL_MODE, mode) |
61 	       MT_EFUSE_CTRL_KICK;
62 	mt76_wr(dev, MT_EFUSE_CTRL, val);
63 
64 	if (!mt76_poll(dev, MT_EFUSE_CTRL, MT_EFUSE_CTRL_KICK, 0, 1000))
65 		return -ETIMEDOUT;
66 
67 	val = mt76_rr(dev, MT_EFUSE_CTRL);
68 	if ((val & MT_EFUSE_CTRL_AOUT) == MT_EFUSE_CTRL_AOUT) {
69 		/* Parts of eeprom not in the usage map (0x80-0xc0,0xf0)
70 		 * will not return valid data but it's ok.
71 		 */
72 		memset(data, 0xff, 16);
73 		return 0;
74 	}
75 
76 	for (i = 0; i < 4; i++) {
77 		val = mt76_rr(dev, MT_EFUSE_DATA(i));
78 		put_unaligned_le32(val, data + 4 * i);
79 	}
80 
81 	return 0;
82 }
83 
84 #define MT_MAP_READS	DIV_ROUND_UP(MT_EFUSE_USAGE_MAP_SIZE, 16)
85 static int
mt76x0_efuse_physical_size_check(struct mt76x0_dev * dev)86 mt76x0_efuse_physical_size_check(struct mt76x0_dev *dev)
87 {
88 	u8 data[MT_MAP_READS * 16];
89 	int ret, i;
90 	u32 start = 0, end = 0, cnt_free;
91 
92 	for (i = 0; i < MT_MAP_READS; i++) {
93 		ret = mt76x0_efuse_read(dev, MT_EE_USAGE_MAP_START + i * 16,
94 					 data + i * 16, MT_EE_PHYSICAL_READ);
95 		if (ret)
96 			return ret;
97 	}
98 
99 	for (i = 0; i < MT_EFUSE_USAGE_MAP_SIZE; i++)
100 		if (!data[i]) {
101 			if (!start)
102 				start = MT_EE_USAGE_MAP_START + i;
103 			end = MT_EE_USAGE_MAP_START + i;
104 		}
105 	cnt_free = end - start + 1;
106 
107 	if (MT_EFUSE_USAGE_MAP_SIZE - cnt_free < 5) {
108 		dev_err(dev->mt76.dev, "Error: your device needs default EEPROM file and this driver doesn't support it!\n");
109 		return -EINVAL;
110 	}
111 
112 	return 0;
113 }
114 
115 static void
mt76x0_set_chip_cap(struct mt76x0_dev * dev,u8 * eeprom)116 mt76x0_set_chip_cap(struct mt76x0_dev *dev, u8 *eeprom)
117 {
118 	enum mt76x2_board_type { BOARD_TYPE_2GHZ = 1, BOARD_TYPE_5GHZ = 2 };
119 	u16 nic_conf0 = get_unaligned_le16(eeprom + MT_EE_NIC_CONF_0);
120 	u16 nic_conf1 = get_unaligned_le16(eeprom + MT_EE_NIC_CONF_1);
121 
122 	dev_dbg(dev->mt76.dev, "NIC_CONF0: %04x NIC_CONF1: %04x\n", nic_conf0, nic_conf1);
123 
124 	switch (FIELD_GET(MT_EE_NIC_CONF_0_BOARD_TYPE, nic_conf0)) {
125 	case BOARD_TYPE_5GHZ:
126 		dev->ee->has_5ghz = true;
127 		break;
128 	case BOARD_TYPE_2GHZ:
129 		dev->ee->has_2ghz = true;
130 		break;
131 	default:
132 		dev->ee->has_2ghz = true;
133 		dev->ee->has_5ghz = true;
134 		break;
135 	}
136 
137 	dev_dbg(dev->mt76.dev, "Has 2GHZ %d 5GHZ %d\n", dev->ee->has_2ghz, dev->ee->has_5ghz);
138 
139 	if (!field_valid(nic_conf1 & 0xff))
140 		nic_conf1 &= 0xff00;
141 
142 	if (nic_conf1 & MT_EE_NIC_CONF_1_HW_RF_CTRL)
143 		dev_err(dev->mt76.dev,
144 			"Error: this driver does not support HW RF ctrl\n");
145 
146 	if (!field_valid(nic_conf0 >> 8))
147 		return;
148 
149 	if (FIELD_GET(MT_EE_NIC_CONF_0_RX_PATH, nic_conf0) > 1 ||
150 	    FIELD_GET(MT_EE_NIC_CONF_0_TX_PATH, nic_conf0) > 1)
151 		dev_err(dev->mt76.dev,
152 			"Error: device has more than 1 RX/TX stream!\n");
153 
154 	dev->ee->pa_type = FIELD_GET(MT_EE_NIC_CONF_0_PA_TYPE, nic_conf0);
155 	dev_dbg(dev->mt76.dev, "PA Type %d\n", dev->ee->pa_type);
156 }
157 
158 static int
mt76x0_set_macaddr(struct mt76x0_dev * dev,const u8 * eeprom)159 mt76x0_set_macaddr(struct mt76x0_dev *dev, const u8 *eeprom)
160 {
161 	const void *src = eeprom + MT_EE_MAC_ADDR;
162 
163 	ether_addr_copy(dev->macaddr, src);
164 
165 	if (!is_valid_ether_addr(dev->macaddr)) {
166 		eth_random_addr(dev->macaddr);
167 		dev_info(dev->mt76.dev,
168 			 "Invalid MAC address, using random address %pM\n",
169 			 dev->macaddr);
170 	}
171 
172 	mt76_wr(dev, MT_MAC_ADDR_DW0, get_unaligned_le32(dev->macaddr));
173 	mt76_wr(dev, MT_MAC_ADDR_DW1, get_unaligned_le16(dev->macaddr + 4) |
174 		FIELD_PREP(MT_MAC_ADDR_DW1_U2ME_MASK, 0xff));
175 
176 	return 0;
177 }
178 
179 static void
mt76x0_set_temp_offset(struct mt76x0_dev * dev,u8 * eeprom)180 mt76x0_set_temp_offset(struct mt76x0_dev *dev, u8 *eeprom)
181 {
182 	u8 temp = eeprom[MT_EE_TEMP_OFFSET];
183 
184 	if (field_valid(temp))
185 		dev->ee->temp_off = sign_extend(temp, 8);
186 	else
187 		dev->ee->temp_off = -10;
188 }
189 
190 static void
mt76x0_set_country_reg(struct mt76x0_dev * dev,u8 * eeprom)191 mt76x0_set_country_reg(struct mt76x0_dev *dev, u8 *eeprom)
192 {
193 	/* Note: - region 31 is not valid for mt76x0 (see rtmp_init.c)
194 	 *	 - comments in rtmp_def.h are incorrect (see rt_channel.c)
195 	 */
196 	static const struct reg_channel_bounds chan_bounds[] = {
197 		/* EEPROM country regions 0 - 7 */
198 		{  1, 11 },	{  1, 13 },	{ 10,  2 },	{ 10,  4 },
199 		{ 14,  1 },	{  1, 14 },	{  3,  7 },	{  5,  9 },
200 		/* EEPROM country regions 32 - 33 */
201 		{  1, 11 },	{  1, 14 }
202 	};
203 	u8 val = eeprom[MT_EE_COUNTRY_REGION_2GHZ];
204 	int idx = -1;
205 
206 	dev_dbg(dev->mt76.dev, "REG 2GHZ %u REG 5GHZ %u\n", val, eeprom[MT_EE_COUNTRY_REGION_5GHZ]);
207 	if (val < 8)
208 		idx = val;
209 	if (val > 31 && val < 33)
210 		idx = val - 32 + 8;
211 
212 	if (idx != -1)
213 		dev_info(dev->mt76.dev,
214 			 "EEPROM country region %02hhx (channels %hhd-%hhd)\n",
215 			 val, chan_bounds[idx].start,
216 			 chan_bounds[idx].start + chan_bounds[idx].num - 1);
217 	else
218 		idx = 5; /* channels 1 - 14 */
219 
220 	dev->ee->reg = chan_bounds[idx];
221 
222 	/* TODO: country region 33 is special - phy should be set to B-mode
223 	 *	 before entering channel 14 (see sta/connect.c)
224 	 */
225 }
226 
227 static void
mt76x0_set_rf_freq_off(struct mt76x0_dev * dev,u8 * eeprom)228 mt76x0_set_rf_freq_off(struct mt76x0_dev *dev, u8 *eeprom)
229 {
230 	u8 comp;
231 
232 	dev->ee->rf_freq_off = field_validate(eeprom[MT_EE_FREQ_OFFSET]);
233 	comp = field_validate(eeprom[MT_EE_FREQ_OFFSET_COMPENSATION]);
234 
235 	if (comp & BIT(7))
236 		dev->ee->rf_freq_off -= comp & 0x7f;
237 	else
238 		dev->ee->rf_freq_off += comp;
239 }
240 
241 static void
mt76x0_set_lna_gain(struct mt76x0_dev * dev,u8 * eeprom)242 mt76x0_set_lna_gain(struct mt76x0_dev *dev, u8 *eeprom)
243 {
244 	u8 gain;
245 
246 	dev->ee->lna_gain_2ghz = eeprom[MT_EE_LNA_GAIN_2GHZ];
247 	dev->ee->lna_gain_5ghz[0] = eeprom[MT_EE_LNA_GAIN_5GHZ_0];
248 
249 	gain = eeprom[MT_EE_LNA_GAIN_5GHZ_1];
250 	if (gain == 0xff || gain == 0)
251 		dev->ee->lna_gain_5ghz[1] = dev->ee->lna_gain_5ghz[0];
252 	else
253 		dev->ee->lna_gain_5ghz[1] = gain;
254 
255 	gain = eeprom[MT_EE_LNA_GAIN_5GHZ_2];
256 	if (gain == 0xff || gain == 0)
257 		dev->ee->lna_gain_5ghz[2] = dev->ee->lna_gain_5ghz[0];
258 	else
259 		dev->ee->lna_gain_5ghz[2] = gain;
260 }
261 
262 static void
mt76x0_set_rssi_offset(struct mt76x0_dev * dev,u8 * eeprom)263 mt76x0_set_rssi_offset(struct mt76x0_dev *dev, u8 *eeprom)
264 {
265 	int i;
266 	s8 *rssi_offset = dev->ee->rssi_offset_2ghz;
267 
268 	for (i = 0; i < 2; i++) {
269 		rssi_offset[i] = eeprom[MT_EE_RSSI_OFFSET + i];
270 
271 		if (rssi_offset[i] < -10 || rssi_offset[i] > 10) {
272 			dev_warn(dev->mt76.dev,
273 				 "Warning: EEPROM RSSI is invalid %02hhx\n",
274 				 rssi_offset[i]);
275 			rssi_offset[i] = 0;
276 		}
277 	}
278 
279 	rssi_offset = dev->ee->rssi_offset_5ghz;
280 
281 	for (i = 0; i < 3; i++) {
282 		rssi_offset[i] = eeprom[MT_EE_RSSI_OFFSET_5GHZ + i];
283 
284 		if (rssi_offset[i] < -10 || rssi_offset[i] > 10) {
285 			dev_warn(dev->mt76.dev,
286 				 "Warning: EEPROM RSSI is invalid %02hhx\n",
287 				 rssi_offset[i]);
288 			rssi_offset[i] = 0;
289 		}
290 	}
291 }
292 
293 static u32
calc_bw40_power_rate(u32 value,int delta)294 calc_bw40_power_rate(u32 value, int delta)
295 {
296 	u32 ret = 0;
297 	int i, tmp;
298 
299 	for (i = 0; i < 4; i++) {
300 		tmp = s6_to_int((value >> i*8) & 0xff) + delta;
301 		ret |= (u32)(int_to_s6(tmp)) << i*8;
302 	}
303 
304 	return ret;
305 }
306 
307 static s8
get_delta(u8 val)308 get_delta(u8 val)
309 {
310 	s8 ret;
311 
312 	if (!field_valid(val) || !(val & BIT(7)))
313 		return 0;
314 
315 	ret = val & 0x1f;
316 	if (ret > 8)
317 		ret = 8;
318 	if (val & BIT(6))
319 		ret = -ret;
320 
321 	return ret;
322 }
323 
324 static void
mt76x0_set_tx_power_per_rate(struct mt76x0_dev * dev,u8 * eeprom)325 mt76x0_set_tx_power_per_rate(struct mt76x0_dev *dev, u8 *eeprom)
326 {
327 	s8 bw40_delta_2g, bw40_delta_5g;
328 	u32 val;
329 	int i;
330 
331 	bw40_delta_2g = get_delta(eeprom[MT_EE_TX_POWER_DELTA_BW40]);
332 	bw40_delta_5g = get_delta(eeprom[MT_EE_TX_POWER_DELTA_BW40 + 1]);
333 
334 	for (i = 0; i < 5; i++) {
335 		val = get_unaligned_le32(eeprom + MT_EE_TX_POWER_BYRATE(i));
336 
337 		/* Skip last 16 bits. */
338 		if (i == 4)
339 			val &= 0x0000ffff;
340 
341 		dev->ee->tx_pwr_cfg_2g[i][0] = val;
342 		dev->ee->tx_pwr_cfg_2g[i][1] = calc_bw40_power_rate(val, bw40_delta_2g);
343 	}
344 
345 	/* Reading per rate tx power for 5 GHz band is a bit more complex. Note
346 	 * we mix 16 bit and 32 bit reads and sometimes do shifts.
347 	 */
348 	val = get_unaligned_le16(eeprom + 0x120);
349 	val <<= 16;
350 	dev->ee->tx_pwr_cfg_5g[0][0] = val;
351 	dev->ee->tx_pwr_cfg_5g[0][1] = calc_bw40_power_rate(val, bw40_delta_5g);
352 
353 	val = get_unaligned_le32(eeprom + 0x122);
354 	dev->ee->tx_pwr_cfg_5g[1][0] = val;
355 	dev->ee->tx_pwr_cfg_5g[1][1] = calc_bw40_power_rate(val, bw40_delta_5g);
356 
357 	val = get_unaligned_le16(eeprom + 0x126);
358 	dev->ee->tx_pwr_cfg_5g[2][0] = val;
359 	dev->ee->tx_pwr_cfg_5g[2][1] = calc_bw40_power_rate(val, bw40_delta_5g);
360 
361 	val = get_unaligned_le16(eeprom + 0xec);
362 	val <<= 16;
363 	dev->ee->tx_pwr_cfg_5g[3][0] = val;
364 	dev->ee->tx_pwr_cfg_5g[3][1] = calc_bw40_power_rate(val, bw40_delta_5g);
365 
366 	val = get_unaligned_le16(eeprom + 0xee);
367 	dev->ee->tx_pwr_cfg_5g[4][0] = val;
368 	dev->ee->tx_pwr_cfg_5g[4][1] = calc_bw40_power_rate(val, bw40_delta_5g);
369 }
370 
371 static void
mt76x0_set_tx_power_per_chan(struct mt76x0_dev * dev,u8 * eeprom)372 mt76x0_set_tx_power_per_chan(struct mt76x0_dev *dev, u8 *eeprom)
373 {
374 	int i;
375 	u8 tx_pwr;
376 
377 	for (i = 0; i < 14; i++) {
378 		tx_pwr = eeprom[MT_EE_TX_POWER_OFFSET_2GHZ + i];
379 		if (tx_pwr <= 0x3f && tx_pwr > 0)
380 			dev->ee->tx_pwr_per_chan[i] = tx_pwr;
381 		else
382 			dev->ee->tx_pwr_per_chan[i] = 5;
383 	}
384 
385 	for (i = 0; i < 40; i++) {
386 		tx_pwr = eeprom[MT_EE_TX_POWER_OFFSET_5GHZ + i];
387 		if (tx_pwr <= 0x3f && tx_pwr > 0)
388 			dev->ee->tx_pwr_per_chan[14 + i] = tx_pwr;
389 		else
390 			dev->ee->tx_pwr_per_chan[14 + i] = 5;
391 	}
392 
393 	dev->ee->tx_pwr_per_chan[54] = dev->ee->tx_pwr_per_chan[22];
394 	dev->ee->tx_pwr_per_chan[55] = dev->ee->tx_pwr_per_chan[28];
395 	dev->ee->tx_pwr_per_chan[56] = dev->ee->tx_pwr_per_chan[34];
396 	dev->ee->tx_pwr_per_chan[57] = dev->ee->tx_pwr_per_chan[44];
397 }
398 
399 int
mt76x0_eeprom_init(struct mt76x0_dev * dev)400 mt76x0_eeprom_init(struct mt76x0_dev *dev)
401 {
402 	u8 *eeprom;
403 	int i, ret;
404 
405 	ret = mt76x0_efuse_physical_size_check(dev);
406 	if (ret)
407 		return ret;
408 
409 	dev->ee = devm_kzalloc(dev->mt76.dev, sizeof(*dev->ee), GFP_KERNEL);
410 	if (!dev->ee)
411 		return -ENOMEM;
412 
413 	eeprom = kmalloc(MT76X0_EEPROM_SIZE, GFP_KERNEL);
414 	if (!eeprom)
415 		return -ENOMEM;
416 
417 	for (i = 0; i + 16 <= MT76X0_EEPROM_SIZE; i += 16) {
418 		ret = mt76x0_efuse_read(dev, i, eeprom + i, MT_EE_READ);
419 		if (ret)
420 			goto out;
421 	}
422 
423 	if (eeprom[MT_EE_VERSION_EE] > MT76X0U_EE_MAX_VER)
424 		dev_warn(dev->mt76.dev,
425 			 "Warning: unsupported EEPROM version %02hhx\n",
426 			 eeprom[MT_EE_VERSION_EE]);
427 	dev_info(dev->mt76.dev, "EEPROM ver:%02hhx fae:%02hhx\n",
428 		 eeprom[MT_EE_VERSION_EE], eeprom[MT_EE_VERSION_FAE]);
429 
430 	mt76x0_set_macaddr(dev, eeprom);
431 	mt76x0_set_chip_cap(dev, eeprom);
432 	mt76x0_set_country_reg(dev, eeprom);
433 	mt76x0_set_rf_freq_off(dev, eeprom);
434 	mt76x0_set_temp_offset(dev, eeprom);
435 	mt76x0_set_lna_gain(dev, eeprom);
436 	mt76x0_set_rssi_offset(dev, eeprom);
437 	dev->chainmask = 0x0101;
438 
439 	mt76x0_set_tx_power_per_rate(dev, eeprom);
440 	mt76x0_set_tx_power_per_chan(dev, eeprom);
441 
442 out:
443 	kfree(eeprom);
444 	return ret;
445 }
446