1 /*
2 * Copyright (c) 2012-2017 Qualcomm Atheros, Inc.
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18 #include <linux/etherdevice.h>
19 #include <net/ieee80211_radiotap.h>
20 #include <linux/if_arp.h>
21 #include <linux/moduleparam.h>
22 #include <linux/ip.h>
23 #include <linux/ipv6.h>
24 #include <net/ipv6.h>
25 #include <linux/prefetch.h>
26
27 #include "wil6210.h"
28 #include "wmi.h"
29 #include "txrx.h"
30 #include "trace.h"
31 #include "txrx_edma.h"
32
33 static bool rtap_include_phy_info;
34 module_param(rtap_include_phy_info, bool, 0444);
35 MODULE_PARM_DESC(rtap_include_phy_info,
36 " Include PHY info in the radiotap header, default - no");
37
38 bool rx_align_2;
39 module_param(rx_align_2, bool, 0444);
40 MODULE_PARM_DESC(rx_align_2, " align Rx buffers on 4*n+2, default - no");
41
42 bool rx_large_buf;
43 module_param(rx_large_buf, bool, 0444);
44 MODULE_PARM_DESC(rx_large_buf, " allocate 8KB RX buffers, default - no");
45
wil_rx_snaplen(void)46 static inline uint wil_rx_snaplen(void)
47 {
48 return rx_align_2 ? 6 : 0;
49 }
50
51 /* wil_ring_wmark_low - low watermark for available descriptor space */
wil_ring_wmark_low(struct wil_ring * ring)52 static inline int wil_ring_wmark_low(struct wil_ring *ring)
53 {
54 return ring->size / 8;
55 }
56
57 /* wil_ring_wmark_high - high watermark for available descriptor space */
wil_ring_wmark_high(struct wil_ring * ring)58 static inline int wil_ring_wmark_high(struct wil_ring *ring)
59 {
60 return ring->size / 4;
61 }
62
63 /* returns true if num avail descriptors is lower than wmark_low */
wil_ring_avail_low(struct wil_ring * ring)64 static inline int wil_ring_avail_low(struct wil_ring *ring)
65 {
66 return wil_ring_avail_tx(ring) < wil_ring_wmark_low(ring);
67 }
68
69 /* returns true if num avail descriptors is higher than wmark_high */
wil_ring_avail_high(struct wil_ring * ring)70 static inline int wil_ring_avail_high(struct wil_ring *ring)
71 {
72 return wil_ring_avail_tx(ring) > wil_ring_wmark_high(ring);
73 }
74
75 /* returns true when all tx vrings are empty */
wil_is_tx_idle(struct wil6210_priv * wil)76 bool wil_is_tx_idle(struct wil6210_priv *wil)
77 {
78 int i;
79 unsigned long data_comp_to;
80
81 for (i = 0; i < WIL6210_MAX_TX_RINGS; i++) {
82 struct wil_ring *vring = &wil->ring_tx[i];
83 int vring_index = vring - wil->ring_tx;
84 struct wil_ring_tx_data *txdata =
85 &wil->ring_tx_data[vring_index];
86
87 spin_lock(&txdata->lock);
88
89 if (!vring->va || !txdata->enabled) {
90 spin_unlock(&txdata->lock);
91 continue;
92 }
93
94 data_comp_to = jiffies + msecs_to_jiffies(
95 WIL_DATA_COMPLETION_TO_MS);
96 if (test_bit(wil_status_napi_en, wil->status)) {
97 while (!wil_ring_is_empty(vring)) {
98 if (time_after(jiffies, data_comp_to)) {
99 wil_dbg_pm(wil,
100 "TO waiting for idle tx\n");
101 spin_unlock(&txdata->lock);
102 return false;
103 }
104 wil_dbg_ratelimited(wil,
105 "tx vring is not empty -> NAPI\n");
106 spin_unlock(&txdata->lock);
107 napi_synchronize(&wil->napi_tx);
108 msleep(20);
109 spin_lock(&txdata->lock);
110 if (!vring->va || !txdata->enabled)
111 break;
112 }
113 }
114
115 spin_unlock(&txdata->lock);
116 }
117
118 return true;
119 }
120
wil_vring_alloc(struct wil6210_priv * wil,struct wil_ring * vring)121 static int wil_vring_alloc(struct wil6210_priv *wil, struct wil_ring *vring)
122 {
123 struct device *dev = wil_to_dev(wil);
124 size_t sz = vring->size * sizeof(vring->va[0]);
125 uint i;
126
127 wil_dbg_misc(wil, "vring_alloc:\n");
128
129 BUILD_BUG_ON(sizeof(vring->va[0]) != 32);
130
131 vring->swhead = 0;
132 vring->swtail = 0;
133 vring->ctx = kcalloc(vring->size, sizeof(vring->ctx[0]), GFP_KERNEL);
134 if (!vring->ctx) {
135 vring->va = NULL;
136 return -ENOMEM;
137 }
138
139 /* vring->va should be aligned on its size rounded up to power of 2
140 * This is granted by the dma_alloc_coherent.
141 *
142 * HW has limitation that all vrings addresses must share the same
143 * upper 16 msb bits part of 48 bits address. To workaround that,
144 * if we are using more than 32 bit addresses switch to 32 bit
145 * allocation before allocating vring memory.
146 *
147 * There's no check for the return value of dma_set_mask_and_coherent,
148 * since we assume if we were able to set the mask during
149 * initialization in this system it will not fail if we set it again
150 */
151 if (wil->dma_addr_size > 32)
152 dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
153
154 vring->va = dma_alloc_coherent(dev, sz, &vring->pa, GFP_KERNEL);
155 if (!vring->va) {
156 kfree(vring->ctx);
157 vring->ctx = NULL;
158 return -ENOMEM;
159 }
160
161 if (wil->dma_addr_size > 32)
162 dma_set_mask_and_coherent(dev,
163 DMA_BIT_MASK(wil->dma_addr_size));
164
165 /* initially, all descriptors are SW owned
166 * For Tx and Rx, ownership bit is at the same location, thus
167 * we can use any
168 */
169 for (i = 0; i < vring->size; i++) {
170 volatile struct vring_tx_desc *_d =
171 &vring->va[i].tx.legacy;
172
173 _d->dma.status = TX_DMA_STATUS_DU;
174 }
175
176 wil_dbg_misc(wil, "vring[%d] 0x%p:%pad 0x%p\n", vring->size,
177 vring->va, &vring->pa, vring->ctx);
178
179 return 0;
180 }
181
wil_txdesc_unmap(struct device * dev,union wil_tx_desc * desc,struct wil_ctx * ctx)182 static void wil_txdesc_unmap(struct device *dev, union wil_tx_desc *desc,
183 struct wil_ctx *ctx)
184 {
185 struct vring_tx_desc *d = &desc->legacy;
186 dma_addr_t pa = wil_desc_addr(&d->dma.addr);
187 u16 dmalen = le16_to_cpu(d->dma.length);
188
189 switch (ctx->mapped_as) {
190 case wil_mapped_as_single:
191 dma_unmap_single(dev, pa, dmalen, DMA_TO_DEVICE);
192 break;
193 case wil_mapped_as_page:
194 dma_unmap_page(dev, pa, dmalen, DMA_TO_DEVICE);
195 break;
196 default:
197 break;
198 }
199 }
200
wil_vring_free(struct wil6210_priv * wil,struct wil_ring * vring)201 static void wil_vring_free(struct wil6210_priv *wil, struct wil_ring *vring)
202 {
203 struct device *dev = wil_to_dev(wil);
204 size_t sz = vring->size * sizeof(vring->va[0]);
205
206 lockdep_assert_held(&wil->mutex);
207 if (!vring->is_rx) {
208 int vring_index = vring - wil->ring_tx;
209
210 wil_dbg_misc(wil, "free Tx vring %d [%d] 0x%p:%pad 0x%p\n",
211 vring_index, vring->size, vring->va,
212 &vring->pa, vring->ctx);
213 } else {
214 wil_dbg_misc(wil, "free Rx vring [%d] 0x%p:%pad 0x%p\n",
215 vring->size, vring->va,
216 &vring->pa, vring->ctx);
217 }
218
219 while (!wil_ring_is_empty(vring)) {
220 dma_addr_t pa;
221 u16 dmalen;
222 struct wil_ctx *ctx;
223
224 if (!vring->is_rx) {
225 struct vring_tx_desc dd, *d = ⅆ
226 volatile struct vring_tx_desc *_d =
227 &vring->va[vring->swtail].tx.legacy;
228
229 ctx = &vring->ctx[vring->swtail];
230 if (!ctx) {
231 wil_dbg_txrx(wil,
232 "ctx(%d) was already completed\n",
233 vring->swtail);
234 vring->swtail = wil_ring_next_tail(vring);
235 continue;
236 }
237 *d = *_d;
238 wil_txdesc_unmap(dev, (union wil_tx_desc *)d, ctx);
239 if (ctx->skb)
240 dev_kfree_skb_any(ctx->skb);
241 vring->swtail = wil_ring_next_tail(vring);
242 } else { /* rx */
243 struct vring_rx_desc dd, *d = ⅆ
244 volatile struct vring_rx_desc *_d =
245 &vring->va[vring->swhead].rx.legacy;
246
247 ctx = &vring->ctx[vring->swhead];
248 *d = *_d;
249 pa = wil_desc_addr(&d->dma.addr);
250 dmalen = le16_to_cpu(d->dma.length);
251 dma_unmap_single(dev, pa, dmalen, DMA_FROM_DEVICE);
252 kfree_skb(ctx->skb);
253 wil_ring_advance_head(vring, 1);
254 }
255 }
256 dma_free_coherent(dev, sz, (void *)vring->va, vring->pa);
257 kfree(vring->ctx);
258 vring->pa = 0;
259 vring->va = NULL;
260 vring->ctx = NULL;
261 }
262
263 /**
264 * Allocate one skb for Rx VRING
265 *
266 * Safe to call from IRQ
267 */
wil_vring_alloc_skb(struct wil6210_priv * wil,struct wil_ring * vring,u32 i,int headroom)268 static int wil_vring_alloc_skb(struct wil6210_priv *wil, struct wil_ring *vring,
269 u32 i, int headroom)
270 {
271 struct device *dev = wil_to_dev(wil);
272 unsigned int sz = wil->rx_buf_len + ETH_HLEN + wil_rx_snaplen();
273 struct vring_rx_desc dd, *d = ⅆ
274 volatile struct vring_rx_desc *_d = &vring->va[i].rx.legacy;
275 dma_addr_t pa;
276 struct sk_buff *skb = dev_alloc_skb(sz + headroom);
277
278 if (unlikely(!skb))
279 return -ENOMEM;
280
281 skb_reserve(skb, headroom);
282 skb_put(skb, sz);
283
284 /**
285 * Make sure that the network stack calculates checksum for packets
286 * which failed the HW checksum calculation
287 */
288 skb->ip_summed = CHECKSUM_NONE;
289
290 pa = dma_map_single(dev, skb->data, skb->len, DMA_FROM_DEVICE);
291 if (unlikely(dma_mapping_error(dev, pa))) {
292 kfree_skb(skb);
293 return -ENOMEM;
294 }
295
296 d->dma.d0 = RX_DMA_D0_CMD_DMA_RT | RX_DMA_D0_CMD_DMA_IT;
297 wil_desc_addr_set(&d->dma.addr, pa);
298 /* ip_length don't care */
299 /* b11 don't care */
300 /* error don't care */
301 d->dma.status = 0; /* BIT(0) should be 0 for HW_OWNED */
302 d->dma.length = cpu_to_le16(sz);
303 *_d = *d;
304 vring->ctx[i].skb = skb;
305
306 return 0;
307 }
308
309 /**
310 * Adds radiotap header
311 *
312 * Any error indicated as "Bad FCS"
313 *
314 * Vendor data for 04:ce:14-1 (Wilocity-1) consists of:
315 * - Rx descriptor: 32 bytes
316 * - Phy info
317 */
wil_rx_add_radiotap_header(struct wil6210_priv * wil,struct sk_buff * skb)318 static void wil_rx_add_radiotap_header(struct wil6210_priv *wil,
319 struct sk_buff *skb)
320 {
321 struct wil6210_rtap {
322 struct ieee80211_radiotap_header rthdr;
323 /* fields should be in the order of bits in rthdr.it_present */
324 /* flags */
325 u8 flags;
326 /* channel */
327 __le16 chnl_freq __aligned(2);
328 __le16 chnl_flags;
329 /* MCS */
330 u8 mcs_present;
331 u8 mcs_flags;
332 u8 mcs_index;
333 } __packed;
334 struct wil6210_rtap_vendor {
335 struct wil6210_rtap rtap;
336 /* vendor */
337 u8 vendor_oui[3] __aligned(2);
338 u8 vendor_ns;
339 __le16 vendor_skip;
340 u8 vendor_data[0];
341 } __packed;
342 struct vring_rx_desc *d = wil_skb_rxdesc(skb);
343 struct wil6210_rtap_vendor *rtap_vendor;
344 int rtap_len = sizeof(struct wil6210_rtap);
345 int phy_length = 0; /* phy info header size, bytes */
346 static char phy_data[128];
347 struct ieee80211_channel *ch = wil->monitor_chandef.chan;
348
349 if (rtap_include_phy_info) {
350 rtap_len = sizeof(*rtap_vendor) + sizeof(*d);
351 /* calculate additional length */
352 if (d->dma.status & RX_DMA_STATUS_PHY_INFO) {
353 /**
354 * PHY info starts from 8-byte boundary
355 * there are 8-byte lines, last line may be partially
356 * written (HW bug), thus FW configures for last line
357 * to be excessive. Driver skips this last line.
358 */
359 int len = min_t(int, 8 + sizeof(phy_data),
360 wil_rxdesc_phy_length(d));
361
362 if (len > 8) {
363 void *p = skb_tail_pointer(skb);
364 void *pa = PTR_ALIGN(p, 8);
365
366 if (skb_tailroom(skb) >= len + (pa - p)) {
367 phy_length = len - 8;
368 memcpy(phy_data, pa, phy_length);
369 }
370 }
371 }
372 rtap_len += phy_length;
373 }
374
375 if (skb_headroom(skb) < rtap_len &&
376 pskb_expand_head(skb, rtap_len, 0, GFP_ATOMIC)) {
377 wil_err(wil, "Unable to expand headroom to %d\n", rtap_len);
378 return;
379 }
380
381 rtap_vendor = skb_push(skb, rtap_len);
382 memset(rtap_vendor, 0, rtap_len);
383
384 rtap_vendor->rtap.rthdr.it_version = PKTHDR_RADIOTAP_VERSION;
385 rtap_vendor->rtap.rthdr.it_len = cpu_to_le16(rtap_len);
386 rtap_vendor->rtap.rthdr.it_present = cpu_to_le32(
387 (1 << IEEE80211_RADIOTAP_FLAGS) |
388 (1 << IEEE80211_RADIOTAP_CHANNEL) |
389 (1 << IEEE80211_RADIOTAP_MCS));
390 if (d->dma.status & RX_DMA_STATUS_ERROR)
391 rtap_vendor->rtap.flags |= IEEE80211_RADIOTAP_F_BADFCS;
392
393 rtap_vendor->rtap.chnl_freq = cpu_to_le16(ch ? ch->center_freq : 58320);
394 rtap_vendor->rtap.chnl_flags = cpu_to_le16(0);
395
396 rtap_vendor->rtap.mcs_present = IEEE80211_RADIOTAP_MCS_HAVE_MCS;
397 rtap_vendor->rtap.mcs_flags = 0;
398 rtap_vendor->rtap.mcs_index = wil_rxdesc_mcs(d);
399
400 if (rtap_include_phy_info) {
401 rtap_vendor->rtap.rthdr.it_present |= cpu_to_le32(1 <<
402 IEEE80211_RADIOTAP_VENDOR_NAMESPACE);
403 /* OUI for Wilocity 04:ce:14 */
404 rtap_vendor->vendor_oui[0] = 0x04;
405 rtap_vendor->vendor_oui[1] = 0xce;
406 rtap_vendor->vendor_oui[2] = 0x14;
407 rtap_vendor->vendor_ns = 1;
408 /* Rx descriptor + PHY data */
409 rtap_vendor->vendor_skip = cpu_to_le16(sizeof(*d) +
410 phy_length);
411 memcpy(rtap_vendor->vendor_data, (void *)d, sizeof(*d));
412 memcpy(rtap_vendor->vendor_data + sizeof(*d), phy_data,
413 phy_length);
414 }
415 }
416
wil_is_rx_idle(struct wil6210_priv * wil)417 static bool wil_is_rx_idle(struct wil6210_priv *wil)
418 {
419 struct vring_rx_desc *_d;
420 struct wil_ring *ring = &wil->ring_rx;
421
422 _d = (struct vring_rx_desc *)&ring->va[ring->swhead].rx.legacy;
423 if (_d->dma.status & RX_DMA_STATUS_DU)
424 return false;
425
426 return true;
427 }
428
429 /**
430 * reap 1 frame from @swhead
431 *
432 * Rx descriptor copied to skb->cb
433 *
434 * Safe to call from IRQ
435 */
wil_vring_reap_rx(struct wil6210_priv * wil,struct wil_ring * vring)436 static struct sk_buff *wil_vring_reap_rx(struct wil6210_priv *wil,
437 struct wil_ring *vring)
438 {
439 struct device *dev = wil_to_dev(wil);
440 struct wil6210_vif *vif;
441 struct net_device *ndev;
442 volatile struct vring_rx_desc *_d;
443 struct vring_rx_desc *d;
444 struct sk_buff *skb;
445 dma_addr_t pa;
446 unsigned int snaplen = wil_rx_snaplen();
447 unsigned int sz = wil->rx_buf_len + ETH_HLEN + snaplen;
448 u16 dmalen;
449 u8 ftype;
450 int cid, mid;
451 int i;
452 struct wil_net_stats *stats;
453
454 BUILD_BUG_ON(sizeof(struct vring_rx_desc) > sizeof(skb->cb));
455
456 again:
457 if (unlikely(wil_ring_is_empty(vring)))
458 return NULL;
459
460 i = (int)vring->swhead;
461 _d = &vring->va[i].rx.legacy;
462 if (unlikely(!(_d->dma.status & RX_DMA_STATUS_DU))) {
463 /* it is not error, we just reached end of Rx done area */
464 return NULL;
465 }
466
467 skb = vring->ctx[i].skb;
468 vring->ctx[i].skb = NULL;
469 wil_ring_advance_head(vring, 1);
470 if (!skb) {
471 wil_err(wil, "No Rx skb at [%d]\n", i);
472 goto again;
473 }
474 d = wil_skb_rxdesc(skb);
475 *d = *_d;
476 pa = wil_desc_addr(&d->dma.addr);
477
478 dma_unmap_single(dev, pa, sz, DMA_FROM_DEVICE);
479 dmalen = le16_to_cpu(d->dma.length);
480
481 trace_wil6210_rx(i, d);
482 wil_dbg_txrx(wil, "Rx[%3d] : %d bytes\n", i, dmalen);
483 wil_hex_dump_txrx("RxD ", DUMP_PREFIX_NONE, 32, 4,
484 (const void *)d, sizeof(*d), false);
485
486 cid = wil_rxdesc_cid(d);
487 mid = wil_rxdesc_mid(d);
488 vif = wil->vifs[mid];
489
490 if (unlikely(!vif)) {
491 wil_dbg_txrx(wil, "skipped RX descriptor with invalid mid %d",
492 mid);
493 kfree_skb(skb);
494 goto again;
495 }
496 ndev = vif_to_ndev(vif);
497 stats = &wil->sta[cid].stats;
498
499 if (unlikely(dmalen > sz)) {
500 wil_err(wil, "Rx size too large: %d bytes!\n", dmalen);
501 stats->rx_large_frame++;
502 kfree_skb(skb);
503 goto again;
504 }
505 skb_trim(skb, dmalen);
506
507 prefetch(skb->data);
508
509 wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1,
510 skb->data, skb_headlen(skb), false);
511
512 stats->last_mcs_rx = wil_rxdesc_mcs(d);
513 if (stats->last_mcs_rx < ARRAY_SIZE(stats->rx_per_mcs))
514 stats->rx_per_mcs[stats->last_mcs_rx]++;
515
516 /* use radiotap header only if required */
517 if (ndev->type == ARPHRD_IEEE80211_RADIOTAP)
518 wil_rx_add_radiotap_header(wil, skb);
519
520 /* no extra checks if in sniffer mode */
521 if (ndev->type != ARPHRD_ETHER)
522 return skb;
523 /* Non-data frames may be delivered through Rx DMA channel (ex: BAR)
524 * Driver should recognize it by frame type, that is found
525 * in Rx descriptor. If type is not data, it is 802.11 frame as is
526 */
527 ftype = wil_rxdesc_ftype(d) << 2;
528 if (unlikely(ftype != IEEE80211_FTYPE_DATA)) {
529 u8 fc1 = wil_rxdesc_fc1(d);
530 int tid = wil_rxdesc_tid(d);
531 u16 seq = wil_rxdesc_seq(d);
532
533 wil_dbg_txrx(wil,
534 "Non-data frame FC[7:0] 0x%02x MID %d CID %d TID %d Seq 0x%03x\n",
535 fc1, mid, cid, tid, seq);
536 stats->rx_non_data_frame++;
537 if (wil_is_back_req(fc1)) {
538 wil_dbg_txrx(wil,
539 "BAR: MID %d CID %d TID %d Seq 0x%03x\n",
540 mid, cid, tid, seq);
541 wil_rx_bar(wil, vif, cid, tid, seq);
542 } else {
543 /* print again all info. One can enable only this
544 * without overhead for printing every Rx frame
545 */
546 wil_dbg_txrx(wil,
547 "Unhandled non-data frame FC[7:0] 0x%02x MID %d CID %d TID %d Seq 0x%03x\n",
548 fc1, mid, cid, tid, seq);
549 wil_hex_dump_txrx("RxD ", DUMP_PREFIX_NONE, 32, 4,
550 (const void *)d, sizeof(*d), false);
551 wil_hex_dump_txrx("Rx ", DUMP_PREFIX_OFFSET, 16, 1,
552 skb->data, skb_headlen(skb), false);
553 }
554 kfree_skb(skb);
555 goto again;
556 }
557
558 if (unlikely(skb->len < ETH_HLEN + snaplen)) {
559 wil_err(wil, "Short frame, len = %d\n", skb->len);
560 stats->rx_short_frame++;
561 kfree_skb(skb);
562 goto again;
563 }
564
565 /* L4 IDENT is on when HW calculated checksum, check status
566 * and in case of error drop the packet
567 * higher stack layers will handle retransmission (if required)
568 */
569 if (likely(d->dma.status & RX_DMA_STATUS_L4I)) {
570 /* L4 protocol identified, csum calculated */
571 if (likely((d->dma.error & RX_DMA_ERROR_L4_ERR) == 0))
572 skb->ip_summed = CHECKSUM_UNNECESSARY;
573 /* If HW reports bad checksum, let IP stack re-check it
574 * For example, HW don't understand Microsoft IP stack that
575 * mis-calculates TCP checksum - if it should be 0x0,
576 * it writes 0xffff in violation of RFC 1624
577 */
578 else
579 stats->rx_csum_err++;
580 }
581
582 if (snaplen) {
583 /* Packet layout
584 * +-------+-------+---------+------------+------+
585 * | SA(6) | DA(6) | SNAP(6) | ETHTYPE(2) | DATA |
586 * +-------+-------+---------+------------+------+
587 * Need to remove SNAP, shifting SA and DA forward
588 */
589 memmove(skb->data + snaplen, skb->data, 2 * ETH_ALEN);
590 skb_pull(skb, snaplen);
591 }
592
593 return skb;
594 }
595
596 /**
597 * allocate and fill up to @count buffers in rx ring
598 * buffers posted at @swtail
599 * Note: we have a single RX queue for servicing all VIFs, but we
600 * allocate skbs with headroom according to main interface only. This
601 * means it will not work with monitor interface together with other VIFs.
602 * Currently we only support monitor interface on its own without other VIFs,
603 * and we will need to fix this code once we add support.
604 */
wil_rx_refill(struct wil6210_priv * wil,int count)605 static int wil_rx_refill(struct wil6210_priv *wil, int count)
606 {
607 struct net_device *ndev = wil->main_ndev;
608 struct wil_ring *v = &wil->ring_rx;
609 u32 next_tail;
610 int rc = 0;
611 int headroom = ndev->type == ARPHRD_IEEE80211_RADIOTAP ?
612 WIL6210_RTAP_SIZE : 0;
613
614 for (; next_tail = wil_ring_next_tail(v),
615 (next_tail != v->swhead) && (count-- > 0);
616 v->swtail = next_tail) {
617 rc = wil_vring_alloc_skb(wil, v, v->swtail, headroom);
618 if (unlikely(rc)) {
619 wil_err_ratelimited(wil, "Error %d in rx refill[%d]\n",
620 rc, v->swtail);
621 break;
622 }
623 }
624
625 /* make sure all writes to descriptors (shared memory) are done before
626 * committing them to HW
627 */
628 wmb();
629
630 wil_w(wil, v->hwtail, v->swtail);
631
632 return rc;
633 }
634
635 /**
636 * reverse_memcmp - Compare two areas of memory, in reverse order
637 * @cs: One area of memory
638 * @ct: Another area of memory
639 * @count: The size of the area.
640 *
641 * Cut'n'paste from original memcmp (see lib/string.c)
642 * with minimal modifications
643 */
reverse_memcmp(const void * cs,const void * ct,size_t count)644 int reverse_memcmp(const void *cs, const void *ct, size_t count)
645 {
646 const unsigned char *su1, *su2;
647 int res = 0;
648
649 for (su1 = cs + count - 1, su2 = ct + count - 1; count > 0;
650 --su1, --su2, count--) {
651 res = *su1 - *su2;
652 if (res)
653 break;
654 }
655 return res;
656 }
657
wil_rx_crypto_check(struct wil6210_priv * wil,struct sk_buff * skb)658 static int wil_rx_crypto_check(struct wil6210_priv *wil, struct sk_buff *skb)
659 {
660 struct vring_rx_desc *d = wil_skb_rxdesc(skb);
661 int cid = wil_rxdesc_cid(d);
662 int tid = wil_rxdesc_tid(d);
663 int key_id = wil_rxdesc_key_id(d);
664 int mc = wil_rxdesc_mcast(d);
665 struct wil_sta_info *s = &wil->sta[cid];
666 struct wil_tid_crypto_rx *c = mc ? &s->group_crypto_rx :
667 &s->tid_crypto_rx[tid];
668 struct wil_tid_crypto_rx_single *cc = &c->key_id[key_id];
669 const u8 *pn = (u8 *)&d->mac.pn_15_0;
670
671 if (!cc->key_set) {
672 wil_err_ratelimited(wil,
673 "Key missing. CID %d TID %d MCast %d KEY_ID %d\n",
674 cid, tid, mc, key_id);
675 return -EINVAL;
676 }
677
678 if (reverse_memcmp(pn, cc->pn, IEEE80211_GCMP_PN_LEN) <= 0) {
679 wil_err_ratelimited(wil,
680 "Replay attack. CID %d TID %d MCast %d KEY_ID %d PN %6phN last %6phN\n",
681 cid, tid, mc, key_id, pn, cc->pn);
682 return -EINVAL;
683 }
684 memcpy(cc->pn, pn, IEEE80211_GCMP_PN_LEN);
685
686 return 0;
687 }
688
wil_rx_error_check(struct wil6210_priv * wil,struct sk_buff * skb,struct wil_net_stats * stats)689 static int wil_rx_error_check(struct wil6210_priv *wil, struct sk_buff *skb,
690 struct wil_net_stats *stats)
691 {
692 struct vring_rx_desc *d = wil_skb_rxdesc(skb);
693
694 if ((d->dma.status & RX_DMA_STATUS_ERROR) &&
695 (d->dma.error & RX_DMA_ERROR_MIC)) {
696 stats->rx_mic_error++;
697 wil_dbg_txrx(wil, "MIC error, dropping packet\n");
698 return -EFAULT;
699 }
700
701 return 0;
702 }
703
wil_get_netif_rx_params(struct sk_buff * skb,int * cid,int * security)704 static void wil_get_netif_rx_params(struct sk_buff *skb, int *cid,
705 int *security)
706 {
707 struct vring_rx_desc *d = wil_skb_rxdesc(skb);
708
709 *cid = wil_rxdesc_cid(d); /* always 0..7, no need to check */
710 *security = wil_rxdesc_security(d);
711 }
712
713 /*
714 * Pass Rx packet to the netif. Update statistics.
715 * Called in softirq context (NAPI poll).
716 */
wil_netif_rx_any(struct sk_buff * skb,struct net_device * ndev)717 void wil_netif_rx_any(struct sk_buff *skb, struct net_device *ndev)
718 {
719 gro_result_t rc = GRO_NORMAL;
720 struct wil6210_vif *vif = ndev_to_vif(ndev);
721 struct wil6210_priv *wil = ndev_to_wil(ndev);
722 struct wireless_dev *wdev = vif_to_wdev(vif);
723 unsigned int len = skb->len;
724 int cid;
725 int security;
726 struct ethhdr *eth = (void *)skb->data;
727 /* here looking for DA, not A1, thus Rxdesc's 'mcast' indication
728 * is not suitable, need to look at data
729 */
730 int mcast = is_multicast_ether_addr(eth->h_dest);
731 struct wil_net_stats *stats;
732 struct sk_buff *xmit_skb = NULL;
733 static const char * const gro_res_str[] = {
734 [GRO_MERGED] = "GRO_MERGED",
735 [GRO_MERGED_FREE] = "GRO_MERGED_FREE",
736 [GRO_HELD] = "GRO_HELD",
737 [GRO_NORMAL] = "GRO_NORMAL",
738 [GRO_DROP] = "GRO_DROP",
739 };
740
741 wil->txrx_ops.get_netif_rx_params(skb, &cid, &security);
742
743 stats = &wil->sta[cid].stats;
744
745 if (ndev->features & NETIF_F_RXHASH)
746 /* fake L4 to ensure it won't be re-calculated later
747 * set hash to any non-zero value to activate rps
748 * mechanism, core will be chosen according
749 * to user-level rps configuration.
750 */
751 skb_set_hash(skb, 1, PKT_HASH_TYPE_L4);
752
753 skb_orphan(skb);
754
755 if (security && (wil->txrx_ops.rx_crypto_check(wil, skb) != 0)) {
756 rc = GRO_DROP;
757 dev_kfree_skb(skb);
758 stats->rx_replay++;
759 goto stats;
760 }
761
762 /* check errors reported by HW and update statistics */
763 if (unlikely(wil->txrx_ops.rx_error_check(wil, skb, stats))) {
764 dev_kfree_skb(skb);
765 return;
766 }
767
768 if (wdev->iftype == NL80211_IFTYPE_AP && !vif->ap_isolate) {
769 if (mcast) {
770 /* send multicast frames both to higher layers in
771 * local net stack and back to the wireless medium
772 */
773 xmit_skb = skb_copy(skb, GFP_ATOMIC);
774 } else {
775 int xmit_cid = wil_find_cid(wil, vif->mid,
776 eth->h_dest);
777
778 if (xmit_cid >= 0) {
779 /* The destination station is associated to
780 * this AP (in this VLAN), so send the frame
781 * directly to it and do not pass it to local
782 * net stack.
783 */
784 xmit_skb = skb;
785 skb = NULL;
786 }
787 }
788 }
789 if (xmit_skb) {
790 /* Send to wireless media and increase priority by 256 to
791 * keep the received priority instead of reclassifying
792 * the frame (see cfg80211_classify8021d).
793 */
794 xmit_skb->dev = ndev;
795 xmit_skb->priority += 256;
796 xmit_skb->protocol = htons(ETH_P_802_3);
797 skb_reset_network_header(xmit_skb);
798 skb_reset_mac_header(xmit_skb);
799 wil_dbg_txrx(wil, "Rx -> Tx %d bytes\n", len);
800 dev_queue_xmit(xmit_skb);
801 }
802
803 if (skb) { /* deliver to local stack */
804 skb->protocol = eth_type_trans(skb, ndev);
805 skb->dev = ndev;
806 rc = napi_gro_receive(&wil->napi_rx, skb);
807 wil_dbg_txrx(wil, "Rx complete %d bytes => %s\n",
808 len, gro_res_str[rc]);
809 }
810 stats:
811 /* statistics. rc set to GRO_NORMAL for AP bridging */
812 if (unlikely(rc == GRO_DROP)) {
813 ndev->stats.rx_dropped++;
814 stats->rx_dropped++;
815 wil_dbg_txrx(wil, "Rx drop %d bytes\n", len);
816 } else {
817 ndev->stats.rx_packets++;
818 stats->rx_packets++;
819 ndev->stats.rx_bytes += len;
820 stats->rx_bytes += len;
821 if (mcast)
822 ndev->stats.multicast++;
823 }
824 }
825
826 /**
827 * Proceed all completed skb's from Rx VRING
828 *
829 * Safe to call from NAPI poll, i.e. softirq with interrupts enabled
830 */
wil_rx_handle(struct wil6210_priv * wil,int * quota)831 void wil_rx_handle(struct wil6210_priv *wil, int *quota)
832 {
833 struct net_device *ndev = wil->main_ndev;
834 struct wireless_dev *wdev = ndev->ieee80211_ptr;
835 struct wil_ring *v = &wil->ring_rx;
836 struct sk_buff *skb;
837
838 if (unlikely(!v->va)) {
839 wil_err(wil, "Rx IRQ while Rx not yet initialized\n");
840 return;
841 }
842 wil_dbg_txrx(wil, "rx_handle\n");
843 while ((*quota > 0) && (NULL != (skb = wil_vring_reap_rx(wil, v)))) {
844 (*quota)--;
845
846 /* monitor is currently supported on main interface only */
847 if (wdev->iftype == NL80211_IFTYPE_MONITOR) {
848 skb->dev = ndev;
849 skb_reset_mac_header(skb);
850 skb->ip_summed = CHECKSUM_UNNECESSARY;
851 skb->pkt_type = PACKET_OTHERHOST;
852 skb->protocol = htons(ETH_P_802_2);
853 wil_netif_rx_any(skb, ndev);
854 } else {
855 wil_rx_reorder(wil, skb);
856 }
857 }
858 wil_rx_refill(wil, v->size);
859 }
860
wil_rx_buf_len_init(struct wil6210_priv * wil)861 static void wil_rx_buf_len_init(struct wil6210_priv *wil)
862 {
863 wil->rx_buf_len = rx_large_buf ?
864 WIL_MAX_ETH_MTU : TXRX_BUF_LEN_DEFAULT - WIL_MAX_MPDU_OVERHEAD;
865 if (mtu_max > wil->rx_buf_len) {
866 /* do not allow RX buffers to be smaller than mtu_max, for
867 * backward compatibility (mtu_max parameter was also used
868 * to support receiving large packets)
869 */
870 wil_info(wil, "Override RX buffer to mtu_max(%d)\n", mtu_max);
871 wil->rx_buf_len = mtu_max;
872 }
873 }
874
wil_rx_init(struct wil6210_priv * wil,u16 size)875 static int wil_rx_init(struct wil6210_priv *wil, u16 size)
876 {
877 struct wil_ring *vring = &wil->ring_rx;
878 int rc;
879
880 wil_dbg_misc(wil, "rx_init\n");
881
882 if (vring->va) {
883 wil_err(wil, "Rx ring already allocated\n");
884 return -EINVAL;
885 }
886
887 wil_rx_buf_len_init(wil);
888
889 vring->size = size;
890 vring->is_rx = true;
891 rc = wil_vring_alloc(wil, vring);
892 if (rc)
893 return rc;
894
895 rc = wmi_rx_chain_add(wil, vring);
896 if (rc)
897 goto err_free;
898
899 rc = wil_rx_refill(wil, vring->size);
900 if (rc)
901 goto err_free;
902
903 return 0;
904 err_free:
905 wil_vring_free(wil, vring);
906
907 return rc;
908 }
909
wil_rx_fini(struct wil6210_priv * wil)910 static void wil_rx_fini(struct wil6210_priv *wil)
911 {
912 struct wil_ring *vring = &wil->ring_rx;
913
914 wil_dbg_misc(wil, "rx_fini\n");
915
916 if (vring->va)
917 wil_vring_free(wil, vring);
918 }
919
wil_tx_desc_map(union wil_tx_desc * desc,dma_addr_t pa,u32 len,int vring_index)920 static int wil_tx_desc_map(union wil_tx_desc *desc, dma_addr_t pa,
921 u32 len, int vring_index)
922 {
923 struct vring_tx_desc *d = &desc->legacy;
924
925 wil_desc_addr_set(&d->dma.addr, pa);
926 d->dma.ip_length = 0;
927 /* 0..6: mac_length; 7:ip_version 0-IP6 1-IP4*/
928 d->dma.b11 = 0/*14 | BIT(7)*/;
929 d->dma.error = 0;
930 d->dma.status = 0; /* BIT(0) should be 0 for HW_OWNED */
931 d->dma.length = cpu_to_le16((u16)len);
932 d->dma.d0 = (vring_index << DMA_CFG_DESC_TX_0_QID_POS);
933 d->mac.d[0] = 0;
934 d->mac.d[1] = 0;
935 d->mac.d[2] = 0;
936 d->mac.ucode_cmd = 0;
937 /* translation type: 0 - bypass; 1 - 802.3; 2 - native wifi */
938 d->mac.d[2] = BIT(MAC_CFG_DESC_TX_2_SNAP_HDR_INSERTION_EN_POS) |
939 (1 << MAC_CFG_DESC_TX_2_L2_TRANSLATION_TYPE_POS);
940
941 return 0;
942 }
943
wil_tx_data_init(struct wil_ring_tx_data * txdata)944 void wil_tx_data_init(struct wil_ring_tx_data *txdata)
945 {
946 spin_lock_bh(&txdata->lock);
947 txdata->dot1x_open = 0;
948 txdata->enabled = 0;
949 txdata->idle = 0;
950 txdata->last_idle = 0;
951 txdata->begin = 0;
952 txdata->agg_wsize = 0;
953 txdata->agg_timeout = 0;
954 txdata->agg_amsdu = 0;
955 txdata->addba_in_progress = false;
956 txdata->mid = U8_MAX;
957 spin_unlock_bh(&txdata->lock);
958 }
959
wil_vring_init_tx(struct wil6210_vif * vif,int id,int size,int cid,int tid)960 static int wil_vring_init_tx(struct wil6210_vif *vif, int id, int size,
961 int cid, int tid)
962 {
963 struct wil6210_priv *wil = vif_to_wil(vif);
964 int rc;
965 struct wmi_vring_cfg_cmd cmd = {
966 .action = cpu_to_le32(WMI_VRING_CMD_ADD),
967 .vring_cfg = {
968 .tx_sw_ring = {
969 .max_mpdu_size =
970 cpu_to_le16(wil_mtu2macbuf(mtu_max)),
971 .ring_size = cpu_to_le16(size),
972 },
973 .ringid = id,
974 .cidxtid = mk_cidxtid(cid, tid),
975 .encap_trans_type = WMI_VRING_ENC_TYPE_802_3,
976 .mac_ctrl = 0,
977 .to_resolution = 0,
978 .agg_max_wsize = 0,
979 .schd_params = {
980 .priority = cpu_to_le16(0),
981 .timeslot_us = cpu_to_le16(0xfff),
982 },
983 },
984 };
985 struct {
986 struct wmi_cmd_hdr wmi;
987 struct wmi_vring_cfg_done_event cmd;
988 } __packed reply = {
989 .cmd = {.status = WMI_FW_STATUS_FAILURE},
990 };
991 struct wil_ring *vring = &wil->ring_tx[id];
992 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[id];
993
994 wil_dbg_misc(wil, "vring_init_tx: max_mpdu_size %d\n",
995 cmd.vring_cfg.tx_sw_ring.max_mpdu_size);
996 lockdep_assert_held(&wil->mutex);
997
998 if (vring->va) {
999 wil_err(wil, "Tx ring [%d] already allocated\n", id);
1000 rc = -EINVAL;
1001 goto out;
1002 }
1003
1004 wil_tx_data_init(txdata);
1005 vring->is_rx = false;
1006 vring->size = size;
1007 rc = wil_vring_alloc(wil, vring);
1008 if (rc)
1009 goto out;
1010
1011 wil->ring2cid_tid[id][0] = cid;
1012 wil->ring2cid_tid[id][1] = tid;
1013
1014 cmd.vring_cfg.tx_sw_ring.ring_mem_base = cpu_to_le64(vring->pa);
1015
1016 if (!vif->privacy)
1017 txdata->dot1x_open = true;
1018 rc = wmi_call(wil, WMI_VRING_CFG_CMDID, vif->mid, &cmd, sizeof(cmd),
1019 WMI_VRING_CFG_DONE_EVENTID, &reply, sizeof(reply), 100);
1020 if (rc)
1021 goto out_free;
1022
1023 if (reply.cmd.status != WMI_FW_STATUS_SUCCESS) {
1024 wil_err(wil, "Tx config failed, status 0x%02x\n",
1025 reply.cmd.status);
1026 rc = -EINVAL;
1027 goto out_free;
1028 }
1029
1030 spin_lock_bh(&txdata->lock);
1031 vring->hwtail = le32_to_cpu(reply.cmd.tx_vring_tail_ptr);
1032 txdata->mid = vif->mid;
1033 txdata->enabled = 1;
1034 spin_unlock_bh(&txdata->lock);
1035
1036 if (txdata->dot1x_open && (agg_wsize >= 0))
1037 wil_addba_tx_request(wil, id, agg_wsize);
1038
1039 return 0;
1040 out_free:
1041 spin_lock_bh(&txdata->lock);
1042 txdata->dot1x_open = false;
1043 txdata->enabled = 0;
1044 spin_unlock_bh(&txdata->lock);
1045 wil_vring_free(wil, vring);
1046 wil->ring2cid_tid[id][0] = WIL6210_MAX_CID;
1047 wil->ring2cid_tid[id][1] = 0;
1048
1049 out:
1050
1051 return rc;
1052 }
1053
wil_vring_init_bcast(struct wil6210_vif * vif,int id,int size)1054 int wil_vring_init_bcast(struct wil6210_vif *vif, int id, int size)
1055 {
1056 struct wil6210_priv *wil = vif_to_wil(vif);
1057 int rc;
1058 struct wmi_bcast_vring_cfg_cmd cmd = {
1059 .action = cpu_to_le32(WMI_VRING_CMD_ADD),
1060 .vring_cfg = {
1061 .tx_sw_ring = {
1062 .max_mpdu_size =
1063 cpu_to_le16(wil_mtu2macbuf(mtu_max)),
1064 .ring_size = cpu_to_le16(size),
1065 },
1066 .ringid = id,
1067 .encap_trans_type = WMI_VRING_ENC_TYPE_802_3,
1068 },
1069 };
1070 struct {
1071 struct wmi_cmd_hdr wmi;
1072 struct wmi_vring_cfg_done_event cmd;
1073 } __packed reply = {
1074 .cmd = {.status = WMI_FW_STATUS_FAILURE},
1075 };
1076 struct wil_ring *vring = &wil->ring_tx[id];
1077 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[id];
1078
1079 wil_dbg_misc(wil, "vring_init_bcast: max_mpdu_size %d\n",
1080 cmd.vring_cfg.tx_sw_ring.max_mpdu_size);
1081 lockdep_assert_held(&wil->mutex);
1082
1083 if (vring->va) {
1084 wil_err(wil, "Tx ring [%d] already allocated\n", id);
1085 rc = -EINVAL;
1086 goto out;
1087 }
1088
1089 wil_tx_data_init(txdata);
1090 vring->is_rx = false;
1091 vring->size = size;
1092 rc = wil_vring_alloc(wil, vring);
1093 if (rc)
1094 goto out;
1095
1096 wil->ring2cid_tid[id][0] = WIL6210_MAX_CID; /* CID */
1097 wil->ring2cid_tid[id][1] = 0; /* TID */
1098
1099 cmd.vring_cfg.tx_sw_ring.ring_mem_base = cpu_to_le64(vring->pa);
1100
1101 if (!vif->privacy)
1102 txdata->dot1x_open = true;
1103 rc = wmi_call(wil, WMI_BCAST_VRING_CFG_CMDID, vif->mid,
1104 &cmd, sizeof(cmd),
1105 WMI_VRING_CFG_DONE_EVENTID, &reply, sizeof(reply), 100);
1106 if (rc)
1107 goto out_free;
1108
1109 if (reply.cmd.status != WMI_FW_STATUS_SUCCESS) {
1110 wil_err(wil, "Tx config failed, status 0x%02x\n",
1111 reply.cmd.status);
1112 rc = -EINVAL;
1113 goto out_free;
1114 }
1115
1116 spin_lock_bh(&txdata->lock);
1117 vring->hwtail = le32_to_cpu(reply.cmd.tx_vring_tail_ptr);
1118 txdata->mid = vif->mid;
1119 txdata->enabled = 1;
1120 spin_unlock_bh(&txdata->lock);
1121
1122 return 0;
1123 out_free:
1124 spin_lock_bh(&txdata->lock);
1125 txdata->enabled = 0;
1126 txdata->dot1x_open = false;
1127 spin_unlock_bh(&txdata->lock);
1128 wil_vring_free(wil, vring);
1129 out:
1130
1131 return rc;
1132 }
1133
wil_find_tx_ucast(struct wil6210_priv * wil,struct wil6210_vif * vif,struct sk_buff * skb)1134 static struct wil_ring *wil_find_tx_ucast(struct wil6210_priv *wil,
1135 struct wil6210_vif *vif,
1136 struct sk_buff *skb)
1137 {
1138 int i;
1139 struct ethhdr *eth = (void *)skb->data;
1140 int cid = wil_find_cid(wil, vif->mid, eth->h_dest);
1141 int min_ring_id = wil_get_min_tx_ring_id(wil);
1142
1143 if (cid < 0)
1144 return NULL;
1145
1146 /* TODO: fix for multiple TID */
1147 for (i = min_ring_id; i < ARRAY_SIZE(wil->ring2cid_tid); i++) {
1148 if (!wil->ring_tx_data[i].dot1x_open &&
1149 skb->protocol != cpu_to_be16(ETH_P_PAE))
1150 continue;
1151 if (wil->ring2cid_tid[i][0] == cid) {
1152 struct wil_ring *v = &wil->ring_tx[i];
1153 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[i];
1154
1155 wil_dbg_txrx(wil, "find_tx_ucast: (%pM) -> [%d]\n",
1156 eth->h_dest, i);
1157 if (v->va && txdata->enabled) {
1158 return v;
1159 } else {
1160 wil_dbg_txrx(wil,
1161 "find_tx_ucast: vring[%d] not valid\n",
1162 i);
1163 return NULL;
1164 }
1165 }
1166 }
1167
1168 return NULL;
1169 }
1170
1171 static int wil_tx_ring(struct wil6210_priv *wil, struct wil6210_vif *vif,
1172 struct wil_ring *ring, struct sk_buff *skb);
1173
wil_find_tx_ring_sta(struct wil6210_priv * wil,struct wil6210_vif * vif,struct sk_buff * skb)1174 static struct wil_ring *wil_find_tx_ring_sta(struct wil6210_priv *wil,
1175 struct wil6210_vif *vif,
1176 struct sk_buff *skb)
1177 {
1178 struct wil_ring *ring;
1179 int i;
1180 u8 cid;
1181 struct wil_ring_tx_data *txdata;
1182 int min_ring_id = wil_get_min_tx_ring_id(wil);
1183
1184 /* In the STA mode, it is expected to have only 1 VRING
1185 * for the AP we connected to.
1186 * find 1-st vring eligible for this skb and use it.
1187 */
1188 for (i = min_ring_id; i < WIL6210_MAX_TX_RINGS; i++) {
1189 ring = &wil->ring_tx[i];
1190 txdata = &wil->ring_tx_data[i];
1191 if (!ring->va || !txdata->enabled || txdata->mid != vif->mid)
1192 continue;
1193
1194 cid = wil->ring2cid_tid[i][0];
1195 if (cid >= WIL6210_MAX_CID) /* skip BCAST */
1196 continue;
1197
1198 if (!wil->ring_tx_data[i].dot1x_open &&
1199 skb->protocol != cpu_to_be16(ETH_P_PAE))
1200 continue;
1201
1202 wil_dbg_txrx(wil, "Tx -> ring %d\n", i);
1203
1204 return ring;
1205 }
1206
1207 wil_dbg_txrx(wil, "Tx while no rings active?\n");
1208
1209 return NULL;
1210 }
1211
1212 /* Use one of 2 strategies:
1213 *
1214 * 1. New (real broadcast):
1215 * use dedicated broadcast vring
1216 * 2. Old (pseudo-DMS):
1217 * Find 1-st vring and return it;
1218 * duplicate skb and send it to other active vrings;
1219 * in all cases override dest address to unicast peer's address
1220 * Use old strategy when new is not supported yet:
1221 * - for PBSS
1222 */
wil_find_tx_bcast_1(struct wil6210_priv * wil,struct wil6210_vif * vif,struct sk_buff * skb)1223 static struct wil_ring *wil_find_tx_bcast_1(struct wil6210_priv *wil,
1224 struct wil6210_vif *vif,
1225 struct sk_buff *skb)
1226 {
1227 struct wil_ring *v;
1228 struct wil_ring_tx_data *txdata;
1229 int i = vif->bcast_ring;
1230
1231 if (i < 0)
1232 return NULL;
1233 v = &wil->ring_tx[i];
1234 txdata = &wil->ring_tx_data[i];
1235 if (!v->va || !txdata->enabled)
1236 return NULL;
1237 if (!wil->ring_tx_data[i].dot1x_open &&
1238 skb->protocol != cpu_to_be16(ETH_P_PAE))
1239 return NULL;
1240
1241 return v;
1242 }
1243
wil_set_da_for_vring(struct wil6210_priv * wil,struct sk_buff * skb,int vring_index)1244 static void wil_set_da_for_vring(struct wil6210_priv *wil,
1245 struct sk_buff *skb, int vring_index)
1246 {
1247 struct ethhdr *eth = (void *)skb->data;
1248 int cid = wil->ring2cid_tid[vring_index][0];
1249
1250 ether_addr_copy(eth->h_dest, wil->sta[cid].addr);
1251 }
1252
wil_find_tx_bcast_2(struct wil6210_priv * wil,struct wil6210_vif * vif,struct sk_buff * skb)1253 static struct wil_ring *wil_find_tx_bcast_2(struct wil6210_priv *wil,
1254 struct wil6210_vif *vif,
1255 struct sk_buff *skb)
1256 {
1257 struct wil_ring *v, *v2;
1258 struct sk_buff *skb2;
1259 int i;
1260 u8 cid;
1261 struct ethhdr *eth = (void *)skb->data;
1262 char *src = eth->h_source;
1263 struct wil_ring_tx_data *txdata, *txdata2;
1264 int min_ring_id = wil_get_min_tx_ring_id(wil);
1265
1266 /* find 1-st vring eligible for data */
1267 for (i = min_ring_id; i < WIL6210_MAX_TX_RINGS; i++) {
1268 v = &wil->ring_tx[i];
1269 txdata = &wil->ring_tx_data[i];
1270 if (!v->va || !txdata->enabled || txdata->mid != vif->mid)
1271 continue;
1272
1273 cid = wil->ring2cid_tid[i][0];
1274 if (cid >= WIL6210_MAX_CID) /* skip BCAST */
1275 continue;
1276 if (!wil->ring_tx_data[i].dot1x_open &&
1277 skb->protocol != cpu_to_be16(ETH_P_PAE))
1278 continue;
1279
1280 /* don't Tx back to source when re-routing Rx->Tx at the AP */
1281 if (0 == memcmp(wil->sta[cid].addr, src, ETH_ALEN))
1282 continue;
1283
1284 goto found;
1285 }
1286
1287 wil_dbg_txrx(wil, "Tx while no vrings active?\n");
1288
1289 return NULL;
1290
1291 found:
1292 wil_dbg_txrx(wil, "BCAST -> ring %d\n", i);
1293 wil_set_da_for_vring(wil, skb, i);
1294
1295 /* find other active vrings and duplicate skb for each */
1296 for (i++; i < WIL6210_MAX_TX_RINGS; i++) {
1297 v2 = &wil->ring_tx[i];
1298 txdata2 = &wil->ring_tx_data[i];
1299 if (!v2->va || txdata2->mid != vif->mid)
1300 continue;
1301 cid = wil->ring2cid_tid[i][0];
1302 if (cid >= WIL6210_MAX_CID) /* skip BCAST */
1303 continue;
1304 if (!wil->ring_tx_data[i].dot1x_open &&
1305 skb->protocol != cpu_to_be16(ETH_P_PAE))
1306 continue;
1307
1308 if (0 == memcmp(wil->sta[cid].addr, src, ETH_ALEN))
1309 continue;
1310
1311 skb2 = skb_copy(skb, GFP_ATOMIC);
1312 if (skb2) {
1313 wil_dbg_txrx(wil, "BCAST DUP -> ring %d\n", i);
1314 wil_set_da_for_vring(wil, skb2, i);
1315 wil_tx_ring(wil, vif, v2, skb2);
1316 } else {
1317 wil_err(wil, "skb_copy failed\n");
1318 }
1319 }
1320
1321 return v;
1322 }
1323
1324 static inline
wil_tx_desc_set_nr_frags(struct vring_tx_desc * d,int nr_frags)1325 void wil_tx_desc_set_nr_frags(struct vring_tx_desc *d, int nr_frags)
1326 {
1327 d->mac.d[2] |= (nr_frags << MAC_CFG_DESC_TX_2_NUM_OF_DESCRIPTORS_POS);
1328 }
1329
1330 /**
1331 * Sets the descriptor @d up for csum and/or TSO offloading. The corresponding
1332 * @skb is used to obtain the protocol and headers length.
1333 * @tso_desc_type is a descriptor type for TSO: 0 - a header, 1 - first data,
1334 * 2 - middle, 3 - last descriptor.
1335 */
1336
wil_tx_desc_offload_setup_tso(struct vring_tx_desc * d,struct sk_buff * skb,int tso_desc_type,bool is_ipv4,int tcp_hdr_len,int skb_net_hdr_len)1337 static void wil_tx_desc_offload_setup_tso(struct vring_tx_desc *d,
1338 struct sk_buff *skb,
1339 int tso_desc_type, bool is_ipv4,
1340 int tcp_hdr_len, int skb_net_hdr_len)
1341 {
1342 d->dma.b11 = ETH_HLEN; /* MAC header length */
1343 d->dma.b11 |= is_ipv4 << DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS;
1344
1345 d->dma.d0 |= (2 << DMA_CFG_DESC_TX_0_L4_TYPE_POS);
1346 /* L4 header len: TCP header length */
1347 d->dma.d0 |= (tcp_hdr_len & DMA_CFG_DESC_TX_0_L4_LENGTH_MSK);
1348
1349 /* Setup TSO: bit and desc type */
1350 d->dma.d0 |= (BIT(DMA_CFG_DESC_TX_0_TCP_SEG_EN_POS)) |
1351 (tso_desc_type << DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_POS);
1352 d->dma.d0 |= (is_ipv4 << DMA_CFG_DESC_TX_0_IPV4_CHECKSUM_EN_POS);
1353
1354 d->dma.ip_length = skb_net_hdr_len;
1355 /* Enable TCP/UDP checksum */
1356 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_POS);
1357 /* Calculate pseudo-header */
1358 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_POS);
1359 }
1360
1361 /**
1362 * Sets the descriptor @d up for csum. The corresponding
1363 * @skb is used to obtain the protocol and headers length.
1364 * Returns the protocol: 0 - not TCP, 1 - TCPv4, 2 - TCPv6.
1365 * Note, if d==NULL, the function only returns the protocol result.
1366 *
1367 * It is very similar to previous wil_tx_desc_offload_setup_tso. This
1368 * is "if unrolling" to optimize the critical path.
1369 */
1370
wil_tx_desc_offload_setup(struct vring_tx_desc * d,struct sk_buff * skb)1371 static int wil_tx_desc_offload_setup(struct vring_tx_desc *d,
1372 struct sk_buff *skb){
1373 int protocol;
1374
1375 if (skb->ip_summed != CHECKSUM_PARTIAL)
1376 return 0;
1377
1378 d->dma.b11 = ETH_HLEN; /* MAC header length */
1379
1380 switch (skb->protocol) {
1381 case cpu_to_be16(ETH_P_IP):
1382 protocol = ip_hdr(skb)->protocol;
1383 d->dma.b11 |= BIT(DMA_CFG_DESC_TX_OFFLOAD_CFG_L3T_IPV4_POS);
1384 break;
1385 case cpu_to_be16(ETH_P_IPV6):
1386 protocol = ipv6_hdr(skb)->nexthdr;
1387 break;
1388 default:
1389 return -EINVAL;
1390 }
1391
1392 switch (protocol) {
1393 case IPPROTO_TCP:
1394 d->dma.d0 |= (2 << DMA_CFG_DESC_TX_0_L4_TYPE_POS);
1395 /* L4 header len: TCP header length */
1396 d->dma.d0 |=
1397 (tcp_hdrlen(skb) & DMA_CFG_DESC_TX_0_L4_LENGTH_MSK);
1398 break;
1399 case IPPROTO_UDP:
1400 /* L4 header len: UDP header length */
1401 d->dma.d0 |=
1402 (sizeof(struct udphdr) & DMA_CFG_DESC_TX_0_L4_LENGTH_MSK);
1403 break;
1404 default:
1405 return -EINVAL;
1406 }
1407
1408 d->dma.ip_length = skb_network_header_len(skb);
1409 /* Enable TCP/UDP checksum */
1410 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_TCP_UDP_CHECKSUM_EN_POS);
1411 /* Calculate pseudo-header */
1412 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_PSEUDO_HEADER_CALC_EN_POS);
1413
1414 return 0;
1415 }
1416
wil_tx_last_desc(struct vring_tx_desc * d)1417 static inline void wil_tx_last_desc(struct vring_tx_desc *d)
1418 {
1419 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_CMD_EOP_POS) |
1420 BIT(DMA_CFG_DESC_TX_0_CMD_MARK_WB_POS) |
1421 BIT(DMA_CFG_DESC_TX_0_CMD_DMA_IT_POS);
1422 }
1423
wil_set_tx_desc_last_tso(volatile struct vring_tx_desc * d)1424 static inline void wil_set_tx_desc_last_tso(volatile struct vring_tx_desc *d)
1425 {
1426 d->dma.d0 |= wil_tso_type_lst <<
1427 DMA_CFG_DESC_TX_0_SEGMENT_BUF_DETAILS_POS;
1428 }
1429
__wil_tx_vring_tso(struct wil6210_priv * wil,struct wil6210_vif * vif,struct wil_ring * vring,struct sk_buff * skb)1430 static int __wil_tx_vring_tso(struct wil6210_priv *wil, struct wil6210_vif *vif,
1431 struct wil_ring *vring, struct sk_buff *skb)
1432 {
1433 struct device *dev = wil_to_dev(wil);
1434
1435 /* point to descriptors in shared memory */
1436 volatile struct vring_tx_desc *_desc = NULL, *_hdr_desc,
1437 *_first_desc = NULL;
1438
1439 /* pointers to shadow descriptors */
1440 struct vring_tx_desc desc_mem, hdr_desc_mem, first_desc_mem,
1441 *d = &hdr_desc_mem, *hdr_desc = &hdr_desc_mem,
1442 *first_desc = &first_desc_mem;
1443
1444 /* pointer to shadow descriptors' context */
1445 struct wil_ctx *hdr_ctx, *first_ctx = NULL;
1446
1447 int descs_used = 0; /* total number of used descriptors */
1448 int sg_desc_cnt = 0; /* number of descriptors for current mss*/
1449
1450 u32 swhead = vring->swhead;
1451 int used, avail = wil_ring_avail_tx(vring);
1452 int nr_frags = skb_shinfo(skb)->nr_frags;
1453 int min_desc_required = nr_frags + 1;
1454 int mss = skb_shinfo(skb)->gso_size; /* payload size w/o headers */
1455 int f, len, hdrlen, headlen;
1456 int vring_index = vring - wil->ring_tx;
1457 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[vring_index];
1458 uint i = swhead;
1459 dma_addr_t pa;
1460 const skb_frag_t *frag = NULL;
1461 int rem_data = mss;
1462 int lenmss;
1463 int hdr_compensation_need = true;
1464 int desc_tso_type = wil_tso_type_first;
1465 bool is_ipv4;
1466 int tcp_hdr_len;
1467 int skb_net_hdr_len;
1468 int gso_type;
1469 int rc = -EINVAL;
1470
1471 wil_dbg_txrx(wil, "tx_vring_tso: %d bytes to vring %d\n", skb->len,
1472 vring_index);
1473
1474 if (unlikely(!txdata->enabled))
1475 return -EINVAL;
1476
1477 /* A typical page 4K is 3-4 payloads, we assume each fragment
1478 * is a full payload, that's how min_desc_required has been
1479 * calculated. In real we might need more or less descriptors,
1480 * this is the initial check only.
1481 */
1482 if (unlikely(avail < min_desc_required)) {
1483 wil_err_ratelimited(wil,
1484 "TSO: Tx ring[%2d] full. No space for %d fragments\n",
1485 vring_index, min_desc_required);
1486 return -ENOMEM;
1487 }
1488
1489 /* Header Length = MAC header len + IP header len + TCP header len*/
1490 hdrlen = ETH_HLEN +
1491 (int)skb_network_header_len(skb) +
1492 tcp_hdrlen(skb);
1493
1494 gso_type = skb_shinfo(skb)->gso_type & (SKB_GSO_TCPV6 | SKB_GSO_TCPV4);
1495 switch (gso_type) {
1496 case SKB_GSO_TCPV4:
1497 /* TCP v4, zero out the IP length and IPv4 checksum fields
1498 * as required by the offloading doc
1499 */
1500 ip_hdr(skb)->tot_len = 0;
1501 ip_hdr(skb)->check = 0;
1502 is_ipv4 = true;
1503 break;
1504 case SKB_GSO_TCPV6:
1505 /* TCP v6, zero out the payload length */
1506 ipv6_hdr(skb)->payload_len = 0;
1507 is_ipv4 = false;
1508 break;
1509 default:
1510 /* other than TCPv4 or TCPv6 types are not supported for TSO.
1511 * It is also illegal for both to be set simultaneously
1512 */
1513 return -EINVAL;
1514 }
1515
1516 if (skb->ip_summed != CHECKSUM_PARTIAL)
1517 return -EINVAL;
1518
1519 /* tcp header length and skb network header length are fixed for all
1520 * packet's descriptors - read then once here
1521 */
1522 tcp_hdr_len = tcp_hdrlen(skb);
1523 skb_net_hdr_len = skb_network_header_len(skb);
1524
1525 _hdr_desc = &vring->va[i].tx.legacy;
1526
1527 pa = dma_map_single(dev, skb->data, hdrlen, DMA_TO_DEVICE);
1528 if (unlikely(dma_mapping_error(dev, pa))) {
1529 wil_err(wil, "TSO: Skb head DMA map error\n");
1530 goto err_exit;
1531 }
1532
1533 wil->txrx_ops.tx_desc_map((union wil_tx_desc *)hdr_desc, pa,
1534 hdrlen, vring_index);
1535 wil_tx_desc_offload_setup_tso(hdr_desc, skb, wil_tso_type_hdr, is_ipv4,
1536 tcp_hdr_len, skb_net_hdr_len);
1537 wil_tx_last_desc(hdr_desc);
1538
1539 vring->ctx[i].mapped_as = wil_mapped_as_single;
1540 hdr_ctx = &vring->ctx[i];
1541
1542 descs_used++;
1543 headlen = skb_headlen(skb) - hdrlen;
1544
1545 for (f = headlen ? -1 : 0; f < nr_frags; f++) {
1546 if (headlen) {
1547 len = headlen;
1548 wil_dbg_txrx(wil, "TSO: process skb head, len %u\n",
1549 len);
1550 } else {
1551 frag = &skb_shinfo(skb)->frags[f];
1552 len = frag->size;
1553 wil_dbg_txrx(wil, "TSO: frag[%d]: len %u\n", f, len);
1554 }
1555
1556 while (len) {
1557 wil_dbg_txrx(wil,
1558 "TSO: len %d, rem_data %d, descs_used %d\n",
1559 len, rem_data, descs_used);
1560
1561 if (descs_used == avail) {
1562 wil_err_ratelimited(wil, "TSO: ring overflow\n");
1563 rc = -ENOMEM;
1564 goto mem_error;
1565 }
1566
1567 lenmss = min_t(int, rem_data, len);
1568 i = (swhead + descs_used) % vring->size;
1569 wil_dbg_txrx(wil, "TSO: lenmss %d, i %d\n", lenmss, i);
1570
1571 if (!headlen) {
1572 pa = skb_frag_dma_map(dev, frag,
1573 frag->size - len, lenmss,
1574 DMA_TO_DEVICE);
1575 vring->ctx[i].mapped_as = wil_mapped_as_page;
1576 } else {
1577 pa = dma_map_single(dev,
1578 skb->data +
1579 skb_headlen(skb) - headlen,
1580 lenmss,
1581 DMA_TO_DEVICE);
1582 vring->ctx[i].mapped_as = wil_mapped_as_single;
1583 headlen -= lenmss;
1584 }
1585
1586 if (unlikely(dma_mapping_error(dev, pa))) {
1587 wil_err(wil, "TSO: DMA map page error\n");
1588 goto mem_error;
1589 }
1590
1591 _desc = &vring->va[i].tx.legacy;
1592
1593 if (!_first_desc) {
1594 _first_desc = _desc;
1595 first_ctx = &vring->ctx[i];
1596 d = first_desc;
1597 } else {
1598 d = &desc_mem;
1599 }
1600
1601 wil->txrx_ops.tx_desc_map((union wil_tx_desc *)d,
1602 pa, lenmss, vring_index);
1603 wil_tx_desc_offload_setup_tso(d, skb, desc_tso_type,
1604 is_ipv4, tcp_hdr_len,
1605 skb_net_hdr_len);
1606
1607 /* use tso_type_first only once */
1608 desc_tso_type = wil_tso_type_mid;
1609
1610 descs_used++; /* desc used so far */
1611 sg_desc_cnt++; /* desc used for this segment */
1612 len -= lenmss;
1613 rem_data -= lenmss;
1614
1615 wil_dbg_txrx(wil,
1616 "TSO: len %d, rem_data %d, descs_used %d, sg_desc_cnt %d,\n",
1617 len, rem_data, descs_used, sg_desc_cnt);
1618
1619 /* Close the segment if reached mss size or last frag*/
1620 if (rem_data == 0 || (f == nr_frags - 1 && len == 0)) {
1621 if (hdr_compensation_need) {
1622 /* first segment include hdr desc for
1623 * release
1624 */
1625 hdr_ctx->nr_frags = sg_desc_cnt;
1626 wil_tx_desc_set_nr_frags(first_desc,
1627 sg_desc_cnt +
1628 1);
1629 hdr_compensation_need = false;
1630 } else {
1631 wil_tx_desc_set_nr_frags(first_desc,
1632 sg_desc_cnt);
1633 }
1634 first_ctx->nr_frags = sg_desc_cnt - 1;
1635
1636 wil_tx_last_desc(d);
1637
1638 /* first descriptor may also be the last
1639 * for this mss - make sure not to copy
1640 * it twice
1641 */
1642 if (first_desc != d)
1643 *_first_desc = *first_desc;
1644
1645 /*last descriptor will be copied at the end
1646 * of this TS processing
1647 */
1648 if (f < nr_frags - 1 || len > 0)
1649 *_desc = *d;
1650
1651 rem_data = mss;
1652 _first_desc = NULL;
1653 sg_desc_cnt = 0;
1654 } else if (first_desc != d) /* update mid descriptor */
1655 *_desc = *d;
1656 }
1657 }
1658
1659 /* first descriptor may also be the last.
1660 * in this case d pointer is invalid
1661 */
1662 if (_first_desc == _desc)
1663 d = first_desc;
1664
1665 /* Last data descriptor */
1666 wil_set_tx_desc_last_tso(d);
1667 *_desc = *d;
1668
1669 /* Fill the total number of descriptors in first desc (hdr)*/
1670 wil_tx_desc_set_nr_frags(hdr_desc, descs_used);
1671 *_hdr_desc = *hdr_desc;
1672
1673 /* hold reference to skb
1674 * to prevent skb release before accounting
1675 * in case of immediate "tx done"
1676 */
1677 vring->ctx[i].skb = skb_get(skb);
1678
1679 /* performance monitoring */
1680 used = wil_ring_used_tx(vring);
1681 if (wil_val_in_range(wil->ring_idle_trsh,
1682 used, used + descs_used)) {
1683 txdata->idle += get_cycles() - txdata->last_idle;
1684 wil_dbg_txrx(wil, "Ring[%2d] not idle %d -> %d\n",
1685 vring_index, used, used + descs_used);
1686 }
1687
1688 /* Make sure to advance the head only after descriptor update is done.
1689 * This will prevent a race condition where the completion thread
1690 * will see the DU bit set from previous run and will handle the
1691 * skb before it was completed.
1692 */
1693 wmb();
1694
1695 /* advance swhead */
1696 wil_ring_advance_head(vring, descs_used);
1697 wil_dbg_txrx(wil, "TSO: Tx swhead %d -> %d\n", swhead, vring->swhead);
1698
1699 /* make sure all writes to descriptors (shared memory) are done before
1700 * committing them to HW
1701 */
1702 wmb();
1703
1704 if (wil->tx_latency)
1705 *(ktime_t *)&skb->cb = ktime_get();
1706 else
1707 memset(skb->cb, 0, sizeof(ktime_t));
1708
1709 wil_w(wil, vring->hwtail, vring->swhead);
1710 return 0;
1711
1712 mem_error:
1713 while (descs_used > 0) {
1714 struct wil_ctx *ctx;
1715
1716 i = (swhead + descs_used - 1) % vring->size;
1717 d = (struct vring_tx_desc *)&vring->va[i].tx.legacy;
1718 _desc = &vring->va[i].tx.legacy;
1719 *d = *_desc;
1720 _desc->dma.status = TX_DMA_STATUS_DU;
1721 ctx = &vring->ctx[i];
1722 wil_txdesc_unmap(dev, (union wil_tx_desc *)d, ctx);
1723 memset(ctx, 0, sizeof(*ctx));
1724 descs_used--;
1725 }
1726 err_exit:
1727 return rc;
1728 }
1729
__wil_tx_ring(struct wil6210_priv * wil,struct wil6210_vif * vif,struct wil_ring * ring,struct sk_buff * skb)1730 static int __wil_tx_ring(struct wil6210_priv *wil, struct wil6210_vif *vif,
1731 struct wil_ring *ring, struct sk_buff *skb)
1732 {
1733 struct device *dev = wil_to_dev(wil);
1734 struct vring_tx_desc dd, *d = ⅆ
1735 volatile struct vring_tx_desc *_d;
1736 u32 swhead = ring->swhead;
1737 int avail = wil_ring_avail_tx(ring);
1738 int nr_frags = skb_shinfo(skb)->nr_frags;
1739 uint f = 0;
1740 int ring_index = ring - wil->ring_tx;
1741 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_index];
1742 uint i = swhead;
1743 dma_addr_t pa;
1744 int used;
1745 bool mcast = (ring_index == vif->bcast_ring);
1746 uint len = skb_headlen(skb);
1747
1748 wil_dbg_txrx(wil, "tx_ring: %d bytes to ring %d, nr_frags %d\n",
1749 skb->len, ring_index, nr_frags);
1750
1751 if (unlikely(!txdata->enabled))
1752 return -EINVAL;
1753
1754 if (unlikely(avail < 1 + nr_frags)) {
1755 wil_err_ratelimited(wil,
1756 "Tx ring[%2d] full. No space for %d fragments\n",
1757 ring_index, 1 + nr_frags);
1758 return -ENOMEM;
1759 }
1760 _d = &ring->va[i].tx.legacy;
1761
1762 pa = dma_map_single(dev, skb->data, skb_headlen(skb), DMA_TO_DEVICE);
1763
1764 wil_dbg_txrx(wil, "Tx[%2d] skb %d bytes 0x%p -> %pad\n", ring_index,
1765 skb_headlen(skb), skb->data, &pa);
1766 wil_hex_dump_txrx("Tx ", DUMP_PREFIX_OFFSET, 16, 1,
1767 skb->data, skb_headlen(skb), false);
1768
1769 if (unlikely(dma_mapping_error(dev, pa)))
1770 return -EINVAL;
1771 ring->ctx[i].mapped_as = wil_mapped_as_single;
1772 /* 1-st segment */
1773 wil->txrx_ops.tx_desc_map((union wil_tx_desc *)d, pa, len,
1774 ring_index);
1775 if (unlikely(mcast)) {
1776 d->mac.d[0] |= BIT(MAC_CFG_DESC_TX_0_MCS_EN_POS); /* MCS 0 */
1777 if (unlikely(len > WIL_BCAST_MCS0_LIMIT)) /* set MCS 1 */
1778 d->mac.d[0] |= (1 << MAC_CFG_DESC_TX_0_MCS_INDEX_POS);
1779 }
1780 /* Process TCP/UDP checksum offloading */
1781 if (unlikely(wil_tx_desc_offload_setup(d, skb))) {
1782 wil_err(wil, "Tx[%2d] Failed to set cksum, drop packet\n",
1783 ring_index);
1784 goto dma_error;
1785 }
1786
1787 ring->ctx[i].nr_frags = nr_frags;
1788 wil_tx_desc_set_nr_frags(d, nr_frags + 1);
1789
1790 /* middle segments */
1791 for (; f < nr_frags; f++) {
1792 const struct skb_frag_struct *frag =
1793 &skb_shinfo(skb)->frags[f];
1794 int len = skb_frag_size(frag);
1795
1796 *_d = *d;
1797 wil_dbg_txrx(wil, "Tx[%2d] desc[%4d]\n", ring_index, i);
1798 wil_hex_dump_txrx("TxD ", DUMP_PREFIX_NONE, 32, 4,
1799 (const void *)d, sizeof(*d), false);
1800 i = (swhead + f + 1) % ring->size;
1801 _d = &ring->va[i].tx.legacy;
1802 pa = skb_frag_dma_map(dev, frag, 0, skb_frag_size(frag),
1803 DMA_TO_DEVICE);
1804 if (unlikely(dma_mapping_error(dev, pa))) {
1805 wil_err(wil, "Tx[%2d] failed to map fragment\n",
1806 ring_index);
1807 goto dma_error;
1808 }
1809 ring->ctx[i].mapped_as = wil_mapped_as_page;
1810 wil->txrx_ops.tx_desc_map((union wil_tx_desc *)d,
1811 pa, len, ring_index);
1812 /* no need to check return code -
1813 * if it succeeded for 1-st descriptor,
1814 * it will succeed here too
1815 */
1816 wil_tx_desc_offload_setup(d, skb);
1817 }
1818 /* for the last seg only */
1819 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_CMD_EOP_POS);
1820 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_CMD_MARK_WB_POS);
1821 d->dma.d0 |= BIT(DMA_CFG_DESC_TX_0_CMD_DMA_IT_POS);
1822 *_d = *d;
1823 wil_dbg_txrx(wil, "Tx[%2d] desc[%4d]\n", ring_index, i);
1824 wil_hex_dump_txrx("TxD ", DUMP_PREFIX_NONE, 32, 4,
1825 (const void *)d, sizeof(*d), false);
1826
1827 /* hold reference to skb
1828 * to prevent skb release before accounting
1829 * in case of immediate "tx done"
1830 */
1831 ring->ctx[i].skb = skb_get(skb);
1832
1833 /* performance monitoring */
1834 used = wil_ring_used_tx(ring);
1835 if (wil_val_in_range(wil->ring_idle_trsh,
1836 used, used + nr_frags + 1)) {
1837 txdata->idle += get_cycles() - txdata->last_idle;
1838 wil_dbg_txrx(wil, "Ring[%2d] not idle %d -> %d\n",
1839 ring_index, used, used + nr_frags + 1);
1840 }
1841
1842 /* Make sure to advance the head only after descriptor update is done.
1843 * This will prevent a race condition where the completion thread
1844 * will see the DU bit set from previous run and will handle the
1845 * skb before it was completed.
1846 */
1847 wmb();
1848
1849 /* advance swhead */
1850 wil_ring_advance_head(ring, nr_frags + 1);
1851 wil_dbg_txrx(wil, "Tx[%2d] swhead %d -> %d\n", ring_index, swhead,
1852 ring->swhead);
1853 trace_wil6210_tx(ring_index, swhead, skb->len, nr_frags);
1854
1855 /* make sure all writes to descriptors (shared memory) are done before
1856 * committing them to HW
1857 */
1858 wmb();
1859
1860 if (wil->tx_latency)
1861 *(ktime_t *)&skb->cb = ktime_get();
1862 else
1863 memset(skb->cb, 0, sizeof(ktime_t));
1864
1865 wil_w(wil, ring->hwtail, ring->swhead);
1866
1867 return 0;
1868 dma_error:
1869 /* unmap what we have mapped */
1870 nr_frags = f + 1; /* frags mapped + one for skb head */
1871 for (f = 0; f < nr_frags; f++) {
1872 struct wil_ctx *ctx;
1873
1874 i = (swhead + f) % ring->size;
1875 ctx = &ring->ctx[i];
1876 _d = &ring->va[i].tx.legacy;
1877 *d = *_d;
1878 _d->dma.status = TX_DMA_STATUS_DU;
1879 wil->txrx_ops.tx_desc_unmap(dev,
1880 (union wil_tx_desc *)d,
1881 ctx);
1882
1883 memset(ctx, 0, sizeof(*ctx));
1884 }
1885
1886 return -EINVAL;
1887 }
1888
wil_tx_ring(struct wil6210_priv * wil,struct wil6210_vif * vif,struct wil_ring * ring,struct sk_buff * skb)1889 static int wil_tx_ring(struct wil6210_priv *wil, struct wil6210_vif *vif,
1890 struct wil_ring *ring, struct sk_buff *skb)
1891 {
1892 int ring_index = ring - wil->ring_tx;
1893 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ring_index];
1894 int rc;
1895
1896 spin_lock(&txdata->lock);
1897
1898 if (test_bit(wil_status_suspending, wil->status) ||
1899 test_bit(wil_status_suspended, wil->status) ||
1900 test_bit(wil_status_resuming, wil->status)) {
1901 wil_dbg_txrx(wil,
1902 "suspend/resume in progress. drop packet\n");
1903 spin_unlock(&txdata->lock);
1904 return -EINVAL;
1905 }
1906
1907 rc = (skb_is_gso(skb) ? wil->txrx_ops.tx_ring_tso : __wil_tx_ring)
1908 (wil, vif, ring, skb);
1909
1910 spin_unlock(&txdata->lock);
1911
1912 return rc;
1913 }
1914
1915 /**
1916 * Check status of tx vrings and stop/wake net queues if needed
1917 * It will start/stop net queues of a specific VIF net_device.
1918 *
1919 * This function does one of two checks:
1920 * In case check_stop is true, will check if net queues need to be stopped. If
1921 * the conditions for stopping are met, netif_tx_stop_all_queues() is called.
1922 * In case check_stop is false, will check if net queues need to be waked. If
1923 * the conditions for waking are met, netif_tx_wake_all_queues() is called.
1924 * vring is the vring which is currently being modified by either adding
1925 * descriptors (tx) into it or removing descriptors (tx complete) from it. Can
1926 * be null when irrelevant (e.g. connect/disconnect events).
1927 *
1928 * The implementation is to stop net queues if modified vring has low
1929 * descriptor availability. Wake if all vrings are not in low descriptor
1930 * availability and modified vring has high descriptor availability.
1931 */
__wil_update_net_queues(struct wil6210_priv * wil,struct wil6210_vif * vif,struct wil_ring * ring,bool check_stop)1932 static inline void __wil_update_net_queues(struct wil6210_priv *wil,
1933 struct wil6210_vif *vif,
1934 struct wil_ring *ring,
1935 bool check_stop)
1936 {
1937 int i;
1938
1939 if (unlikely(!vif))
1940 return;
1941
1942 if (ring)
1943 wil_dbg_txrx(wil, "vring %d, mid %d, check_stop=%d, stopped=%d",
1944 (int)(ring - wil->ring_tx), vif->mid, check_stop,
1945 vif->net_queue_stopped);
1946 else
1947 wil_dbg_txrx(wil, "check_stop=%d, mid=%d, stopped=%d",
1948 check_stop, vif->mid, vif->net_queue_stopped);
1949
1950 if (check_stop == vif->net_queue_stopped)
1951 /* net queues already in desired state */
1952 return;
1953
1954 if (check_stop) {
1955 if (!ring || unlikely(wil_ring_avail_low(ring))) {
1956 /* not enough room in the vring */
1957 netif_tx_stop_all_queues(vif_to_ndev(vif));
1958 vif->net_queue_stopped = true;
1959 wil_dbg_txrx(wil, "netif_tx_stop called\n");
1960 }
1961 return;
1962 }
1963
1964 /* Do not wake the queues in suspend flow */
1965 if (test_bit(wil_status_suspending, wil->status) ||
1966 test_bit(wil_status_suspended, wil->status))
1967 return;
1968
1969 /* check wake */
1970 for (i = 0; i < WIL6210_MAX_TX_RINGS; i++) {
1971 struct wil_ring *cur_ring = &wil->ring_tx[i];
1972 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[i];
1973
1974 if (txdata->mid != vif->mid || !cur_ring->va ||
1975 !txdata->enabled || cur_ring == ring)
1976 continue;
1977
1978 if (wil_ring_avail_low(cur_ring)) {
1979 wil_dbg_txrx(wil, "ring %d full, can't wake\n",
1980 (int)(cur_ring - wil->ring_tx));
1981 return;
1982 }
1983 }
1984
1985 if (!ring || wil_ring_avail_high(ring)) {
1986 /* enough room in the ring */
1987 wil_dbg_txrx(wil, "calling netif_tx_wake\n");
1988 netif_tx_wake_all_queues(vif_to_ndev(vif));
1989 vif->net_queue_stopped = false;
1990 }
1991 }
1992
wil_update_net_queues(struct wil6210_priv * wil,struct wil6210_vif * vif,struct wil_ring * ring,bool check_stop)1993 void wil_update_net_queues(struct wil6210_priv *wil, struct wil6210_vif *vif,
1994 struct wil_ring *ring, bool check_stop)
1995 {
1996 spin_lock(&wil->net_queue_lock);
1997 __wil_update_net_queues(wil, vif, ring, check_stop);
1998 spin_unlock(&wil->net_queue_lock);
1999 }
2000
wil_update_net_queues_bh(struct wil6210_priv * wil,struct wil6210_vif * vif,struct wil_ring * ring,bool check_stop)2001 void wil_update_net_queues_bh(struct wil6210_priv *wil, struct wil6210_vif *vif,
2002 struct wil_ring *ring, bool check_stop)
2003 {
2004 spin_lock_bh(&wil->net_queue_lock);
2005 __wil_update_net_queues(wil, vif, ring, check_stop);
2006 spin_unlock_bh(&wil->net_queue_lock);
2007 }
2008
wil_start_xmit(struct sk_buff * skb,struct net_device * ndev)2009 netdev_tx_t wil_start_xmit(struct sk_buff *skb, struct net_device *ndev)
2010 {
2011 struct wil6210_vif *vif = ndev_to_vif(ndev);
2012 struct wil6210_priv *wil = vif_to_wil(vif);
2013 struct ethhdr *eth = (void *)skb->data;
2014 bool bcast = is_multicast_ether_addr(eth->h_dest);
2015 struct wil_ring *ring;
2016 static bool pr_once_fw;
2017 int rc;
2018
2019 wil_dbg_txrx(wil, "start_xmit\n");
2020 if (unlikely(!test_bit(wil_status_fwready, wil->status))) {
2021 if (!pr_once_fw) {
2022 wil_err(wil, "FW not ready\n");
2023 pr_once_fw = true;
2024 }
2025 goto drop;
2026 }
2027 if (unlikely(!test_bit(wil_vif_fwconnected, vif->status))) {
2028 wil_dbg_ratelimited(wil,
2029 "VIF not connected, packet dropped\n");
2030 goto drop;
2031 }
2032 if (unlikely(vif->wdev.iftype == NL80211_IFTYPE_MONITOR)) {
2033 wil_err(wil, "Xmit in monitor mode not supported\n");
2034 goto drop;
2035 }
2036 pr_once_fw = false;
2037
2038 /* find vring */
2039 if (vif->wdev.iftype == NL80211_IFTYPE_STATION && !vif->pbss) {
2040 /* in STA mode (ESS), all to same VRING (to AP) */
2041 ring = wil_find_tx_ring_sta(wil, vif, skb);
2042 } else if (bcast) {
2043 if (vif->pbss)
2044 /* in pbss, no bcast VRING - duplicate skb in
2045 * all stations VRINGs
2046 */
2047 ring = wil_find_tx_bcast_2(wil, vif, skb);
2048 else if (vif->wdev.iftype == NL80211_IFTYPE_AP)
2049 /* AP has a dedicated bcast VRING */
2050 ring = wil_find_tx_bcast_1(wil, vif, skb);
2051 else
2052 /* unexpected combination, fallback to duplicating
2053 * the skb in all stations VRINGs
2054 */
2055 ring = wil_find_tx_bcast_2(wil, vif, skb);
2056 } else {
2057 /* unicast, find specific VRING by dest. address */
2058 ring = wil_find_tx_ucast(wil, vif, skb);
2059 }
2060 if (unlikely(!ring)) {
2061 wil_dbg_txrx(wil, "No Tx RING found for %pM\n", eth->h_dest);
2062 goto drop;
2063 }
2064 /* set up vring entry */
2065 rc = wil_tx_ring(wil, vif, ring, skb);
2066
2067 switch (rc) {
2068 case 0:
2069 /* shall we stop net queues? */
2070 wil_update_net_queues_bh(wil, vif, ring, true);
2071 /* statistics will be updated on the tx_complete */
2072 dev_kfree_skb_any(skb);
2073 return NETDEV_TX_OK;
2074 case -ENOMEM:
2075 return NETDEV_TX_BUSY;
2076 default:
2077 break; /* goto drop; */
2078 }
2079 drop:
2080 ndev->stats.tx_dropped++;
2081 dev_kfree_skb_any(skb);
2082
2083 return NET_XMIT_DROP;
2084 }
2085
wil_tx_latency_calc(struct wil6210_priv * wil,struct sk_buff * skb,struct wil_sta_info * sta)2086 void wil_tx_latency_calc(struct wil6210_priv *wil, struct sk_buff *skb,
2087 struct wil_sta_info *sta)
2088 {
2089 int skb_time_us;
2090 int bin;
2091
2092 if (!wil->tx_latency)
2093 return;
2094
2095 if (ktime_to_ms(*(ktime_t *)&skb->cb) == 0)
2096 return;
2097
2098 skb_time_us = ktime_us_delta(ktime_get(), *(ktime_t *)&skb->cb);
2099 bin = skb_time_us / wil->tx_latency_res;
2100 bin = min_t(int, bin, WIL_NUM_LATENCY_BINS - 1);
2101
2102 wil_dbg_txrx(wil, "skb time %dus => bin %d\n", skb_time_us, bin);
2103 sta->tx_latency_bins[bin]++;
2104 sta->stats.tx_latency_total_us += skb_time_us;
2105 if (skb_time_us < sta->stats.tx_latency_min_us)
2106 sta->stats.tx_latency_min_us = skb_time_us;
2107 if (skb_time_us > sta->stats.tx_latency_max_us)
2108 sta->stats.tx_latency_max_us = skb_time_us;
2109 }
2110
2111 /**
2112 * Clean up transmitted skb's from the Tx VRING
2113 *
2114 * Return number of descriptors cleared
2115 *
2116 * Safe to call from IRQ
2117 */
wil_tx_complete(struct wil6210_vif * vif,int ringid)2118 int wil_tx_complete(struct wil6210_vif *vif, int ringid)
2119 {
2120 struct wil6210_priv *wil = vif_to_wil(vif);
2121 struct net_device *ndev = vif_to_ndev(vif);
2122 struct device *dev = wil_to_dev(wil);
2123 struct wil_ring *vring = &wil->ring_tx[ringid];
2124 struct wil_ring_tx_data *txdata = &wil->ring_tx_data[ringid];
2125 int done = 0;
2126 int cid = wil->ring2cid_tid[ringid][0];
2127 struct wil_net_stats *stats = NULL;
2128 volatile struct vring_tx_desc *_d;
2129 int used_before_complete;
2130 int used_new;
2131
2132 if (unlikely(!vring->va)) {
2133 wil_err(wil, "Tx irq[%d]: vring not initialized\n", ringid);
2134 return 0;
2135 }
2136
2137 if (unlikely(!txdata->enabled)) {
2138 wil_info(wil, "Tx irq[%d]: vring disabled\n", ringid);
2139 return 0;
2140 }
2141
2142 wil_dbg_txrx(wil, "tx_complete: (%d)\n", ringid);
2143
2144 used_before_complete = wil_ring_used_tx(vring);
2145
2146 if (cid < WIL6210_MAX_CID)
2147 stats = &wil->sta[cid].stats;
2148
2149 while (!wil_ring_is_empty(vring)) {
2150 int new_swtail;
2151 struct wil_ctx *ctx = &vring->ctx[vring->swtail];
2152 /**
2153 * For the fragmented skb, HW will set DU bit only for the
2154 * last fragment. look for it.
2155 * In TSO the first DU will include hdr desc
2156 */
2157 int lf = (vring->swtail + ctx->nr_frags) % vring->size;
2158 /* TODO: check we are not past head */
2159
2160 _d = &vring->va[lf].tx.legacy;
2161 if (unlikely(!(_d->dma.status & TX_DMA_STATUS_DU)))
2162 break;
2163
2164 new_swtail = (lf + 1) % vring->size;
2165 while (vring->swtail != new_swtail) {
2166 struct vring_tx_desc dd, *d = ⅆ
2167 u16 dmalen;
2168 struct sk_buff *skb;
2169
2170 ctx = &vring->ctx[vring->swtail];
2171 skb = ctx->skb;
2172 _d = &vring->va[vring->swtail].tx.legacy;
2173
2174 *d = *_d;
2175
2176 dmalen = le16_to_cpu(d->dma.length);
2177 trace_wil6210_tx_done(ringid, vring->swtail, dmalen,
2178 d->dma.error);
2179 wil_dbg_txrx(wil,
2180 "TxC[%2d][%3d] : %d bytes, status 0x%02x err 0x%02x\n",
2181 ringid, vring->swtail, dmalen,
2182 d->dma.status, d->dma.error);
2183 wil_hex_dump_txrx("TxCD ", DUMP_PREFIX_NONE, 32, 4,
2184 (const void *)d, sizeof(*d), false);
2185
2186 wil->txrx_ops.tx_desc_unmap(dev,
2187 (union wil_tx_desc *)d,
2188 ctx);
2189
2190 if (skb) {
2191 if (likely(d->dma.error == 0)) {
2192 ndev->stats.tx_packets++;
2193 ndev->stats.tx_bytes += skb->len;
2194 if (stats) {
2195 stats->tx_packets++;
2196 stats->tx_bytes += skb->len;
2197
2198 wil_tx_latency_calc(wil, skb,
2199 &wil->sta[cid]);
2200 }
2201 } else {
2202 ndev->stats.tx_errors++;
2203 if (stats)
2204 stats->tx_errors++;
2205 }
2206 wil_consume_skb(skb, d->dma.error == 0);
2207 }
2208 memset(ctx, 0, sizeof(*ctx));
2209 /* Make sure the ctx is zeroed before updating the tail
2210 * to prevent a case where wil_tx_ring will see
2211 * this descriptor as used and handle it before ctx zero
2212 * is completed.
2213 */
2214 wmb();
2215 /* There is no need to touch HW descriptor:
2216 * - ststus bit TX_DMA_STATUS_DU is set by design,
2217 * so hardware will not try to process this desc.,
2218 * - rest of descriptor will be initialized on Tx.
2219 */
2220 vring->swtail = wil_ring_next_tail(vring);
2221 done++;
2222 }
2223 }
2224
2225 /* performance monitoring */
2226 used_new = wil_ring_used_tx(vring);
2227 if (wil_val_in_range(wil->ring_idle_trsh,
2228 used_new, used_before_complete)) {
2229 wil_dbg_txrx(wil, "Ring[%2d] idle %d -> %d\n",
2230 ringid, used_before_complete, used_new);
2231 txdata->last_idle = get_cycles();
2232 }
2233
2234 /* shall we wake net queues? */
2235 if (done)
2236 wil_update_net_queues(wil, vif, vring, false);
2237
2238 return done;
2239 }
2240
wil_tx_init(struct wil6210_priv * wil)2241 static inline int wil_tx_init(struct wil6210_priv *wil)
2242 {
2243 return 0;
2244 }
2245
wil_tx_fini(struct wil6210_priv * wil)2246 static inline void wil_tx_fini(struct wil6210_priv *wil) {}
2247
wil_get_reorder_params(struct wil6210_priv * wil,struct sk_buff * skb,int * tid,int * cid,int * mid,u16 * seq,int * mcast,int * retry)2248 static void wil_get_reorder_params(struct wil6210_priv *wil,
2249 struct sk_buff *skb, int *tid, int *cid,
2250 int *mid, u16 *seq, int *mcast, int *retry)
2251 {
2252 struct vring_rx_desc *d = wil_skb_rxdesc(skb);
2253
2254 *tid = wil_rxdesc_tid(d);
2255 *cid = wil_rxdesc_cid(d);
2256 *mid = wil_rxdesc_mid(d);
2257 *seq = wil_rxdesc_seq(d);
2258 *mcast = wil_rxdesc_mcast(d);
2259 *retry = wil_rxdesc_retry(d);
2260 }
2261
wil_init_txrx_ops_legacy_dma(struct wil6210_priv * wil)2262 void wil_init_txrx_ops_legacy_dma(struct wil6210_priv *wil)
2263 {
2264 wil->txrx_ops.configure_interrupt_moderation =
2265 wil_configure_interrupt_moderation;
2266 /* TX ops */
2267 wil->txrx_ops.tx_desc_map = wil_tx_desc_map;
2268 wil->txrx_ops.tx_desc_unmap = wil_txdesc_unmap;
2269 wil->txrx_ops.tx_ring_tso = __wil_tx_vring_tso;
2270 wil->txrx_ops.ring_init_tx = wil_vring_init_tx;
2271 wil->txrx_ops.ring_fini_tx = wil_vring_free;
2272 wil->txrx_ops.ring_init_bcast = wil_vring_init_bcast;
2273 wil->txrx_ops.tx_init = wil_tx_init;
2274 wil->txrx_ops.tx_fini = wil_tx_fini;
2275 /* RX ops */
2276 wil->txrx_ops.rx_init = wil_rx_init;
2277 wil->txrx_ops.wmi_addba_rx_resp = wmi_addba_rx_resp;
2278 wil->txrx_ops.get_reorder_params = wil_get_reorder_params;
2279 wil->txrx_ops.get_netif_rx_params =
2280 wil_get_netif_rx_params;
2281 wil->txrx_ops.rx_crypto_check = wil_rx_crypto_check;
2282 wil->txrx_ops.rx_error_check = wil_rx_error_check;
2283 wil->txrx_ops.is_rx_idle = wil_is_rx_idle;
2284 wil->txrx_ops.rx_fini = wil_rx_fini;
2285 }
2286
