1 /*
2 * Copyright (c) 2016 Qualcomm Atheros, Inc. All rights reserved.
3 * Copyright (c) 2015 The Linux Foundation. All rights reserved.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18 #ifndef _AHB_H_
19 #define _AHB_H_
20
21 #include <linux/platform_device.h>
22
23 struct ath10k_ahb {
24 struct platform_device *pdev;
25 void __iomem *mem;
26 unsigned long mem_len;
27 void __iomem *gcc_mem;
28 void __iomem *tcsr_mem;
29
30 int irq;
31
32 struct clk *cmd_clk;
33 struct clk *ref_clk;
34 struct clk *rtc_clk;
35
36 struct reset_control *core_cold_rst;
37 struct reset_control *radio_cold_rst;
38 struct reset_control *radio_warm_rst;
39 struct reset_control *radio_srif_rst;
40 struct reset_control *cpu_init_rst;
41 };
42
43 #ifdef CONFIG_ATH10K_AHB
44
45 #define ATH10K_GCC_REG_BASE 0x1800000
46 #define ATH10K_GCC_REG_SIZE 0x60000
47
48 #define ATH10K_TCSR_REG_BASE 0x1900000
49 #define ATH10K_TCSR_REG_SIZE 0x80000
50
51 #define ATH10K_AHB_GCC_FEPLL_PLL_DIV 0x2f020
52 #define ATH10K_AHB_WIFI_SCRATCH_5_REG 0x4f014
53
54 #define ATH10K_AHB_WLAN_CORE_ID_REG 0x82030
55
56 #define ATH10K_AHB_TCSR_WIFI0_GLB_CFG 0x49000
57 #define ATH10K_AHB_TCSR_WIFI1_GLB_CFG 0x49004
58 #define TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK BIT(25)
59
60 #define ATH10K_AHB_TCSR_WCSS0_HALTREQ 0x52000
61 #define ATH10K_AHB_TCSR_WCSS1_HALTREQ 0x52010
62 #define ATH10K_AHB_TCSR_WCSS0_HALTACK 0x52004
63 #define ATH10K_AHB_TCSR_WCSS1_HALTACK 0x52014
64
65 #define ATH10K_AHB_AXI_BUS_HALT_TIMEOUT 10 /* msec */
66 #define AHB_AXI_BUS_HALT_REQ 1
67 #define AHB_AXI_BUS_HALT_ACK 1
68
69 #define ATH10K_AHB_CORE_CTRL_CPU_INTR_MASK 1
70
71 int ath10k_ahb_init(void);
72 void ath10k_ahb_exit(void);
73
74 #else /* CONFIG_ATH10K_AHB */
75
ath10k_ahb_init(void)76 static inline int ath10k_ahb_init(void)
77 {
78 return 0;
79 }
80
ath10k_ahb_exit(void)81 static inline void ath10k_ahb_exit(void)
82 {
83 }
84
85 #endif /* CONFIG_ATH10K_AHB */
86
87 #endif /* _AHB_H_ */
88
