1 /*
2 * Copyright (c) 2016-2017 Qualcomm Atheros, Inc. All rights reserved.
3 * Copyright (c) 2015 The Linux Foundation. All rights reserved.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17 #include <linux/module.h>
18 #include <linux/of.h>
19 #include <linux/of_device.h>
20 #include <linux/clk.h>
21 #include <linux/reset.h>
22 #include "core.h"
23 #include "debug.h"
24 #include "pci.h"
25 #include "ahb.h"
26
27 static const struct of_device_id ath10k_ahb_of_match[] = {
28 { .compatible = "qcom,ipq4019-wifi",
29 .data = (void *)ATH10K_HW_QCA4019
30 },
31 { }
32 };
33
34 MODULE_DEVICE_TABLE(of, ath10k_ahb_of_match);
35
36 #define QCA4019_SRAM_ADDR 0x000C0000
37 #define QCA4019_SRAM_LEN 0x00040000 /* 256 kb */
38
ath10k_ahb_priv(struct ath10k * ar)39 static inline struct ath10k_ahb *ath10k_ahb_priv(struct ath10k *ar)
40 {
41 return &((struct ath10k_pci *)ar->drv_priv)->ahb[0];
42 }
43
ath10k_ahb_write32(struct ath10k * ar,u32 offset,u32 value)44 static void ath10k_ahb_write32(struct ath10k *ar, u32 offset, u32 value)
45 {
46 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
47
48 iowrite32(value, ar_ahb->mem + offset);
49 }
50
ath10k_ahb_read32(struct ath10k * ar,u32 offset)51 static u32 ath10k_ahb_read32(struct ath10k *ar, u32 offset)
52 {
53 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
54
55 return ioread32(ar_ahb->mem + offset);
56 }
57
ath10k_ahb_gcc_read32(struct ath10k * ar,u32 offset)58 static u32 ath10k_ahb_gcc_read32(struct ath10k *ar, u32 offset)
59 {
60 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
61
62 return ioread32(ar_ahb->gcc_mem + offset);
63 }
64
ath10k_ahb_tcsr_write32(struct ath10k * ar,u32 offset,u32 value)65 static void ath10k_ahb_tcsr_write32(struct ath10k *ar, u32 offset, u32 value)
66 {
67 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
68
69 iowrite32(value, ar_ahb->tcsr_mem + offset);
70 }
71
ath10k_ahb_tcsr_read32(struct ath10k * ar,u32 offset)72 static u32 ath10k_ahb_tcsr_read32(struct ath10k *ar, u32 offset)
73 {
74 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
75
76 return ioread32(ar_ahb->tcsr_mem + offset);
77 }
78
ath10k_ahb_soc_read32(struct ath10k * ar,u32 addr)79 static u32 ath10k_ahb_soc_read32(struct ath10k *ar, u32 addr)
80 {
81 return ath10k_ahb_read32(ar, RTC_SOC_BASE_ADDRESS + addr);
82 }
83
ath10k_ahb_get_num_banks(struct ath10k * ar)84 static int ath10k_ahb_get_num_banks(struct ath10k *ar)
85 {
86 if (ar->hw_rev == ATH10K_HW_QCA4019)
87 return 1;
88
89 ath10k_warn(ar, "unknown number of banks, assuming 1\n");
90 return 1;
91 }
92
ath10k_ahb_clock_init(struct ath10k * ar)93 static int ath10k_ahb_clock_init(struct ath10k *ar)
94 {
95 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
96 struct device *dev;
97
98 dev = &ar_ahb->pdev->dev;
99
100 ar_ahb->cmd_clk = devm_clk_get(dev, "wifi_wcss_cmd");
101 if (IS_ERR_OR_NULL(ar_ahb->cmd_clk)) {
102 ath10k_err(ar, "failed to get cmd clk: %ld\n",
103 PTR_ERR(ar_ahb->cmd_clk));
104 return ar_ahb->cmd_clk ? PTR_ERR(ar_ahb->cmd_clk) : -ENODEV;
105 }
106
107 ar_ahb->ref_clk = devm_clk_get(dev, "wifi_wcss_ref");
108 if (IS_ERR_OR_NULL(ar_ahb->ref_clk)) {
109 ath10k_err(ar, "failed to get ref clk: %ld\n",
110 PTR_ERR(ar_ahb->ref_clk));
111 return ar_ahb->ref_clk ? PTR_ERR(ar_ahb->ref_clk) : -ENODEV;
112 }
113
114 ar_ahb->rtc_clk = devm_clk_get(dev, "wifi_wcss_rtc");
115 if (IS_ERR_OR_NULL(ar_ahb->rtc_clk)) {
116 ath10k_err(ar, "failed to get rtc clk: %ld\n",
117 PTR_ERR(ar_ahb->rtc_clk));
118 return ar_ahb->rtc_clk ? PTR_ERR(ar_ahb->rtc_clk) : -ENODEV;
119 }
120
121 return 0;
122 }
123
ath10k_ahb_clock_deinit(struct ath10k * ar)124 static void ath10k_ahb_clock_deinit(struct ath10k *ar)
125 {
126 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
127
128 ar_ahb->cmd_clk = NULL;
129 ar_ahb->ref_clk = NULL;
130 ar_ahb->rtc_clk = NULL;
131 }
132
ath10k_ahb_clock_enable(struct ath10k * ar)133 static int ath10k_ahb_clock_enable(struct ath10k *ar)
134 {
135 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
136 int ret;
137
138 if (IS_ERR_OR_NULL(ar_ahb->cmd_clk) ||
139 IS_ERR_OR_NULL(ar_ahb->ref_clk) ||
140 IS_ERR_OR_NULL(ar_ahb->rtc_clk)) {
141 ath10k_err(ar, "clock(s) is/are not initialized\n");
142 ret = -EIO;
143 goto out;
144 }
145
146 ret = clk_prepare_enable(ar_ahb->cmd_clk);
147 if (ret) {
148 ath10k_err(ar, "failed to enable cmd clk: %d\n", ret);
149 goto out;
150 }
151
152 ret = clk_prepare_enable(ar_ahb->ref_clk);
153 if (ret) {
154 ath10k_err(ar, "failed to enable ref clk: %d\n", ret);
155 goto err_cmd_clk_disable;
156 }
157
158 ret = clk_prepare_enable(ar_ahb->rtc_clk);
159 if (ret) {
160 ath10k_err(ar, "failed to enable rtc clk: %d\n", ret);
161 goto err_ref_clk_disable;
162 }
163
164 return 0;
165
166 err_ref_clk_disable:
167 clk_disable_unprepare(ar_ahb->ref_clk);
168
169 err_cmd_clk_disable:
170 clk_disable_unprepare(ar_ahb->cmd_clk);
171
172 out:
173 return ret;
174 }
175
ath10k_ahb_clock_disable(struct ath10k * ar)176 static void ath10k_ahb_clock_disable(struct ath10k *ar)
177 {
178 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
179
180 clk_disable_unprepare(ar_ahb->cmd_clk);
181
182 clk_disable_unprepare(ar_ahb->ref_clk);
183
184 clk_disable_unprepare(ar_ahb->rtc_clk);
185 }
186
ath10k_ahb_rst_ctrl_init(struct ath10k * ar)187 static int ath10k_ahb_rst_ctrl_init(struct ath10k *ar)
188 {
189 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
190 struct device *dev;
191
192 dev = &ar_ahb->pdev->dev;
193
194 ar_ahb->core_cold_rst = devm_reset_control_get_exclusive(dev,
195 "wifi_core_cold");
196 if (IS_ERR(ar_ahb->core_cold_rst)) {
197 ath10k_err(ar, "failed to get core cold rst ctrl: %ld\n",
198 PTR_ERR(ar_ahb->core_cold_rst));
199 return PTR_ERR(ar_ahb->core_cold_rst);
200 }
201
202 ar_ahb->radio_cold_rst = devm_reset_control_get_exclusive(dev,
203 "wifi_radio_cold");
204 if (IS_ERR(ar_ahb->radio_cold_rst)) {
205 ath10k_err(ar, "failed to get radio cold rst ctrl: %ld\n",
206 PTR_ERR(ar_ahb->radio_cold_rst));
207 return PTR_ERR(ar_ahb->radio_cold_rst);
208 }
209
210 ar_ahb->radio_warm_rst = devm_reset_control_get_exclusive(dev,
211 "wifi_radio_warm");
212 if (IS_ERR(ar_ahb->radio_warm_rst)) {
213 ath10k_err(ar, "failed to get radio warm rst ctrl: %ld\n",
214 PTR_ERR(ar_ahb->radio_warm_rst));
215 return PTR_ERR(ar_ahb->radio_warm_rst);
216 }
217
218 ar_ahb->radio_srif_rst = devm_reset_control_get_exclusive(dev,
219 "wifi_radio_srif");
220 if (IS_ERR(ar_ahb->radio_srif_rst)) {
221 ath10k_err(ar, "failed to get radio srif rst ctrl: %ld\n",
222 PTR_ERR(ar_ahb->radio_srif_rst));
223 return PTR_ERR(ar_ahb->radio_srif_rst);
224 }
225
226 ar_ahb->cpu_init_rst = devm_reset_control_get_exclusive(dev,
227 "wifi_cpu_init");
228 if (IS_ERR(ar_ahb->cpu_init_rst)) {
229 ath10k_err(ar, "failed to get cpu init rst ctrl: %ld\n",
230 PTR_ERR(ar_ahb->cpu_init_rst));
231 return PTR_ERR(ar_ahb->cpu_init_rst);
232 }
233
234 return 0;
235 }
236
ath10k_ahb_rst_ctrl_deinit(struct ath10k * ar)237 static void ath10k_ahb_rst_ctrl_deinit(struct ath10k *ar)
238 {
239 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
240
241 ar_ahb->core_cold_rst = NULL;
242 ar_ahb->radio_cold_rst = NULL;
243 ar_ahb->radio_warm_rst = NULL;
244 ar_ahb->radio_srif_rst = NULL;
245 ar_ahb->cpu_init_rst = NULL;
246 }
247
ath10k_ahb_release_reset(struct ath10k * ar)248 static int ath10k_ahb_release_reset(struct ath10k *ar)
249 {
250 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
251 int ret;
252
253 if (IS_ERR_OR_NULL(ar_ahb->radio_cold_rst) ||
254 IS_ERR_OR_NULL(ar_ahb->radio_warm_rst) ||
255 IS_ERR_OR_NULL(ar_ahb->radio_srif_rst) ||
256 IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) {
257 ath10k_err(ar, "rst ctrl(s) is/are not initialized\n");
258 return -EINVAL;
259 }
260
261 ret = reset_control_deassert(ar_ahb->radio_cold_rst);
262 if (ret) {
263 ath10k_err(ar, "failed to deassert radio cold rst: %d\n", ret);
264 return ret;
265 }
266
267 ret = reset_control_deassert(ar_ahb->radio_warm_rst);
268 if (ret) {
269 ath10k_err(ar, "failed to deassert radio warm rst: %d\n", ret);
270 return ret;
271 }
272
273 ret = reset_control_deassert(ar_ahb->radio_srif_rst);
274 if (ret) {
275 ath10k_err(ar, "failed to deassert radio srif rst: %d\n", ret);
276 return ret;
277 }
278
279 ret = reset_control_deassert(ar_ahb->cpu_init_rst);
280 if (ret) {
281 ath10k_err(ar, "failed to deassert cpu init rst: %d\n", ret);
282 return ret;
283 }
284
285 return 0;
286 }
287
ath10k_ahb_halt_axi_bus(struct ath10k * ar,u32 haltreq_reg,u32 haltack_reg)288 static void ath10k_ahb_halt_axi_bus(struct ath10k *ar, u32 haltreq_reg,
289 u32 haltack_reg)
290 {
291 unsigned long timeout;
292 u32 val;
293
294 /* Issue halt axi bus request */
295 val = ath10k_ahb_tcsr_read32(ar, haltreq_reg);
296 val |= AHB_AXI_BUS_HALT_REQ;
297 ath10k_ahb_tcsr_write32(ar, haltreq_reg, val);
298
299 /* Wait for axi bus halted ack */
300 timeout = jiffies + msecs_to_jiffies(ATH10K_AHB_AXI_BUS_HALT_TIMEOUT);
301 do {
302 val = ath10k_ahb_tcsr_read32(ar, haltack_reg);
303 if (val & AHB_AXI_BUS_HALT_ACK)
304 break;
305
306 mdelay(1);
307 } while (time_before(jiffies, timeout));
308
309 if (!(val & AHB_AXI_BUS_HALT_ACK)) {
310 ath10k_err(ar, "failed to halt axi bus: %d\n", val);
311 return;
312 }
313
314 ath10k_dbg(ar, ATH10K_DBG_AHB, "axi bus halted\n");
315 }
316
ath10k_ahb_halt_chip(struct ath10k * ar)317 static void ath10k_ahb_halt_chip(struct ath10k *ar)
318 {
319 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
320 u32 core_id, glb_cfg_reg, haltreq_reg, haltack_reg;
321 u32 val;
322 int ret;
323
324 if (IS_ERR_OR_NULL(ar_ahb->core_cold_rst) ||
325 IS_ERR_OR_NULL(ar_ahb->radio_cold_rst) ||
326 IS_ERR_OR_NULL(ar_ahb->radio_warm_rst) ||
327 IS_ERR_OR_NULL(ar_ahb->radio_srif_rst) ||
328 IS_ERR_OR_NULL(ar_ahb->cpu_init_rst)) {
329 ath10k_err(ar, "rst ctrl(s) is/are not initialized\n");
330 return;
331 }
332
333 core_id = ath10k_ahb_read32(ar, ATH10K_AHB_WLAN_CORE_ID_REG);
334
335 switch (core_id) {
336 case 0:
337 glb_cfg_reg = ATH10K_AHB_TCSR_WIFI0_GLB_CFG;
338 haltreq_reg = ATH10K_AHB_TCSR_WCSS0_HALTREQ;
339 haltack_reg = ATH10K_AHB_TCSR_WCSS0_HALTACK;
340 break;
341 case 1:
342 glb_cfg_reg = ATH10K_AHB_TCSR_WIFI1_GLB_CFG;
343 haltreq_reg = ATH10K_AHB_TCSR_WCSS1_HALTREQ;
344 haltack_reg = ATH10K_AHB_TCSR_WCSS1_HALTACK;
345 break;
346 default:
347 ath10k_err(ar, "invalid core id %d found, skipping reset sequence\n",
348 core_id);
349 return;
350 }
351
352 ath10k_ahb_halt_axi_bus(ar, haltreq_reg, haltack_reg);
353
354 val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg);
355 val |= TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK;
356 ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val);
357
358 ret = reset_control_assert(ar_ahb->core_cold_rst);
359 if (ret)
360 ath10k_err(ar, "failed to assert core cold rst: %d\n", ret);
361 msleep(1);
362
363 ret = reset_control_assert(ar_ahb->radio_cold_rst);
364 if (ret)
365 ath10k_err(ar, "failed to assert radio cold rst: %d\n", ret);
366 msleep(1);
367
368 ret = reset_control_assert(ar_ahb->radio_warm_rst);
369 if (ret)
370 ath10k_err(ar, "failed to assert radio warm rst: %d\n", ret);
371 msleep(1);
372
373 ret = reset_control_assert(ar_ahb->radio_srif_rst);
374 if (ret)
375 ath10k_err(ar, "failed to assert radio srif rst: %d\n", ret);
376 msleep(1);
377
378 ret = reset_control_assert(ar_ahb->cpu_init_rst);
379 if (ret)
380 ath10k_err(ar, "failed to assert cpu init rst: %d\n", ret);
381 msleep(10);
382
383 /* Clear halt req and core clock disable req before
384 * deasserting wifi core reset.
385 */
386 val = ath10k_ahb_tcsr_read32(ar, haltreq_reg);
387 val &= ~AHB_AXI_BUS_HALT_REQ;
388 ath10k_ahb_tcsr_write32(ar, haltreq_reg, val);
389
390 val = ath10k_ahb_tcsr_read32(ar, glb_cfg_reg);
391 val &= ~TCSR_WIFIX_GLB_CFG_DISABLE_CORE_CLK;
392 ath10k_ahb_tcsr_write32(ar, glb_cfg_reg, val);
393
394 ret = reset_control_deassert(ar_ahb->core_cold_rst);
395 if (ret)
396 ath10k_err(ar, "failed to deassert core cold rst: %d\n", ret);
397
398 ath10k_dbg(ar, ATH10K_DBG_AHB, "core %d reset done\n", core_id);
399 }
400
ath10k_ahb_interrupt_handler(int irq,void * arg)401 static irqreturn_t ath10k_ahb_interrupt_handler(int irq, void *arg)
402 {
403 struct ath10k *ar = arg;
404
405 if (!ath10k_pci_irq_pending(ar))
406 return IRQ_NONE;
407
408 ath10k_pci_disable_and_clear_legacy_irq(ar);
409 ath10k_pci_irq_msi_fw_mask(ar);
410 napi_schedule(&ar->napi);
411
412 return IRQ_HANDLED;
413 }
414
ath10k_ahb_request_irq_legacy(struct ath10k * ar)415 static int ath10k_ahb_request_irq_legacy(struct ath10k *ar)
416 {
417 struct ath10k_pci *ar_pci = ath10k_pci_priv(ar);
418 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
419 int ret;
420
421 ret = request_irq(ar_ahb->irq,
422 ath10k_ahb_interrupt_handler,
423 IRQF_SHARED, "ath10k_ahb", ar);
424 if (ret) {
425 ath10k_warn(ar, "failed to request legacy irq %d: %d\n",
426 ar_ahb->irq, ret);
427 return ret;
428 }
429 ar_pci->oper_irq_mode = ATH10K_PCI_IRQ_LEGACY;
430
431 return 0;
432 }
433
ath10k_ahb_release_irq_legacy(struct ath10k * ar)434 static void ath10k_ahb_release_irq_legacy(struct ath10k *ar)
435 {
436 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
437
438 free_irq(ar_ahb->irq, ar);
439 }
440
ath10k_ahb_irq_disable(struct ath10k * ar)441 static void ath10k_ahb_irq_disable(struct ath10k *ar)
442 {
443 ath10k_ce_disable_interrupts(ar);
444 ath10k_pci_disable_and_clear_legacy_irq(ar);
445 }
446
ath10k_ahb_resource_init(struct ath10k * ar)447 static int ath10k_ahb_resource_init(struct ath10k *ar)
448 {
449 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
450 struct platform_device *pdev;
451 struct resource *res;
452 int ret;
453
454 pdev = ar_ahb->pdev;
455
456 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
457 if (!res) {
458 ath10k_err(ar, "failed to get memory resource\n");
459 ret = -ENXIO;
460 goto out;
461 }
462
463 ar_ahb->mem = devm_ioremap_resource(&pdev->dev, res);
464 if (IS_ERR(ar_ahb->mem)) {
465 ath10k_err(ar, "mem ioremap error\n");
466 ret = PTR_ERR(ar_ahb->mem);
467 goto out;
468 }
469
470 ar_ahb->mem_len = resource_size(res);
471
472 ar_ahb->gcc_mem = ioremap_nocache(ATH10K_GCC_REG_BASE,
473 ATH10K_GCC_REG_SIZE);
474 if (!ar_ahb->gcc_mem) {
475 ath10k_err(ar, "gcc mem ioremap error\n");
476 ret = -ENOMEM;
477 goto err_mem_unmap;
478 }
479
480 ar_ahb->tcsr_mem = ioremap_nocache(ATH10K_TCSR_REG_BASE,
481 ATH10K_TCSR_REG_SIZE);
482 if (!ar_ahb->tcsr_mem) {
483 ath10k_err(ar, "tcsr mem ioremap error\n");
484 ret = -ENOMEM;
485 goto err_gcc_mem_unmap;
486 }
487
488 ret = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
489 if (ret) {
490 ath10k_err(ar, "failed to set 32-bit dma mask: %d\n", ret);
491 goto err_tcsr_mem_unmap;
492 }
493
494 ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
495 if (ret) {
496 ath10k_err(ar, "failed to set 32-bit consistent dma: %d\n",
497 ret);
498 goto err_tcsr_mem_unmap;
499 }
500
501 ret = ath10k_ahb_clock_init(ar);
502 if (ret)
503 goto err_tcsr_mem_unmap;
504
505 ret = ath10k_ahb_rst_ctrl_init(ar);
506 if (ret)
507 goto err_clock_deinit;
508
509 ar_ahb->irq = platform_get_irq_byname(pdev, "legacy");
510 if (ar_ahb->irq < 0) {
511 ath10k_err(ar, "failed to get irq number: %d\n", ar_ahb->irq);
512 ret = ar_ahb->irq;
513 goto err_clock_deinit;
514 }
515
516 ath10k_dbg(ar, ATH10K_DBG_BOOT, "irq: %d\n", ar_ahb->irq);
517
518 ath10k_dbg(ar, ATH10K_DBG_BOOT, "mem: 0x%pK mem_len: %lu gcc mem: 0x%pK tcsr_mem: 0x%pK\n",
519 ar_ahb->mem, ar_ahb->mem_len,
520 ar_ahb->gcc_mem, ar_ahb->tcsr_mem);
521 return 0;
522
523 err_clock_deinit:
524 ath10k_ahb_clock_deinit(ar);
525
526 err_tcsr_mem_unmap:
527 iounmap(ar_ahb->tcsr_mem);
528
529 err_gcc_mem_unmap:
530 ar_ahb->tcsr_mem = NULL;
531 iounmap(ar_ahb->gcc_mem);
532
533 err_mem_unmap:
534 ar_ahb->gcc_mem = NULL;
535 devm_iounmap(&pdev->dev, ar_ahb->mem);
536
537 out:
538 ar_ahb->mem = NULL;
539 return ret;
540 }
541
ath10k_ahb_resource_deinit(struct ath10k * ar)542 static void ath10k_ahb_resource_deinit(struct ath10k *ar)
543 {
544 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
545 struct device *dev;
546
547 dev = &ar_ahb->pdev->dev;
548
549 if (ar_ahb->mem)
550 devm_iounmap(dev, ar_ahb->mem);
551
552 if (ar_ahb->gcc_mem)
553 iounmap(ar_ahb->gcc_mem);
554
555 if (ar_ahb->tcsr_mem)
556 iounmap(ar_ahb->tcsr_mem);
557
558 ar_ahb->mem = NULL;
559 ar_ahb->gcc_mem = NULL;
560 ar_ahb->tcsr_mem = NULL;
561
562 ath10k_ahb_clock_deinit(ar);
563 ath10k_ahb_rst_ctrl_deinit(ar);
564 }
565
ath10k_ahb_prepare_device(struct ath10k * ar)566 static int ath10k_ahb_prepare_device(struct ath10k *ar)
567 {
568 u32 val;
569 int ret;
570
571 ret = ath10k_ahb_clock_enable(ar);
572 if (ret) {
573 ath10k_err(ar, "failed to enable clocks\n");
574 return ret;
575 }
576
577 /* Clock for the target is supplied from outside of target (ie,
578 * external clock module controlled by the host). Target needs
579 * to know what frequency target cpu is configured which is needed
580 * for target internal use. Read target cpu frequency info from
581 * gcc register and write into target's scratch register where
582 * target expects this information.
583 */
584 val = ath10k_ahb_gcc_read32(ar, ATH10K_AHB_GCC_FEPLL_PLL_DIV);
585 ath10k_ahb_write32(ar, ATH10K_AHB_WIFI_SCRATCH_5_REG, val);
586
587 ret = ath10k_ahb_release_reset(ar);
588 if (ret)
589 goto err_clk_disable;
590
591 ath10k_ahb_irq_disable(ar);
592
593 ath10k_ahb_write32(ar, FW_INDICATOR_ADDRESS, FW_IND_HOST_READY);
594
595 ret = ath10k_pci_wait_for_target_init(ar);
596 if (ret)
597 goto err_halt_chip;
598
599 return 0;
600
601 err_halt_chip:
602 ath10k_ahb_halt_chip(ar);
603
604 err_clk_disable:
605 ath10k_ahb_clock_disable(ar);
606
607 return ret;
608 }
609
ath10k_ahb_chip_reset(struct ath10k * ar)610 static int ath10k_ahb_chip_reset(struct ath10k *ar)
611 {
612 int ret;
613
614 ath10k_ahb_halt_chip(ar);
615 ath10k_ahb_clock_disable(ar);
616
617 ret = ath10k_ahb_prepare_device(ar);
618 if (ret)
619 return ret;
620
621 return 0;
622 }
623
ath10k_ahb_wake_target_cpu(struct ath10k * ar)624 static int ath10k_ahb_wake_target_cpu(struct ath10k *ar)
625 {
626 u32 addr, val;
627
628 addr = SOC_CORE_BASE_ADDRESS | CORE_CTRL_ADDRESS;
629 val = ath10k_ahb_read32(ar, addr);
630 val |= ATH10K_AHB_CORE_CTRL_CPU_INTR_MASK;
631 ath10k_ahb_write32(ar, addr, val);
632
633 return 0;
634 }
635
ath10k_ahb_hif_start(struct ath10k * ar)636 static int ath10k_ahb_hif_start(struct ath10k *ar)
637 {
638 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif start\n");
639
640 napi_enable(&ar->napi);
641 ath10k_ce_enable_interrupts(ar);
642 ath10k_pci_enable_legacy_irq(ar);
643
644 ath10k_pci_rx_post(ar);
645
646 return 0;
647 }
648
ath10k_ahb_hif_stop(struct ath10k * ar)649 static void ath10k_ahb_hif_stop(struct ath10k *ar)
650 {
651 struct ath10k_ahb *ar_ahb = ath10k_ahb_priv(ar);
652
653 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif stop\n");
654
655 ath10k_ahb_irq_disable(ar);
656 synchronize_irq(ar_ahb->irq);
657
658 ath10k_pci_flush(ar);
659
660 napi_synchronize(&ar->napi);
661 napi_disable(&ar->napi);
662 }
663
ath10k_ahb_hif_power_up(struct ath10k * ar)664 static int ath10k_ahb_hif_power_up(struct ath10k *ar)
665 {
666 int ret;
667
668 ath10k_dbg(ar, ATH10K_DBG_BOOT, "boot ahb hif power up\n");
669
670 ret = ath10k_ahb_chip_reset(ar);
671 if (ret) {
672 ath10k_err(ar, "failed to reset chip: %d\n", ret);
673 goto out;
674 }
675
676 ret = ath10k_pci_init_pipes(ar);
677 if (ret) {
678 ath10k_err(ar, "failed to initialize CE: %d\n", ret);
679 goto out;
680 }
681
682 ret = ath10k_pci_init_config(ar);
683 if (ret) {
684 ath10k_err(ar, "failed to setup init config: %d\n", ret);
685 goto err_ce_deinit;
686 }
687
688 ret = ath10k_ahb_wake_target_cpu(ar);
689 if (ret) {
690 ath10k_err(ar, "could not wake up target CPU: %d\n", ret);
691 goto err_ce_deinit;
692 }
693
694 return 0;
695
696 err_ce_deinit:
697 ath10k_pci_ce_deinit(ar);
698 out:
699 return ret;
700 }
701
ath10k_ahb_qca4019_targ_cpu_to_ce_addr(struct ath10k * ar,u32 addr)702 static u32 ath10k_ahb_qca4019_targ_cpu_to_ce_addr(struct ath10k *ar, u32 addr)
703 {
704 u32 val = 0, region = addr & 0xfffff;
705
706 val = ath10k_pci_read32(ar, PCIE_BAR_REG_ADDRESS);
707
708 if (region >= QCA4019_SRAM_ADDR && region <=
709 (QCA4019_SRAM_ADDR + QCA4019_SRAM_LEN)) {
710 /* SRAM contents for QCA4019 can be directly accessed and
711 * no conversions are required
712 */
713 val |= region;
714 } else {
715 val |= 0x100000 | region;
716 }
717
718 return val;
719 }
720
721 static const struct ath10k_hif_ops ath10k_ahb_hif_ops = {
722 .tx_sg = ath10k_pci_hif_tx_sg,
723 .diag_read = ath10k_pci_hif_diag_read,
724 .diag_write = ath10k_pci_diag_write_mem,
725 .exchange_bmi_msg = ath10k_pci_hif_exchange_bmi_msg,
726 .start = ath10k_ahb_hif_start,
727 .stop = ath10k_ahb_hif_stop,
728 .map_service_to_pipe = ath10k_pci_hif_map_service_to_pipe,
729 .get_default_pipe = ath10k_pci_hif_get_default_pipe,
730 .send_complete_check = ath10k_pci_hif_send_complete_check,
731 .get_free_queue_number = ath10k_pci_hif_get_free_queue_number,
732 .power_up = ath10k_ahb_hif_power_up,
733 .power_down = ath10k_pci_hif_power_down,
734 .read32 = ath10k_ahb_read32,
735 .write32 = ath10k_ahb_write32,
736 };
737
738 static const struct ath10k_bus_ops ath10k_ahb_bus_ops = {
739 .read32 = ath10k_ahb_read32,
740 .write32 = ath10k_ahb_write32,
741 .get_num_banks = ath10k_ahb_get_num_banks,
742 };
743
ath10k_ahb_probe(struct platform_device * pdev)744 static int ath10k_ahb_probe(struct platform_device *pdev)
745 {
746 struct ath10k *ar;
747 struct ath10k_ahb *ar_ahb;
748 struct ath10k_pci *ar_pci;
749 const struct of_device_id *of_id;
750 enum ath10k_hw_rev hw_rev;
751 size_t size;
752 int ret;
753 u32 chip_id;
754
755 of_id = of_match_device(ath10k_ahb_of_match, &pdev->dev);
756 if (!of_id) {
757 dev_err(&pdev->dev, "failed to find matching device tree id\n");
758 return -EINVAL;
759 }
760
761 hw_rev = (enum ath10k_hw_rev)of_id->data;
762
763 size = sizeof(*ar_pci) + sizeof(*ar_ahb);
764 ar = ath10k_core_create(size, &pdev->dev, ATH10K_BUS_AHB,
765 hw_rev, &ath10k_ahb_hif_ops);
766 if (!ar) {
767 dev_err(&pdev->dev, "failed to allocate core\n");
768 return -ENOMEM;
769 }
770
771 ath10k_dbg(ar, ATH10K_DBG_BOOT, "ahb probe\n");
772
773 ar_pci = ath10k_pci_priv(ar);
774 ar_ahb = ath10k_ahb_priv(ar);
775
776 ar_ahb->pdev = pdev;
777 platform_set_drvdata(pdev, ar);
778
779 ret = ath10k_ahb_resource_init(ar);
780 if (ret)
781 goto err_core_destroy;
782
783 ar->dev_id = 0;
784 ar_pci->mem = ar_ahb->mem;
785 ar_pci->mem_len = ar_ahb->mem_len;
786 ar_pci->ar = ar;
787 ar_pci->ce.bus_ops = &ath10k_ahb_bus_ops;
788 ar_pci->targ_cpu_to_ce_addr = ath10k_ahb_qca4019_targ_cpu_to_ce_addr;
789 ar->ce_priv = &ar_pci->ce;
790
791 ret = ath10k_pci_setup_resource(ar);
792 if (ret) {
793 ath10k_err(ar, "failed to setup resource: %d\n", ret);
794 goto err_resource_deinit;
795 }
796
797 ath10k_pci_init_napi(ar);
798
799 ret = ath10k_ahb_request_irq_legacy(ar);
800 if (ret)
801 goto err_free_pipes;
802
803 ret = ath10k_ahb_prepare_device(ar);
804 if (ret)
805 goto err_free_irq;
806
807 ath10k_pci_ce_deinit(ar);
808
809 chip_id = ath10k_ahb_soc_read32(ar, SOC_CHIP_ID_ADDRESS);
810 if (chip_id == 0xffffffff) {
811 ath10k_err(ar, "failed to get chip id\n");
812 ret = -ENODEV;
813 goto err_halt_device;
814 }
815
816 ret = ath10k_core_register(ar, chip_id);
817 if (ret) {
818 ath10k_err(ar, "failed to register driver core: %d\n", ret);
819 goto err_halt_device;
820 }
821
822 return 0;
823
824 err_halt_device:
825 ath10k_ahb_halt_chip(ar);
826 ath10k_ahb_clock_disable(ar);
827
828 err_free_irq:
829 ath10k_ahb_release_irq_legacy(ar);
830
831 err_free_pipes:
832 ath10k_pci_free_pipes(ar);
833
834 err_resource_deinit:
835 ath10k_ahb_resource_deinit(ar);
836
837 err_core_destroy:
838 ath10k_core_destroy(ar);
839 platform_set_drvdata(pdev, NULL);
840
841 return ret;
842 }
843
ath10k_ahb_remove(struct platform_device * pdev)844 static int ath10k_ahb_remove(struct platform_device *pdev)
845 {
846 struct ath10k *ar = platform_get_drvdata(pdev);
847 struct ath10k_ahb *ar_ahb;
848
849 if (!ar)
850 return -EINVAL;
851
852 ar_ahb = ath10k_ahb_priv(ar);
853
854 if (!ar_ahb)
855 return -EINVAL;
856
857 ath10k_dbg(ar, ATH10K_DBG_AHB, "ahb remove\n");
858
859 ath10k_core_unregister(ar);
860 ath10k_ahb_irq_disable(ar);
861 ath10k_ahb_release_irq_legacy(ar);
862 ath10k_pci_release_resource(ar);
863 ath10k_ahb_halt_chip(ar);
864 ath10k_ahb_clock_disable(ar);
865 ath10k_ahb_resource_deinit(ar);
866 ath10k_core_destroy(ar);
867
868 platform_set_drvdata(pdev, NULL);
869
870 return 0;
871 }
872
873 static struct platform_driver ath10k_ahb_driver = {
874 .driver = {
875 .name = "ath10k_ahb",
876 .of_match_table = ath10k_ahb_of_match,
877 },
878 .probe = ath10k_ahb_probe,
879 .remove = ath10k_ahb_remove,
880 };
881
ath10k_ahb_init(void)882 int ath10k_ahb_init(void)
883 {
884 int ret;
885
886 ret = platform_driver_register(&ath10k_ahb_driver);
887 if (ret)
888 printk(KERN_ERR "failed to register ath10k ahb driver: %d\n",
889 ret);
890 return ret;
891 }
892
ath10k_ahb_exit(void)893 void ath10k_ahb_exit(void)
894 {
895 platform_driver_unregister(&ath10k_ahb_driver);
896 }
897
