1 /* Freescale QUICC Engine HDLC Device Driver 2 * 3 * Copyright 2014 Freescale Semiconductor Inc. 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License as published by the 7 * Free Software Foundation; either version 2 of the License, or (at your 8 * option) any later version. 9 */ 10 11 #ifndef _UCC_HDLC_H_ 12 #define _UCC_HDLC_H_ 13 14 #include <linux/kernel.h> 15 #include <linux/list.h> 16 17 #include <soc/fsl/qe/immap_qe.h> 18 #include <soc/fsl/qe/qe.h> 19 20 #include <soc/fsl/qe/ucc.h> 21 #include <soc/fsl/qe/ucc_fast.h> 22 23 /* UCC HDLC event register */ 24 #define UCCE_HDLC_RX_EVENTS \ 25 (UCC_HDLC_UCCE_RXF | UCC_HDLC_UCCE_RXB | UCC_HDLC_UCCE_BSY) 26 #define UCCE_HDLC_TX_EVENTS (UCC_HDLC_UCCE_TXB | UCC_HDLC_UCCE_TXE) 27 28 struct ucc_hdlc_param { 29 __be16 riptr; 30 __be16 tiptr; 31 __be16 res0; 32 __be16 mrblr; 33 __be32 rstate; 34 __be32 rbase; 35 __be16 rbdstat; 36 __be16 rbdlen; 37 __be32 rdptr; 38 __be32 tstate; 39 __be32 tbase; 40 __be16 tbdstat; 41 __be16 tbdlen; 42 __be32 tdptr; 43 __be32 rbptr; 44 __be32 tbptr; 45 __be32 rcrc; 46 __be32 res1; 47 __be32 tcrc; 48 __be32 res2; 49 __be32 res3; 50 __be32 c_mask; 51 __be32 c_pres; 52 __be16 disfc; 53 __be16 crcec; 54 __be16 abtsc; 55 __be16 nmarc; 56 __be32 max_cnt; 57 __be16 mflr; 58 __be16 rfthr; 59 __be16 rfcnt; 60 __be16 hmask; 61 __be16 haddr1; 62 __be16 haddr2; 63 __be16 haddr3; 64 __be16 haddr4; 65 __be16 ts_tmp; 66 __be16 tmp_mb; 67 }; 68 69 struct ucc_hdlc_private { 70 struct ucc_tdm *utdm; 71 struct ucc_tdm_info *ut_info; 72 struct ucc_fast_private *uccf; 73 struct device *dev; 74 struct net_device *ndev; 75 struct napi_struct napi; 76 struct ucc_fast __iomem *uf_regs; /* UCC Fast registers */ 77 struct ucc_hdlc_param __iomem *ucc_pram; 78 u16 tsa; 79 bool hdlc_busy; 80 bool loopback; 81 bool hdlc_bus; 82 83 u8 *tx_buffer; 84 u8 *rx_buffer; 85 dma_addr_t dma_tx_addr; 86 dma_addr_t dma_rx_addr; 87 88 struct qe_bd *tx_bd_base; 89 struct qe_bd *rx_bd_base; 90 dma_addr_t dma_tx_bd; 91 dma_addr_t dma_rx_bd; 92 struct qe_bd *curtx_bd; 93 struct qe_bd *currx_bd; 94 struct qe_bd *dirty_tx; 95 u16 currx_bdnum; 96 97 struct sk_buff **tx_skbuff; 98 struct sk_buff **rx_skbuff; 99 u16 skb_curtx; 100 u16 skb_currx; 101 unsigned short skb_dirtytx; 102 103 unsigned short tx_ring_size; 104 unsigned short rx_ring_size; 105 u32 ucc_pram_offset; 106 107 unsigned short encoding; 108 unsigned short parity; 109 u32 clocking; 110 spinlock_t lock; /* lock for Tx BD and Tx buffer */ 111 #ifdef CONFIG_PM 112 struct ucc_hdlc_param *ucc_pram_bak; 113 u32 gumr; 114 u8 guemr; 115 u32 cmxsi1cr_l, cmxsi1cr_h; 116 u32 cmxsi1syr; 117 u32 cmxucr[4]; 118 #endif 119 }; 120 121 #define TX_BD_RING_LEN 0x10 122 #define RX_BD_RING_LEN 0x20 123 #define RX_CLEAN_MAX 0x10 124 #define NUM_OF_BUF 4 125 #define MAX_RX_BUF_LENGTH (48 * 0x20) 126 #define MAX_FRAME_LENGTH (MAX_RX_BUF_LENGTH + 8) 127 #define ALIGNMENT_OF_UCC_HDLC_PRAM 64 128 #define SI_BANK_SIZE 128 129 #define MAX_HDLC_NUM 4 130 #define HDLC_HEAD_LEN 2 131 #define HDLC_CRC_SIZE 2 132 #define TX_RING_MOD_MASK(size) (size - 1) 133 #define RX_RING_MOD_MASK(size) (size - 1) 134 135 #define HDLC_HEAD_MASK 0x0000 136 #define DEFAULT_HDLC_HEAD 0xff44 137 #define DEFAULT_ADDR_MASK 0x00ff 138 #define DEFAULT_HDLC_ADDR 0x00ff 139 140 #define BMR_GBL 0x20000000 141 #define BMR_BIG_ENDIAN 0x10000000 142 #define CRC_16BIT_MASK 0x0000F0B8 143 #define CRC_16BIT_PRES 0x0000FFFF 144 #define DEFAULT_RFTHR 1 145 146 #define DEFAULT_PPP_HEAD 0xff03 147 148 #endif 149
