1 /* Applied Micro X-Gene SoC MDIO Driver
2 *
3 * Copyright (c) 2016, Applied Micro Circuits Corporation
4 * Author: Iyappan Subramanian <isubramanian@apm.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19
20 #ifndef __MDIO_XGENE_H__
21 #define __MDIO_XGENE_H__
22
23 #define BLOCK_XG_MDIO_CSR_OFFSET 0x5000
24 #define BLOCK_DIAG_CSR_OFFSET 0xd000
25 #define XGENET_CONFIG_REG_ADDR 0x20
26
27 #define MAC_ADDR_REG_OFFSET 0x00
28 #define MAC_COMMAND_REG_OFFSET 0x04
29 #define MAC_WRITE_REG_OFFSET 0x08
30 #define MAC_READ_REG_OFFSET 0x0c
31 #define MAC_COMMAND_DONE_REG_OFFSET 0x10
32
33 #define CLKEN_OFFSET 0x08
34 #define SRST_OFFSET 0x00
35
36 #define MENET_CFG_MEM_RAM_SHUTDOWN_ADDR 0x70
37 #define MENET_BLOCK_MEM_RDY_ADDR 0x74
38
39 #define MAC_CONFIG_1_ADDR 0x00
40 #define MII_MGMT_COMMAND_ADDR 0x24
41 #define MII_MGMT_ADDRESS_ADDR 0x28
42 #define MII_MGMT_CONTROL_ADDR 0x2c
43 #define MII_MGMT_STATUS_ADDR 0x30
44 #define MII_MGMT_INDICATORS_ADDR 0x34
45 #define SOFT_RESET BIT(31)
46
47 #define MII_MGMT_CONFIG_ADDR 0x20
48 #define MII_MGMT_COMMAND_ADDR 0x24
49 #define MII_MGMT_ADDRESS_ADDR 0x28
50 #define MII_MGMT_CONTROL_ADDR 0x2c
51 #define MII_MGMT_STATUS_ADDR 0x30
52 #define MII_MGMT_INDICATORS_ADDR 0x34
53
54 #define MIIM_COMMAND_ADDR 0x20
55 #define MIIM_FIELD_ADDR 0x24
56 #define MIIM_CONFIGURATION_ADDR 0x28
57 #define MIIM_LINKFAILVECTOR_ADDR 0x2c
58 #define MIIM_INDICATOR_ADDR 0x30
59 #define MIIMRD_FIELD_ADDR 0x34
60
61 #define MDIO_CSR_OFFSET 0x5000
62
63 #define REG_ADDR_POS 0
64 #define REG_ADDR_LEN 5
65 #define PHY_ADDR_POS 8
66 #define PHY_ADDR_LEN 5
67
68 #define HSTMIIMWRDAT_POS 0
69 #define HSTMIIMWRDAT_LEN 16
70 #define HSTPHYADX_POS 23
71 #define HSTPHYADX_LEN 5
72 #define HSTREGADX_POS 18
73 #define HSTREGADX_LEN 5
74 #define HSTLDCMD BIT(3)
75 #define HSTMIIMCMD_POS 0
76 #define HSTMIIMCMD_LEN 3
77
78 #define BUSY_MASK BIT(0)
79 #define READ_CYCLE_MASK BIT(0)
80
81 enum xgene_enet_cmd {
82 XGENE_ENET_WR_CMD = BIT(31),
83 XGENE_ENET_RD_CMD = BIT(30)
84 };
85
86 enum {
87 MIIM_CMD_IDLE,
88 MIIM_CMD_LEGACY_WRITE,
89 MIIM_CMD_LEGACY_READ,
90 };
91
92 enum xgene_mdio_id {
93 XGENE_MDIO_RGMII = 1,
94 XGENE_MDIO_XFI
95 };
96
97 struct xgene_mdio_pdata {
98 struct clk *clk;
99 struct device *dev;
100 void __iomem *mac_csr_addr;
101 void __iomem *diag_csr_addr;
102 void __iomem *mdio_csr_addr;
103 struct mii_bus *mdio_bus;
104 int mdio_id;
105 spinlock_t mac_lock; /* mac lock */
106 };
107
108 /* Set the specified value into a bit-field defined by its starting position
109 * and length within a single u64.
110 */
xgene_enet_set_field_value(int pos,int len,u64 val)111 static inline u64 xgene_enet_set_field_value(int pos, int len, u64 val)
112 {
113 return (val & ((1ULL << len) - 1)) << pos;
114 }
115
116 #define SET_VAL(field, val) \
117 xgene_enet_set_field_value(field ## _POS, field ## _LEN, val)
118
119 #define SET_BIT(field) \
120 xgene_enet_set_field_value(field ## _POS, 1, 1)
121
122 /* Get the value from a bit-field defined by its starting position
123 * and length within the specified u64.
124 */
xgene_enet_get_field_value(int pos,int len,u64 src)125 static inline u64 xgene_enet_get_field_value(int pos, int len, u64 src)
126 {
127 return (src >> pos) & ((1ULL << len) - 1);
128 }
129
130 #define GET_VAL(field, src) \
131 xgene_enet_get_field_value(field ## _POS, field ## _LEN, src)
132
133 #define GET_BIT(field, src) \
134 xgene_enet_get_field_value(field ## _POS, 1, src)
135
136 u32 xgene_mdio_rd_mac(struct xgene_mdio_pdata *pdata, u32 rd_addr);
137 void xgene_mdio_wr_mac(struct xgene_mdio_pdata *pdata, u32 wr_addr, u32 data);
138 int xgene_mdio_rgmii_read(struct mii_bus *bus, int phy_id, int reg);
139 int xgene_mdio_rgmii_write(struct mii_bus *bus, int phy_id, int reg, u16 data);
140 struct phy_device *xgene_enet_phy_register(struct mii_bus *bus, int phy_addr);
141
142 #endif /* __MDIO_XGENE_H__ */
143
