1 /* Copyright Altera Corporation (C) 2014. All rights reserved.
2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License, version 2,
5 * as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 *
12 * You should have received a copy of the GNU General Public License
13 * along with this program. If not, see <http://www.gnu.org/licenses/>.
14 *
15 * Adopted from dwmac-sti.c
16 */
17
18 #include <linux/mfd/syscon.h>
19 #include <linux/of.h>
20 #include <linux/of_address.h>
21 #include <linux/of_net.h>
22 #include <linux/phy.h>
23 #include <linux/regmap.h>
24 #include <linux/reset.h>
25 #include <linux/stmmac.h>
26
27 #include "stmmac.h"
28 #include "stmmac_platform.h"
29
30 #include "altr_tse_pcs.h"
31
32 #define SGMII_ADAPTER_CTRL_REG 0x00
33 #define SGMII_ADAPTER_DISABLE 0x0001
34
35 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII 0x0
36 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII 0x1
37 #define SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII 0x2
38 #define SYSMGR_EMACGRP_CTRL_PHYSEL_WIDTH 2
39 #define SYSMGR_EMACGRP_CTRL_PHYSEL_MASK 0x00000003
40 #define SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK 0x00000010
41
42 #define SYSMGR_FPGAGRP_MODULE_REG 0x00000028
43 #define SYSMGR_FPGAGRP_MODULE_EMAC 0x00000004
44
45 #define EMAC_SPLITTER_CTRL_REG 0x0
46 #define EMAC_SPLITTER_CTRL_SPEED_MASK 0x3
47 #define EMAC_SPLITTER_CTRL_SPEED_10 0x2
48 #define EMAC_SPLITTER_CTRL_SPEED_100 0x3
49 #define EMAC_SPLITTER_CTRL_SPEED_1000 0x0
50
51 struct socfpga_dwmac {
52 int interface;
53 u32 reg_offset;
54 u32 reg_shift;
55 struct device *dev;
56 struct regmap *sys_mgr_base_addr;
57 struct reset_control *stmmac_rst;
58 struct reset_control *stmmac_ocp_rst;
59 void __iomem *splitter_base;
60 bool f2h_ptp_ref_clk;
61 struct tse_pcs pcs;
62 };
63
socfpga_dwmac_fix_mac_speed(void * priv,unsigned int speed)64 static void socfpga_dwmac_fix_mac_speed(void *priv, unsigned int speed)
65 {
66 struct socfpga_dwmac *dwmac = (struct socfpga_dwmac *)priv;
67 void __iomem *splitter_base = dwmac->splitter_base;
68 void __iomem *tse_pcs_base = dwmac->pcs.tse_pcs_base;
69 void __iomem *sgmii_adapter_base = dwmac->pcs.sgmii_adapter_base;
70 struct device *dev = dwmac->dev;
71 struct net_device *ndev = dev_get_drvdata(dev);
72 struct phy_device *phy_dev = ndev->phydev;
73 u32 val;
74
75 if ((tse_pcs_base) && (sgmii_adapter_base))
76 writew(SGMII_ADAPTER_DISABLE,
77 sgmii_adapter_base + SGMII_ADAPTER_CTRL_REG);
78
79 if (splitter_base) {
80 val = readl(splitter_base + EMAC_SPLITTER_CTRL_REG);
81 val &= ~EMAC_SPLITTER_CTRL_SPEED_MASK;
82
83 switch (speed) {
84 case 1000:
85 val |= EMAC_SPLITTER_CTRL_SPEED_1000;
86 break;
87 case 100:
88 val |= EMAC_SPLITTER_CTRL_SPEED_100;
89 break;
90 case 10:
91 val |= EMAC_SPLITTER_CTRL_SPEED_10;
92 break;
93 default:
94 return;
95 }
96 writel(val, splitter_base + EMAC_SPLITTER_CTRL_REG);
97 }
98
99 if (tse_pcs_base && sgmii_adapter_base)
100 tse_pcs_fix_mac_speed(&dwmac->pcs, phy_dev, speed);
101 }
102
socfpga_dwmac_parse_data(struct socfpga_dwmac * dwmac,struct device * dev)103 static int socfpga_dwmac_parse_data(struct socfpga_dwmac *dwmac, struct device *dev)
104 {
105 struct device_node *np = dev->of_node;
106 struct regmap *sys_mgr_base_addr;
107 u32 reg_offset, reg_shift;
108 int ret, index;
109 struct device_node *np_splitter = NULL;
110 struct device_node *np_sgmii_adapter = NULL;
111 struct resource res_splitter;
112 struct resource res_tse_pcs;
113 struct resource res_sgmii_adapter;
114
115 dwmac->interface = of_get_phy_mode(np);
116
117 sys_mgr_base_addr = syscon_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
118 if (IS_ERR(sys_mgr_base_addr)) {
119 dev_info(dev, "No sysmgr-syscon node found\n");
120 return PTR_ERR(sys_mgr_base_addr);
121 }
122
123 ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, ®_offset);
124 if (ret) {
125 dev_info(dev, "Could not read reg_offset from sysmgr-syscon!\n");
126 return -EINVAL;
127 }
128
129 ret = of_property_read_u32_index(np, "altr,sysmgr-syscon", 2, ®_shift);
130 if (ret) {
131 dev_info(dev, "Could not read reg_shift from sysmgr-syscon!\n");
132 return -EINVAL;
133 }
134
135 dwmac->f2h_ptp_ref_clk = of_property_read_bool(np, "altr,f2h_ptp_ref_clk");
136
137 np_splitter = of_parse_phandle(np, "altr,emac-splitter", 0);
138 if (np_splitter) {
139 ret = of_address_to_resource(np_splitter, 0, &res_splitter);
140 of_node_put(np_splitter);
141 if (ret) {
142 dev_info(dev, "Missing emac splitter address\n");
143 return -EINVAL;
144 }
145
146 dwmac->splitter_base = devm_ioremap_resource(dev, &res_splitter);
147 if (IS_ERR(dwmac->splitter_base)) {
148 dev_info(dev, "Failed to mapping emac splitter\n");
149 return PTR_ERR(dwmac->splitter_base);
150 }
151 }
152
153 np_sgmii_adapter = of_parse_phandle(np,
154 "altr,gmii-to-sgmii-converter", 0);
155 if (np_sgmii_adapter) {
156 index = of_property_match_string(np_sgmii_adapter, "reg-names",
157 "hps_emac_interface_splitter_avalon_slave");
158
159 if (index >= 0) {
160 if (of_address_to_resource(np_sgmii_adapter, index,
161 &res_splitter)) {
162 dev_err(dev,
163 "%s: ERROR: missing emac splitter address\n",
164 __func__);
165 ret = -EINVAL;
166 goto err_node_put;
167 }
168
169 dwmac->splitter_base =
170 devm_ioremap_resource(dev, &res_splitter);
171
172 if (IS_ERR(dwmac->splitter_base)) {
173 ret = PTR_ERR(dwmac->splitter_base);
174 goto err_node_put;
175 }
176 }
177
178 index = of_property_match_string(np_sgmii_adapter, "reg-names",
179 "gmii_to_sgmii_adapter_avalon_slave");
180
181 if (index >= 0) {
182 if (of_address_to_resource(np_sgmii_adapter, index,
183 &res_sgmii_adapter)) {
184 dev_err(dev,
185 "%s: ERROR: failed mapping adapter\n",
186 __func__);
187 ret = -EINVAL;
188 goto err_node_put;
189 }
190
191 dwmac->pcs.sgmii_adapter_base =
192 devm_ioremap_resource(dev, &res_sgmii_adapter);
193
194 if (IS_ERR(dwmac->pcs.sgmii_adapter_base)) {
195 ret = PTR_ERR(dwmac->pcs.sgmii_adapter_base);
196 goto err_node_put;
197 }
198 }
199
200 index = of_property_match_string(np_sgmii_adapter, "reg-names",
201 "eth_tse_control_port");
202
203 if (index >= 0) {
204 if (of_address_to_resource(np_sgmii_adapter, index,
205 &res_tse_pcs)) {
206 dev_err(dev,
207 "%s: ERROR: failed mapping tse control port\n",
208 __func__);
209 ret = -EINVAL;
210 goto err_node_put;
211 }
212
213 dwmac->pcs.tse_pcs_base =
214 devm_ioremap_resource(dev, &res_tse_pcs);
215
216 if (IS_ERR(dwmac->pcs.tse_pcs_base)) {
217 ret = PTR_ERR(dwmac->pcs.tse_pcs_base);
218 goto err_node_put;
219 }
220 }
221 }
222 dwmac->reg_offset = reg_offset;
223 dwmac->reg_shift = reg_shift;
224 dwmac->sys_mgr_base_addr = sys_mgr_base_addr;
225 dwmac->dev = dev;
226 of_node_put(np_sgmii_adapter);
227
228 return 0;
229
230 err_node_put:
231 of_node_put(np_sgmii_adapter);
232 return ret;
233 }
234
socfpga_dwmac_set_phy_mode(struct socfpga_dwmac * dwmac)235 static int socfpga_dwmac_set_phy_mode(struct socfpga_dwmac *dwmac)
236 {
237 struct regmap *sys_mgr_base_addr = dwmac->sys_mgr_base_addr;
238 int phymode = dwmac->interface;
239 u32 reg_offset = dwmac->reg_offset;
240 u32 reg_shift = dwmac->reg_shift;
241 u32 ctrl, val, module;
242
243 switch (phymode) {
244 case PHY_INTERFACE_MODE_RGMII:
245 case PHY_INTERFACE_MODE_RGMII_ID:
246 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
247 break;
248 case PHY_INTERFACE_MODE_MII:
249 case PHY_INTERFACE_MODE_GMII:
250 case PHY_INTERFACE_MODE_SGMII:
251 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
252 break;
253 default:
254 dev_err(dwmac->dev, "bad phy mode %d\n", phymode);
255 return -EINVAL;
256 }
257
258 /* Overwrite val to GMII if splitter core is enabled. The phymode here
259 * is the actual phy mode on phy hardware, but phy interface from
260 * EMAC core is GMII.
261 */
262 if (dwmac->splitter_base)
263 val = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
264
265 /* Assert reset to the enet controller before changing the phy mode */
266 reset_control_assert(dwmac->stmmac_ocp_rst);
267 reset_control_assert(dwmac->stmmac_rst);
268
269 regmap_read(sys_mgr_base_addr, reg_offset, &ctrl);
270 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PHYSEL_MASK << reg_shift);
271 ctrl |= val << reg_shift;
272
273 if (dwmac->f2h_ptp_ref_clk ||
274 phymode == PHY_INTERFACE_MODE_MII ||
275 phymode == PHY_INTERFACE_MODE_GMII ||
276 phymode == PHY_INTERFACE_MODE_SGMII) {
277 ctrl |= SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2);
278 regmap_read(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
279 &module);
280 module |= (SYSMGR_FPGAGRP_MODULE_EMAC << (reg_shift / 2));
281 regmap_write(sys_mgr_base_addr, SYSMGR_FPGAGRP_MODULE_REG,
282 module);
283 } else {
284 ctrl &= ~(SYSMGR_EMACGRP_CTRL_PTP_REF_CLK_MASK << (reg_shift / 2));
285 }
286
287 regmap_write(sys_mgr_base_addr, reg_offset, ctrl);
288
289 /* Deassert reset for the phy configuration to be sampled by
290 * the enet controller, and operation to start in requested mode
291 */
292 reset_control_deassert(dwmac->stmmac_ocp_rst);
293 reset_control_deassert(dwmac->stmmac_rst);
294 if (phymode == PHY_INTERFACE_MODE_SGMII) {
295 if (tse_pcs_init(dwmac->pcs.tse_pcs_base, &dwmac->pcs) != 0) {
296 dev_err(dwmac->dev, "Unable to initialize TSE PCS");
297 return -EINVAL;
298 }
299 }
300
301 return 0;
302 }
303
socfpga_dwmac_probe(struct platform_device * pdev)304 static int socfpga_dwmac_probe(struct platform_device *pdev)
305 {
306 struct plat_stmmacenet_data *plat_dat;
307 struct stmmac_resources stmmac_res;
308 struct device *dev = &pdev->dev;
309 int ret;
310 struct socfpga_dwmac *dwmac;
311 struct net_device *ndev;
312 struct stmmac_priv *stpriv;
313
314 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
315 if (ret)
316 return ret;
317
318 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
319 if (IS_ERR(plat_dat))
320 return PTR_ERR(plat_dat);
321
322 dwmac = devm_kzalloc(dev, sizeof(*dwmac), GFP_KERNEL);
323 if (!dwmac) {
324 ret = -ENOMEM;
325 goto err_remove_config_dt;
326 }
327
328 dwmac->stmmac_ocp_rst = devm_reset_control_get_optional(dev, "stmmaceth-ocp");
329 if (IS_ERR(dwmac->stmmac_ocp_rst)) {
330 ret = PTR_ERR(dwmac->stmmac_ocp_rst);
331 dev_err(dev, "error getting reset control of ocp %d\n", ret);
332 goto err_remove_config_dt;
333 }
334
335 reset_control_deassert(dwmac->stmmac_ocp_rst);
336
337 ret = socfpga_dwmac_parse_data(dwmac, dev);
338 if (ret) {
339 dev_err(dev, "Unable to parse OF data\n");
340 goto err_remove_config_dt;
341 }
342
343 plat_dat->bsp_priv = dwmac;
344 plat_dat->fix_mac_speed = socfpga_dwmac_fix_mac_speed;
345
346 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
347 if (ret)
348 goto err_remove_config_dt;
349
350 ndev = platform_get_drvdata(pdev);
351 stpriv = netdev_priv(ndev);
352
353 /* The socfpga driver needs to control the stmmac reset to set the phy
354 * mode. Create a copy of the core reset handle so it can be used by
355 * the driver later.
356 */
357 dwmac->stmmac_rst = stpriv->plat->stmmac_rst;
358
359 ret = socfpga_dwmac_set_phy_mode(dwmac);
360 if (ret)
361 goto err_dvr_remove;
362
363 return 0;
364
365 err_dvr_remove:
366 stmmac_dvr_remove(&pdev->dev);
367 err_remove_config_dt:
368 stmmac_remove_config_dt(pdev, plat_dat);
369
370 return ret;
371 }
372
373 #ifdef CONFIG_PM_SLEEP
socfpga_dwmac_resume(struct device * dev)374 static int socfpga_dwmac_resume(struct device *dev)
375 {
376 struct net_device *ndev = dev_get_drvdata(dev);
377 struct stmmac_priv *priv = netdev_priv(ndev);
378
379 socfpga_dwmac_set_phy_mode(priv->plat->bsp_priv);
380
381 /* Before the enet controller is suspended, the phy is suspended.
382 * This causes the phy clock to be gated. The enet controller is
383 * resumed before the phy, so the clock is still gated "off" when
384 * the enet controller is resumed. This code makes sure the phy
385 * is "resumed" before reinitializing the enet controller since
386 * the enet controller depends on an active phy clock to complete
387 * a DMA reset. A DMA reset will "time out" if executed
388 * with no phy clock input on the Synopsys enet controller.
389 * Verified through Synopsys Case #8000711656.
390 *
391 * Note that the phy clock is also gated when the phy is isolated.
392 * Phy "suspend" and "isolate" controls are located in phy basic
393 * control register 0, and can be modified by the phy driver
394 * framework.
395 */
396 if (ndev->phydev)
397 phy_resume(ndev->phydev);
398
399 return stmmac_resume(dev);
400 }
401 #endif /* CONFIG_PM_SLEEP */
402
403 static SIMPLE_DEV_PM_OPS(socfpga_dwmac_pm_ops, stmmac_suspend,
404 socfpga_dwmac_resume);
405
406 static const struct of_device_id socfpga_dwmac_match[] = {
407 { .compatible = "altr,socfpga-stmmac" },
408 { }
409 };
410 MODULE_DEVICE_TABLE(of, socfpga_dwmac_match);
411
412 static struct platform_driver socfpga_dwmac_driver = {
413 .probe = socfpga_dwmac_probe,
414 .remove = stmmac_pltfr_remove,
415 .driver = {
416 .name = "socfpga-dwmac",
417 .pm = &socfpga_dwmac_pm_ops,
418 .of_match_table = socfpga_dwmac_match,
419 },
420 };
421 module_platform_driver(socfpga_dwmac_driver);
422
423 MODULE_LICENSE("GPL v2");
424
