1 /*
2 * Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer
3 *
4 * Copyright (C) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * You should have received a copy of the GNU General Public License
11 * along with this program. If not, see <http://www.gnu.org/licenses/>.
12 */
13
14 #include <linux/clk.h>
15 #include <linux/clk-provider.h>
16 #include <linux/device.h>
17 #include <linux/ethtool.h>
18 #include <linux/io.h>
19 #include <linux/ioport.h>
20 #include <linux/module.h>
21 #include <linux/of_device.h>
22 #include <linux/of_net.h>
23 #include <linux/mfd/syscon.h>
24 #include <linux/platform_device.h>
25 #include <linux/stmmac.h>
26
27 #include "stmmac_platform.h"
28
29 #define PRG_ETH0 0x0
30
31 #define PRG_ETH0_RGMII_MODE BIT(0)
32
33 #define PRG_ETH0_EXT_PHY_MODE_MASK GENMASK(2, 0)
34 #define PRG_ETH0_EXT_RGMII_MODE 1
35 #define PRG_ETH0_EXT_RMII_MODE 4
36
37 /* mux to choose between fclk_div2 (bit unset) and mpll2 (bit set) */
38 #define PRG_ETH0_CLK_M250_SEL_SHIFT 4
39 #define PRG_ETH0_CLK_M250_SEL_MASK GENMASK(4, 4)
40
41 #define PRG_ETH0_TXDLY_SHIFT 5
42 #define PRG_ETH0_TXDLY_MASK GENMASK(6, 5)
43
44 /* divider for the result of m250_sel */
45 #define PRG_ETH0_CLK_M250_DIV_SHIFT 7
46 #define PRG_ETH0_CLK_M250_DIV_WIDTH 3
47
48 #define PRG_ETH0_RGMII_TX_CLK_EN 10
49
50 #define PRG_ETH0_INVERTED_RMII_CLK BIT(11)
51 #define PRG_ETH0_TX_AND_PHY_REF_CLK BIT(12)
52
53 #define MUX_CLK_NUM_PARENTS 2
54
55 struct meson8b_dwmac;
56
57 struct meson8b_dwmac_data {
58 int (*set_phy_mode)(struct meson8b_dwmac *dwmac);
59 };
60
61 struct meson8b_dwmac {
62 struct device *dev;
63 void __iomem *regs;
64
65 const struct meson8b_dwmac_data *data;
66 phy_interface_t phy_mode;
67 struct clk *rgmii_tx_clk;
68 u32 tx_delay_ns;
69 };
70
71 struct meson8b_dwmac_clk_configs {
72 struct clk_mux m250_mux;
73 struct clk_divider m250_div;
74 struct clk_fixed_factor fixed_div2;
75 struct clk_gate rgmii_tx_en;
76 };
77
meson8b_dwmac_mask_bits(struct meson8b_dwmac * dwmac,u32 reg,u32 mask,u32 value)78 static void meson8b_dwmac_mask_bits(struct meson8b_dwmac *dwmac, u32 reg,
79 u32 mask, u32 value)
80 {
81 u32 data;
82
83 data = readl(dwmac->regs + reg);
84 data &= ~mask;
85 data |= (value & mask);
86
87 writel(data, dwmac->regs + reg);
88 }
89
meson8b_dwmac_register_clk(struct meson8b_dwmac * dwmac,const char * name_suffix,const char ** parent_names,int num_parents,const struct clk_ops * ops,struct clk_hw * hw)90 static struct clk *meson8b_dwmac_register_clk(struct meson8b_dwmac *dwmac,
91 const char *name_suffix,
92 const char **parent_names,
93 int num_parents,
94 const struct clk_ops *ops,
95 struct clk_hw *hw)
96 {
97 struct clk_init_data init;
98 char clk_name[32];
99
100 snprintf(clk_name, sizeof(clk_name), "%s#%s", dev_name(dwmac->dev),
101 name_suffix);
102
103 init.name = clk_name;
104 init.ops = ops;
105 init.flags = CLK_SET_RATE_PARENT;
106 init.parent_names = parent_names;
107 init.num_parents = num_parents;
108
109 hw->init = &init;
110
111 return devm_clk_register(dwmac->dev, hw);
112 }
113
meson8b_init_rgmii_tx_clk(struct meson8b_dwmac * dwmac)114 static int meson8b_init_rgmii_tx_clk(struct meson8b_dwmac *dwmac)
115 {
116 int i, ret;
117 struct clk *clk;
118 struct device *dev = dwmac->dev;
119 const char *parent_name, *mux_parent_names[MUX_CLK_NUM_PARENTS];
120 struct meson8b_dwmac_clk_configs *clk_configs;
121
122 clk_configs = devm_kzalloc(dev, sizeof(*clk_configs), GFP_KERNEL);
123 if (!clk_configs)
124 return -ENOMEM;
125
126 /* get the mux parents from DT */
127 for (i = 0; i < MUX_CLK_NUM_PARENTS; i++) {
128 char name[16];
129
130 snprintf(name, sizeof(name), "clkin%d", i);
131 clk = devm_clk_get(dev, name);
132 if (IS_ERR(clk)) {
133 ret = PTR_ERR(clk);
134 if (ret != -EPROBE_DEFER)
135 dev_err(dev, "Missing clock %s\n", name);
136 return ret;
137 }
138
139 mux_parent_names[i] = __clk_get_name(clk);
140 }
141
142 clk_configs->m250_mux.reg = dwmac->regs + PRG_ETH0;
143 clk_configs->m250_mux.shift = PRG_ETH0_CLK_M250_SEL_SHIFT;
144 clk_configs->m250_mux.mask = PRG_ETH0_CLK_M250_SEL_MASK;
145 clk = meson8b_dwmac_register_clk(dwmac, "m250_sel", mux_parent_names,
146 MUX_CLK_NUM_PARENTS, &clk_mux_ops,
147 &clk_configs->m250_mux.hw);
148 if (WARN_ON(IS_ERR(clk)))
149 return PTR_ERR(clk);
150
151 parent_name = __clk_get_name(clk);
152 clk_configs->m250_div.reg = dwmac->regs + PRG_ETH0;
153 clk_configs->m250_div.shift = PRG_ETH0_CLK_M250_DIV_SHIFT;
154 clk_configs->m250_div.width = PRG_ETH0_CLK_M250_DIV_WIDTH;
155 clk_configs->m250_div.flags = CLK_DIVIDER_ONE_BASED |
156 CLK_DIVIDER_ALLOW_ZERO |
157 CLK_DIVIDER_ROUND_CLOSEST;
158 clk = meson8b_dwmac_register_clk(dwmac, "m250_div", &parent_name, 1,
159 &clk_divider_ops,
160 &clk_configs->m250_div.hw);
161 if (WARN_ON(IS_ERR(clk)))
162 return PTR_ERR(clk);
163
164 parent_name = __clk_get_name(clk);
165 clk_configs->fixed_div2.mult = 1;
166 clk_configs->fixed_div2.div = 2;
167 clk = meson8b_dwmac_register_clk(dwmac, "fixed_div2", &parent_name, 1,
168 &clk_fixed_factor_ops,
169 &clk_configs->fixed_div2.hw);
170 if (WARN_ON(IS_ERR(clk)))
171 return PTR_ERR(clk);
172
173 parent_name = __clk_get_name(clk);
174 clk_configs->rgmii_tx_en.reg = dwmac->regs + PRG_ETH0;
175 clk_configs->rgmii_tx_en.bit_idx = PRG_ETH0_RGMII_TX_CLK_EN;
176 clk = meson8b_dwmac_register_clk(dwmac, "rgmii_tx_en", &parent_name, 1,
177 &clk_gate_ops,
178 &clk_configs->rgmii_tx_en.hw);
179 if (WARN_ON(IS_ERR(clk)))
180 return PTR_ERR(clk);
181
182 dwmac->rgmii_tx_clk = clk;
183
184 return 0;
185 }
186
meson8b_set_phy_mode(struct meson8b_dwmac * dwmac)187 static int meson8b_set_phy_mode(struct meson8b_dwmac *dwmac)
188 {
189 switch (dwmac->phy_mode) {
190 case PHY_INTERFACE_MODE_RGMII:
191 case PHY_INTERFACE_MODE_RGMII_RXID:
192 case PHY_INTERFACE_MODE_RGMII_ID:
193 case PHY_INTERFACE_MODE_RGMII_TXID:
194 /* enable RGMII mode */
195 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
196 PRG_ETH0_RGMII_MODE,
197 PRG_ETH0_RGMII_MODE);
198 break;
199 case PHY_INTERFACE_MODE_RMII:
200 /* disable RGMII mode -> enables RMII mode */
201 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
202 PRG_ETH0_RGMII_MODE, 0);
203 break;
204 default:
205 dev_err(dwmac->dev, "fail to set phy-mode %s\n",
206 phy_modes(dwmac->phy_mode));
207 return -EINVAL;
208 }
209
210 return 0;
211 }
212
meson_axg_set_phy_mode(struct meson8b_dwmac * dwmac)213 static int meson_axg_set_phy_mode(struct meson8b_dwmac *dwmac)
214 {
215 switch (dwmac->phy_mode) {
216 case PHY_INTERFACE_MODE_RGMII:
217 case PHY_INTERFACE_MODE_RGMII_RXID:
218 case PHY_INTERFACE_MODE_RGMII_ID:
219 case PHY_INTERFACE_MODE_RGMII_TXID:
220 /* enable RGMII mode */
221 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
222 PRG_ETH0_EXT_PHY_MODE_MASK,
223 PRG_ETH0_EXT_RGMII_MODE);
224 break;
225 case PHY_INTERFACE_MODE_RMII:
226 /* disable RGMII mode -> enables RMII mode */
227 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
228 PRG_ETH0_EXT_PHY_MODE_MASK,
229 PRG_ETH0_EXT_RMII_MODE);
230 break;
231 default:
232 dev_err(dwmac->dev, "fail to set phy-mode %s\n",
233 phy_modes(dwmac->phy_mode));
234 return -EINVAL;
235 }
236
237 return 0;
238 }
239
meson8b_init_prg_eth(struct meson8b_dwmac * dwmac)240 static int meson8b_init_prg_eth(struct meson8b_dwmac *dwmac)
241 {
242 int ret;
243 u8 tx_dly_val = 0;
244
245 switch (dwmac->phy_mode) {
246 case PHY_INTERFACE_MODE_RGMII:
247 case PHY_INTERFACE_MODE_RGMII_RXID:
248 /* TX clock delay in ns = "8ns / 4 * tx_dly_val" (where
249 * 8ns are exactly one cycle of the 125MHz RGMII TX clock):
250 * 0ns = 0x0, 2ns = 0x1, 4ns = 0x2, 6ns = 0x3
251 */
252 tx_dly_val = dwmac->tx_delay_ns >> 1;
253 /* fall through */
254
255 case PHY_INTERFACE_MODE_RGMII_ID:
256 case PHY_INTERFACE_MODE_RGMII_TXID:
257 /* only relevant for RMII mode -> disable in RGMII mode */
258 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
259 PRG_ETH0_INVERTED_RMII_CLK, 0);
260
261 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK,
262 tx_dly_val << PRG_ETH0_TXDLY_SHIFT);
263
264 /* Configure the 125MHz RGMII TX clock, the IP block changes
265 * the output automatically (= without us having to configure
266 * a register) based on the line-speed (125MHz for Gbit speeds,
267 * 25MHz for 100Mbit/s and 2.5MHz for 10Mbit/s).
268 */
269 ret = clk_set_rate(dwmac->rgmii_tx_clk, 125 * 1000 * 1000);
270 if (ret) {
271 dev_err(dwmac->dev,
272 "failed to set RGMII TX clock\n");
273 return ret;
274 }
275
276 ret = clk_prepare_enable(dwmac->rgmii_tx_clk);
277 if (ret) {
278 dev_err(dwmac->dev,
279 "failed to enable the RGMII TX clock\n");
280 return ret;
281 }
282
283 devm_add_action_or_reset(dwmac->dev,
284 (void(*)(void *))clk_disable_unprepare,
285 dwmac->rgmii_tx_clk);
286 break;
287
288 case PHY_INTERFACE_MODE_RMII:
289 /* invert internal clk_rmii_i to generate 25/2.5 tx_rx_clk */
290 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0,
291 PRG_ETH0_INVERTED_RMII_CLK,
292 PRG_ETH0_INVERTED_RMII_CLK);
293
294 /* TX clock delay cannot be configured in RMII mode */
295 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TXDLY_MASK,
296 0);
297
298 break;
299
300 default:
301 dev_err(dwmac->dev, "unsupported phy-mode %s\n",
302 phy_modes(dwmac->phy_mode));
303 return -EINVAL;
304 }
305
306 /* enable TX_CLK and PHY_REF_CLK generator */
307 meson8b_dwmac_mask_bits(dwmac, PRG_ETH0, PRG_ETH0_TX_AND_PHY_REF_CLK,
308 PRG_ETH0_TX_AND_PHY_REF_CLK);
309
310 return 0;
311 }
312
meson8b_dwmac_probe(struct platform_device * pdev)313 static int meson8b_dwmac_probe(struct platform_device *pdev)
314 {
315 struct plat_stmmacenet_data *plat_dat;
316 struct stmmac_resources stmmac_res;
317 struct resource *res;
318 struct meson8b_dwmac *dwmac;
319 int ret;
320
321 ret = stmmac_get_platform_resources(pdev, &stmmac_res);
322 if (ret)
323 return ret;
324
325 plat_dat = stmmac_probe_config_dt(pdev, &stmmac_res.mac);
326 if (IS_ERR(plat_dat))
327 return PTR_ERR(plat_dat);
328
329 dwmac = devm_kzalloc(&pdev->dev, sizeof(*dwmac), GFP_KERNEL);
330 if (!dwmac) {
331 ret = -ENOMEM;
332 goto err_remove_config_dt;
333 }
334
335 dwmac->data = (const struct meson8b_dwmac_data *)
336 of_device_get_match_data(&pdev->dev);
337 if (!dwmac->data) {
338 ret = -EINVAL;
339 goto err_remove_config_dt;
340 }
341 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
342 dwmac->regs = devm_ioremap_resource(&pdev->dev, res);
343 if (IS_ERR(dwmac->regs)) {
344 ret = PTR_ERR(dwmac->regs);
345 goto err_remove_config_dt;
346 }
347
348 dwmac->dev = &pdev->dev;
349 dwmac->phy_mode = of_get_phy_mode(pdev->dev.of_node);
350 if (dwmac->phy_mode < 0) {
351 dev_err(&pdev->dev, "missing phy-mode property\n");
352 ret = -EINVAL;
353 goto err_remove_config_dt;
354 }
355
356 /* use 2ns as fallback since this value was previously hardcoded */
357 if (of_property_read_u32(pdev->dev.of_node, "amlogic,tx-delay-ns",
358 &dwmac->tx_delay_ns))
359 dwmac->tx_delay_ns = 2;
360
361 ret = meson8b_init_rgmii_tx_clk(dwmac);
362 if (ret)
363 goto err_remove_config_dt;
364
365 ret = dwmac->data->set_phy_mode(dwmac);
366 if (ret)
367 goto err_remove_config_dt;
368
369 ret = meson8b_init_prg_eth(dwmac);
370 if (ret)
371 goto err_remove_config_dt;
372
373 plat_dat->bsp_priv = dwmac;
374
375 ret = stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res);
376 if (ret)
377 goto err_remove_config_dt;
378
379 return 0;
380
381 err_remove_config_dt:
382 stmmac_remove_config_dt(pdev, plat_dat);
383
384 return ret;
385 }
386
387 static const struct meson8b_dwmac_data meson8b_dwmac_data = {
388 .set_phy_mode = meson8b_set_phy_mode,
389 };
390
391 static const struct meson8b_dwmac_data meson_axg_dwmac_data = {
392 .set_phy_mode = meson_axg_set_phy_mode,
393 };
394
395 static const struct of_device_id meson8b_dwmac_match[] = {
396 {
397 .compatible = "amlogic,meson8b-dwmac",
398 .data = &meson8b_dwmac_data,
399 },
400 {
401 .compatible = "amlogic,meson8m2-dwmac",
402 .data = &meson8b_dwmac_data,
403 },
404 {
405 .compatible = "amlogic,meson-gxbb-dwmac",
406 .data = &meson8b_dwmac_data,
407 },
408 {
409 .compatible = "amlogic,meson-axg-dwmac",
410 .data = &meson_axg_dwmac_data,
411 },
412 { }
413 };
414 MODULE_DEVICE_TABLE(of, meson8b_dwmac_match);
415
416 static struct platform_driver meson8b_dwmac_driver = {
417 .probe = meson8b_dwmac_probe,
418 .remove = stmmac_pltfr_remove,
419 .driver = {
420 .name = "meson8b-dwmac",
421 .pm = &stmmac_pltfr_pm_ops,
422 .of_match_table = meson8b_dwmac_match,
423 },
424 };
425 module_platform_driver(meson8b_dwmac_driver);
426
427 MODULE_AUTHOR("Martin Blumenstingl <martin.blumenstingl@googlemail.com>");
428 MODULE_DESCRIPTION("Amlogic Meson8b, Meson8m2 and GXBB DWMAC glue layer");
429 MODULE_LICENSE("GPL v2");
430
