1 /*
2 * Copyright (C) 2003 - 2009 NetXen, Inc.
3 * Copyright (C) 2009 - QLogic Corporation.
4 * All rights reserved.
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * as published by the Free Software Foundation; either version 2
9 * of the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, see <http://www.gnu.org/licenses/>.
18 *
19 * The full GNU General Public License is included in this distribution
20 * in the file called "COPYING".
21 *
22 */
23
24 #include <linux/io-64-nonatomic-lo-hi.h>
25 #include <linux/slab.h>
26 #include "netxen_nic.h"
27 #include "netxen_nic_hw.h"
28
29 #include <net/ip.h>
30
31 #define MASK(n) ((1ULL<<(n))-1)
32 #define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
33 #define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
34 #define MS_WIN(addr) (addr & 0x0ffc0000)
35
36 #define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
37
38 #define CRB_BLK(off) ((off >> 20) & 0x3f)
39 #define CRB_SUBBLK(off) ((off >> 16) & 0xf)
40 #define CRB_WINDOW_2M (0x130060)
41 #define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
42 #define CRB_INDIRECT_2M (0x1e0000UL)
43
44 static void netxen_nic_io_write_128M(struct netxen_adapter *adapter,
45 void __iomem *addr, u32 data);
46 static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter,
47 void __iomem *addr);
48
49 #define PCI_OFFSET_FIRST_RANGE(adapter, off) \
50 ((adapter)->ahw.pci_base0 + (off))
51 #define PCI_OFFSET_SECOND_RANGE(adapter, off) \
52 ((adapter)->ahw.pci_base1 + (off) - SECOND_PAGE_GROUP_START)
53 #define PCI_OFFSET_THIRD_RANGE(adapter, off) \
54 ((adapter)->ahw.pci_base2 + (off) - THIRD_PAGE_GROUP_START)
55
pci_base_offset(struct netxen_adapter * adapter,unsigned long off)56 static void __iomem *pci_base_offset(struct netxen_adapter *adapter,
57 unsigned long off)
58 {
59 if (ADDR_IN_RANGE(off, FIRST_PAGE_GROUP_START, FIRST_PAGE_GROUP_END))
60 return PCI_OFFSET_FIRST_RANGE(adapter, off);
61
62 if (ADDR_IN_RANGE(off, SECOND_PAGE_GROUP_START, SECOND_PAGE_GROUP_END))
63 return PCI_OFFSET_SECOND_RANGE(adapter, off);
64
65 if (ADDR_IN_RANGE(off, THIRD_PAGE_GROUP_START, THIRD_PAGE_GROUP_END))
66 return PCI_OFFSET_THIRD_RANGE(adapter, off);
67
68 return NULL;
69 }
70
71 static crb_128M_2M_block_map_t
72 crb_128M_2M_map[64] __cacheline_aligned_in_smp = {
73 {{{0, 0, 0, 0} } }, /* 0: PCI */
74 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
75 {1, 0x0110000, 0x0120000, 0x130000},
76 {1, 0x0120000, 0x0122000, 0x124000},
77 {1, 0x0130000, 0x0132000, 0x126000},
78 {1, 0x0140000, 0x0142000, 0x128000},
79 {1, 0x0150000, 0x0152000, 0x12a000},
80 {1, 0x0160000, 0x0170000, 0x110000},
81 {1, 0x0170000, 0x0172000, 0x12e000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {1, 0x01e0000, 0x01e0800, 0x122000},
89 {0, 0x0000000, 0x0000000, 0x000000} } },
90 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
91 {{{0, 0, 0, 0} } }, /* 3: */
92 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
93 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
94 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
95 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
96 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {0, 0x0000000, 0x0000000, 0x000000},
108 {0, 0x0000000, 0x0000000, 0x000000},
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {0, 0x0000000, 0x0000000, 0x000000},
111 {1, 0x08f0000, 0x08f2000, 0x172000} } },
112 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {0, 0x0000000, 0x0000000, 0x000000},
127 {1, 0x09f0000, 0x09f2000, 0x176000} } },
128 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {0, 0x0000000, 0x0000000, 0x000000},
143 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
144 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
145 {0, 0x0000000, 0x0000000, 0x000000},
146 {0, 0x0000000, 0x0000000, 0x000000},
147 {0, 0x0000000, 0x0000000, 0x000000},
148 {0, 0x0000000, 0x0000000, 0x000000},
149 {0, 0x0000000, 0x0000000, 0x000000},
150 {0, 0x0000000, 0x0000000, 0x000000},
151 {0, 0x0000000, 0x0000000, 0x000000},
152 {0, 0x0000000, 0x0000000, 0x000000},
153 {0, 0x0000000, 0x0000000, 0x000000},
154 {0, 0x0000000, 0x0000000, 0x000000},
155 {0, 0x0000000, 0x0000000, 0x000000},
156 {0, 0x0000000, 0x0000000, 0x000000},
157 {0, 0x0000000, 0x0000000, 0x000000},
158 {0, 0x0000000, 0x0000000, 0x000000},
159 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
160 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
161 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
162 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
163 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
164 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
165 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
166 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
167 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
168 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
169 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
170 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
171 {{{0, 0, 0, 0} } }, /* 23: */
172 {{{0, 0, 0, 0} } }, /* 24: */
173 {{{0, 0, 0, 0} } }, /* 25: */
174 {{{0, 0, 0, 0} } }, /* 26: */
175 {{{0, 0, 0, 0} } }, /* 27: */
176 {{{0, 0, 0, 0} } }, /* 28: */
177 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
178 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
179 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
180 {{{0} } }, /* 32: PCI */
181 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
182 {1, 0x2110000, 0x2120000, 0x130000},
183 {1, 0x2120000, 0x2122000, 0x124000},
184 {1, 0x2130000, 0x2132000, 0x126000},
185 {1, 0x2140000, 0x2142000, 0x128000},
186 {1, 0x2150000, 0x2152000, 0x12a000},
187 {1, 0x2160000, 0x2170000, 0x110000},
188 {1, 0x2170000, 0x2172000, 0x12e000},
189 {0, 0x0000000, 0x0000000, 0x000000},
190 {0, 0x0000000, 0x0000000, 0x000000},
191 {0, 0x0000000, 0x0000000, 0x000000},
192 {0, 0x0000000, 0x0000000, 0x000000},
193 {0, 0x0000000, 0x0000000, 0x000000},
194 {0, 0x0000000, 0x0000000, 0x000000},
195 {0, 0x0000000, 0x0000000, 0x000000},
196 {0, 0x0000000, 0x0000000, 0x000000} } },
197 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
198 {{{0} } }, /* 35: */
199 {{{0} } }, /* 36: */
200 {{{0} } }, /* 37: */
201 {{{0} } }, /* 38: */
202 {{{0} } }, /* 39: */
203 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
204 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
205 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
206 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
207 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
208 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
209 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
210 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
211 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
212 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
213 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
214 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
215 {{{0} } }, /* 52: */
216 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
217 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
218 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
219 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
220 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
221 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
222 {{{0} } }, /* 59: I2C0 */
223 {{{0} } }, /* 60: I2C1 */
224 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
225 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
226 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
227 };
228
229 /*
230 * top 12 bits of crb internal address (hub, agent)
231 */
232 static unsigned crb_hub_agt[64] =
233 {
234 0,
235 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
236 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
237 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
238 0,
239 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
240 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
241 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
242 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
243 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
244 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
245 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
246 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
247 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
248 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
249 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
250 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
251 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
252 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
253 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
254 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
255 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
256 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
257 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
258 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
259 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
260 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
261 0,
262 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
263 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
264 0,
265 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
266 0,
267 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
268 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
269 0,
270 0,
271 0,
272 0,
273 0,
274 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
275 0,
276 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
277 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
278 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
279 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
280 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
281 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
282 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
283 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
284 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
285 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
286 0,
287 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
288 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
289 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
290 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
291 0,
292 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
293 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
294 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
295 0,
296 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
297 0,
298 };
299
300 /* PCI Windowing for DDR regions. */
301
302 #define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
303
304 #define NETXEN_PCIE_SEM_TIMEOUT 10000
305
306 static int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu);
307
308 int
netxen_pcie_sem_lock(struct netxen_adapter * adapter,int sem,u32 id_reg)309 netxen_pcie_sem_lock(struct netxen_adapter *adapter, int sem, u32 id_reg)
310 {
311 int done = 0, timeout = 0;
312
313 while (!done) {
314 done = NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_LOCK(sem)));
315 if (done == 1)
316 break;
317 if (++timeout >= NETXEN_PCIE_SEM_TIMEOUT)
318 return -EIO;
319 msleep(1);
320 }
321
322 if (id_reg)
323 NXWR32(adapter, id_reg, adapter->portnum);
324
325 return 0;
326 }
327
328 void
netxen_pcie_sem_unlock(struct netxen_adapter * adapter,int sem)329 netxen_pcie_sem_unlock(struct netxen_adapter *adapter, int sem)
330 {
331 NXRD32(adapter, NETXEN_PCIE_REG(PCIE_SEM_UNLOCK(sem)));
332 }
333
netxen_niu_xg_init_port(struct netxen_adapter * adapter,int port)334 static int netxen_niu_xg_init_port(struct netxen_adapter *adapter, int port)
335 {
336 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
337 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_1+(0x10000*port), 0x1447);
338 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0+(0x10000*port), 0x5);
339 }
340
341 return 0;
342 }
343
344 /* Disable an XG interface */
netxen_niu_disable_xg_port(struct netxen_adapter * adapter)345 static int netxen_niu_disable_xg_port(struct netxen_adapter *adapter)
346 {
347 __u32 mac_cfg;
348 u32 port = adapter->physical_port;
349
350 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
351 return 0;
352
353 if (port >= NETXEN_NIU_MAX_XG_PORTS)
354 return -EINVAL;
355
356 mac_cfg = 0;
357 if (NXWR32(adapter,
358 NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg))
359 return -EIO;
360 return 0;
361 }
362
363 #define NETXEN_UNICAST_ADDR(port, index) \
364 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
365 #define NETXEN_MCAST_ADDR(port, index) \
366 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
367 #define MAC_HI(addr) \
368 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
369 #define MAC_LO(addr) \
370 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
371
netxen_p2_nic_set_promisc(struct netxen_adapter * adapter,u32 mode)372 static int netxen_p2_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
373 {
374 u32 mac_cfg;
375 u32 cnt = 0;
376 __u32 reg = 0x0200;
377 u32 port = adapter->physical_port;
378 u16 board_type = adapter->ahw.board_type;
379
380 if (port >= NETXEN_NIU_MAX_XG_PORTS)
381 return -EINVAL;
382
383 mac_cfg = NXRD32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port));
384 mac_cfg &= ~0x4;
385 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg);
386
387 if ((board_type == NETXEN_BRDTYPE_P2_SB31_10G_IMEZ) ||
388 (board_type == NETXEN_BRDTYPE_P2_SB31_10G_HMEZ))
389 reg = (0x20 << port);
390
391 NXWR32(adapter, NETXEN_NIU_FRAME_COUNT_SELECT, reg);
392
393 mdelay(10);
394
395 while (NXRD32(adapter, NETXEN_NIU_FRAME_COUNT) && ++cnt < 20)
396 mdelay(10);
397
398 if (cnt < 20) {
399
400 reg = NXRD32(adapter,
401 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port));
402
403 if (mode == NETXEN_NIU_PROMISC_MODE)
404 reg = (reg | 0x2000UL);
405 else
406 reg = (reg & ~0x2000UL);
407
408 if (mode == NETXEN_NIU_ALLMULTI_MODE)
409 reg = (reg | 0x1000UL);
410 else
411 reg = (reg & ~0x1000UL);
412
413 NXWR32(adapter,
414 NETXEN_NIU_XGE_CONFIG_1 + (0x10000 * port), reg);
415 }
416
417 mac_cfg |= 0x4;
418 NXWR32(adapter, NETXEN_NIU_XGE_CONFIG_0 + (0x10000 * port), mac_cfg);
419
420 return 0;
421 }
422
netxen_p2_nic_set_mac_addr(struct netxen_adapter * adapter,u8 * addr)423 static int netxen_p2_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
424 {
425 u32 mac_hi, mac_lo;
426 u32 reg_hi, reg_lo;
427
428 u8 phy = adapter->physical_port;
429
430 if (phy >= NETXEN_NIU_MAX_XG_PORTS)
431 return -EINVAL;
432
433 mac_lo = ((u32)addr[0] << 16) | ((u32)addr[1] << 24);
434 mac_hi = addr[2] | ((u32)addr[3] << 8) |
435 ((u32)addr[4] << 16) | ((u32)addr[5] << 24);
436
437 reg_lo = NETXEN_NIU_XGE_STATION_ADDR_0_1 + (0x10000 * phy);
438 reg_hi = NETXEN_NIU_XGE_STATION_ADDR_0_HI + (0x10000 * phy);
439
440 /* write twice to flush */
441 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
442 return -EIO;
443 if (NXWR32(adapter, reg_lo, mac_lo) || NXWR32(adapter, reg_hi, mac_hi))
444 return -EIO;
445
446 return 0;
447 }
448
449 static int
netxen_nic_enable_mcast_filter(struct netxen_adapter * adapter)450 netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
451 {
452 u32 val = 0;
453 u16 port = adapter->physical_port;
454 u8 *addr = adapter->mac_addr;
455
456 if (adapter->mc_enabled)
457 return 0;
458
459 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
460 val |= (1UL << (28+port));
461 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
462
463 /* add broadcast addr to filter */
464 val = 0xffffff;
465 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
466 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
467
468 /* add station addr to filter */
469 val = MAC_HI(addr);
470 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
471 val = MAC_LO(addr);
472 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, val);
473
474 adapter->mc_enabled = 1;
475 return 0;
476 }
477
478 static int
netxen_nic_disable_mcast_filter(struct netxen_adapter * adapter)479 netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
480 {
481 u32 val = 0;
482 u16 port = adapter->physical_port;
483 u8 *addr = adapter->mac_addr;
484
485 if (!adapter->mc_enabled)
486 return 0;
487
488 val = NXRD32(adapter, NETXEN_MAC_ADDR_CNTL_REG);
489 val &= ~(1UL << (28+port));
490 NXWR32(adapter, NETXEN_MAC_ADDR_CNTL_REG, val);
491
492 val = MAC_HI(addr);
493 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
494 val = MAC_LO(addr);
495 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 0)+4, val);
496
497 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
498 NXWR32(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
499
500 adapter->mc_enabled = 0;
501 return 0;
502 }
503
504 static int
netxen_nic_set_mcast_addr(struct netxen_adapter * adapter,int index,u8 * addr)505 netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
506 int index, u8 *addr)
507 {
508 u32 hi = 0, lo = 0;
509 u16 port = adapter->physical_port;
510
511 lo = MAC_LO(addr);
512 hi = MAC_HI(addr);
513
514 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index), hi);
515 NXWR32(adapter, NETXEN_MCAST_ADDR(port, index)+4, lo);
516
517 return 0;
518 }
519
netxen_p2_nic_set_multi(struct net_device * netdev)520 static void netxen_p2_nic_set_multi(struct net_device *netdev)
521 {
522 struct netxen_adapter *adapter = netdev_priv(netdev);
523 struct netdev_hw_addr *ha;
524 u8 null_addr[ETH_ALEN];
525 int i;
526
527 eth_zero_addr(null_addr);
528
529 if (netdev->flags & IFF_PROMISC) {
530
531 adapter->set_promisc(adapter,
532 NETXEN_NIU_PROMISC_MODE);
533
534 /* Full promiscuous mode */
535 netxen_nic_disable_mcast_filter(adapter);
536
537 return;
538 }
539
540 if (netdev_mc_empty(netdev)) {
541 adapter->set_promisc(adapter,
542 NETXEN_NIU_NON_PROMISC_MODE);
543 netxen_nic_disable_mcast_filter(adapter);
544 return;
545 }
546
547 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
548 if (netdev->flags & IFF_ALLMULTI ||
549 netdev_mc_count(netdev) > adapter->max_mc_count) {
550 netxen_nic_disable_mcast_filter(adapter);
551 return;
552 }
553
554 netxen_nic_enable_mcast_filter(adapter);
555
556 i = 0;
557 netdev_for_each_mc_addr(ha, netdev)
558 netxen_nic_set_mcast_addr(adapter, i++, ha->addr);
559
560 /* Clear out remaining addresses */
561 while (i < adapter->max_mc_count)
562 netxen_nic_set_mcast_addr(adapter, i++, null_addr);
563 }
564
565 static int
netxen_send_cmd_descs(struct netxen_adapter * adapter,struct cmd_desc_type0 * cmd_desc_arr,int nr_desc)566 netxen_send_cmd_descs(struct netxen_adapter *adapter,
567 struct cmd_desc_type0 *cmd_desc_arr, int nr_desc)
568 {
569 u32 i, producer;
570 struct netxen_cmd_buffer *pbuf;
571 struct nx_host_tx_ring *tx_ring;
572
573 i = 0;
574
575 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
576 return -EIO;
577
578 tx_ring = adapter->tx_ring;
579 __netif_tx_lock_bh(tx_ring->txq);
580
581 producer = tx_ring->producer;
582
583 if (nr_desc >= netxen_tx_avail(tx_ring)) {
584 netif_tx_stop_queue(tx_ring->txq);
585 smp_mb();
586 if (netxen_tx_avail(tx_ring) > nr_desc) {
587 if (netxen_tx_avail(tx_ring) > TX_STOP_THRESH)
588 netif_tx_wake_queue(tx_ring->txq);
589 } else {
590 __netif_tx_unlock_bh(tx_ring->txq);
591 return -EBUSY;
592 }
593 }
594
595 do {
596 pbuf = &tx_ring->cmd_buf_arr[producer];
597 pbuf->skb = NULL;
598 pbuf->frag_count = 0;
599
600 memcpy(&tx_ring->desc_head[producer],
601 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
602
603 producer = get_next_index(producer, tx_ring->num_desc);
604 i++;
605
606 } while (i != nr_desc);
607
608 tx_ring->producer = producer;
609
610 netxen_nic_update_cmd_producer(adapter, tx_ring);
611
612 __netif_tx_unlock_bh(tx_ring->txq);
613
614 return 0;
615 }
616
617 static int
nx_p3_sre_macaddr_change(struct netxen_adapter * adapter,u8 * addr,unsigned op)618 nx_p3_sre_macaddr_change(struct netxen_adapter *adapter, u8 *addr, unsigned op)
619 {
620 nx_nic_req_t req;
621 nx_mac_req_t *mac_req;
622 u64 word;
623
624 memset(&req, 0, sizeof(nx_nic_req_t));
625 req.qhdr = cpu_to_le64(NX_NIC_REQUEST << 23);
626
627 word = NX_MAC_EVENT | ((u64)adapter->portnum << 16);
628 req.req_hdr = cpu_to_le64(word);
629
630 mac_req = (nx_mac_req_t *)&req.words[0];
631 mac_req->op = op;
632 memcpy(mac_req->mac_addr, addr, ETH_ALEN);
633
634 return netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
635 }
636
nx_p3_nic_add_mac(struct netxen_adapter * adapter,const u8 * addr,struct list_head * del_list)637 static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
638 const u8 *addr, struct list_head *del_list)
639 {
640 struct list_head *head;
641 nx_mac_list_t *cur;
642
643 /* look up if already exists */
644 list_for_each(head, del_list) {
645 cur = list_entry(head, nx_mac_list_t, list);
646
647 if (ether_addr_equal(addr, cur->mac_addr)) {
648 list_move_tail(head, &adapter->mac_list);
649 return 0;
650 }
651 }
652
653 cur = kzalloc(sizeof(nx_mac_list_t), GFP_ATOMIC);
654 if (cur == NULL)
655 return -ENOMEM;
656
657 memcpy(cur->mac_addr, addr, ETH_ALEN);
658 list_add_tail(&cur->list, &adapter->mac_list);
659 return nx_p3_sre_macaddr_change(adapter,
660 cur->mac_addr, NETXEN_MAC_ADD);
661 }
662
netxen_p3_nic_set_multi(struct net_device * netdev)663 static void netxen_p3_nic_set_multi(struct net_device *netdev)
664 {
665 struct netxen_adapter *adapter = netdev_priv(netdev);
666 struct netdev_hw_addr *ha;
667 static const u8 bcast_addr[ETH_ALEN] = {
668 0xff, 0xff, 0xff, 0xff, 0xff, 0xff
669 };
670 u32 mode = VPORT_MISS_MODE_DROP;
671 LIST_HEAD(del_list);
672 struct list_head *head;
673 nx_mac_list_t *cur;
674
675 if (adapter->is_up != NETXEN_ADAPTER_UP_MAGIC)
676 return;
677
678 list_splice_tail_init(&adapter->mac_list, &del_list);
679
680 nx_p3_nic_add_mac(adapter, adapter->mac_addr, &del_list);
681 nx_p3_nic_add_mac(adapter, bcast_addr, &del_list);
682
683 if (netdev->flags & IFF_PROMISC) {
684 mode = VPORT_MISS_MODE_ACCEPT_ALL;
685 goto send_fw_cmd;
686 }
687
688 if ((netdev->flags & IFF_ALLMULTI) ||
689 (netdev_mc_count(netdev) > adapter->max_mc_count)) {
690 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
691 goto send_fw_cmd;
692 }
693
694 if (!netdev_mc_empty(netdev)) {
695 netdev_for_each_mc_addr(ha, netdev)
696 nx_p3_nic_add_mac(adapter, ha->addr, &del_list);
697 }
698
699 send_fw_cmd:
700 adapter->set_promisc(adapter, mode);
701 head = &del_list;
702 while (!list_empty(head)) {
703 cur = list_entry(head->next, nx_mac_list_t, list);
704
705 nx_p3_sre_macaddr_change(adapter,
706 cur->mac_addr, NETXEN_MAC_DEL);
707 list_del(&cur->list);
708 kfree(cur);
709 }
710 }
711
netxen_p3_nic_set_promisc(struct netxen_adapter * adapter,u32 mode)712 static int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
713 {
714 nx_nic_req_t req;
715 u64 word;
716
717 memset(&req, 0, sizeof(nx_nic_req_t));
718
719 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
720
721 word = NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE |
722 ((u64)adapter->portnum << 16);
723 req.req_hdr = cpu_to_le64(word);
724
725 req.words[0] = cpu_to_le64(mode);
726
727 return netxen_send_cmd_descs(adapter,
728 (struct cmd_desc_type0 *)&req, 1);
729 }
730
netxen_p3_free_mac_list(struct netxen_adapter * adapter)731 void netxen_p3_free_mac_list(struct netxen_adapter *adapter)
732 {
733 nx_mac_list_t *cur;
734 struct list_head *head = &adapter->mac_list;
735
736 while (!list_empty(head)) {
737 cur = list_entry(head->next, nx_mac_list_t, list);
738 nx_p3_sre_macaddr_change(adapter,
739 cur->mac_addr, NETXEN_MAC_DEL);
740 list_del(&cur->list);
741 kfree(cur);
742 }
743 }
744
netxen_p3_nic_set_mac_addr(struct netxen_adapter * adapter,u8 * addr)745 static int netxen_p3_nic_set_mac_addr(struct netxen_adapter *adapter, u8 *addr)
746 {
747 /* assuming caller has already copied new addr to netdev */
748 netxen_p3_nic_set_multi(adapter->netdev);
749 return 0;
750 }
751
752 #define NETXEN_CONFIG_INTR_COALESCE 3
753
754 /*
755 * Send the interrupt coalescing parameter set by ethtool to the card.
756 */
netxen_config_intr_coalesce(struct netxen_adapter * adapter)757 int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
758 {
759 nx_nic_req_t req;
760 u64 word[6];
761 int rv, i;
762
763 memset(&req, 0, sizeof(nx_nic_req_t));
764 memset(word, 0, sizeof(word));
765
766 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
767
768 word[0] = NETXEN_CONFIG_INTR_COALESCE | ((u64)adapter->portnum << 16);
769 req.req_hdr = cpu_to_le64(word[0]);
770
771 memcpy(&word[0], &adapter->coal, sizeof(adapter->coal));
772 for (i = 0; i < 6; i++)
773 req.words[i] = cpu_to_le64(word[i]);
774
775 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
776 if (rv != 0) {
777 printk(KERN_ERR "ERROR. Could not send "
778 "interrupt coalescing parameters\n");
779 }
780
781 return rv;
782 }
783
netxen_config_hw_lro(struct netxen_adapter * adapter,int enable)784 int netxen_config_hw_lro(struct netxen_adapter *adapter, int enable)
785 {
786 nx_nic_req_t req;
787 u64 word;
788 int rv = 0;
789
790 if (!test_bit(__NX_FW_ATTACHED, &adapter->state))
791 return 0;
792
793 memset(&req, 0, sizeof(nx_nic_req_t));
794
795 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
796
797 word = NX_NIC_H2C_OPCODE_CONFIG_HW_LRO | ((u64)adapter->portnum << 16);
798 req.req_hdr = cpu_to_le64(word);
799
800 req.words[0] = cpu_to_le64(enable);
801
802 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
803 if (rv != 0) {
804 printk(KERN_ERR "ERROR. Could not send "
805 "configure hw lro request\n");
806 }
807
808 return rv;
809 }
810
netxen_config_bridged_mode(struct netxen_adapter * adapter,int enable)811 int netxen_config_bridged_mode(struct netxen_adapter *adapter, int enable)
812 {
813 nx_nic_req_t req;
814 u64 word;
815 int rv = 0;
816
817 if (!!(adapter->flags & NETXEN_NIC_BRIDGE_ENABLED) == enable)
818 return rv;
819
820 memset(&req, 0, sizeof(nx_nic_req_t));
821
822 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
823
824 word = NX_NIC_H2C_OPCODE_CONFIG_BRIDGING |
825 ((u64)adapter->portnum << 16);
826 req.req_hdr = cpu_to_le64(word);
827
828 req.words[0] = cpu_to_le64(enable);
829
830 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
831 if (rv != 0) {
832 printk(KERN_ERR "ERROR. Could not send "
833 "configure bridge mode request\n");
834 }
835
836 adapter->flags ^= NETXEN_NIC_BRIDGE_ENABLED;
837
838 return rv;
839 }
840
841
842 #define RSS_HASHTYPE_IP_TCP 0x3
843
netxen_config_rss(struct netxen_adapter * adapter,int enable)844 int netxen_config_rss(struct netxen_adapter *adapter, int enable)
845 {
846 nx_nic_req_t req;
847 u64 word;
848 int i, rv;
849
850 static const u64 key[] = {
851 0xbeac01fa6a42b73bULL, 0x8030f20c77cb2da3ULL,
852 0xae7b30b4d0ca2bcbULL, 0x43a38fb04167253dULL,
853 0x255b0ec26d5a56daULL
854 };
855
856
857 memset(&req, 0, sizeof(nx_nic_req_t));
858 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
859
860 word = NX_NIC_H2C_OPCODE_CONFIG_RSS | ((u64)adapter->portnum << 16);
861 req.req_hdr = cpu_to_le64(word);
862
863 /*
864 * RSS request:
865 * bits 3-0: hash_method
866 * 5-4: hash_type_ipv4
867 * 7-6: hash_type_ipv6
868 * 8: enable
869 * 9: use indirection table
870 * 47-10: reserved
871 * 63-48: indirection table mask
872 */
873 word = ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 4) |
874 ((u64)(RSS_HASHTYPE_IP_TCP & 0x3) << 6) |
875 ((u64)(enable & 0x1) << 8) |
876 ((0x7ULL) << 48);
877 req.words[0] = cpu_to_le64(word);
878 for (i = 0; i < ARRAY_SIZE(key); i++)
879 req.words[i+1] = cpu_to_le64(key[i]);
880
881
882 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
883 if (rv != 0) {
884 printk(KERN_ERR "%s: could not configure RSS\n",
885 adapter->netdev->name);
886 }
887
888 return rv;
889 }
890
netxen_config_ipaddr(struct netxen_adapter * adapter,__be32 ip,int cmd)891 int netxen_config_ipaddr(struct netxen_adapter *adapter, __be32 ip, int cmd)
892 {
893 nx_nic_req_t req;
894 u64 word;
895 int rv;
896
897 memset(&req, 0, sizeof(nx_nic_req_t));
898 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
899
900 word = NX_NIC_H2C_OPCODE_CONFIG_IPADDR | ((u64)adapter->portnum << 16);
901 req.req_hdr = cpu_to_le64(word);
902
903 req.words[0] = cpu_to_le64(cmd);
904 memcpy(&req.words[1], &ip, sizeof(u32));
905
906 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
907 if (rv != 0) {
908 printk(KERN_ERR "%s: could not notify %s IP 0x%x request\n",
909 adapter->netdev->name,
910 (cmd == NX_IP_UP) ? "Add" : "Remove", ip);
911 }
912 return rv;
913 }
914
netxen_linkevent_request(struct netxen_adapter * adapter,int enable)915 int netxen_linkevent_request(struct netxen_adapter *adapter, int enable)
916 {
917 nx_nic_req_t req;
918 u64 word;
919 int rv;
920
921 memset(&req, 0, sizeof(nx_nic_req_t));
922 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
923
924 word = NX_NIC_H2C_OPCODE_GET_LINKEVENT | ((u64)adapter->portnum << 16);
925 req.req_hdr = cpu_to_le64(word);
926 req.words[0] = cpu_to_le64(enable | (enable << 8));
927
928 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
929 if (rv != 0) {
930 printk(KERN_ERR "%s: could not configure link notification\n",
931 adapter->netdev->name);
932 }
933
934 return rv;
935 }
936
netxen_send_lro_cleanup(struct netxen_adapter * adapter)937 int netxen_send_lro_cleanup(struct netxen_adapter *adapter)
938 {
939 nx_nic_req_t req;
940 u64 word;
941 int rv;
942
943 if (!test_bit(__NX_FW_ATTACHED, &adapter->state))
944 return 0;
945
946 memset(&req, 0, sizeof(nx_nic_req_t));
947 req.qhdr = cpu_to_le64(NX_HOST_REQUEST << 23);
948
949 word = NX_NIC_H2C_OPCODE_LRO_REQUEST |
950 ((u64)adapter->portnum << 16) |
951 ((u64)NX_NIC_LRO_REQUEST_CLEANUP << 56) ;
952
953 req.req_hdr = cpu_to_le64(word);
954
955 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
956 if (rv != 0) {
957 printk(KERN_ERR "%s: could not cleanup lro flows\n",
958 adapter->netdev->name);
959 }
960 return rv;
961 }
962
963 /*
964 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
965 * @returns 0 on success, negative on failure
966 */
967
968 #define MTU_FUDGE_FACTOR 100
969
netxen_nic_change_mtu(struct net_device * netdev,int mtu)970 int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
971 {
972 struct netxen_adapter *adapter = netdev_priv(netdev);
973 int rc = 0;
974
975 if (adapter->set_mtu)
976 rc = adapter->set_mtu(adapter, mtu);
977
978 if (!rc)
979 netdev->mtu = mtu;
980
981 return rc;
982 }
983
netxen_get_flash_block(struct netxen_adapter * adapter,int base,int size,__le32 * buf)984 static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
985 int size, __le32 * buf)
986 {
987 int i, v, addr;
988 __le32 *ptr32;
989 int ret;
990
991 addr = base;
992 ptr32 = buf;
993 for (i = 0; i < size / sizeof(u32); i++) {
994 ret = netxen_rom_fast_read(adapter, addr, &v);
995 if (ret)
996 return ret;
997
998 *ptr32 = cpu_to_le32(v);
999 ptr32++;
1000 addr += sizeof(u32);
1001 }
1002 if ((char *)buf + size > (char *)ptr32) {
1003 __le32 local;
1004 ret = netxen_rom_fast_read(adapter, addr, &v);
1005 if (ret)
1006 return ret;
1007 local = cpu_to_le32(v);
1008 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
1009 }
1010
1011 return 0;
1012 }
1013
netxen_get_flash_mac_addr(struct netxen_adapter * adapter,u64 * mac)1014 int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, u64 *mac)
1015 {
1016 __le32 *pmac = (__le32 *) mac;
1017 u32 offset;
1018
1019 offset = NX_FW_MAC_ADDR_OFFSET + (adapter->portnum * sizeof(u64));
1020
1021 if (netxen_get_flash_block(adapter, offset, sizeof(u64), pmac) == -1)
1022 return -1;
1023
1024 if (*mac == ~0ULL) {
1025
1026 offset = NX_OLD_MAC_ADDR_OFFSET +
1027 (adapter->portnum * sizeof(u64));
1028
1029 if (netxen_get_flash_block(adapter,
1030 offset, sizeof(u64), pmac) == -1)
1031 return -1;
1032
1033 if (*mac == ~0ULL)
1034 return -1;
1035 }
1036 return 0;
1037 }
1038
netxen_p3_get_mac_addr(struct netxen_adapter * adapter,u64 * mac)1039 int netxen_p3_get_mac_addr(struct netxen_adapter *adapter, u64 *mac)
1040 {
1041 uint32_t crbaddr, mac_hi, mac_lo;
1042 int pci_func = adapter->ahw.pci_func;
1043
1044 crbaddr = CRB_MAC_BLOCK_START +
1045 (4 * ((pci_func/2) * 3)) + (4 * (pci_func & 1));
1046
1047 mac_lo = NXRD32(adapter, crbaddr);
1048 mac_hi = NXRD32(adapter, crbaddr+4);
1049
1050 if (pci_func & 1)
1051 *mac = le64_to_cpu((mac_lo >> 16) | ((u64)mac_hi << 16));
1052 else
1053 *mac = le64_to_cpu((u64)mac_lo | ((u64)mac_hi << 32));
1054
1055 return 0;
1056 }
1057
1058 /*
1059 * Changes the CRB window to the specified window.
1060 */
1061 static void
netxen_nic_pci_set_crbwindow_128M(struct netxen_adapter * adapter,u32 window)1062 netxen_nic_pci_set_crbwindow_128M(struct netxen_adapter *adapter,
1063 u32 window)
1064 {
1065 void __iomem *offset;
1066 int count = 10;
1067 u8 func = adapter->ahw.pci_func;
1068
1069 if (adapter->ahw.crb_win == window)
1070 return;
1071
1072 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1073 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
1074
1075 writel(window, offset);
1076 do {
1077 if (window == readl(offset))
1078 break;
1079
1080 if (printk_ratelimit())
1081 dev_warn(&adapter->pdev->dev,
1082 "failed to set CRB window to %d\n",
1083 (window == NETXEN_WINDOW_ONE));
1084 udelay(1);
1085
1086 } while (--count > 0);
1087
1088 if (count > 0)
1089 adapter->ahw.crb_win = window;
1090 }
1091
1092 /*
1093 * Returns < 0 if off is not valid,
1094 * 1 if window access is needed. 'off' is set to offset from
1095 * CRB space in 128M pci map
1096 * 0 if no window access is needed. 'off' is set to 2M addr
1097 * In: 'off' is offset from base in 128M pci map
1098 */
1099 static int
netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter * adapter,ulong off,void __iomem ** addr)1100 netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter,
1101 ulong off, void __iomem **addr)
1102 {
1103 crb_128M_2M_sub_block_map_t *m;
1104
1105
1106 if ((off >= NETXEN_CRB_MAX) || (off < NETXEN_PCI_CRBSPACE))
1107 return -EINVAL;
1108
1109 off -= NETXEN_PCI_CRBSPACE;
1110
1111 /*
1112 * Try direct map
1113 */
1114 m = &crb_128M_2M_map[CRB_BLK(off)].sub_block[CRB_SUBBLK(off)];
1115
1116 if (m->valid && (m->start_128M <= off) && (m->end_128M > off)) {
1117 *addr = adapter->ahw.pci_base0 + m->start_2M +
1118 (off - m->start_128M);
1119 return 0;
1120 }
1121
1122 /*
1123 * Not in direct map, use crb window
1124 */
1125 *addr = adapter->ahw.pci_base0 + CRB_INDIRECT_2M +
1126 (off & MASK(16));
1127 return 1;
1128 }
1129
1130 /*
1131 * In: 'off' is offset from CRB space in 128M pci map
1132 * Out: 'off' is 2M pci map addr
1133 * side effect: lock crb window
1134 */
1135 static void
netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter * adapter,ulong off)1136 netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong off)
1137 {
1138 u32 window;
1139 void __iomem *addr = adapter->ahw.pci_base0 + CRB_WINDOW_2M;
1140
1141 off -= NETXEN_PCI_CRBSPACE;
1142
1143 window = CRB_HI(off);
1144
1145 writel(window, addr);
1146 if (readl(addr) != window) {
1147 if (printk_ratelimit())
1148 dev_warn(&adapter->pdev->dev,
1149 "failed to set CRB window to %d off 0x%lx\n",
1150 window, off);
1151 }
1152 }
1153
1154 static void __iomem *
netxen_nic_map_indirect_address_128M(struct netxen_adapter * adapter,ulong win_off,void __iomem ** mem_ptr)1155 netxen_nic_map_indirect_address_128M(struct netxen_adapter *adapter,
1156 ulong win_off, void __iomem **mem_ptr)
1157 {
1158 ulong off = win_off;
1159 void __iomem *addr;
1160 resource_size_t mem_base;
1161
1162 if (ADDR_IN_WINDOW1(win_off))
1163 off = NETXEN_CRB_NORMAL(win_off);
1164
1165 addr = pci_base_offset(adapter, off);
1166 if (addr)
1167 return addr;
1168
1169 if (adapter->ahw.pci_len0 == 0)
1170 off -= NETXEN_PCI_CRBSPACE;
1171
1172 mem_base = pci_resource_start(adapter->pdev, 0);
1173 *mem_ptr = ioremap(mem_base + (off & PAGE_MASK), PAGE_SIZE);
1174 if (*mem_ptr)
1175 addr = *mem_ptr + (off & (PAGE_SIZE - 1));
1176
1177 return addr;
1178 }
1179
1180 static int
netxen_nic_hw_write_wx_128M(struct netxen_adapter * adapter,ulong off,u32 data)1181 netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter, ulong off, u32 data)
1182 {
1183 unsigned long flags;
1184 void __iomem *addr, *mem_ptr = NULL;
1185
1186 addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr);
1187 if (!addr)
1188 return -EIO;
1189
1190 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1191 netxen_nic_io_write_128M(adapter, addr, data);
1192 } else { /* Window 0 */
1193 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
1194 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1195 writel(data, addr);
1196 netxen_nic_pci_set_crbwindow_128M(adapter,
1197 NETXEN_WINDOW_ONE);
1198 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
1199 }
1200
1201 if (mem_ptr)
1202 iounmap(mem_ptr);
1203
1204 return 0;
1205 }
1206
1207 static u32
netxen_nic_hw_read_wx_128M(struct netxen_adapter * adapter,ulong off)1208 netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter, ulong off)
1209 {
1210 unsigned long flags;
1211 void __iomem *addr, *mem_ptr = NULL;
1212 u32 data;
1213
1214 addr = netxen_nic_map_indirect_address_128M(adapter, off, &mem_ptr);
1215 if (!addr)
1216 return -EIO;
1217
1218 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1219 data = netxen_nic_io_read_128M(adapter, addr);
1220 } else { /* Window 0 */
1221 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
1222 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1223 data = readl(addr);
1224 netxen_nic_pci_set_crbwindow_128M(adapter,
1225 NETXEN_WINDOW_ONE);
1226 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
1227 }
1228
1229 if (mem_ptr)
1230 iounmap(mem_ptr);
1231
1232 return data;
1233 }
1234
1235 static int
netxen_nic_hw_write_wx_2M(struct netxen_adapter * adapter,ulong off,u32 data)1236 netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter, ulong off, u32 data)
1237 {
1238 unsigned long flags;
1239 int rv;
1240 void __iomem *addr = NULL;
1241
1242 rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr);
1243
1244 if (rv == 0) {
1245 writel(data, addr);
1246 return 0;
1247 }
1248
1249 if (rv > 0) {
1250 /* indirect access */
1251 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
1252 crb_win_lock(adapter);
1253 netxen_nic_pci_set_crbwindow_2M(adapter, off);
1254 writel(data, addr);
1255 crb_win_unlock(adapter);
1256 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
1257 return 0;
1258 }
1259
1260 dev_err(&adapter->pdev->dev,
1261 "%s: invalid offset: 0x%016lx\n", __func__, off);
1262 dump_stack();
1263 return -EIO;
1264 }
1265
1266 static u32
netxen_nic_hw_read_wx_2M(struct netxen_adapter * adapter,ulong off)1267 netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter, ulong off)
1268 {
1269 unsigned long flags;
1270 int rv;
1271 u32 data;
1272 void __iomem *addr = NULL;
1273
1274 rv = netxen_nic_pci_get_crb_addr_2M(adapter, off, &addr);
1275
1276 if (rv == 0)
1277 return readl(addr);
1278
1279 if (rv > 0) {
1280 /* indirect access */
1281 write_lock_irqsave(&adapter->ahw.crb_lock, flags);
1282 crb_win_lock(adapter);
1283 netxen_nic_pci_set_crbwindow_2M(adapter, off);
1284 data = readl(addr);
1285 crb_win_unlock(adapter);
1286 write_unlock_irqrestore(&adapter->ahw.crb_lock, flags);
1287 return data;
1288 }
1289
1290 dev_err(&adapter->pdev->dev,
1291 "%s: invalid offset: 0x%016lx\n", __func__, off);
1292 dump_stack();
1293 return -1;
1294 }
1295
1296 /* window 1 registers only */
netxen_nic_io_write_128M(struct netxen_adapter * adapter,void __iomem * addr,u32 data)1297 static void netxen_nic_io_write_128M(struct netxen_adapter *adapter,
1298 void __iomem *addr, u32 data)
1299 {
1300 read_lock(&adapter->ahw.crb_lock);
1301 writel(data, addr);
1302 read_unlock(&adapter->ahw.crb_lock);
1303 }
1304
netxen_nic_io_read_128M(struct netxen_adapter * adapter,void __iomem * addr)1305 static u32 netxen_nic_io_read_128M(struct netxen_adapter *adapter,
1306 void __iomem *addr)
1307 {
1308 u32 val;
1309
1310 read_lock(&adapter->ahw.crb_lock);
1311 val = readl(addr);
1312 read_unlock(&adapter->ahw.crb_lock);
1313
1314 return val;
1315 }
1316
netxen_nic_io_write_2M(struct netxen_adapter * adapter,void __iomem * addr,u32 data)1317 static void netxen_nic_io_write_2M(struct netxen_adapter *adapter,
1318 void __iomem *addr, u32 data)
1319 {
1320 writel(data, addr);
1321 }
1322
netxen_nic_io_read_2M(struct netxen_adapter * adapter,void __iomem * addr)1323 static u32 netxen_nic_io_read_2M(struct netxen_adapter *adapter,
1324 void __iomem *addr)
1325 {
1326 return readl(addr);
1327 }
1328
1329 void __iomem *
netxen_get_ioaddr(struct netxen_adapter * adapter,u32 offset)1330 netxen_get_ioaddr(struct netxen_adapter *adapter, u32 offset)
1331 {
1332 void __iomem *addr = NULL;
1333
1334 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1335 if ((offset < NETXEN_CRB_PCIX_HOST2) &&
1336 (offset > NETXEN_CRB_PCIX_HOST))
1337 addr = PCI_OFFSET_SECOND_RANGE(adapter, offset);
1338 else
1339 addr = NETXEN_CRB_NORMALIZE(adapter, offset);
1340 } else {
1341 WARN_ON(netxen_nic_pci_get_crb_addr_2M(adapter,
1342 offset, &addr));
1343 }
1344
1345 return addr;
1346 }
1347
1348 static int
netxen_nic_pci_set_window_128M(struct netxen_adapter * adapter,u64 addr,u32 * start)1349 netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1350 u64 addr, u32 *start)
1351 {
1352 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1353 *start = (addr - NETXEN_ADDR_OCM0 + NETXEN_PCI_OCM0);
1354 return 0;
1355 } else if (ADDR_IN_RANGE(addr,
1356 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1357 *start = (addr - NETXEN_ADDR_OCM1 + NETXEN_PCI_OCM1);
1358 return 0;
1359 }
1360
1361 return -EIO;
1362 }
1363
1364 static int
netxen_nic_pci_set_window_2M(struct netxen_adapter * adapter,u64 addr,u32 * start)1365 netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1366 u64 addr, u32 *start)
1367 {
1368 u32 window;
1369
1370 window = OCM_WIN(addr);
1371
1372 writel(window, adapter->ahw.ocm_win_crb);
1373 /* read back to flush */
1374 readl(adapter->ahw.ocm_win_crb);
1375
1376 adapter->ahw.ocm_win = window;
1377 *start = NETXEN_PCI_OCM0_2M + GET_MEM_OFFS_2M(addr);
1378 return 0;
1379 }
1380
1381 static int
netxen_nic_pci_mem_access_direct(struct netxen_adapter * adapter,u64 off,u64 * data,int op)1382 netxen_nic_pci_mem_access_direct(struct netxen_adapter *adapter, u64 off,
1383 u64 *data, int op)
1384 {
1385 void __iomem *addr, *mem_ptr = NULL;
1386 resource_size_t mem_base;
1387 int ret;
1388 u32 start;
1389
1390 spin_lock(&adapter->ahw.mem_lock);
1391
1392 ret = adapter->pci_set_window(adapter, off, &start);
1393 if (ret != 0)
1394 goto unlock;
1395
1396 if (NX_IS_REVISION_P3(adapter->ahw.revision_id)) {
1397 addr = adapter->ahw.pci_base0 + start;
1398 } else {
1399 addr = pci_base_offset(adapter, start);
1400 if (addr)
1401 goto noremap;
1402
1403 mem_base = pci_resource_start(adapter->pdev, 0) +
1404 (start & PAGE_MASK);
1405 mem_ptr = ioremap(mem_base, PAGE_SIZE);
1406 if (mem_ptr == NULL) {
1407 ret = -EIO;
1408 goto unlock;
1409 }
1410
1411 addr = mem_ptr + (start & (PAGE_SIZE-1));
1412 }
1413 noremap:
1414 if (op == 0) /* read */
1415 *data = readq(addr);
1416 else /* write */
1417 writeq(*data, addr);
1418
1419 unlock:
1420 spin_unlock(&adapter->ahw.mem_lock);
1421
1422 if (mem_ptr)
1423 iounmap(mem_ptr);
1424 return ret;
1425 }
1426
1427 void
netxen_pci_camqm_read_2M(struct netxen_adapter * adapter,u64 off,u64 * data)1428 netxen_pci_camqm_read_2M(struct netxen_adapter *adapter, u64 off, u64 *data)
1429 {
1430 void __iomem *addr = adapter->ahw.pci_base0 +
1431 NETXEN_PCI_CAMQM_2M_BASE + (off - NETXEN_PCI_CAMQM);
1432
1433 spin_lock(&adapter->ahw.mem_lock);
1434 *data = readq(addr);
1435 spin_unlock(&adapter->ahw.mem_lock);
1436 }
1437
1438 void
netxen_pci_camqm_write_2M(struct netxen_adapter * adapter,u64 off,u64 data)1439 netxen_pci_camqm_write_2M(struct netxen_adapter *adapter, u64 off, u64 data)
1440 {
1441 void __iomem *addr = adapter->ahw.pci_base0 +
1442 NETXEN_PCI_CAMQM_2M_BASE + (off - NETXEN_PCI_CAMQM);
1443
1444 spin_lock(&adapter->ahw.mem_lock);
1445 writeq(data, addr);
1446 spin_unlock(&adapter->ahw.mem_lock);
1447 }
1448
1449 #define MAX_CTL_CHECK 1000
1450
1451 static int
netxen_nic_pci_mem_write_128M(struct netxen_adapter * adapter,u64 off,u64 data)1452 netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1453 u64 off, u64 data)
1454 {
1455 int j, ret;
1456 u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo;
1457 void __iomem *mem_crb;
1458
1459 /* Only 64-bit aligned access */
1460 if (off & 7)
1461 return -EIO;
1462
1463 /* P2 has different SIU and MIU test agent base addr */
1464 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1465 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1466 mem_crb = pci_base_offset(adapter,
1467 NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE);
1468 addr_hi = SIU_TEST_AGT_ADDR_HI;
1469 data_lo = SIU_TEST_AGT_WRDATA_LO;
1470 data_hi = SIU_TEST_AGT_WRDATA_HI;
1471 off_lo = off & SIU_TEST_AGT_ADDR_MASK;
1472 off_hi = SIU_TEST_AGT_UPPER_ADDR(off);
1473 goto correct;
1474 }
1475
1476 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1477 mem_crb = pci_base_offset(adapter,
1478 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1479 addr_hi = MIU_TEST_AGT_ADDR_HI;
1480 data_lo = MIU_TEST_AGT_WRDATA_LO;
1481 data_hi = MIU_TEST_AGT_WRDATA_HI;
1482 off_lo = off & MIU_TEST_AGT_ADDR_MASK;
1483 off_hi = 0;
1484 goto correct;
1485 }
1486
1487 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) ||
1488 ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1489 if (adapter->ahw.pci_len0 != 0) {
1490 return netxen_nic_pci_mem_access_direct(adapter,
1491 off, &data, 1);
1492 }
1493 }
1494
1495 return -EIO;
1496
1497 correct:
1498 spin_lock(&adapter->ahw.mem_lock);
1499 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1500
1501 writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1502 writel(off_hi, (mem_crb + addr_hi));
1503 writel(data & 0xffffffff, (mem_crb + data_lo));
1504 writel((data >> 32) & 0xffffffff, (mem_crb + data_hi));
1505 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1506 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1507 (mem_crb + TEST_AGT_CTRL));
1508
1509 for (j = 0; j < MAX_CTL_CHECK; j++) {
1510 temp = readl((mem_crb + TEST_AGT_CTRL));
1511 if ((temp & TA_CTL_BUSY) == 0)
1512 break;
1513 }
1514
1515 if (j >= MAX_CTL_CHECK) {
1516 if (printk_ratelimit())
1517 dev_err(&adapter->pdev->dev,
1518 "failed to write through agent\n");
1519 ret = -EIO;
1520 } else
1521 ret = 0;
1522
1523 netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE);
1524 spin_unlock(&adapter->ahw.mem_lock);
1525 return ret;
1526 }
1527
1528 static int
netxen_nic_pci_mem_read_128M(struct netxen_adapter * adapter,u64 off,u64 * data)1529 netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1530 u64 off, u64 *data)
1531 {
1532 int j, ret;
1533 u32 temp, off_lo, off_hi, addr_hi, data_hi, data_lo;
1534 u64 val;
1535 void __iomem *mem_crb;
1536
1537 /* Only 64-bit aligned access */
1538 if (off & 7)
1539 return -EIO;
1540
1541 /* P2 has different SIU and MIU test agent base addr */
1542 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1543 NETXEN_ADDR_QDR_NET_MAX_P2)) {
1544 mem_crb = pci_base_offset(adapter,
1545 NETXEN_CRB_QDR_NET+SIU_TEST_AGT_BASE);
1546 addr_hi = SIU_TEST_AGT_ADDR_HI;
1547 data_lo = SIU_TEST_AGT_RDDATA_LO;
1548 data_hi = SIU_TEST_AGT_RDDATA_HI;
1549 off_lo = off & SIU_TEST_AGT_ADDR_MASK;
1550 off_hi = SIU_TEST_AGT_UPPER_ADDR(off);
1551 goto correct;
1552 }
1553
1554 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1555 mem_crb = pci_base_offset(adapter,
1556 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1557 addr_hi = MIU_TEST_AGT_ADDR_HI;
1558 data_lo = MIU_TEST_AGT_RDDATA_LO;
1559 data_hi = MIU_TEST_AGT_RDDATA_HI;
1560 off_lo = off & MIU_TEST_AGT_ADDR_MASK;
1561 off_hi = 0;
1562 goto correct;
1563 }
1564
1565 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX) ||
1566 ADDR_IN_RANGE(off, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1567 if (adapter->ahw.pci_len0 != 0) {
1568 return netxen_nic_pci_mem_access_direct(adapter,
1569 off, data, 0);
1570 }
1571 }
1572
1573 return -EIO;
1574
1575 correct:
1576 spin_lock(&adapter->ahw.mem_lock);
1577 netxen_nic_pci_set_crbwindow_128M(adapter, 0);
1578
1579 writel(off_lo, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1580 writel(off_hi, (mem_crb + addr_hi));
1581 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1582 writel((TA_CTL_START|TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1583
1584 for (j = 0; j < MAX_CTL_CHECK; j++) {
1585 temp = readl(mem_crb + TEST_AGT_CTRL);
1586 if ((temp & TA_CTL_BUSY) == 0)
1587 break;
1588 }
1589
1590 if (j >= MAX_CTL_CHECK) {
1591 if (printk_ratelimit())
1592 dev_err(&adapter->pdev->dev,
1593 "failed to read through agent\n");
1594 ret = -EIO;
1595 } else {
1596
1597 temp = readl(mem_crb + data_hi);
1598 val = ((u64)temp << 32);
1599 val |= readl(mem_crb + data_lo);
1600 *data = val;
1601 ret = 0;
1602 }
1603
1604 netxen_nic_pci_set_crbwindow_128M(adapter, NETXEN_WINDOW_ONE);
1605 spin_unlock(&adapter->ahw.mem_lock);
1606
1607 return ret;
1608 }
1609
1610 static int
netxen_nic_pci_mem_write_2M(struct netxen_adapter * adapter,u64 off,u64 data)1611 netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1612 u64 off, u64 data)
1613 {
1614 int j, ret;
1615 u32 temp, off8;
1616 void __iomem *mem_crb;
1617
1618 /* Only 64-bit aligned access */
1619 if (off & 7)
1620 return -EIO;
1621
1622 /* P3 onward, test agent base for MIU and SIU is same */
1623 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1624 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1625 mem_crb = netxen_get_ioaddr(adapter,
1626 NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1627 goto correct;
1628 }
1629
1630 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1631 mem_crb = netxen_get_ioaddr(adapter,
1632 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1633 goto correct;
1634 }
1635
1636 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX))
1637 return netxen_nic_pci_mem_access_direct(adapter, off, &data, 1);
1638
1639 return -EIO;
1640
1641 correct:
1642 off8 = off & 0xfffffff8;
1643
1644 spin_lock(&adapter->ahw.mem_lock);
1645
1646 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1647 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1648
1649 writel(data & 0xffffffff,
1650 mem_crb + MIU_TEST_AGT_WRDATA_LO);
1651 writel((data >> 32) & 0xffffffff,
1652 mem_crb + MIU_TEST_AGT_WRDATA_HI);
1653
1654 writel((TA_CTL_ENABLE | TA_CTL_WRITE), (mem_crb + TEST_AGT_CTRL));
1655 writel((TA_CTL_START | TA_CTL_ENABLE | TA_CTL_WRITE),
1656 (mem_crb + TEST_AGT_CTRL));
1657
1658 for (j = 0; j < MAX_CTL_CHECK; j++) {
1659 temp = readl(mem_crb + TEST_AGT_CTRL);
1660 if ((temp & TA_CTL_BUSY) == 0)
1661 break;
1662 }
1663
1664 if (j >= MAX_CTL_CHECK) {
1665 if (printk_ratelimit())
1666 dev_err(&adapter->pdev->dev,
1667 "failed to write through agent\n");
1668 ret = -EIO;
1669 } else
1670 ret = 0;
1671
1672 spin_unlock(&adapter->ahw.mem_lock);
1673
1674 return ret;
1675 }
1676
1677 static int
netxen_nic_pci_mem_read_2M(struct netxen_adapter * adapter,u64 off,u64 * data)1678 netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1679 u64 off, u64 *data)
1680 {
1681 int j, ret;
1682 u32 temp, off8;
1683 u64 val;
1684 void __iomem *mem_crb;
1685
1686 /* Only 64-bit aligned access */
1687 if (off & 7)
1688 return -EIO;
1689
1690 /* P3 onward, test agent base for MIU and SIU is same */
1691 if (ADDR_IN_RANGE(off, NETXEN_ADDR_QDR_NET,
1692 NETXEN_ADDR_QDR_NET_MAX_P3)) {
1693 mem_crb = netxen_get_ioaddr(adapter,
1694 NETXEN_CRB_QDR_NET+MIU_TEST_AGT_BASE);
1695 goto correct;
1696 }
1697
1698 if (ADDR_IN_RANGE(off, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1699 mem_crb = netxen_get_ioaddr(adapter,
1700 NETXEN_CRB_DDR_NET+MIU_TEST_AGT_BASE);
1701 goto correct;
1702 }
1703
1704 if (ADDR_IN_RANGE(off, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1705 return netxen_nic_pci_mem_access_direct(adapter,
1706 off, data, 0);
1707 }
1708
1709 return -EIO;
1710
1711 correct:
1712 off8 = off & 0xfffffff8;
1713
1714 spin_lock(&adapter->ahw.mem_lock);
1715
1716 writel(off8, (mem_crb + MIU_TEST_AGT_ADDR_LO));
1717 writel(0, (mem_crb + MIU_TEST_AGT_ADDR_HI));
1718 writel(TA_CTL_ENABLE, (mem_crb + TEST_AGT_CTRL));
1719 writel((TA_CTL_START | TA_CTL_ENABLE), (mem_crb + TEST_AGT_CTRL));
1720
1721 for (j = 0; j < MAX_CTL_CHECK; j++) {
1722 temp = readl(mem_crb + TEST_AGT_CTRL);
1723 if ((temp & TA_CTL_BUSY) == 0)
1724 break;
1725 }
1726
1727 if (j >= MAX_CTL_CHECK) {
1728 if (printk_ratelimit())
1729 dev_err(&adapter->pdev->dev,
1730 "failed to read through agent\n");
1731 ret = -EIO;
1732 } else {
1733 val = (u64)(readl(mem_crb + MIU_TEST_AGT_RDDATA_HI)) << 32;
1734 val |= readl(mem_crb + MIU_TEST_AGT_RDDATA_LO);
1735 *data = val;
1736 ret = 0;
1737 }
1738
1739 spin_unlock(&adapter->ahw.mem_lock);
1740
1741 return ret;
1742 }
1743
1744 void
netxen_setup_hwops(struct netxen_adapter * adapter)1745 netxen_setup_hwops(struct netxen_adapter *adapter)
1746 {
1747 adapter->init_port = netxen_niu_xg_init_port;
1748 adapter->stop_port = netxen_niu_disable_xg_port;
1749
1750 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1751 adapter->crb_read = netxen_nic_hw_read_wx_128M,
1752 adapter->crb_write = netxen_nic_hw_write_wx_128M,
1753 adapter->pci_set_window = netxen_nic_pci_set_window_128M,
1754 adapter->pci_mem_read = netxen_nic_pci_mem_read_128M,
1755 adapter->pci_mem_write = netxen_nic_pci_mem_write_128M,
1756 adapter->io_read = netxen_nic_io_read_128M,
1757 adapter->io_write = netxen_nic_io_write_128M,
1758
1759 adapter->macaddr_set = netxen_p2_nic_set_mac_addr;
1760 adapter->set_multi = netxen_p2_nic_set_multi;
1761 adapter->set_mtu = netxen_nic_set_mtu_xgb;
1762 adapter->set_promisc = netxen_p2_nic_set_promisc;
1763
1764 } else {
1765 adapter->crb_read = netxen_nic_hw_read_wx_2M,
1766 adapter->crb_write = netxen_nic_hw_write_wx_2M,
1767 adapter->pci_set_window = netxen_nic_pci_set_window_2M,
1768 adapter->pci_mem_read = netxen_nic_pci_mem_read_2M,
1769 adapter->pci_mem_write = netxen_nic_pci_mem_write_2M,
1770 adapter->io_read = netxen_nic_io_read_2M,
1771 adapter->io_write = netxen_nic_io_write_2M,
1772
1773 adapter->set_mtu = nx_fw_cmd_set_mtu;
1774 adapter->set_promisc = netxen_p3_nic_set_promisc;
1775 adapter->macaddr_set = netxen_p3_nic_set_mac_addr;
1776 adapter->set_multi = netxen_p3_nic_set_multi;
1777
1778 adapter->phy_read = nx_fw_cmd_query_phy;
1779 adapter->phy_write = nx_fw_cmd_set_phy;
1780 }
1781 }
1782
netxen_nic_get_board_info(struct netxen_adapter * adapter)1783 int netxen_nic_get_board_info(struct netxen_adapter *adapter)
1784 {
1785 int offset, board_type, magic;
1786 struct pci_dev *pdev = adapter->pdev;
1787
1788 offset = NX_FW_MAGIC_OFFSET;
1789 if (netxen_rom_fast_read(adapter, offset, &magic))
1790 return -EIO;
1791
1792 if (magic != NETXEN_BDINFO_MAGIC) {
1793 dev_err(&pdev->dev, "invalid board config, magic=%08x\n",
1794 magic);
1795 return -EIO;
1796 }
1797
1798 offset = NX_BRDTYPE_OFFSET;
1799 if (netxen_rom_fast_read(adapter, offset, &board_type))
1800 return -EIO;
1801
1802 if (board_type == NETXEN_BRDTYPE_P3_4_GB_MM) {
1803 u32 gpio = NXRD32(adapter, NETXEN_ROMUSB_GLB_PAD_GPIO_I);
1804 if ((gpio & 0x8000) == 0)
1805 board_type = NETXEN_BRDTYPE_P3_10G_TP;
1806 }
1807
1808 adapter->ahw.board_type = board_type;
1809
1810 switch (board_type) {
1811 case NETXEN_BRDTYPE_P2_SB35_4G:
1812 adapter->ahw.port_type = NETXEN_NIC_GBE;
1813 break;
1814 case NETXEN_BRDTYPE_P2_SB31_10G:
1815 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
1816 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
1817 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
1818 case NETXEN_BRDTYPE_P3_HMEZ:
1819 case NETXEN_BRDTYPE_P3_XG_LOM:
1820 case NETXEN_BRDTYPE_P3_10G_CX4:
1821 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
1822 case NETXEN_BRDTYPE_P3_IMEZ:
1823 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
1824 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
1825 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
1826 case NETXEN_BRDTYPE_P3_10G_XFP:
1827 case NETXEN_BRDTYPE_P3_10000_BASE_T:
1828 adapter->ahw.port_type = NETXEN_NIC_XGBE;
1829 break;
1830 case NETXEN_BRDTYPE_P1_BD:
1831 case NETXEN_BRDTYPE_P1_SB:
1832 case NETXEN_BRDTYPE_P1_SMAX:
1833 case NETXEN_BRDTYPE_P1_SOCK:
1834 case NETXEN_BRDTYPE_P3_REF_QG:
1835 case NETXEN_BRDTYPE_P3_4_GB:
1836 case NETXEN_BRDTYPE_P3_4_GB_MM:
1837 adapter->ahw.port_type = NETXEN_NIC_GBE;
1838 break;
1839 case NETXEN_BRDTYPE_P3_10G_TP:
1840 adapter->ahw.port_type = (adapter->portnum < 2) ?
1841 NETXEN_NIC_XGBE : NETXEN_NIC_GBE;
1842 break;
1843 default:
1844 dev_err(&pdev->dev, "unknown board type %x\n", board_type);
1845 adapter->ahw.port_type = NETXEN_NIC_XGBE;
1846 break;
1847 }
1848
1849 return 0;
1850 }
1851
1852 /* NIU access sections */
netxen_nic_set_mtu_xgb(struct netxen_adapter * adapter,int new_mtu)1853 static int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
1854 {
1855 new_mtu += MTU_FUDGE_FACTOR;
1856 if (adapter->physical_port == 0)
1857 NXWR32(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE, new_mtu);
1858 else
1859 NXWR32(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE, new_mtu);
1860 return 0;
1861 }
1862
netxen_nic_set_link_parameters(struct netxen_adapter * adapter)1863 void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
1864 {
1865 __u32 status;
1866 __u32 autoneg;
1867 __u32 port_mode;
1868
1869 if (!netif_carrier_ok(adapter->netdev)) {
1870 adapter->link_speed = 0;
1871 adapter->link_duplex = -1;
1872 adapter->link_autoneg = AUTONEG_ENABLE;
1873 return;
1874 }
1875
1876 if (adapter->ahw.port_type == NETXEN_NIC_GBE) {
1877 port_mode = NXRD32(adapter, NETXEN_PORT_MODE_ADDR);
1878 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
1879 adapter->link_speed = SPEED_1000;
1880 adapter->link_duplex = DUPLEX_FULL;
1881 adapter->link_autoneg = AUTONEG_DISABLE;
1882 return;
1883 }
1884
1885 if (adapter->phy_read &&
1886 adapter->phy_read(adapter,
1887 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
1888 &status) == 0) {
1889 if (netxen_get_phy_link(status)) {
1890 switch (netxen_get_phy_speed(status)) {
1891 case 0:
1892 adapter->link_speed = SPEED_10;
1893 break;
1894 case 1:
1895 adapter->link_speed = SPEED_100;
1896 break;
1897 case 2:
1898 adapter->link_speed = SPEED_1000;
1899 break;
1900 default:
1901 adapter->link_speed = 0;
1902 break;
1903 }
1904 switch (netxen_get_phy_duplex(status)) {
1905 case 0:
1906 adapter->link_duplex = DUPLEX_HALF;
1907 break;
1908 case 1:
1909 adapter->link_duplex = DUPLEX_FULL;
1910 break;
1911 default:
1912 adapter->link_duplex = -1;
1913 break;
1914 }
1915 if (adapter->phy_read &&
1916 adapter->phy_read(adapter,
1917 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
1918 &autoneg) == 0)
1919 adapter->link_autoneg = autoneg;
1920 } else
1921 goto link_down;
1922 } else {
1923 link_down:
1924 adapter->link_speed = 0;
1925 adapter->link_duplex = -1;
1926 }
1927 }
1928 }
1929
1930 int
netxen_nic_wol_supported(struct netxen_adapter * adapter)1931 netxen_nic_wol_supported(struct netxen_adapter *adapter)
1932 {
1933 u32 wol_cfg;
1934
1935 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1936 return 0;
1937
1938 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG_NV);
1939 if (wol_cfg & (1UL << adapter->portnum)) {
1940 wol_cfg = NXRD32(adapter, NETXEN_WOL_CONFIG);
1941 if (wol_cfg & (1 << adapter->portnum))
1942 return 1;
1943 }
1944
1945 return 0;
1946 }
1947
netxen_md_cntrl(struct netxen_adapter * adapter,struct netxen_minidump_template_hdr * template_hdr,struct netxen_minidump_entry_crb * crtEntry)1948 static u32 netxen_md_cntrl(struct netxen_adapter *adapter,
1949 struct netxen_minidump_template_hdr *template_hdr,
1950 struct netxen_minidump_entry_crb *crtEntry)
1951 {
1952 int loop_cnt, i, rv = 0, timeout_flag;
1953 u32 op_count, stride;
1954 u32 opcode, read_value, addr;
1955 unsigned long timeout, timeout_jiffies;
1956 addr = crtEntry->addr;
1957 op_count = crtEntry->op_count;
1958 stride = crtEntry->addr_stride;
1959
1960 for (loop_cnt = 0; loop_cnt < op_count; loop_cnt++) {
1961 for (i = 0; i < sizeof(crtEntry->opcode) * 8; i++) {
1962 opcode = (crtEntry->opcode & (0x1 << i));
1963 if (opcode) {
1964 switch (opcode) {
1965 case NX_DUMP_WCRB:
1966 NX_WR_DUMP_REG(addr,
1967 adapter->ahw.pci_base0,
1968 crtEntry->value_1);
1969 break;
1970 case NX_DUMP_RWCRB:
1971 NX_RD_DUMP_REG(addr,
1972 adapter->ahw.pci_base0,
1973 &read_value);
1974 NX_WR_DUMP_REG(addr,
1975 adapter->ahw.pci_base0,
1976 read_value);
1977 break;
1978 case NX_DUMP_ANDCRB:
1979 NX_RD_DUMP_REG(addr,
1980 adapter->ahw.pci_base0,
1981 &read_value);
1982 read_value &= crtEntry->value_2;
1983 NX_WR_DUMP_REG(addr,
1984 adapter->ahw.pci_base0,
1985 read_value);
1986 break;
1987 case NX_DUMP_ORCRB:
1988 NX_RD_DUMP_REG(addr,
1989 adapter->ahw.pci_base0,
1990 &read_value);
1991 read_value |= crtEntry->value_3;
1992 NX_WR_DUMP_REG(addr,
1993 adapter->ahw.pci_base0,
1994 read_value);
1995 break;
1996 case NX_DUMP_POLLCRB:
1997 timeout = crtEntry->poll_timeout;
1998 NX_RD_DUMP_REG(addr,
1999 adapter->ahw.pci_base0,
2000 &read_value);
2001 timeout_jiffies =
2002 msecs_to_jiffies(timeout) + jiffies;
2003 for (timeout_flag = 0;
2004 !timeout_flag
2005 && ((read_value & crtEntry->value_2)
2006 != crtEntry->value_1);) {
2007 if (time_after(jiffies,
2008 timeout_jiffies))
2009 timeout_flag = 1;
2010 NX_RD_DUMP_REG(addr,
2011 adapter->ahw.pci_base0,
2012 &read_value);
2013 }
2014
2015 if (timeout_flag) {
2016 dev_err(&adapter->pdev->dev, "%s : "
2017 "Timeout in poll_crb control operation.\n"
2018 , __func__);
2019 return -1;
2020 }
2021 break;
2022 case NX_DUMP_RD_SAVE:
2023 /* Decide which address to use */
2024 if (crtEntry->state_index_a)
2025 addr =
2026 template_hdr->saved_state_array
2027 [crtEntry->state_index_a];
2028 NX_RD_DUMP_REG(addr,
2029 adapter->ahw.pci_base0,
2030 &read_value);
2031 template_hdr->saved_state_array
2032 [crtEntry->state_index_v]
2033 = read_value;
2034 break;
2035 case NX_DUMP_WRT_SAVED:
2036 /* Decide which value to use */
2037 if (crtEntry->state_index_v)
2038 read_value =
2039 template_hdr->saved_state_array
2040 [crtEntry->state_index_v];
2041 else
2042 read_value = crtEntry->value_1;
2043
2044 /* Decide which address to use */
2045 if (crtEntry->state_index_a)
2046 addr =
2047 template_hdr->saved_state_array
2048 [crtEntry->state_index_a];
2049
2050 NX_WR_DUMP_REG(addr,
2051 adapter->ahw.pci_base0,
2052 read_value);
2053 break;
2054 case NX_DUMP_MOD_SAVE_ST:
2055 read_value =
2056 template_hdr->saved_state_array
2057 [crtEntry->state_index_v];
2058 read_value <<= crtEntry->shl;
2059 read_value >>= crtEntry->shr;
2060 if (crtEntry->value_2)
2061 read_value &=
2062 crtEntry->value_2;
2063 read_value |= crtEntry->value_3;
2064 read_value += crtEntry->value_1;
2065 /* Write value back to state area.*/
2066 template_hdr->saved_state_array
2067 [crtEntry->state_index_v]
2068 = read_value;
2069 break;
2070 default:
2071 rv = 1;
2072 break;
2073 }
2074 }
2075 }
2076 addr = addr + stride;
2077 }
2078 return rv;
2079 }
2080
2081 /* Read memory or MN */
2082 static u32
netxen_md_rdmem(struct netxen_adapter * adapter,struct netxen_minidump_entry_rdmem * memEntry,u64 * data_buff)2083 netxen_md_rdmem(struct netxen_adapter *adapter,
2084 struct netxen_minidump_entry_rdmem
2085 *memEntry, u64 *data_buff)
2086 {
2087 u64 addr, value = 0;
2088 int i = 0, loop_cnt;
2089
2090 addr = (u64)memEntry->read_addr;
2091 loop_cnt = memEntry->read_data_size; /* This is size in bytes */
2092 loop_cnt /= sizeof(value);
2093
2094 for (i = 0; i < loop_cnt; i++) {
2095 if (netxen_nic_pci_mem_read_2M(adapter, addr, &value))
2096 goto out;
2097 *data_buff++ = value;
2098 addr += sizeof(value);
2099 }
2100 out:
2101 return i * sizeof(value);
2102 }
2103
2104 /* Read CRB operation */
netxen_md_rd_crb(struct netxen_adapter * adapter,struct netxen_minidump_entry_crb * crbEntry,u32 * data_buff)2105 static u32 netxen_md_rd_crb(struct netxen_adapter *adapter,
2106 struct netxen_minidump_entry_crb
2107 *crbEntry, u32 *data_buff)
2108 {
2109 int loop_cnt;
2110 u32 op_count, addr, stride, value;
2111
2112 addr = crbEntry->addr;
2113 op_count = crbEntry->op_count;
2114 stride = crbEntry->addr_stride;
2115
2116 for (loop_cnt = 0; loop_cnt < op_count; loop_cnt++) {
2117 NX_RD_DUMP_REG(addr, adapter->ahw.pci_base0, &value);
2118 *data_buff++ = addr;
2119 *data_buff++ = value;
2120 addr = addr + stride;
2121 }
2122 return loop_cnt * (2 * sizeof(u32));
2123 }
2124
2125 /* Read ROM */
2126 static u32
netxen_md_rdrom(struct netxen_adapter * adapter,struct netxen_minidump_entry_rdrom * romEntry,__le32 * data_buff)2127 netxen_md_rdrom(struct netxen_adapter *adapter,
2128 struct netxen_minidump_entry_rdrom
2129 *romEntry, __le32 *data_buff)
2130 {
2131 int i, count = 0;
2132 u32 size, lck_val;
2133 u32 val;
2134 u32 fl_addr, waddr, raddr;
2135 fl_addr = romEntry->read_addr;
2136 size = romEntry->read_data_size/4;
2137 lock_try:
2138 lck_val = readl((void __iomem *)(adapter->ahw.pci_base0 +
2139 NX_FLASH_SEM2_LK));
2140 if (!lck_val && count < MAX_CTL_CHECK) {
2141 msleep(20);
2142 count++;
2143 goto lock_try;
2144 }
2145 writel(adapter->ahw.pci_func, (void __iomem *)(adapter->ahw.pci_base0 +
2146 NX_FLASH_LOCK_ID));
2147 for (i = 0; i < size; i++) {
2148 waddr = fl_addr & 0xFFFF0000;
2149 NX_WR_DUMP_REG(FLASH_ROM_WINDOW, adapter->ahw.pci_base0, waddr);
2150 raddr = FLASH_ROM_DATA + (fl_addr & 0x0000FFFF);
2151 NX_RD_DUMP_REG(raddr, adapter->ahw.pci_base0, &val);
2152 *data_buff++ = cpu_to_le32(val);
2153 fl_addr += sizeof(val);
2154 }
2155 readl((void __iomem *)(adapter->ahw.pci_base0 + NX_FLASH_SEM2_ULK));
2156 return romEntry->read_data_size;
2157 }
2158
2159 /* Handle L2 Cache */
2160 static u32
netxen_md_L2Cache(struct netxen_adapter * adapter,struct netxen_minidump_entry_cache * cacheEntry,u32 * data_buff)2161 netxen_md_L2Cache(struct netxen_adapter *adapter,
2162 struct netxen_minidump_entry_cache
2163 *cacheEntry, u32 *data_buff)
2164 {
2165 int loop_cnt, i, k, timeout_flag = 0;
2166 u32 addr, read_addr, read_value, cntrl_addr, tag_reg_addr;
2167 u32 tag_value, read_cnt;
2168 u8 cntl_value_w, cntl_value_r;
2169 unsigned long timeout, timeout_jiffies;
2170
2171 loop_cnt = cacheEntry->op_count;
2172 read_addr = cacheEntry->read_addr;
2173 cntrl_addr = cacheEntry->control_addr;
2174 cntl_value_w = (u32) cacheEntry->write_value;
2175 tag_reg_addr = cacheEntry->tag_reg_addr;
2176 tag_value = cacheEntry->init_tag_value;
2177 read_cnt = cacheEntry->read_addr_cnt;
2178
2179 for (i = 0; i < loop_cnt; i++) {
2180 NX_WR_DUMP_REG(tag_reg_addr, adapter->ahw.pci_base0, tag_value);
2181 if (cntl_value_w)
2182 NX_WR_DUMP_REG(cntrl_addr, adapter->ahw.pci_base0,
2183 (u32)cntl_value_w);
2184 if (cacheEntry->poll_mask) {
2185 timeout = cacheEntry->poll_wait;
2186 NX_RD_DUMP_REG(cntrl_addr, adapter->ahw.pci_base0,
2187 &cntl_value_r);
2188 timeout_jiffies = msecs_to_jiffies(timeout) + jiffies;
2189 for (timeout_flag = 0; !timeout_flag &&
2190 ((cntl_value_r & cacheEntry->poll_mask) != 0);) {
2191 if (time_after(jiffies, timeout_jiffies))
2192 timeout_flag = 1;
2193 NX_RD_DUMP_REG(cntrl_addr,
2194 adapter->ahw.pci_base0,
2195 &cntl_value_r);
2196 }
2197 if (timeout_flag) {
2198 dev_err(&adapter->pdev->dev,
2199 "Timeout in processing L2 Tag poll.\n");
2200 return -1;
2201 }
2202 }
2203 addr = read_addr;
2204 for (k = 0; k < read_cnt; k++) {
2205 NX_RD_DUMP_REG(addr, adapter->ahw.pci_base0,
2206 &read_value);
2207 *data_buff++ = read_value;
2208 addr += cacheEntry->read_addr_stride;
2209 }
2210 tag_value += cacheEntry->tag_value_stride;
2211 }
2212 return read_cnt * loop_cnt * sizeof(read_value);
2213 }
2214
2215
2216 /* Handle L1 Cache */
netxen_md_L1Cache(struct netxen_adapter * adapter,struct netxen_minidump_entry_cache * cacheEntry,u32 * data_buff)2217 static u32 netxen_md_L1Cache(struct netxen_adapter *adapter,
2218 struct netxen_minidump_entry_cache
2219 *cacheEntry, u32 *data_buff)
2220 {
2221 int i, k, loop_cnt;
2222 u32 addr, read_addr, read_value, cntrl_addr, tag_reg_addr;
2223 u32 tag_value, read_cnt;
2224 u8 cntl_value_w;
2225
2226 loop_cnt = cacheEntry->op_count;
2227 read_addr = cacheEntry->read_addr;
2228 cntrl_addr = cacheEntry->control_addr;
2229 cntl_value_w = (u32) cacheEntry->write_value;
2230 tag_reg_addr = cacheEntry->tag_reg_addr;
2231 tag_value = cacheEntry->init_tag_value;
2232 read_cnt = cacheEntry->read_addr_cnt;
2233
2234 for (i = 0; i < loop_cnt; i++) {
2235 NX_WR_DUMP_REG(tag_reg_addr, adapter->ahw.pci_base0, tag_value);
2236 NX_WR_DUMP_REG(cntrl_addr, adapter->ahw.pci_base0,
2237 (u32) cntl_value_w);
2238 addr = read_addr;
2239 for (k = 0; k < read_cnt; k++) {
2240 NX_RD_DUMP_REG(addr,
2241 adapter->ahw.pci_base0,
2242 &read_value);
2243 *data_buff++ = read_value;
2244 addr += cacheEntry->read_addr_stride;
2245 }
2246 tag_value += cacheEntry->tag_value_stride;
2247 }
2248 return read_cnt * loop_cnt * sizeof(read_value);
2249 }
2250
2251 /* Reading OCM memory */
2252 static u32
netxen_md_rdocm(struct netxen_adapter * adapter,struct netxen_minidump_entry_rdocm * ocmEntry,u32 * data_buff)2253 netxen_md_rdocm(struct netxen_adapter *adapter,
2254 struct netxen_minidump_entry_rdocm
2255 *ocmEntry, u32 *data_buff)
2256 {
2257 int i, loop_cnt;
2258 u32 value;
2259 void __iomem *addr;
2260 addr = (ocmEntry->read_addr + adapter->ahw.pci_base0);
2261 loop_cnt = ocmEntry->op_count;
2262
2263 for (i = 0; i < loop_cnt; i++) {
2264 value = readl(addr);
2265 *data_buff++ = value;
2266 addr += ocmEntry->read_addr_stride;
2267 }
2268 return i * sizeof(u32);
2269 }
2270
2271 /* Read MUX data */
2272 static u32
netxen_md_rdmux(struct netxen_adapter * adapter,struct netxen_minidump_entry_mux * muxEntry,u32 * data_buff)2273 netxen_md_rdmux(struct netxen_adapter *adapter, struct netxen_minidump_entry_mux
2274 *muxEntry, u32 *data_buff)
2275 {
2276 int loop_cnt = 0;
2277 u32 read_addr, read_value, select_addr, sel_value;
2278
2279 read_addr = muxEntry->read_addr;
2280 sel_value = muxEntry->select_value;
2281 select_addr = muxEntry->select_addr;
2282
2283 for (loop_cnt = 0; loop_cnt < muxEntry->op_count; loop_cnt++) {
2284 NX_WR_DUMP_REG(select_addr, adapter->ahw.pci_base0, sel_value);
2285 NX_RD_DUMP_REG(read_addr, adapter->ahw.pci_base0, &read_value);
2286 *data_buff++ = sel_value;
2287 *data_buff++ = read_value;
2288 sel_value += muxEntry->select_value_stride;
2289 }
2290 return loop_cnt * (2 * sizeof(u32));
2291 }
2292
2293 /* Handling Queue State Reads */
2294 static u32
netxen_md_rdqueue(struct netxen_adapter * adapter,struct netxen_minidump_entry_queue * queueEntry,u32 * data_buff)2295 netxen_md_rdqueue(struct netxen_adapter *adapter,
2296 struct netxen_minidump_entry_queue
2297 *queueEntry, u32 *data_buff)
2298 {
2299 int loop_cnt, k;
2300 u32 queue_id, read_addr, read_value, read_stride, select_addr, read_cnt;
2301
2302 read_cnt = queueEntry->read_addr_cnt;
2303 read_stride = queueEntry->read_addr_stride;
2304 select_addr = queueEntry->select_addr;
2305
2306 for (loop_cnt = 0, queue_id = 0; loop_cnt < queueEntry->op_count;
2307 loop_cnt++) {
2308 NX_WR_DUMP_REG(select_addr, adapter->ahw.pci_base0, queue_id);
2309 read_addr = queueEntry->read_addr;
2310 for (k = 0; k < read_cnt; k++) {
2311 NX_RD_DUMP_REG(read_addr, adapter->ahw.pci_base0,
2312 &read_value);
2313 *data_buff++ = read_value;
2314 read_addr += read_stride;
2315 }
2316 queue_id += queueEntry->queue_id_stride;
2317 }
2318 return loop_cnt * (read_cnt * sizeof(read_value));
2319 }
2320
2321
2322 /*
2323 * We catch an error where driver does not read
2324 * as much data as we expect from the entry.
2325 */
2326
netxen_md_entry_err_chk(struct netxen_adapter * adapter,struct netxen_minidump_entry * entry,int esize)2327 static int netxen_md_entry_err_chk(struct netxen_adapter *adapter,
2328 struct netxen_minidump_entry *entry, int esize)
2329 {
2330 if (esize < 0) {
2331 entry->hdr.driver_flags |= NX_DUMP_SKIP;
2332 return esize;
2333 }
2334 if (esize != entry->hdr.entry_capture_size) {
2335 entry->hdr.entry_capture_size = esize;
2336 entry->hdr.driver_flags |= NX_DUMP_SIZE_ERR;
2337 dev_info(&adapter->pdev->dev,
2338 "Invalidate dump, Type:%d\tMask:%d\tSize:%dCap_size:%d\n",
2339 entry->hdr.entry_type, entry->hdr.entry_capture_mask,
2340 esize, entry->hdr.entry_capture_size);
2341 dev_info(&adapter->pdev->dev, "Aborting further dump capture\n");
2342 }
2343 return 0;
2344 }
2345
netxen_parse_md_template(struct netxen_adapter * adapter)2346 static int netxen_parse_md_template(struct netxen_adapter *adapter)
2347 {
2348 int num_of_entries, buff_level, e_cnt, esize;
2349 int rv = 0, sane_start = 0, sane_end = 0;
2350 char *dbuff;
2351 void *template_buff = adapter->mdump.md_template;
2352 char *dump_buff = adapter->mdump.md_capture_buff;
2353 int capture_mask = adapter->mdump.md_capture_mask;
2354 struct netxen_minidump_template_hdr *template_hdr;
2355 struct netxen_minidump_entry *entry;
2356
2357 if ((capture_mask & 0x3) != 0x3) {
2358 dev_err(&adapter->pdev->dev, "Capture mask %02x below minimum needed "
2359 "for valid firmware dump\n", capture_mask);
2360 return -EINVAL;
2361 }
2362 template_hdr = (struct netxen_minidump_template_hdr *) template_buff;
2363 num_of_entries = template_hdr->num_of_entries;
2364 entry = (struct netxen_minidump_entry *) ((char *) template_buff +
2365 template_hdr->first_entry_offset);
2366 memcpy(dump_buff, template_buff, adapter->mdump.md_template_size);
2367 dump_buff = dump_buff + adapter->mdump.md_template_size;
2368
2369 if (template_hdr->entry_type == TLHDR)
2370 sane_start = 1;
2371
2372 for (e_cnt = 0, buff_level = 0; e_cnt < num_of_entries; e_cnt++) {
2373 if (!(entry->hdr.entry_capture_mask & capture_mask)) {
2374 entry->hdr.driver_flags |= NX_DUMP_SKIP;
2375 entry = (struct netxen_minidump_entry *)
2376 ((char *) entry + entry->hdr.entry_size);
2377 continue;
2378 }
2379 switch (entry->hdr.entry_type) {
2380 case RDNOP:
2381 entry->hdr.driver_flags |= NX_DUMP_SKIP;
2382 break;
2383 case RDEND:
2384 entry->hdr.driver_flags |= NX_DUMP_SKIP;
2385 sane_end += 1;
2386 break;
2387 case CNTRL:
2388 rv = netxen_md_cntrl(adapter,
2389 template_hdr, (void *)entry);
2390 if (rv)
2391 entry->hdr.driver_flags |= NX_DUMP_SKIP;
2392 break;
2393 case RDCRB:
2394 dbuff = dump_buff + buff_level;
2395 esize = netxen_md_rd_crb(adapter,
2396 (void *) entry, (void *) dbuff);
2397 rv = netxen_md_entry_err_chk
2398 (adapter, entry, esize);
2399 if (rv < 0)
2400 break;
2401 buff_level += esize;
2402 break;
2403 case RDMN:
2404 case RDMEM:
2405 dbuff = dump_buff + buff_level;
2406 esize = netxen_md_rdmem(adapter,
2407 (void *) entry, (void *) dbuff);
2408 rv = netxen_md_entry_err_chk
2409 (adapter, entry, esize);
2410 if (rv < 0)
2411 break;
2412 buff_level += esize;
2413 break;
2414 case BOARD:
2415 case RDROM:
2416 dbuff = dump_buff + buff_level;
2417 esize = netxen_md_rdrom(adapter,
2418 (void *) entry, (void *) dbuff);
2419 rv = netxen_md_entry_err_chk
2420 (adapter, entry, esize);
2421 if (rv < 0)
2422 break;
2423 buff_level += esize;
2424 break;
2425 case L2ITG:
2426 case L2DTG:
2427 case L2DAT:
2428 case L2INS:
2429 dbuff = dump_buff + buff_level;
2430 esize = netxen_md_L2Cache(adapter,
2431 (void *) entry, (void *) dbuff);
2432 rv = netxen_md_entry_err_chk
2433 (adapter, entry, esize);
2434 if (rv < 0)
2435 break;
2436 buff_level += esize;
2437 break;
2438 case L1DAT:
2439 case L1INS:
2440 dbuff = dump_buff + buff_level;
2441 esize = netxen_md_L1Cache(adapter,
2442 (void *) entry, (void *) dbuff);
2443 rv = netxen_md_entry_err_chk
2444 (adapter, entry, esize);
2445 if (rv < 0)
2446 break;
2447 buff_level += esize;
2448 break;
2449 case RDOCM:
2450 dbuff = dump_buff + buff_level;
2451 esize = netxen_md_rdocm(adapter,
2452 (void *) entry, (void *) dbuff);
2453 rv = netxen_md_entry_err_chk
2454 (adapter, entry, esize);
2455 if (rv < 0)
2456 break;
2457 buff_level += esize;
2458 break;
2459 case RDMUX:
2460 dbuff = dump_buff + buff_level;
2461 esize = netxen_md_rdmux(adapter,
2462 (void *) entry, (void *) dbuff);
2463 rv = netxen_md_entry_err_chk
2464 (adapter, entry, esize);
2465 if (rv < 0)
2466 break;
2467 buff_level += esize;
2468 break;
2469 case QUEUE:
2470 dbuff = dump_buff + buff_level;
2471 esize = netxen_md_rdqueue(adapter,
2472 (void *) entry, (void *) dbuff);
2473 rv = netxen_md_entry_err_chk
2474 (adapter, entry, esize);
2475 if (rv < 0)
2476 break;
2477 buff_level += esize;
2478 break;
2479 default:
2480 entry->hdr.driver_flags |= NX_DUMP_SKIP;
2481 break;
2482 }
2483 /* Next entry in the template */
2484 entry = (struct netxen_minidump_entry *)
2485 ((char *) entry + entry->hdr.entry_size);
2486 }
2487 if (!sane_start || sane_end > 1) {
2488 dev_err(&adapter->pdev->dev,
2489 "Firmware minidump template configuration error.\n");
2490 }
2491 return 0;
2492 }
2493
2494 static int
netxen_collect_minidump(struct netxen_adapter * adapter)2495 netxen_collect_minidump(struct netxen_adapter *adapter)
2496 {
2497 int ret = 0;
2498 struct netxen_minidump_template_hdr *hdr;
2499 hdr = (struct netxen_minidump_template_hdr *)
2500 adapter->mdump.md_template;
2501 hdr->driver_capture_mask = adapter->mdump.md_capture_mask;
2502 hdr->driver_timestamp = ktime_get_seconds();
2503 hdr->driver_info_word2 = adapter->fw_version;
2504 hdr->driver_info_word3 = NXRD32(adapter, CRB_DRIVER_VERSION);
2505 ret = netxen_parse_md_template(adapter);
2506 if (ret)
2507 return ret;
2508
2509 return ret;
2510 }
2511
2512
2513 void
netxen_dump_fw(struct netxen_adapter * adapter)2514 netxen_dump_fw(struct netxen_adapter *adapter)
2515 {
2516 struct netxen_minidump_template_hdr *hdr;
2517 int i, k, data_size = 0;
2518 u32 capture_mask;
2519 hdr = (struct netxen_minidump_template_hdr *)
2520 adapter->mdump.md_template;
2521 capture_mask = adapter->mdump.md_capture_mask;
2522
2523 for (i = 0x2, k = 1; (i & NX_DUMP_MASK_MAX); i <<= 1, k++) {
2524 if (i & capture_mask)
2525 data_size += hdr->capture_size_array[k];
2526 }
2527 if (!data_size) {
2528 dev_err(&adapter->pdev->dev,
2529 "Invalid cap sizes for capture_mask=0x%x\n",
2530 adapter->mdump.md_capture_mask);
2531 return;
2532 }
2533 adapter->mdump.md_capture_size = data_size;
2534 adapter->mdump.md_dump_size = adapter->mdump.md_template_size +
2535 adapter->mdump.md_capture_size;
2536 if (!adapter->mdump.md_capture_buff) {
2537 adapter->mdump.md_capture_buff =
2538 vzalloc(adapter->mdump.md_dump_size);
2539 if (!adapter->mdump.md_capture_buff)
2540 return;
2541
2542 if (netxen_collect_minidump(adapter)) {
2543 adapter->mdump.has_valid_dump = 0;
2544 adapter->mdump.md_dump_size = 0;
2545 vfree(adapter->mdump.md_capture_buff);
2546 adapter->mdump.md_capture_buff = NULL;
2547 dev_err(&adapter->pdev->dev,
2548 "Error in collecting firmware minidump.\n");
2549 } else {
2550 adapter->mdump.md_timestamp = jiffies;
2551 adapter->mdump.has_valid_dump = 1;
2552 adapter->fw_mdump_rdy = 1;
2553 dev_info(&adapter->pdev->dev, "%s Successfully "
2554 "collected fw dump.\n", adapter->netdev->name);
2555 }
2556
2557 } else {
2558 dev_info(&adapter->pdev->dev,
2559 "Cannot overwrite previously collected "
2560 "firmware minidump.\n");
2561 adapter->fw_mdump_rdy = 1;
2562 return;
2563 }
2564 }
2565
