1 // SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0
2 /* Copyright (c) 2016-2018 Mellanox Technologies. All rights reserved */
3 
4 #include <linux/kernel.h>
5 #include <linux/module.h>
6 #include <linux/types.h>
7 #include <linux/pci.h>
8 #include <linux/netdevice.h>
9 #include <linux/etherdevice.h>
10 #include <linux/slab.h>
11 #include <linux/device.h>
12 #include <linux/skbuff.h>
13 #include <linux/if_vlan.h>
14 #include <net/switchdev.h>
15 
16 #include "pci.h"
17 #include "core.h"
18 #include "reg.h"
19 #include "port.h"
20 #include "trap.h"
21 #include "txheader.h"
22 #include "ib.h"
23 
24 static const char mlxsw_sib_driver_name[] = "mlxsw_switchib";
25 static const char mlxsw_sib2_driver_name[] = "mlxsw_switchib2";
26 
27 struct mlxsw_sib_port;
28 
29 struct mlxsw_sib {
30 	struct mlxsw_sib_port **ports;
31 	struct mlxsw_core *core;
32 	const struct mlxsw_bus_info *bus_info;
33 };
34 
35 struct mlxsw_sib_port {
36 	struct mlxsw_sib *mlxsw_sib;
37 	u8 local_port;
38 	struct {
39 		u8 module;
40 	} mapping;
41 };
42 
43 /* tx_v1_hdr_version
44  * Tx header version.
45  * Must be set to 1.
46  */
47 MLXSW_ITEM32(tx_v1, hdr, version, 0x00, 28, 4);
48 
49 /* tx_v1_hdr_ctl
50  * Packet control type.
51  * 0 - Ethernet control (e.g. EMADs, LACP)
52  * 1 - Ethernet data
53  */
54 MLXSW_ITEM32(tx_v1, hdr, ctl, 0x00, 26, 2);
55 
56 /* tx_v1_hdr_proto
57  * Packet protocol type. Must be set to 1 (Ethernet).
58  */
59 MLXSW_ITEM32(tx_v1, hdr, proto, 0x00, 21, 3);
60 
61 /* tx_v1_hdr_swid
62  * Switch partition ID. Must be set to 0.
63  */
64 MLXSW_ITEM32(tx_v1, hdr, swid, 0x00, 12, 3);
65 
66 /* tx_v1_hdr_control_tclass
67  * Indicates if the packet should use the control TClass and not one
68  * of the data TClasses.
69  */
70 MLXSW_ITEM32(tx_v1, hdr, control_tclass, 0x00, 6, 1);
71 
72 /* tx_v1_hdr_port_mid
73  * Destination local port for unicast packets.
74  * Destination multicast ID for multicast packets.
75  *
76  * Control packets are directed to a specific egress port, while data
77  * packets are transmitted through the CPU port (0) into the switch partition,
78  * where forwarding rules are applied.
79  */
80 MLXSW_ITEM32(tx_v1, hdr, port_mid, 0x04, 16, 16);
81 
82 /* tx_v1_hdr_type
83  * 0 - Data packets
84  * 6 - Control packets
85  */
86 MLXSW_ITEM32(tx_v1, hdr, type, 0x0C, 0, 4);
87 
88 static void
mlxsw_sib_tx_v1_hdr_construct(struct sk_buff * skb,const struct mlxsw_tx_info * tx_info)89 mlxsw_sib_tx_v1_hdr_construct(struct sk_buff *skb,
90 			      const struct mlxsw_tx_info *tx_info)
91 {
92 	char *txhdr = skb_push(skb, MLXSW_TXHDR_LEN);
93 
94 	memset(txhdr, 0, MLXSW_TXHDR_LEN);
95 
96 	mlxsw_tx_v1_hdr_version_set(txhdr, MLXSW_TXHDR_VERSION_1);
97 	mlxsw_tx_v1_hdr_ctl_set(txhdr, MLXSW_TXHDR_ETH_CTL);
98 	mlxsw_tx_v1_hdr_proto_set(txhdr, MLXSW_TXHDR_PROTO_ETH);
99 	mlxsw_tx_v1_hdr_swid_set(txhdr, 0);
100 	mlxsw_tx_v1_hdr_control_tclass_set(txhdr, 1);
101 	mlxsw_tx_v1_hdr_port_mid_set(txhdr, tx_info->local_port);
102 	mlxsw_tx_v1_hdr_type_set(txhdr, MLXSW_TXHDR_TYPE_CONTROL);
103 }
104 
105 static int
mlxsw_sib_port_admin_status_set(struct mlxsw_sib_port * mlxsw_sib_port,bool is_up)106 mlxsw_sib_port_admin_status_set(struct mlxsw_sib_port *mlxsw_sib_port,
107 				bool is_up)
108 {
109 	struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib;
110 	char paos_pl[MLXSW_REG_PAOS_LEN];
111 
112 	mlxsw_reg_paos_pack(paos_pl, mlxsw_sib_port->local_port,
113 			    is_up ? MLXSW_PORT_ADMIN_STATUS_UP :
114 			    MLXSW_PORT_ADMIN_STATUS_DOWN);
115 	return mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(paos), paos_pl);
116 }
117 
mlxsw_sib_port_mtu_set(struct mlxsw_sib_port * mlxsw_sib_port,u16 mtu)118 static int mlxsw_sib_port_mtu_set(struct mlxsw_sib_port *mlxsw_sib_port,
119 				  u16 mtu)
120 {
121 	struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib;
122 	char pmtu_pl[MLXSW_REG_PMTU_LEN];
123 	int max_mtu;
124 	int err;
125 
126 	mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sib_port->local_port, 0);
127 	err = mlxsw_reg_query(mlxsw_sib->core, MLXSW_REG(pmtu), pmtu_pl);
128 	if (err)
129 		return err;
130 	max_mtu = mlxsw_reg_pmtu_max_mtu_get(pmtu_pl);
131 
132 	if (mtu > max_mtu)
133 		return -EINVAL;
134 
135 	mlxsw_reg_pmtu_pack(pmtu_pl, mlxsw_sib_port->local_port, mtu);
136 	return mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(pmtu), pmtu_pl);
137 }
138 
mlxsw_sib_port_set(struct mlxsw_sib_port * mlxsw_sib_port,u8 port)139 static int mlxsw_sib_port_set(struct mlxsw_sib_port *mlxsw_sib_port, u8 port)
140 {
141 	struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib;
142 	char plib_pl[MLXSW_REG_PLIB_LEN] = {0};
143 	int err;
144 
145 	mlxsw_reg_plib_local_port_set(plib_pl, mlxsw_sib_port->local_port);
146 	mlxsw_reg_plib_ib_port_set(plib_pl, port);
147 	err = mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(plib), plib_pl);
148 	return err;
149 }
150 
mlxsw_sib_port_swid_set(struct mlxsw_sib_port * mlxsw_sib_port,u8 swid)151 static int mlxsw_sib_port_swid_set(struct mlxsw_sib_port *mlxsw_sib_port,
152 				   u8 swid)
153 {
154 	struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib;
155 	char pspa_pl[MLXSW_REG_PSPA_LEN];
156 
157 	mlxsw_reg_pspa_pack(pspa_pl, swid, mlxsw_sib_port->local_port);
158 	return mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(pspa), pspa_pl);
159 }
160 
mlxsw_sib_port_module_info_get(struct mlxsw_sib * mlxsw_sib,u8 local_port,u8 * p_module,u8 * p_width)161 static int mlxsw_sib_port_module_info_get(struct mlxsw_sib *mlxsw_sib,
162 					  u8 local_port, u8 *p_module,
163 					  u8 *p_width)
164 {
165 	char pmlp_pl[MLXSW_REG_PMLP_LEN];
166 	int err;
167 
168 	mlxsw_reg_pmlp_pack(pmlp_pl, local_port);
169 	err = mlxsw_reg_query(mlxsw_sib->core, MLXSW_REG(pmlp), pmlp_pl);
170 	if (err)
171 		return err;
172 	*p_module = mlxsw_reg_pmlp_module_get(pmlp_pl, 0);
173 	*p_width = mlxsw_reg_pmlp_width_get(pmlp_pl);
174 	return 0;
175 }
176 
mlxsw_sib_port_speed_set(struct mlxsw_sib_port * mlxsw_sib_port,u16 speed,u16 width)177 static int mlxsw_sib_port_speed_set(struct mlxsw_sib_port *mlxsw_sib_port,
178 				    u16 speed, u16 width)
179 {
180 	struct mlxsw_sib *mlxsw_sib = mlxsw_sib_port->mlxsw_sib;
181 	char ptys_pl[MLXSW_REG_PTYS_LEN];
182 
183 	mlxsw_reg_ptys_ib_pack(ptys_pl, mlxsw_sib_port->local_port, speed,
184 			       width);
185 	return mlxsw_reg_write(mlxsw_sib->core, MLXSW_REG(ptys), ptys_pl);
186 }
187 
mlxsw_sib_port_created(struct mlxsw_sib * mlxsw_sib,u8 local_port)188 static bool mlxsw_sib_port_created(struct mlxsw_sib *mlxsw_sib, u8 local_port)
189 {
190 	return mlxsw_sib->ports[local_port] != NULL;
191 }
192 
__mlxsw_sib_port_create(struct mlxsw_sib * mlxsw_sib,u8 local_port,u8 module,u8 width)193 static int __mlxsw_sib_port_create(struct mlxsw_sib *mlxsw_sib, u8 local_port,
194 				   u8 module, u8 width)
195 {
196 	struct mlxsw_sib_port *mlxsw_sib_port;
197 	int err;
198 
199 	mlxsw_sib_port = kzalloc(sizeof(*mlxsw_sib_port), GFP_KERNEL);
200 	if (!mlxsw_sib_port)
201 		return -ENOMEM;
202 	mlxsw_sib_port->mlxsw_sib = mlxsw_sib;
203 	mlxsw_sib_port->local_port = local_port;
204 	mlxsw_sib_port->mapping.module = module;
205 
206 	err = mlxsw_sib_port_swid_set(mlxsw_sib_port, 0);
207 	if (err) {
208 		dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to set SWID\n",
209 			mlxsw_sib_port->local_port);
210 		goto err_port_swid_set;
211 	}
212 
213 	/* Expose the IB port number as it's front panel name */
214 	err = mlxsw_sib_port_set(mlxsw_sib_port, module + 1);
215 	if (err) {
216 		dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to set IB port\n",
217 			mlxsw_sib_port->local_port);
218 		goto err_port_ib_set;
219 	}
220 
221 	/* Supports all speeds from SDR to FDR (bitmask) and support bus width
222 	 * of 1x, 2x and 4x (3 bits bitmask)
223 	 */
224 	err = mlxsw_sib_port_speed_set(mlxsw_sib_port,
225 				       MLXSW_REG_PTYS_IB_SPEED_EDR - 1,
226 				       BIT(3) - 1);
227 	if (err) {
228 		dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to set speed\n",
229 			mlxsw_sib_port->local_port);
230 		goto err_port_speed_set;
231 	}
232 
233 	/* Change to the maximum MTU the device supports, the SMA will take
234 	 * care of the active MTU
235 	 */
236 	err = mlxsw_sib_port_mtu_set(mlxsw_sib_port, MLXSW_IB_DEFAULT_MTU);
237 	if (err) {
238 		dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to set MTU\n",
239 			mlxsw_sib_port->local_port);
240 		goto err_port_mtu_set;
241 	}
242 
243 	err = mlxsw_sib_port_admin_status_set(mlxsw_sib_port, true);
244 	if (err) {
245 		dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to change admin state to UP\n",
246 			mlxsw_sib_port->local_port);
247 		goto err_port_admin_set;
248 	}
249 
250 	mlxsw_core_port_ib_set(mlxsw_sib->core, mlxsw_sib_port->local_port,
251 			       mlxsw_sib_port);
252 	mlxsw_sib->ports[local_port] = mlxsw_sib_port;
253 	return 0;
254 
255 err_port_admin_set:
256 err_port_mtu_set:
257 err_port_speed_set:
258 err_port_ib_set:
259 	mlxsw_sib_port_swid_set(mlxsw_sib_port, MLXSW_PORT_SWID_DISABLED_PORT);
260 err_port_swid_set:
261 	kfree(mlxsw_sib_port);
262 	return err;
263 }
264 
mlxsw_sib_port_create(struct mlxsw_sib * mlxsw_sib,u8 local_port,u8 module,u8 width)265 static int mlxsw_sib_port_create(struct mlxsw_sib *mlxsw_sib, u8 local_port,
266 				 u8 module, u8 width)
267 {
268 	int err;
269 
270 	err = mlxsw_core_port_init(mlxsw_sib->core, local_port);
271 	if (err) {
272 		dev_err(mlxsw_sib->bus_info->dev, "Port %d: Failed to init core port\n",
273 			local_port);
274 		return err;
275 	}
276 	err = __mlxsw_sib_port_create(mlxsw_sib, local_port, module, width);
277 	if (err)
278 		goto err_port_create;
279 
280 	return 0;
281 
282 err_port_create:
283 	mlxsw_core_port_fini(mlxsw_sib->core, local_port);
284 	return err;
285 }
286 
__mlxsw_sib_port_remove(struct mlxsw_sib * mlxsw_sib,u8 local_port)287 static void __mlxsw_sib_port_remove(struct mlxsw_sib *mlxsw_sib, u8 local_port)
288 {
289 	struct mlxsw_sib_port *mlxsw_sib_port = mlxsw_sib->ports[local_port];
290 
291 	mlxsw_core_port_clear(mlxsw_sib->core, local_port, mlxsw_sib);
292 	mlxsw_sib->ports[local_port] = NULL;
293 	mlxsw_sib_port_admin_status_set(mlxsw_sib_port, false);
294 	mlxsw_sib_port_swid_set(mlxsw_sib_port, MLXSW_PORT_SWID_DISABLED_PORT);
295 	kfree(mlxsw_sib_port);
296 }
297 
mlxsw_sib_port_remove(struct mlxsw_sib * mlxsw_sib,u8 local_port)298 static void mlxsw_sib_port_remove(struct mlxsw_sib *mlxsw_sib, u8 local_port)
299 {
300 	__mlxsw_sib_port_remove(mlxsw_sib, local_port);
301 	mlxsw_core_port_fini(mlxsw_sib->core, local_port);
302 }
303 
mlxsw_sib_ports_remove(struct mlxsw_sib * mlxsw_sib)304 static void mlxsw_sib_ports_remove(struct mlxsw_sib *mlxsw_sib)
305 {
306 	int i;
307 
308 	for (i = 1; i < MLXSW_PORT_MAX_IB_PORTS; i++)
309 		if (mlxsw_sib_port_created(mlxsw_sib, i))
310 			mlxsw_sib_port_remove(mlxsw_sib, i);
311 	kfree(mlxsw_sib->ports);
312 }
313 
mlxsw_sib_ports_create(struct mlxsw_sib * mlxsw_sib)314 static int mlxsw_sib_ports_create(struct mlxsw_sib *mlxsw_sib)
315 {
316 	size_t alloc_size;
317 	u8 module, width;
318 	int i;
319 	int err;
320 
321 	alloc_size = sizeof(struct mlxsw_sib_port *) * MLXSW_PORT_MAX_IB_PORTS;
322 	mlxsw_sib->ports = kzalloc(alloc_size, GFP_KERNEL);
323 	if (!mlxsw_sib->ports)
324 		return -ENOMEM;
325 
326 	for (i = 1; i < MLXSW_PORT_MAX_IB_PORTS; i++) {
327 		err = mlxsw_sib_port_module_info_get(mlxsw_sib, i, &module,
328 						     &width);
329 		if (err)
330 			goto err_port_module_info_get;
331 		if (!width)
332 			continue;
333 		err = mlxsw_sib_port_create(mlxsw_sib, i, module, width);
334 		if (err)
335 			goto err_port_create;
336 	}
337 	return 0;
338 
339 err_port_create:
340 err_port_module_info_get:
341 	for (i--; i >= 1; i--)
342 		if (mlxsw_sib_port_created(mlxsw_sib, i))
343 			mlxsw_sib_port_remove(mlxsw_sib, i);
344 	kfree(mlxsw_sib->ports);
345 	return err;
346 }
347 
348 static void
mlxsw_sib_pude_ib_event_func(struct mlxsw_sib_port * mlxsw_sib_port,enum mlxsw_reg_pude_oper_status status)349 mlxsw_sib_pude_ib_event_func(struct mlxsw_sib_port *mlxsw_sib_port,
350 			     enum mlxsw_reg_pude_oper_status status)
351 {
352 	if (status == MLXSW_PORT_OPER_STATUS_UP)
353 		pr_info("ib link for port %d - up\n",
354 			mlxsw_sib_port->mapping.module + 1);
355 	else
356 		pr_info("ib link for port %d - down\n",
357 			mlxsw_sib_port->mapping.module + 1);
358 }
359 
mlxsw_sib_pude_event_func(const struct mlxsw_reg_info * reg,char * pude_pl,void * priv)360 static void mlxsw_sib_pude_event_func(const struct mlxsw_reg_info *reg,
361 				      char *pude_pl, void *priv)
362 {
363 	struct mlxsw_sib *mlxsw_sib = priv;
364 	struct mlxsw_sib_port *mlxsw_sib_port;
365 	enum mlxsw_reg_pude_oper_status status;
366 	u8 local_port;
367 
368 	local_port = mlxsw_reg_pude_local_port_get(pude_pl);
369 	mlxsw_sib_port = mlxsw_sib->ports[local_port];
370 	if (!mlxsw_sib_port) {
371 		dev_warn(mlxsw_sib->bus_info->dev, "Port %d: Link event received for non-existent port\n",
372 			 local_port);
373 		return;
374 	}
375 
376 	status = mlxsw_reg_pude_oper_status_get(pude_pl);
377 	mlxsw_sib_pude_ib_event_func(mlxsw_sib_port, status);
378 }
379 
380 static const struct mlxsw_listener mlxsw_sib_listener[] = {
381 	MLXSW_EVENTL(mlxsw_sib_pude_event_func, PUDE, EMAD),
382 };
383 
mlxsw_sib_taps_init(struct mlxsw_sib * mlxsw_sib)384 static int mlxsw_sib_taps_init(struct mlxsw_sib *mlxsw_sib)
385 {
386 	int i;
387 	int err;
388 
389 	for (i = 0; i < ARRAY_SIZE(mlxsw_sib_listener); i++) {
390 		err = mlxsw_core_trap_register(mlxsw_sib->core,
391 					       &mlxsw_sib_listener[i],
392 					       mlxsw_sib);
393 		if (err)
394 			goto err_rx_listener_register;
395 	}
396 
397 	return 0;
398 
399 err_rx_listener_register:
400 	for (i--; i >= 0; i--) {
401 		mlxsw_core_trap_unregister(mlxsw_sib->core,
402 					   &mlxsw_sib_listener[i],
403 					   mlxsw_sib);
404 	}
405 
406 	return err;
407 }
408 
mlxsw_sib_traps_fini(struct mlxsw_sib * mlxsw_sib)409 static void mlxsw_sib_traps_fini(struct mlxsw_sib *mlxsw_sib)
410 {
411 	int i;
412 
413 	for (i = 0; i < ARRAY_SIZE(mlxsw_sib_listener); i++) {
414 		mlxsw_core_trap_unregister(mlxsw_sib->core,
415 					   &mlxsw_sib_listener[i], mlxsw_sib);
416 	}
417 }
418 
mlxsw_sib_basic_trap_groups_set(struct mlxsw_core * mlxsw_core)419 static int mlxsw_sib_basic_trap_groups_set(struct mlxsw_core *mlxsw_core)
420 {
421 	char htgt_pl[MLXSW_REG_HTGT_LEN];
422 
423 	mlxsw_reg_htgt_pack(htgt_pl, MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
424 			    MLXSW_REG_HTGT_INVALID_POLICER,
425 			    MLXSW_REG_HTGT_DEFAULT_PRIORITY,
426 			    MLXSW_REG_HTGT_DEFAULT_TC);
427 	mlxsw_reg_htgt_swid_set(htgt_pl, MLXSW_PORT_SWID_ALL_SWIDS);
428 	mlxsw_reg_htgt_local_path_rdq_set(htgt_pl,
429 					MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD);
430 	return mlxsw_reg_write(mlxsw_core, MLXSW_REG(htgt), htgt_pl);
431 }
432 
mlxsw_sib_init(struct mlxsw_core * mlxsw_core,const struct mlxsw_bus_info * mlxsw_bus_info)433 static int mlxsw_sib_init(struct mlxsw_core *mlxsw_core,
434 			  const struct mlxsw_bus_info *mlxsw_bus_info)
435 {
436 	struct mlxsw_sib *mlxsw_sib = mlxsw_core_driver_priv(mlxsw_core);
437 	int err;
438 
439 	mlxsw_sib->core = mlxsw_core;
440 	mlxsw_sib->bus_info = mlxsw_bus_info;
441 
442 	err = mlxsw_sib_ports_create(mlxsw_sib);
443 	if (err) {
444 		dev_err(mlxsw_sib->bus_info->dev, "Failed to create ports\n");
445 		return err;
446 	}
447 
448 	err = mlxsw_sib_taps_init(mlxsw_sib);
449 	if (err) {
450 		dev_err(mlxsw_sib->bus_info->dev, "Failed to set traps\n");
451 		goto err_traps_init_err;
452 	}
453 
454 	return 0;
455 
456 err_traps_init_err:
457 	mlxsw_sib_ports_remove(mlxsw_sib);
458 	return err;
459 }
460 
mlxsw_sib_fini(struct mlxsw_core * mlxsw_core)461 static void mlxsw_sib_fini(struct mlxsw_core *mlxsw_core)
462 {
463 	struct mlxsw_sib *mlxsw_sib = mlxsw_core_driver_priv(mlxsw_core);
464 
465 	mlxsw_sib_traps_fini(mlxsw_sib);
466 	mlxsw_sib_ports_remove(mlxsw_sib);
467 }
468 
469 static const struct mlxsw_config_profile mlxsw_sib_config_profile = {
470 	.used_max_system_port		= 1,
471 	.max_system_port		= 48000,
472 	.used_max_ib_mc			= 1,
473 	.max_ib_mc			= 27,
474 	.used_max_pkey			= 1,
475 	.max_pkey			= 32,
476 	.swid_config			= {
477 		{
478 			.used_type	= 1,
479 			.type		= MLXSW_PORT_SWID_TYPE_IB,
480 		}
481 	},
482 };
483 
484 static struct mlxsw_driver mlxsw_sib_driver = {
485 	.kind			= mlxsw_sib_driver_name,
486 	.priv_size		= sizeof(struct mlxsw_sib),
487 	.init			= mlxsw_sib_init,
488 	.fini			= mlxsw_sib_fini,
489 	.basic_trap_groups_set	= mlxsw_sib_basic_trap_groups_set,
490 	.txhdr_construct	= mlxsw_sib_tx_v1_hdr_construct,
491 	.txhdr_len		= MLXSW_TXHDR_LEN,
492 	.profile		= &mlxsw_sib_config_profile,
493 };
494 
495 static struct mlxsw_driver mlxsw_sib2_driver = {
496 	.kind			= mlxsw_sib2_driver_name,
497 	.priv_size		= sizeof(struct mlxsw_sib),
498 	.init			= mlxsw_sib_init,
499 	.fini			= mlxsw_sib_fini,
500 	.basic_trap_groups_set	= mlxsw_sib_basic_trap_groups_set,
501 	.txhdr_construct	= mlxsw_sib_tx_v1_hdr_construct,
502 	.txhdr_len		= MLXSW_TXHDR_LEN,
503 	.profile		= &mlxsw_sib_config_profile,
504 };
505 
506 static const struct pci_device_id mlxsw_sib_pci_id_table[] = {
507 	{PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SWITCHIB), 0},
508 	{0, },
509 };
510 
511 static struct pci_driver mlxsw_sib_pci_driver = {
512 	.name = mlxsw_sib_driver_name,
513 	.id_table = mlxsw_sib_pci_id_table,
514 };
515 
516 static const struct pci_device_id mlxsw_sib2_pci_id_table[] = {
517 	{PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_SWITCHIB2), 0},
518 	{0, },
519 };
520 
521 static struct pci_driver mlxsw_sib2_pci_driver = {
522 	.name = mlxsw_sib2_driver_name,
523 	.id_table = mlxsw_sib2_pci_id_table,
524 };
525 
mlxsw_sib_module_init(void)526 static int __init mlxsw_sib_module_init(void)
527 {
528 	int err;
529 
530 	err = mlxsw_core_driver_register(&mlxsw_sib_driver);
531 	if (err)
532 		return err;
533 
534 	err = mlxsw_core_driver_register(&mlxsw_sib2_driver);
535 	if (err)
536 		goto err_sib2_driver_register;
537 
538 	err = mlxsw_pci_driver_register(&mlxsw_sib_pci_driver);
539 	if (err)
540 		goto err_sib_pci_driver_register;
541 
542 	err = mlxsw_pci_driver_register(&mlxsw_sib2_pci_driver);
543 	if (err)
544 		goto err_sib2_pci_driver_register;
545 
546 	return 0;
547 
548 err_sib2_pci_driver_register:
549 	mlxsw_pci_driver_unregister(&mlxsw_sib_pci_driver);
550 err_sib_pci_driver_register:
551 	mlxsw_core_driver_unregister(&mlxsw_sib2_driver);
552 err_sib2_driver_register:
553 	mlxsw_core_driver_unregister(&mlxsw_sib_driver);
554 	return err;
555 }
556 
mlxsw_sib_module_exit(void)557 static void __exit mlxsw_sib_module_exit(void)
558 {
559 	mlxsw_pci_driver_unregister(&mlxsw_sib2_pci_driver);
560 	mlxsw_pci_driver_unregister(&mlxsw_sib_pci_driver);
561 	mlxsw_core_driver_unregister(&mlxsw_sib2_driver);
562 	mlxsw_core_driver_unregister(&mlxsw_sib_driver);
563 }
564 
565 module_init(mlxsw_sib_module_init);
566 module_exit(mlxsw_sib_module_exit);
567 
568 MODULE_LICENSE("Dual BSD/GPL");
569 MODULE_AUTHOR("Elad Raz <eladr@@mellanox.com>");
570 MODULE_DESCRIPTION("Mellanox SwitchIB and SwitchIB-2 driver");
571 MODULE_ALIAS("mlxsw_switchib2");
572 MODULE_DEVICE_TABLE(pci, mlxsw_sib_pci_id_table);
573 MODULE_DEVICE_TABLE(pci, mlxsw_sib2_pci_id_table);
574