1 /*
2 * Copyright (c) 2018 Mellanox Technologies. All rights reserved.
3 *
4 * This software is available to you under a choice of one of two
5 * licenses. You may choose to be licensed under the terms of the GNU
6 * General Public License (GPL) Version 2, available from the file
7 * COPYING in the main directory of this source tree, or the
8 * OpenIB.org BSD license below:
9 *
10 * Redistribution and use in source and binary forms, with or
11 * without modification, are permitted provided that the following
12 * conditions are met:
13 *
14 * - Redistributions of source code must retain the above
15 * copyright notice, this list of conditions and the following
16 * disclaimer.
17 *
18 * - Redistributions in binary form must reproduce the above
19 * copyright notice, this list of conditions and the following
20 * disclaimer in the documentation and/or other materials
21 * provided with the distribution.
22 *
23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
30 * SOFTWARE.
31 *
32 */
33
34 #include <linux/mlx5/device.h>
35
36 #include "accel/tls.h"
37 #include "mlx5_core.h"
38 #include "fpga/tls.h"
39
mlx5_accel_tls_add_flow(struct mlx5_core_dev * mdev,void * flow,struct tls_crypto_info * crypto_info,u32 start_offload_tcp_sn,u32 * p_swid,bool direction_sx)40 int mlx5_accel_tls_add_flow(struct mlx5_core_dev *mdev, void *flow,
41 struct tls_crypto_info *crypto_info,
42 u32 start_offload_tcp_sn, u32 *p_swid,
43 bool direction_sx)
44 {
45 return mlx5_fpga_tls_add_flow(mdev, flow, crypto_info,
46 start_offload_tcp_sn, p_swid,
47 direction_sx);
48 }
49
mlx5_accel_tls_del_flow(struct mlx5_core_dev * mdev,u32 swid,bool direction_sx)50 void mlx5_accel_tls_del_flow(struct mlx5_core_dev *mdev, u32 swid,
51 bool direction_sx)
52 {
53 mlx5_fpga_tls_del_flow(mdev, swid, GFP_KERNEL, direction_sx);
54 }
55
mlx5_accel_tls_resync_rx(struct mlx5_core_dev * mdev,u32 handle,u32 seq,u64 rcd_sn)56 int mlx5_accel_tls_resync_rx(struct mlx5_core_dev *mdev, u32 handle, u32 seq,
57 u64 rcd_sn)
58 {
59 return mlx5_fpga_tls_resync_rx(mdev, handle, seq, rcd_sn);
60 }
61
mlx5_accel_is_tls_device(struct mlx5_core_dev * mdev)62 bool mlx5_accel_is_tls_device(struct mlx5_core_dev *mdev)
63 {
64 return mlx5_fpga_is_tls_device(mdev);
65 }
66
mlx5_accel_tls_device_caps(struct mlx5_core_dev * mdev)67 u32 mlx5_accel_tls_device_caps(struct mlx5_core_dev *mdev)
68 {
69 return mlx5_fpga_tls_device_caps(mdev);
70 }
71
mlx5_accel_tls_init(struct mlx5_core_dev * mdev)72 int mlx5_accel_tls_init(struct mlx5_core_dev *mdev)
73 {
74 return mlx5_fpga_tls_init(mdev);
75 }
76
mlx5_accel_tls_cleanup(struct mlx5_core_dev * mdev)77 void mlx5_accel_tls_cleanup(struct mlx5_core_dev *mdev)
78 {
79 mlx5_fpga_tls_cleanup(mdev);
80 }
81
