1 // SPDX-License-Identifier: GPL-2.0+
2 // Copyright (c) 2016-2017 Hisilicon Limited.
3
4 #include <linux/device.h>
5 #include <linux/dma-direction.h>
6 #include <linux/dma-mapping.h>
7 #include <linux/err.h>
8 #include <linux/pci.h>
9 #include <linux/slab.h>
10 #include "hclgevf_cmd.h"
11 #include "hclgevf_main.h"
12 #include "hnae3.h"
13
14 #define hclgevf_is_csq(ring) ((ring)->flag & HCLGEVF_TYPE_CSQ)
15 #define hclgevf_ring_to_dma_dir(ring) (hclgevf_is_csq(ring) ? \
16 DMA_TO_DEVICE : DMA_FROM_DEVICE)
17 #define cmq_ring_to_dev(ring) (&(ring)->dev->pdev->dev)
18
hclgevf_ring_space(struct hclgevf_cmq_ring * ring)19 static int hclgevf_ring_space(struct hclgevf_cmq_ring *ring)
20 {
21 int ntc = ring->next_to_clean;
22 int ntu = ring->next_to_use;
23 int used;
24
25 used = (ntu - ntc + ring->desc_num) % ring->desc_num;
26
27 return ring->desc_num - used - 1;
28 }
29
hclgevf_cmd_csq_clean(struct hclgevf_hw * hw)30 static int hclgevf_cmd_csq_clean(struct hclgevf_hw *hw)
31 {
32 struct hclgevf_cmq_ring *csq = &hw->cmq.csq;
33 u16 ntc = csq->next_to_clean;
34 struct hclgevf_desc *desc;
35 int clean = 0;
36 u32 head;
37
38 desc = &csq->desc[ntc];
39 head = hclgevf_read_dev(hw, HCLGEVF_NIC_CSQ_HEAD_REG);
40 while (head != ntc) {
41 memset(desc, 0, sizeof(*desc));
42 ntc++;
43 if (ntc == csq->desc_num)
44 ntc = 0;
45 desc = &csq->desc[ntc];
46 clean++;
47 }
48 csq->next_to_clean = ntc;
49
50 return clean;
51 }
52
hclgevf_cmd_csq_done(struct hclgevf_hw * hw)53 static bool hclgevf_cmd_csq_done(struct hclgevf_hw *hw)
54 {
55 u32 head;
56
57 head = hclgevf_read_dev(hw, HCLGEVF_NIC_CSQ_HEAD_REG);
58
59 return head == hw->cmq.csq.next_to_use;
60 }
61
hclgevf_is_special_opcode(u16 opcode)62 static bool hclgevf_is_special_opcode(u16 opcode)
63 {
64 u16 spec_opcode[] = {0x30, 0x31, 0x32};
65 int i;
66
67 for (i = 0; i < ARRAY_SIZE(spec_opcode); i++) {
68 if (spec_opcode[i] == opcode)
69 return true;
70 }
71
72 return false;
73 }
74
hclgevf_alloc_cmd_desc(struct hclgevf_cmq_ring * ring)75 static int hclgevf_alloc_cmd_desc(struct hclgevf_cmq_ring *ring)
76 {
77 int size = ring->desc_num * sizeof(struct hclgevf_desc);
78
79 ring->desc = dma_zalloc_coherent(cmq_ring_to_dev(ring),
80 size, &ring->desc_dma_addr,
81 GFP_KERNEL);
82 if (!ring->desc)
83 return -ENOMEM;
84
85 return 0;
86 }
87
hclgevf_free_cmd_desc(struct hclgevf_cmq_ring * ring)88 static void hclgevf_free_cmd_desc(struct hclgevf_cmq_ring *ring)
89 {
90 int size = ring->desc_num * sizeof(struct hclgevf_desc);
91
92 if (ring->desc) {
93 dma_free_coherent(cmq_ring_to_dev(ring), size,
94 ring->desc, ring->desc_dma_addr);
95 ring->desc = NULL;
96 }
97 }
98
hclgevf_init_cmd_queue(struct hclgevf_dev * hdev,struct hclgevf_cmq_ring * ring)99 static int hclgevf_init_cmd_queue(struct hclgevf_dev *hdev,
100 struct hclgevf_cmq_ring *ring)
101 {
102 struct hclgevf_hw *hw = &hdev->hw;
103 int ring_type = ring->flag;
104 u32 reg_val;
105 int ret;
106
107 ring->desc_num = HCLGEVF_NIC_CMQ_DESC_NUM;
108 spin_lock_init(&ring->lock);
109 ring->next_to_clean = 0;
110 ring->next_to_use = 0;
111 ring->dev = hdev;
112
113 /* allocate CSQ/CRQ descriptor */
114 ret = hclgevf_alloc_cmd_desc(ring);
115 if (ret) {
116 dev_err(&hdev->pdev->dev, "failed(%d) to alloc %s desc\n", ret,
117 (ring_type == HCLGEVF_TYPE_CSQ) ? "CSQ" : "CRQ");
118 return ret;
119 }
120
121 /* initialize the hardware registers with csq/crq dma-address,
122 * descriptor number, head & tail pointers
123 */
124 switch (ring_type) {
125 case HCLGEVF_TYPE_CSQ:
126 reg_val = (u32)ring->desc_dma_addr;
127 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_L_REG, reg_val);
128 reg_val = (u32)((ring->desc_dma_addr >> 31) >> 1);
129 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_H_REG, reg_val);
130
131 reg_val = (ring->desc_num >> HCLGEVF_NIC_CMQ_DESC_NUM_S);
132 reg_val |= HCLGEVF_NIC_CMQ_ENABLE;
133 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_DEPTH_REG, reg_val);
134
135 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_TAIL_REG, 0);
136 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_HEAD_REG, 0);
137 break;
138 case HCLGEVF_TYPE_CRQ:
139 reg_val = (u32)ring->desc_dma_addr;
140 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_BASEADDR_L_REG, reg_val);
141 reg_val = (u32)((ring->desc_dma_addr >> 31) >> 1);
142 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_BASEADDR_H_REG, reg_val);
143
144 reg_val = (ring->desc_num >> HCLGEVF_NIC_CMQ_DESC_NUM_S);
145 reg_val |= HCLGEVF_NIC_CMQ_ENABLE;
146 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_DEPTH_REG, reg_val);
147
148 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_TAIL_REG, 0);
149 hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_HEAD_REG, 0);
150 break;
151 }
152
153 return 0;
154 }
155
hclgevf_cmd_setup_basic_desc(struct hclgevf_desc * desc,enum hclgevf_opcode_type opcode,bool is_read)156 void hclgevf_cmd_setup_basic_desc(struct hclgevf_desc *desc,
157 enum hclgevf_opcode_type opcode, bool is_read)
158 {
159 memset(desc, 0, sizeof(struct hclgevf_desc));
160 desc->opcode = cpu_to_le16(opcode);
161 desc->flag = cpu_to_le16(HCLGEVF_CMD_FLAG_NO_INTR |
162 HCLGEVF_CMD_FLAG_IN);
163 if (is_read)
164 desc->flag |= cpu_to_le16(HCLGEVF_CMD_FLAG_WR);
165 else
166 desc->flag &= cpu_to_le16(~HCLGEVF_CMD_FLAG_WR);
167 }
168
169 /* hclgevf_cmd_send - send command to command queue
170 * @hw: pointer to the hw struct
171 * @desc: prefilled descriptor for describing the command
172 * @num : the number of descriptors to be sent
173 *
174 * This is the main send command for command queue, it
175 * sends the queue, cleans the queue, etc
176 */
hclgevf_cmd_send(struct hclgevf_hw * hw,struct hclgevf_desc * desc,int num)177 int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclgevf_desc *desc, int num)
178 {
179 struct hclgevf_dev *hdev = (struct hclgevf_dev *)hw->hdev;
180 struct hclgevf_desc *desc_to_use;
181 bool complete = false;
182 u32 timeout = 0;
183 int handle = 0;
184 int status = 0;
185 u16 retval;
186 u16 opcode;
187 int ntc;
188
189 spin_lock_bh(&hw->cmq.csq.lock);
190
191 if (num > hclgevf_ring_space(&hw->cmq.csq)) {
192 spin_unlock_bh(&hw->cmq.csq.lock);
193 return -EBUSY;
194 }
195
196 /* Record the location of desc in the ring for this time
197 * which will be use for hardware to write back
198 */
199 ntc = hw->cmq.csq.next_to_use;
200 opcode = le16_to_cpu(desc[0].opcode);
201 while (handle < num) {
202 desc_to_use = &hw->cmq.csq.desc[hw->cmq.csq.next_to_use];
203 *desc_to_use = desc[handle];
204 (hw->cmq.csq.next_to_use)++;
205 if (hw->cmq.csq.next_to_use == hw->cmq.csq.desc_num)
206 hw->cmq.csq.next_to_use = 0;
207 handle++;
208 }
209
210 /* Write to hardware */
211 hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_TAIL_REG,
212 hw->cmq.csq.next_to_use);
213
214 /* If the command is sync, wait for the firmware to write back,
215 * if multi descriptors to be sent, use the first one to check
216 */
217 if (HCLGEVF_SEND_SYNC(le16_to_cpu(desc->flag))) {
218 do {
219 if (hclgevf_cmd_csq_done(hw))
220 break;
221 udelay(1);
222 timeout++;
223 } while (timeout < hw->cmq.tx_timeout);
224 }
225
226 if (hclgevf_cmd_csq_done(hw)) {
227 complete = true;
228 handle = 0;
229
230 while (handle < num) {
231 /* Get the result of hardware write back */
232 desc_to_use = &hw->cmq.csq.desc[ntc];
233 desc[handle] = *desc_to_use;
234
235 if (likely(!hclgevf_is_special_opcode(opcode)))
236 retval = le16_to_cpu(desc[handle].retval);
237 else
238 retval = le16_to_cpu(desc[0].retval);
239
240 if ((enum hclgevf_cmd_return_status)retval ==
241 HCLGEVF_CMD_EXEC_SUCCESS)
242 status = 0;
243 else
244 status = -EIO;
245 hw->cmq.last_status = (enum hclgevf_cmd_status)retval;
246 ntc++;
247 handle++;
248 if (ntc == hw->cmq.csq.desc_num)
249 ntc = 0;
250 }
251 }
252
253 if (!complete)
254 status = -EAGAIN;
255
256 /* Clean the command send queue */
257 handle = hclgevf_cmd_csq_clean(hw);
258 if (handle != num) {
259 dev_warn(&hdev->pdev->dev,
260 "cleaned %d, need to clean %d\n", handle, num);
261 }
262
263 spin_unlock_bh(&hw->cmq.csq.lock);
264
265 return status;
266 }
267
hclgevf_cmd_query_firmware_version(struct hclgevf_hw * hw,u32 * version)268 static int hclgevf_cmd_query_firmware_version(struct hclgevf_hw *hw,
269 u32 *version)
270 {
271 struct hclgevf_query_version_cmd *resp;
272 struct hclgevf_desc desc;
273 int status;
274
275 resp = (struct hclgevf_query_version_cmd *)desc.data;
276
277 hclgevf_cmd_setup_basic_desc(&desc, HCLGEVF_OPC_QUERY_FW_VER, 1);
278 status = hclgevf_cmd_send(hw, &desc, 1);
279 if (!status)
280 *version = le32_to_cpu(resp->firmware);
281
282 return status;
283 }
284
hclgevf_cmd_init(struct hclgevf_dev * hdev)285 int hclgevf_cmd_init(struct hclgevf_dev *hdev)
286 {
287 u32 version;
288 int ret;
289
290 /* setup Tx write back timeout */
291 hdev->hw.cmq.tx_timeout = HCLGEVF_CMDQ_TX_TIMEOUT;
292
293 /* setup queue CSQ/CRQ rings */
294 hdev->hw.cmq.csq.flag = HCLGEVF_TYPE_CSQ;
295 ret = hclgevf_init_cmd_queue(hdev, &hdev->hw.cmq.csq);
296 if (ret) {
297 dev_err(&hdev->pdev->dev,
298 "failed(%d) to initialize CSQ ring\n", ret);
299 return ret;
300 }
301
302 hdev->hw.cmq.crq.flag = HCLGEVF_TYPE_CRQ;
303 ret = hclgevf_init_cmd_queue(hdev, &hdev->hw.cmq.crq);
304 if (ret) {
305 dev_err(&hdev->pdev->dev,
306 "failed(%d) to initialize CRQ ring\n", ret);
307 goto err_csq;
308 }
309
310 /* initialize the pointers of async rx queue of mailbox */
311 hdev->arq.hdev = hdev;
312 hdev->arq.head = 0;
313 hdev->arq.tail = 0;
314 hdev->arq.count = 0;
315
316 /* get firmware version */
317 ret = hclgevf_cmd_query_firmware_version(&hdev->hw, &version);
318 if (ret) {
319 dev_err(&hdev->pdev->dev,
320 "failed(%d) to query firmware version\n", ret);
321 goto err_crq;
322 }
323 hdev->fw_version = version;
324
325 dev_info(&hdev->pdev->dev, "The firmware version is %08x\n", version);
326
327 return 0;
328 err_crq:
329 hclgevf_free_cmd_desc(&hdev->hw.cmq.crq);
330 err_csq:
331 hclgevf_free_cmd_desc(&hdev->hw.cmq.csq);
332
333 return ret;
334 }
335
hclgevf_cmd_uninit(struct hclgevf_dev * hdev)336 void hclgevf_cmd_uninit(struct hclgevf_dev *hdev)
337 {
338 hclgevf_free_cmd_desc(&hdev->hw.cmq.csq);
339 hclgevf_free_cmd_desc(&hdev->hw.cmq.crq);
340 }
341
