1 /*
2 * Applied Micro X-Gene SoC Ethernet v2 Driver
3 *
4 * Copyright (c) 2017, Applied Micro Circuits Corporation
5 * Author(s): Iyappan Subramanian <isubramanian@apm.com>
6 * Keyur Chudgar <kchudgar@apm.com>
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program. If not, see <http://www.gnu.org/licenses/>.
20 */
21
22 #include "main.h"
23
xge_mac_reset(struct xge_pdata * pdata)24 void xge_mac_reset(struct xge_pdata *pdata)
25 {
26 xge_wr_csr(pdata, MAC_CONFIG_1, SOFT_RESET);
27 xge_wr_csr(pdata, MAC_CONFIG_1, 0);
28 }
29
xge_mac_set_speed(struct xge_pdata * pdata)30 void xge_mac_set_speed(struct xge_pdata *pdata)
31 {
32 u32 icm0, icm2, ecm0, mc2;
33 u32 intf_ctrl, rgmii;
34
35 icm0 = xge_rd_csr(pdata, ICM_CONFIG0_REG_0);
36 icm2 = xge_rd_csr(pdata, ICM_CONFIG2_REG_0);
37 ecm0 = xge_rd_csr(pdata, ECM_CONFIG0_REG_0);
38 rgmii = xge_rd_csr(pdata, RGMII_REG_0);
39 mc2 = xge_rd_csr(pdata, MAC_CONFIG_2);
40 intf_ctrl = xge_rd_csr(pdata, INTERFACE_CONTROL);
41 icm2 |= CFG_WAITASYNCRD_EN;
42
43 switch (pdata->phy_speed) {
44 case SPEED_10:
45 SET_REG_BITS(&mc2, INTF_MODE, 1);
46 SET_REG_BITS(&intf_ctrl, HD_MODE, 0);
47 SET_REG_BITS(&icm0, CFG_MACMODE, 0);
48 SET_REG_BITS(&icm2, CFG_WAITASYNCRD, 500);
49 SET_REG_BIT(&rgmii, CFG_SPEED_125, 0);
50 break;
51 case SPEED_100:
52 SET_REG_BITS(&mc2, INTF_MODE, 1);
53 SET_REG_BITS(&intf_ctrl, HD_MODE, 1);
54 SET_REG_BITS(&icm0, CFG_MACMODE, 1);
55 SET_REG_BITS(&icm2, CFG_WAITASYNCRD, 80);
56 SET_REG_BIT(&rgmii, CFG_SPEED_125, 0);
57 break;
58 default:
59 SET_REG_BITS(&mc2, INTF_MODE, 2);
60 SET_REG_BITS(&intf_ctrl, HD_MODE, 2);
61 SET_REG_BITS(&icm0, CFG_MACMODE, 2);
62 SET_REG_BITS(&icm2, CFG_WAITASYNCRD, 16);
63 SET_REG_BIT(&rgmii, CFG_SPEED_125, 1);
64 break;
65 }
66
67 mc2 |= FULL_DUPLEX | CRC_EN | PAD_CRC;
68 SET_REG_BITS(&ecm0, CFG_WFIFOFULLTHR, 0x32);
69
70 xge_wr_csr(pdata, MAC_CONFIG_2, mc2);
71 xge_wr_csr(pdata, INTERFACE_CONTROL, intf_ctrl);
72 xge_wr_csr(pdata, RGMII_REG_0, rgmii);
73 xge_wr_csr(pdata, ICM_CONFIG0_REG_0, icm0);
74 xge_wr_csr(pdata, ICM_CONFIG2_REG_0, icm2);
75 xge_wr_csr(pdata, ECM_CONFIG0_REG_0, ecm0);
76 }
77
xge_mac_set_station_addr(struct xge_pdata * pdata)78 void xge_mac_set_station_addr(struct xge_pdata *pdata)
79 {
80 u8 *dev_addr = pdata->ndev->dev_addr;
81 u32 addr0, addr1;
82
83 addr0 = (dev_addr[3] << 24) | (dev_addr[2] << 16) |
84 (dev_addr[1] << 8) | dev_addr[0];
85 addr1 = (dev_addr[5] << 24) | (dev_addr[4] << 16);
86
87 xge_wr_csr(pdata, STATION_ADDR0, addr0);
88 xge_wr_csr(pdata, STATION_ADDR1, addr1);
89 }
90
xge_mac_init(struct xge_pdata * pdata)91 void xge_mac_init(struct xge_pdata *pdata)
92 {
93 xge_mac_reset(pdata);
94 xge_mac_set_speed(pdata);
95 xge_mac_set_station_addr(pdata);
96 }
97
xge_mac_enable(struct xge_pdata * pdata)98 void xge_mac_enable(struct xge_pdata *pdata)
99 {
100 u32 data;
101
102 data = xge_rd_csr(pdata, MAC_CONFIG_1);
103 data |= TX_EN | RX_EN;
104 xge_wr_csr(pdata, MAC_CONFIG_1, data);
105
106 data = xge_rd_csr(pdata, MAC_CONFIG_1);
107 }
108
xge_mac_disable(struct xge_pdata * pdata)109 void xge_mac_disable(struct xge_pdata *pdata)
110 {
111 u32 data;
112
113 data = xge_rd_csr(pdata, MAC_CONFIG_1);
114 data &= ~(TX_EN | RX_EN);
115 xge_wr_csr(pdata, MAC_CONFIG_1, data);
116 }
117
