1 /* 2 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name> 3 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org> 4 * Copyright (c) 2015, The Linux Foundation. All rights reserved. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 and 8 * only version 2 as published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #ifndef __QCA8K_H 17 #define __QCA8K_H 18 19 #include <linux/delay.h> 20 #include <linux/regmap.h> 21 22 #define QCA8K_NUM_PORTS 7 23 24 #define PHY_ID_QCA8337 0x004dd036 25 #define QCA8K_ID_QCA8337 0x13 26 27 #define QCA8K_NUM_FDB_RECORDS 2048 28 29 #define QCA8K_CPU_PORT 0 30 31 /* Global control registers */ 32 #define QCA8K_REG_MASK_CTRL 0x000 33 #define QCA8K_MASK_CTRL_ID_M 0xff 34 #define QCA8K_MASK_CTRL_ID_S 8 35 #define QCA8K_REG_PORT0_PAD_CTRL 0x004 36 #define QCA8K_REG_PORT5_PAD_CTRL 0x008 37 #define QCA8K_REG_PORT6_PAD_CTRL 0x00c 38 #define QCA8K_PORT_PAD_RGMII_EN BIT(26) 39 #define QCA8K_PORT_PAD_RGMII_TX_DELAY(x) \ 40 ((0x8 + (x & 0x3)) << 22) 41 #define QCA8K_PORT_PAD_RGMII_RX_DELAY(x) \ 42 ((0x10 + (x & 0x3)) << 20) 43 #define QCA8K_PORT_PAD_RGMII_RX_DELAY_EN BIT(24) 44 #define QCA8K_PORT_PAD_SGMII_EN BIT(7) 45 #define QCA8K_REG_MODULE_EN 0x030 46 #define QCA8K_MODULE_EN_MIB BIT(0) 47 #define QCA8K_REG_MIB 0x034 48 #define QCA8K_MIB_FLUSH BIT(24) 49 #define QCA8K_MIB_CPU_KEEP BIT(20) 50 #define QCA8K_MIB_BUSY BIT(17) 51 #define QCA8K_GOL_MAC_ADDR0 0x60 52 #define QCA8K_GOL_MAC_ADDR1 0x64 53 #define QCA8K_REG_PORT_STATUS(_i) (0x07c + (_i) * 4) 54 #define QCA8K_PORT_STATUS_SPEED GENMASK(1, 0) 55 #define QCA8K_PORT_STATUS_SPEED_10 0 56 #define QCA8K_PORT_STATUS_SPEED_100 0x1 57 #define QCA8K_PORT_STATUS_SPEED_1000 0x2 58 #define QCA8K_PORT_STATUS_TXMAC BIT(2) 59 #define QCA8K_PORT_STATUS_RXMAC BIT(3) 60 #define QCA8K_PORT_STATUS_TXFLOW BIT(4) 61 #define QCA8K_PORT_STATUS_RXFLOW BIT(5) 62 #define QCA8K_PORT_STATUS_DUPLEX BIT(6) 63 #define QCA8K_PORT_STATUS_LINK_UP BIT(8) 64 #define QCA8K_PORT_STATUS_LINK_AUTO BIT(9) 65 #define QCA8K_PORT_STATUS_LINK_PAUSE BIT(10) 66 #define QCA8K_REG_PORT_HDR_CTRL(_i) (0x9c + (_i * 4)) 67 #define QCA8K_PORT_HDR_CTRL_RX_MASK GENMASK(3, 2) 68 #define QCA8K_PORT_HDR_CTRL_RX_S 2 69 #define QCA8K_PORT_HDR_CTRL_TX_MASK GENMASK(1, 0) 70 #define QCA8K_PORT_HDR_CTRL_TX_S 0 71 #define QCA8K_PORT_HDR_CTRL_ALL 2 72 #define QCA8K_PORT_HDR_CTRL_MGMT 1 73 #define QCA8K_PORT_HDR_CTRL_NONE 0 74 75 /* EEE control registers */ 76 #define QCA8K_REG_EEE_CTRL 0x100 77 #define QCA8K_REG_EEE_CTRL_LPI_EN(_i) ((_i + 1) * 2) 78 79 /* ACL registers */ 80 #define QCA8K_REG_PORT_VLAN_CTRL0(_i) (0x420 + (_i * 8)) 81 #define QCA8K_PORT_VLAN_CVID(x) (x << 16) 82 #define QCA8K_PORT_VLAN_SVID(x) x 83 #define QCA8K_REG_PORT_VLAN_CTRL1(_i) (0x424 + (_i * 8)) 84 #define QCA8K_REG_IPV4_PRI_BASE_ADDR 0x470 85 #define QCA8K_REG_IPV4_PRI_ADDR_MASK 0x474 86 87 /* Lookup registers */ 88 #define QCA8K_REG_ATU_DATA0 0x600 89 #define QCA8K_ATU_ADDR2_S 24 90 #define QCA8K_ATU_ADDR3_S 16 91 #define QCA8K_ATU_ADDR4_S 8 92 #define QCA8K_REG_ATU_DATA1 0x604 93 #define QCA8K_ATU_PORT_M 0x7f 94 #define QCA8K_ATU_PORT_S 16 95 #define QCA8K_ATU_ADDR0_S 8 96 #define QCA8K_REG_ATU_DATA2 0x608 97 #define QCA8K_ATU_VID_M 0xfff 98 #define QCA8K_ATU_VID_S 8 99 #define QCA8K_ATU_STATUS_M 0xf 100 #define QCA8K_ATU_STATUS_STATIC 0xf 101 #define QCA8K_REG_ATU_FUNC 0x60c 102 #define QCA8K_ATU_FUNC_BUSY BIT(31) 103 #define QCA8K_ATU_FUNC_PORT_EN BIT(14) 104 #define QCA8K_ATU_FUNC_MULTI_EN BIT(13) 105 #define QCA8K_ATU_FUNC_FULL BIT(12) 106 #define QCA8K_ATU_FUNC_PORT_M 0xf 107 #define QCA8K_ATU_FUNC_PORT_S 8 108 #define QCA8K_REG_GLOBAL_FW_CTRL0 0x620 109 #define QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN BIT(10) 110 #define QCA8K_REG_GLOBAL_FW_CTRL1 0x624 111 #define QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S 24 112 #define QCA8K_GLOBAL_FW_CTRL1_BC_DP_S 16 113 #define QCA8K_GLOBAL_FW_CTRL1_MC_DP_S 8 114 #define QCA8K_GLOBAL_FW_CTRL1_UC_DP_S 0 115 #define QCA8K_PORT_LOOKUP_CTRL(_i) (0x660 + (_i) * 0xc) 116 #define QCA8K_PORT_LOOKUP_MEMBER GENMASK(6, 0) 117 #define QCA8K_PORT_LOOKUP_STATE_MASK GENMASK(18, 16) 118 #define QCA8K_PORT_LOOKUP_STATE_DISABLED (0 << 16) 119 #define QCA8K_PORT_LOOKUP_STATE_BLOCKING (1 << 16) 120 #define QCA8K_PORT_LOOKUP_STATE_LISTENING (2 << 16) 121 #define QCA8K_PORT_LOOKUP_STATE_LEARNING (3 << 16) 122 #define QCA8K_PORT_LOOKUP_STATE_FORWARD (4 << 16) 123 #define QCA8K_PORT_LOOKUP_STATE GENMASK(18, 16) 124 #define QCA8K_PORT_LOOKUP_LEARN BIT(20) 125 126 /* Pkt edit registers */ 127 #define QCA8K_EGRESS_VLAN(x) (0x0c70 + (4 * (x / 2))) 128 129 /* L3 registers */ 130 #define QCA8K_HROUTER_CONTROL 0xe00 131 #define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_M GENMASK(17, 16) 132 #define QCA8K_HROUTER_CONTROL_GLB_LOCKTIME_S 16 133 #define QCA8K_HROUTER_CONTROL_ARP_AGE_MODE 1 134 #define QCA8K_HROUTER_PBASED_CONTROL1 0xe08 135 #define QCA8K_HROUTER_PBASED_CONTROL2 0xe0c 136 #define QCA8K_HNAT_CONTROL 0xe38 137 138 /* MIB registers */ 139 #define QCA8K_PORT_MIB_COUNTER(_i) (0x1000 + (_i) * 0x100) 140 141 /* QCA specific MII registers */ 142 #define MII_ATH_MMD_ADDR 0x0d 143 #define MII_ATH_MMD_DATA 0x0e 144 145 enum { 146 QCA8K_PORT_SPEED_10M = 0, 147 QCA8K_PORT_SPEED_100M = 1, 148 QCA8K_PORT_SPEED_1000M = 2, 149 QCA8K_PORT_SPEED_ERR = 3, 150 }; 151 152 enum qca8k_fdb_cmd { 153 QCA8K_FDB_FLUSH = 1, 154 QCA8K_FDB_LOAD = 2, 155 QCA8K_FDB_PURGE = 3, 156 QCA8K_FDB_NEXT = 6, 157 QCA8K_FDB_SEARCH = 7, 158 }; 159 160 struct ar8xxx_port_status { 161 int enabled; 162 }; 163 164 struct qca8k_priv { 165 struct regmap *regmap; 166 struct mii_bus *bus; 167 struct ar8xxx_port_status port_sts[QCA8K_NUM_PORTS]; 168 struct dsa_switch *ds; 169 struct mutex reg_mutex; 170 struct device *dev; 171 }; 172 173 struct qca8k_mib_desc { 174 unsigned int size; 175 unsigned int offset; 176 const char *name; 177 }; 178 179 struct qca8k_fdb { 180 u16 vid; 181 u8 port_mask; 182 u8 aging; 183 u8 mac[6]; 184 }; 185 186 #endif /* __QCA8K_H */ 187
