1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright (C) 2009 Felix Fietkau <nbd@nbd.name>
4 * Copyright (C) 2011-2012 Gabor Juhos <juhosg@openwrt.org>
5 * Copyright (c) 2015, The Linux Foundation. All rights reserved.
6 * Copyright (c) 2016 John Crispin <john@phrozen.org>
7 */
8
9 #include <linux/module.h>
10 #include <linux/phy.h>
11 #include <linux/netdevice.h>
12 #include <net/dsa.h>
13 #include <linux/of_net.h>
14 #include <linux/of_platform.h>
15 #include <linux/if_bridge.h>
16 #include <linux/mdio.h>
17 #include <linux/etherdevice.h>
18
19 #include "qca8k.h"
20
21 #define MIB_DESC(_s, _o, _n) \
22 { \
23 .size = (_s), \
24 .offset = (_o), \
25 .name = (_n), \
26 }
27
28 static const struct qca8k_mib_desc ar8327_mib[] = {
29 MIB_DESC(1, 0x00, "RxBroad"),
30 MIB_DESC(1, 0x04, "RxPause"),
31 MIB_DESC(1, 0x08, "RxMulti"),
32 MIB_DESC(1, 0x0c, "RxFcsErr"),
33 MIB_DESC(1, 0x10, "RxAlignErr"),
34 MIB_DESC(1, 0x14, "RxRunt"),
35 MIB_DESC(1, 0x18, "RxFragment"),
36 MIB_DESC(1, 0x1c, "Rx64Byte"),
37 MIB_DESC(1, 0x20, "Rx128Byte"),
38 MIB_DESC(1, 0x24, "Rx256Byte"),
39 MIB_DESC(1, 0x28, "Rx512Byte"),
40 MIB_DESC(1, 0x2c, "Rx1024Byte"),
41 MIB_DESC(1, 0x30, "Rx1518Byte"),
42 MIB_DESC(1, 0x34, "RxMaxByte"),
43 MIB_DESC(1, 0x38, "RxTooLong"),
44 MIB_DESC(2, 0x3c, "RxGoodByte"),
45 MIB_DESC(2, 0x44, "RxBadByte"),
46 MIB_DESC(1, 0x4c, "RxOverFlow"),
47 MIB_DESC(1, 0x50, "Filtered"),
48 MIB_DESC(1, 0x54, "TxBroad"),
49 MIB_DESC(1, 0x58, "TxPause"),
50 MIB_DESC(1, 0x5c, "TxMulti"),
51 MIB_DESC(1, 0x60, "TxUnderRun"),
52 MIB_DESC(1, 0x64, "Tx64Byte"),
53 MIB_DESC(1, 0x68, "Tx128Byte"),
54 MIB_DESC(1, 0x6c, "Tx256Byte"),
55 MIB_DESC(1, 0x70, "Tx512Byte"),
56 MIB_DESC(1, 0x74, "Tx1024Byte"),
57 MIB_DESC(1, 0x78, "Tx1518Byte"),
58 MIB_DESC(1, 0x7c, "TxMaxByte"),
59 MIB_DESC(1, 0x80, "TxOverSize"),
60 MIB_DESC(2, 0x84, "TxByte"),
61 MIB_DESC(1, 0x8c, "TxCollision"),
62 MIB_DESC(1, 0x90, "TxAbortCol"),
63 MIB_DESC(1, 0x94, "TxMultiCol"),
64 MIB_DESC(1, 0x98, "TxSingleCol"),
65 MIB_DESC(1, 0x9c, "TxExcDefer"),
66 MIB_DESC(1, 0xa0, "TxDefer"),
67 MIB_DESC(1, 0xa4, "TxLateCol"),
68 };
69
70 /* The 32bit switch registers are accessed indirectly. To achieve this we need
71 * to set the page of the register. Track the last page that was set to reduce
72 * mdio writes
73 */
74 static u16 qca8k_current_page = 0xffff;
75
76 static void
qca8k_split_addr(u32 regaddr,u16 * r1,u16 * r2,u16 * page)77 qca8k_split_addr(u32 regaddr, u16 *r1, u16 *r2, u16 *page)
78 {
79 regaddr >>= 1;
80 *r1 = regaddr & 0x1e;
81
82 regaddr >>= 5;
83 *r2 = regaddr & 0x7;
84
85 regaddr >>= 3;
86 *page = regaddr & 0x3ff;
87 }
88
89 static u32
qca8k_mii_read32(struct mii_bus * bus,int phy_id,u32 regnum)90 qca8k_mii_read32(struct mii_bus *bus, int phy_id, u32 regnum)
91 {
92 u32 val;
93 int ret;
94
95 ret = bus->read(bus, phy_id, regnum);
96 if (ret >= 0) {
97 val = ret;
98 ret = bus->read(bus, phy_id, regnum + 1);
99 val |= ret << 16;
100 }
101
102 if (ret < 0) {
103 dev_err_ratelimited(&bus->dev,
104 "failed to read qca8k 32bit register\n");
105 return ret;
106 }
107
108 return val;
109 }
110
111 static void
qca8k_mii_write32(struct mii_bus * bus,int phy_id,u32 regnum,u32 val)112 qca8k_mii_write32(struct mii_bus *bus, int phy_id, u32 regnum, u32 val)
113 {
114 u16 lo, hi;
115 int ret;
116
117 lo = val & 0xffff;
118 hi = (u16)(val >> 16);
119
120 ret = bus->write(bus, phy_id, regnum, lo);
121 if (ret >= 0)
122 ret = bus->write(bus, phy_id, regnum + 1, hi);
123 if (ret < 0)
124 dev_err_ratelimited(&bus->dev,
125 "failed to write qca8k 32bit register\n");
126 }
127
128 static void
qca8k_set_page(struct mii_bus * bus,u16 page)129 qca8k_set_page(struct mii_bus *bus, u16 page)
130 {
131 if (page == qca8k_current_page)
132 return;
133
134 if (bus->write(bus, 0x18, 0, page) < 0)
135 dev_err_ratelimited(&bus->dev,
136 "failed to set qca8k page\n");
137 qca8k_current_page = page;
138 }
139
140 static u32
qca8k_read(struct qca8k_priv * priv,u32 reg)141 qca8k_read(struct qca8k_priv *priv, u32 reg)
142 {
143 u16 r1, r2, page;
144 u32 val;
145
146 qca8k_split_addr(reg, &r1, &r2, &page);
147
148 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
149
150 qca8k_set_page(priv->bus, page);
151 val = qca8k_mii_read32(priv->bus, 0x10 | r2, r1);
152
153 mutex_unlock(&priv->bus->mdio_lock);
154
155 return val;
156 }
157
158 static void
qca8k_write(struct qca8k_priv * priv,u32 reg,u32 val)159 qca8k_write(struct qca8k_priv *priv, u32 reg, u32 val)
160 {
161 u16 r1, r2, page;
162
163 qca8k_split_addr(reg, &r1, &r2, &page);
164
165 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
166
167 qca8k_set_page(priv->bus, page);
168 qca8k_mii_write32(priv->bus, 0x10 | r2, r1, val);
169
170 mutex_unlock(&priv->bus->mdio_lock);
171 }
172
173 static u32
qca8k_rmw(struct qca8k_priv * priv,u32 reg,u32 mask,u32 val)174 qca8k_rmw(struct qca8k_priv *priv, u32 reg, u32 mask, u32 val)
175 {
176 u16 r1, r2, page;
177 u32 ret;
178
179 qca8k_split_addr(reg, &r1, &r2, &page);
180
181 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED);
182
183 qca8k_set_page(priv->bus, page);
184 ret = qca8k_mii_read32(priv->bus, 0x10 | r2, r1);
185 ret &= ~mask;
186 ret |= val;
187 qca8k_mii_write32(priv->bus, 0x10 | r2, r1, ret);
188
189 mutex_unlock(&priv->bus->mdio_lock);
190
191 return ret;
192 }
193
194 static void
qca8k_reg_set(struct qca8k_priv * priv,u32 reg,u32 val)195 qca8k_reg_set(struct qca8k_priv *priv, u32 reg, u32 val)
196 {
197 qca8k_rmw(priv, reg, 0, val);
198 }
199
200 static void
qca8k_reg_clear(struct qca8k_priv * priv,u32 reg,u32 val)201 qca8k_reg_clear(struct qca8k_priv *priv, u32 reg, u32 val)
202 {
203 qca8k_rmw(priv, reg, val, 0);
204 }
205
206 static int
qca8k_regmap_read(void * ctx,uint32_t reg,uint32_t * val)207 qca8k_regmap_read(void *ctx, uint32_t reg, uint32_t *val)
208 {
209 struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
210
211 *val = qca8k_read(priv, reg);
212
213 return 0;
214 }
215
216 static int
qca8k_regmap_write(void * ctx,uint32_t reg,uint32_t val)217 qca8k_regmap_write(void *ctx, uint32_t reg, uint32_t val)
218 {
219 struct qca8k_priv *priv = (struct qca8k_priv *)ctx;
220
221 qca8k_write(priv, reg, val);
222
223 return 0;
224 }
225
226 static const struct regmap_range qca8k_readable_ranges[] = {
227 regmap_reg_range(0x0000, 0x00e4), /* Global control */
228 regmap_reg_range(0x0100, 0x0168), /* EEE control */
229 regmap_reg_range(0x0200, 0x0270), /* Parser control */
230 regmap_reg_range(0x0400, 0x0454), /* ACL */
231 regmap_reg_range(0x0600, 0x0718), /* Lookup */
232 regmap_reg_range(0x0800, 0x0b70), /* QM */
233 regmap_reg_range(0x0c00, 0x0c80), /* PKT */
234 regmap_reg_range(0x0e00, 0x0e98), /* L3 */
235 regmap_reg_range(0x1000, 0x10ac), /* MIB - Port0 */
236 regmap_reg_range(0x1100, 0x11ac), /* MIB - Port1 */
237 regmap_reg_range(0x1200, 0x12ac), /* MIB - Port2 */
238 regmap_reg_range(0x1300, 0x13ac), /* MIB - Port3 */
239 regmap_reg_range(0x1400, 0x14ac), /* MIB - Port4 */
240 regmap_reg_range(0x1500, 0x15ac), /* MIB - Port5 */
241 regmap_reg_range(0x1600, 0x16ac), /* MIB - Port6 */
242
243 };
244
245 static const struct regmap_access_table qca8k_readable_table = {
246 .yes_ranges = qca8k_readable_ranges,
247 .n_yes_ranges = ARRAY_SIZE(qca8k_readable_ranges),
248 };
249
250 static struct regmap_config qca8k_regmap_config = {
251 .reg_bits = 16,
252 .val_bits = 32,
253 .reg_stride = 4,
254 .max_register = 0x16ac, /* end MIB - Port6 range */
255 .reg_read = qca8k_regmap_read,
256 .reg_write = qca8k_regmap_write,
257 .rd_table = &qca8k_readable_table,
258 };
259
260 static int
qca8k_busy_wait(struct qca8k_priv * priv,u32 reg,u32 mask)261 qca8k_busy_wait(struct qca8k_priv *priv, u32 reg, u32 mask)
262 {
263 unsigned long timeout;
264
265 timeout = jiffies + msecs_to_jiffies(20);
266
267 /* loop until the busy flag has cleared */
268 do {
269 u32 val = qca8k_read(priv, reg);
270 int busy = val & mask;
271
272 if (!busy)
273 break;
274 cond_resched();
275 } while (!time_after_eq(jiffies, timeout));
276
277 return time_after_eq(jiffies, timeout);
278 }
279
280 static void
qca8k_fdb_read(struct qca8k_priv * priv,struct qca8k_fdb * fdb)281 qca8k_fdb_read(struct qca8k_priv *priv, struct qca8k_fdb *fdb)
282 {
283 u32 reg[4];
284 int i;
285
286 /* load the ARL table into an array */
287 for (i = 0; i < 4; i++)
288 reg[i] = qca8k_read(priv, QCA8K_REG_ATU_DATA0 + (i * 4));
289
290 /* vid - 83:72 */
291 fdb->vid = (reg[2] >> QCA8K_ATU_VID_S) & QCA8K_ATU_VID_M;
292 /* aging - 67:64 */
293 fdb->aging = reg[2] & QCA8K_ATU_STATUS_M;
294 /* portmask - 54:48 */
295 fdb->port_mask = (reg[1] >> QCA8K_ATU_PORT_S) & QCA8K_ATU_PORT_M;
296 /* mac - 47:0 */
297 fdb->mac[0] = (reg[1] >> QCA8K_ATU_ADDR0_S) & 0xff;
298 fdb->mac[1] = reg[1] & 0xff;
299 fdb->mac[2] = (reg[0] >> QCA8K_ATU_ADDR2_S) & 0xff;
300 fdb->mac[3] = (reg[0] >> QCA8K_ATU_ADDR3_S) & 0xff;
301 fdb->mac[4] = (reg[0] >> QCA8K_ATU_ADDR4_S) & 0xff;
302 fdb->mac[5] = reg[0] & 0xff;
303 }
304
305 static void
qca8k_fdb_write(struct qca8k_priv * priv,u16 vid,u8 port_mask,const u8 * mac,u8 aging)306 qca8k_fdb_write(struct qca8k_priv *priv, u16 vid, u8 port_mask, const u8 *mac,
307 u8 aging)
308 {
309 u32 reg[3] = { 0 };
310 int i;
311
312 /* vid - 83:72 */
313 reg[2] = (vid & QCA8K_ATU_VID_M) << QCA8K_ATU_VID_S;
314 /* aging - 67:64 */
315 reg[2] |= aging & QCA8K_ATU_STATUS_M;
316 /* portmask - 54:48 */
317 reg[1] = (port_mask & QCA8K_ATU_PORT_M) << QCA8K_ATU_PORT_S;
318 /* mac - 47:0 */
319 reg[1] |= mac[0] << QCA8K_ATU_ADDR0_S;
320 reg[1] |= mac[1];
321 reg[0] |= mac[2] << QCA8K_ATU_ADDR2_S;
322 reg[0] |= mac[3] << QCA8K_ATU_ADDR3_S;
323 reg[0] |= mac[4] << QCA8K_ATU_ADDR4_S;
324 reg[0] |= mac[5];
325
326 /* load the array into the ARL table */
327 for (i = 0; i < 3; i++)
328 qca8k_write(priv, QCA8K_REG_ATU_DATA0 + (i * 4), reg[i]);
329 }
330
331 static int
qca8k_fdb_access(struct qca8k_priv * priv,enum qca8k_fdb_cmd cmd,int port)332 qca8k_fdb_access(struct qca8k_priv *priv, enum qca8k_fdb_cmd cmd, int port)
333 {
334 u32 reg;
335
336 /* Set the command and FDB index */
337 reg = QCA8K_ATU_FUNC_BUSY;
338 reg |= cmd;
339 if (port >= 0) {
340 reg |= QCA8K_ATU_FUNC_PORT_EN;
341 reg |= (port & QCA8K_ATU_FUNC_PORT_M) << QCA8K_ATU_FUNC_PORT_S;
342 }
343
344 /* Write the function register triggering the table access */
345 qca8k_write(priv, QCA8K_REG_ATU_FUNC, reg);
346
347 /* wait for completion */
348 if (qca8k_busy_wait(priv, QCA8K_REG_ATU_FUNC, QCA8K_ATU_FUNC_BUSY))
349 return -1;
350
351 /* Check for table full violation when adding an entry */
352 if (cmd == QCA8K_FDB_LOAD) {
353 reg = qca8k_read(priv, QCA8K_REG_ATU_FUNC);
354 if (reg & QCA8K_ATU_FUNC_FULL)
355 return -1;
356 }
357
358 return 0;
359 }
360
361 static int
qca8k_fdb_next(struct qca8k_priv * priv,struct qca8k_fdb * fdb,int port)362 qca8k_fdb_next(struct qca8k_priv *priv, struct qca8k_fdb *fdb, int port)
363 {
364 int ret;
365
366 qca8k_fdb_write(priv, fdb->vid, fdb->port_mask, fdb->mac, fdb->aging);
367 ret = qca8k_fdb_access(priv, QCA8K_FDB_NEXT, port);
368 if (ret >= 0)
369 qca8k_fdb_read(priv, fdb);
370
371 return ret;
372 }
373
374 static int
qca8k_fdb_add(struct qca8k_priv * priv,const u8 * mac,u16 port_mask,u16 vid,u8 aging)375 qca8k_fdb_add(struct qca8k_priv *priv, const u8 *mac, u16 port_mask,
376 u16 vid, u8 aging)
377 {
378 int ret;
379
380 mutex_lock(&priv->reg_mutex);
381 qca8k_fdb_write(priv, vid, port_mask, mac, aging);
382 ret = qca8k_fdb_access(priv, QCA8K_FDB_LOAD, -1);
383 mutex_unlock(&priv->reg_mutex);
384
385 return ret;
386 }
387
388 static int
qca8k_fdb_del(struct qca8k_priv * priv,const u8 * mac,u16 port_mask,u16 vid)389 qca8k_fdb_del(struct qca8k_priv *priv, const u8 *mac, u16 port_mask, u16 vid)
390 {
391 int ret;
392
393 mutex_lock(&priv->reg_mutex);
394 qca8k_fdb_write(priv, vid, port_mask, mac, 0);
395 ret = qca8k_fdb_access(priv, QCA8K_FDB_PURGE, -1);
396 mutex_unlock(&priv->reg_mutex);
397
398 return ret;
399 }
400
401 static void
qca8k_fdb_flush(struct qca8k_priv * priv)402 qca8k_fdb_flush(struct qca8k_priv *priv)
403 {
404 mutex_lock(&priv->reg_mutex);
405 qca8k_fdb_access(priv, QCA8K_FDB_FLUSH, -1);
406 mutex_unlock(&priv->reg_mutex);
407 }
408
409 static void
qca8k_mib_init(struct qca8k_priv * priv)410 qca8k_mib_init(struct qca8k_priv *priv)
411 {
412 mutex_lock(&priv->reg_mutex);
413 qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_FLUSH | QCA8K_MIB_BUSY);
414 qca8k_busy_wait(priv, QCA8K_REG_MIB, QCA8K_MIB_BUSY);
415 qca8k_reg_set(priv, QCA8K_REG_MIB, QCA8K_MIB_CPU_KEEP);
416 qca8k_write(priv, QCA8K_REG_MODULE_EN, QCA8K_MODULE_EN_MIB);
417 mutex_unlock(&priv->reg_mutex);
418 }
419
420 static int
qca8k_set_pad_ctrl(struct qca8k_priv * priv,int port,int mode)421 qca8k_set_pad_ctrl(struct qca8k_priv *priv, int port, int mode)
422 {
423 u32 reg;
424
425 switch (port) {
426 case 0:
427 reg = QCA8K_REG_PORT0_PAD_CTRL;
428 break;
429 case 6:
430 reg = QCA8K_REG_PORT6_PAD_CTRL;
431 break;
432 default:
433 pr_err("Can't set PAD_CTRL on port %d\n", port);
434 return -EINVAL;
435 }
436
437 /* Configure a port to be directly connected to an external
438 * PHY or MAC.
439 */
440 switch (mode) {
441 case PHY_INTERFACE_MODE_RGMII:
442 qca8k_write(priv, reg,
443 QCA8K_PORT_PAD_RGMII_EN |
444 QCA8K_PORT_PAD_RGMII_TX_DELAY(3) |
445 QCA8K_PORT_PAD_RGMII_RX_DELAY(3));
446
447 /* According to the datasheet, RGMII delay is enabled through
448 * PORT5_PAD_CTRL for all ports, rather than individual port
449 * registers
450 */
451 qca8k_write(priv, QCA8K_REG_PORT5_PAD_CTRL,
452 QCA8K_PORT_PAD_RGMII_RX_DELAY_EN);
453 break;
454 case PHY_INTERFACE_MODE_SGMII:
455 qca8k_write(priv, reg, QCA8K_PORT_PAD_SGMII_EN);
456 break;
457 default:
458 pr_err("xMII mode %d not supported\n", mode);
459 return -EINVAL;
460 }
461
462 return 0;
463 }
464
465 static void
qca8k_port_set_status(struct qca8k_priv * priv,int port,int enable)466 qca8k_port_set_status(struct qca8k_priv *priv, int port, int enable)
467 {
468 u32 mask = QCA8K_PORT_STATUS_TXMAC | QCA8K_PORT_STATUS_RXMAC;
469
470 /* Port 0 and 6 have no internal PHY */
471 if (port > 0 && port < 6)
472 mask |= QCA8K_PORT_STATUS_LINK_AUTO;
473
474 if (enable)
475 qca8k_reg_set(priv, QCA8K_REG_PORT_STATUS(port), mask);
476 else
477 qca8k_reg_clear(priv, QCA8K_REG_PORT_STATUS(port), mask);
478 }
479
480 static int
qca8k_setup(struct dsa_switch * ds)481 qca8k_setup(struct dsa_switch *ds)
482 {
483 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
484 int ret, i, phy_mode = -1;
485 u32 mask;
486
487 /* Make sure that port 0 is the cpu port */
488 if (!dsa_is_cpu_port(ds, 0)) {
489 pr_err("port 0 is not the CPU port\n");
490 return -EINVAL;
491 }
492
493 mutex_init(&priv->reg_mutex);
494
495 /* Start by setting up the register mapping */
496 priv->regmap = devm_regmap_init(ds->dev, NULL, priv,
497 &qca8k_regmap_config);
498 if (IS_ERR(priv->regmap))
499 pr_warn("regmap initialization failed");
500
501 /* Initialize CPU port pad mode (xMII type, delays...) */
502 phy_mode = of_get_phy_mode(ds->ports[QCA8K_CPU_PORT].dn);
503 if (phy_mode < 0) {
504 pr_err("Can't find phy-mode for master device\n");
505 return phy_mode;
506 }
507 ret = qca8k_set_pad_ctrl(priv, QCA8K_CPU_PORT, phy_mode);
508 if (ret < 0)
509 return ret;
510
511 /* Enable CPU Port, force it to maximum bandwidth and full-duplex */
512 mask = QCA8K_PORT_STATUS_SPEED_1000 | QCA8K_PORT_STATUS_TXFLOW |
513 QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_DUPLEX;
514 qca8k_write(priv, QCA8K_REG_PORT_STATUS(QCA8K_CPU_PORT), mask);
515 qca8k_reg_set(priv, QCA8K_REG_GLOBAL_FW_CTRL0,
516 QCA8K_GLOBAL_FW_CTRL0_CPU_PORT_EN);
517 qca8k_port_set_status(priv, QCA8K_CPU_PORT, 1);
518 priv->port_sts[QCA8K_CPU_PORT].enabled = 1;
519
520 /* Enable MIB counters */
521 qca8k_mib_init(priv);
522
523 /* Enable QCA header mode on the cpu port */
524 qca8k_write(priv, QCA8K_REG_PORT_HDR_CTRL(QCA8K_CPU_PORT),
525 QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_TX_S |
526 QCA8K_PORT_HDR_CTRL_ALL << QCA8K_PORT_HDR_CTRL_RX_S);
527
528 /* Disable forwarding by default on all ports */
529 for (i = 0; i < QCA8K_NUM_PORTS; i++)
530 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
531 QCA8K_PORT_LOOKUP_MEMBER, 0);
532
533 /* Disable MAC by default on all user ports */
534 for (i = 1; i < QCA8K_NUM_PORTS; i++)
535 if (dsa_is_user_port(ds, i))
536 qca8k_port_set_status(priv, i, 0);
537
538 /* Forward all unknown frames to CPU port for Linux processing */
539 qca8k_write(priv, QCA8K_REG_GLOBAL_FW_CTRL1,
540 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_IGMP_DP_S |
541 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_BC_DP_S |
542 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_MC_DP_S |
543 BIT(0) << QCA8K_GLOBAL_FW_CTRL1_UC_DP_S);
544
545 /* Setup connection between CPU port & user ports */
546 for (i = 0; i < DSA_MAX_PORTS; i++) {
547 /* CPU port gets connected to all user ports of the switch */
548 if (dsa_is_cpu_port(ds, i)) {
549 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(QCA8K_CPU_PORT),
550 QCA8K_PORT_LOOKUP_MEMBER, dsa_user_ports(ds));
551 }
552
553 /* Invividual user ports get connected to CPU port only */
554 if (dsa_is_user_port(ds, i)) {
555 int shift = 16 * (i % 2);
556
557 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(i),
558 QCA8K_PORT_LOOKUP_MEMBER,
559 BIT(QCA8K_CPU_PORT));
560
561 /* Enable ARP Auto-learning by default */
562 qca8k_reg_set(priv, QCA8K_PORT_LOOKUP_CTRL(i),
563 QCA8K_PORT_LOOKUP_LEARN);
564
565 /* For port based vlans to work we need to set the
566 * default egress vid
567 */
568 qca8k_rmw(priv, QCA8K_EGRESS_VLAN(i),
569 0xffff << shift, 1 << shift);
570 qca8k_write(priv, QCA8K_REG_PORT_VLAN_CTRL0(i),
571 QCA8K_PORT_VLAN_CVID(1) |
572 QCA8K_PORT_VLAN_SVID(1));
573 }
574 }
575
576 /* Flush the FDB table */
577 qca8k_fdb_flush(priv);
578
579 return 0;
580 }
581
582 static void
qca8k_adjust_link(struct dsa_switch * ds,int port,struct phy_device * phy)583 qca8k_adjust_link(struct dsa_switch *ds, int port, struct phy_device *phy)
584 {
585 struct qca8k_priv *priv = ds->priv;
586 u32 reg;
587
588 /* Force fixed-link setting for CPU port, skip others. */
589 if (!phy_is_pseudo_fixed_link(phy))
590 return;
591
592 /* Set port speed */
593 switch (phy->speed) {
594 case 10:
595 reg = QCA8K_PORT_STATUS_SPEED_10;
596 break;
597 case 100:
598 reg = QCA8K_PORT_STATUS_SPEED_100;
599 break;
600 case 1000:
601 reg = QCA8K_PORT_STATUS_SPEED_1000;
602 break;
603 default:
604 dev_dbg(priv->dev, "port%d link speed %dMbps not supported.\n",
605 port, phy->speed);
606 return;
607 }
608
609 /* Set duplex mode */
610 if (phy->duplex == DUPLEX_FULL)
611 reg |= QCA8K_PORT_STATUS_DUPLEX;
612
613 /* Force flow control */
614 if (dsa_is_cpu_port(ds, port))
615 reg |= QCA8K_PORT_STATUS_RXFLOW | QCA8K_PORT_STATUS_TXFLOW;
616
617 /* Force link down before changing MAC options */
618 qca8k_port_set_status(priv, port, 0);
619 qca8k_write(priv, QCA8K_REG_PORT_STATUS(port), reg);
620 qca8k_port_set_status(priv, port, 1);
621 }
622
623 static int
qca8k_phy_read(struct dsa_switch * ds,int phy,int regnum)624 qca8k_phy_read(struct dsa_switch *ds, int phy, int regnum)
625 {
626 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
627
628 return mdiobus_read(priv->bus, phy, regnum);
629 }
630
631 static int
qca8k_phy_write(struct dsa_switch * ds,int phy,int regnum,u16 val)632 qca8k_phy_write(struct dsa_switch *ds, int phy, int regnum, u16 val)
633 {
634 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
635
636 return mdiobus_write(priv->bus, phy, regnum, val);
637 }
638
639 static void
qca8k_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)640 qca8k_get_strings(struct dsa_switch *ds, int port, u32 stringset, uint8_t *data)
641 {
642 int i;
643
644 if (stringset != ETH_SS_STATS)
645 return;
646
647 for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++)
648 strncpy(data + i * ETH_GSTRING_LEN, ar8327_mib[i].name,
649 ETH_GSTRING_LEN);
650 }
651
652 static void
qca8k_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)653 qca8k_get_ethtool_stats(struct dsa_switch *ds, int port,
654 uint64_t *data)
655 {
656 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
657 const struct qca8k_mib_desc *mib;
658 u32 reg, i;
659 u64 hi;
660
661 for (i = 0; i < ARRAY_SIZE(ar8327_mib); i++) {
662 mib = &ar8327_mib[i];
663 reg = QCA8K_PORT_MIB_COUNTER(port) + mib->offset;
664
665 data[i] = qca8k_read(priv, reg);
666 if (mib->size == 2) {
667 hi = qca8k_read(priv, reg + 4);
668 data[i] |= hi << 32;
669 }
670 }
671 }
672
673 static int
qca8k_get_sset_count(struct dsa_switch * ds,int port,int sset)674 qca8k_get_sset_count(struct dsa_switch *ds, int port, int sset)
675 {
676 if (sset != ETH_SS_STATS)
677 return 0;
678
679 return ARRAY_SIZE(ar8327_mib);
680 }
681
682 static int
qca8k_set_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * eee)683 qca8k_set_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *eee)
684 {
685 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
686 u32 lpi_en = QCA8K_REG_EEE_CTRL_LPI_EN(port);
687 u32 reg;
688
689 mutex_lock(&priv->reg_mutex);
690 reg = qca8k_read(priv, QCA8K_REG_EEE_CTRL);
691 if (eee->eee_enabled)
692 reg |= lpi_en;
693 else
694 reg &= ~lpi_en;
695 qca8k_write(priv, QCA8K_REG_EEE_CTRL, reg);
696 mutex_unlock(&priv->reg_mutex);
697
698 return 0;
699 }
700
701 static int
qca8k_get_mac_eee(struct dsa_switch * ds,int port,struct ethtool_eee * e)702 qca8k_get_mac_eee(struct dsa_switch *ds, int port, struct ethtool_eee *e)
703 {
704 /* Nothing to do on the port's MAC */
705 return 0;
706 }
707
708 static void
qca8k_port_stp_state_set(struct dsa_switch * ds,int port,u8 state)709 qca8k_port_stp_state_set(struct dsa_switch *ds, int port, u8 state)
710 {
711 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
712 u32 stp_state;
713
714 switch (state) {
715 case BR_STATE_DISABLED:
716 stp_state = QCA8K_PORT_LOOKUP_STATE_DISABLED;
717 break;
718 case BR_STATE_BLOCKING:
719 stp_state = QCA8K_PORT_LOOKUP_STATE_BLOCKING;
720 break;
721 case BR_STATE_LISTENING:
722 stp_state = QCA8K_PORT_LOOKUP_STATE_LISTENING;
723 break;
724 case BR_STATE_LEARNING:
725 stp_state = QCA8K_PORT_LOOKUP_STATE_LEARNING;
726 break;
727 case BR_STATE_FORWARDING:
728 default:
729 stp_state = QCA8K_PORT_LOOKUP_STATE_FORWARD;
730 break;
731 }
732
733 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
734 QCA8K_PORT_LOOKUP_STATE_MASK, stp_state);
735 }
736
737 static int
qca8k_port_bridge_join(struct dsa_switch * ds,int port,struct net_device * br)738 qca8k_port_bridge_join(struct dsa_switch *ds, int port, struct net_device *br)
739 {
740 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
741 int port_mask = BIT(QCA8K_CPU_PORT);
742 int i;
743
744 for (i = 1; i < QCA8K_NUM_PORTS; i++) {
745 if (dsa_to_port(ds, i)->bridge_dev != br)
746 continue;
747 /* Add this port to the portvlan mask of the other ports
748 * in the bridge
749 */
750 qca8k_reg_set(priv,
751 QCA8K_PORT_LOOKUP_CTRL(i),
752 BIT(port));
753 if (i != port)
754 port_mask |= BIT(i);
755 }
756 /* Add all other ports to this ports portvlan mask */
757 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
758 QCA8K_PORT_LOOKUP_MEMBER, port_mask);
759
760 return 0;
761 }
762
763 static void
qca8k_port_bridge_leave(struct dsa_switch * ds,int port,struct net_device * br)764 qca8k_port_bridge_leave(struct dsa_switch *ds, int port, struct net_device *br)
765 {
766 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
767 int i;
768
769 for (i = 1; i < QCA8K_NUM_PORTS; i++) {
770 if (dsa_to_port(ds, i)->bridge_dev != br)
771 continue;
772 /* Remove this port to the portvlan mask of the other ports
773 * in the bridge
774 */
775 qca8k_reg_clear(priv,
776 QCA8K_PORT_LOOKUP_CTRL(i),
777 BIT(port));
778 }
779
780 /* Set the cpu port to be the only one in the portvlan mask of
781 * this port
782 */
783 qca8k_rmw(priv, QCA8K_PORT_LOOKUP_CTRL(port),
784 QCA8K_PORT_LOOKUP_MEMBER, BIT(QCA8K_CPU_PORT));
785 }
786
787 static int
qca8k_port_enable(struct dsa_switch * ds,int port,struct phy_device * phy)788 qca8k_port_enable(struct dsa_switch *ds, int port,
789 struct phy_device *phy)
790 {
791 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
792
793 qca8k_port_set_status(priv, port, 1);
794 priv->port_sts[port].enabled = 1;
795
796 return 0;
797 }
798
799 static void
qca8k_port_disable(struct dsa_switch * ds,int port,struct phy_device * phy)800 qca8k_port_disable(struct dsa_switch *ds, int port,
801 struct phy_device *phy)
802 {
803 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
804
805 qca8k_port_set_status(priv, port, 0);
806 priv->port_sts[port].enabled = 0;
807 }
808
809 static int
qca8k_port_fdb_insert(struct qca8k_priv * priv,const u8 * addr,u16 port_mask,u16 vid)810 qca8k_port_fdb_insert(struct qca8k_priv *priv, const u8 *addr,
811 u16 port_mask, u16 vid)
812 {
813 /* Set the vid to the port vlan id if no vid is set */
814 if (!vid)
815 vid = 1;
816
817 return qca8k_fdb_add(priv, addr, port_mask, vid,
818 QCA8K_ATU_STATUS_STATIC);
819 }
820
821 static int
qca8k_port_fdb_add(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid)822 qca8k_port_fdb_add(struct dsa_switch *ds, int port,
823 const unsigned char *addr, u16 vid)
824 {
825 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
826 u16 port_mask = BIT(port);
827
828 return qca8k_port_fdb_insert(priv, addr, port_mask, vid);
829 }
830
831 static int
qca8k_port_fdb_del(struct dsa_switch * ds,int port,const unsigned char * addr,u16 vid)832 qca8k_port_fdb_del(struct dsa_switch *ds, int port,
833 const unsigned char *addr, u16 vid)
834 {
835 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
836 u16 port_mask = BIT(port);
837
838 if (!vid)
839 vid = 1;
840
841 return qca8k_fdb_del(priv, addr, port_mask, vid);
842 }
843
844 static int
qca8k_port_fdb_dump(struct dsa_switch * ds,int port,dsa_fdb_dump_cb_t * cb,void * data)845 qca8k_port_fdb_dump(struct dsa_switch *ds, int port,
846 dsa_fdb_dump_cb_t *cb, void *data)
847 {
848 struct qca8k_priv *priv = (struct qca8k_priv *)ds->priv;
849 struct qca8k_fdb _fdb = { 0 };
850 int cnt = QCA8K_NUM_FDB_RECORDS;
851 bool is_static;
852 int ret = 0;
853
854 mutex_lock(&priv->reg_mutex);
855 while (cnt-- && !qca8k_fdb_next(priv, &_fdb, port)) {
856 if (!_fdb.aging)
857 break;
858 is_static = (_fdb.aging == QCA8K_ATU_STATUS_STATIC);
859 ret = cb(_fdb.mac, _fdb.vid, is_static, data);
860 if (ret)
861 break;
862 }
863 mutex_unlock(&priv->reg_mutex);
864
865 return 0;
866 }
867
868 static enum dsa_tag_protocol
qca8k_get_tag_protocol(struct dsa_switch * ds,int port)869 qca8k_get_tag_protocol(struct dsa_switch *ds, int port)
870 {
871 return DSA_TAG_PROTO_QCA;
872 }
873
874 static const struct dsa_switch_ops qca8k_switch_ops = {
875 .get_tag_protocol = qca8k_get_tag_protocol,
876 .setup = qca8k_setup,
877 .adjust_link = qca8k_adjust_link,
878 .get_strings = qca8k_get_strings,
879 .phy_read = qca8k_phy_read,
880 .phy_write = qca8k_phy_write,
881 .get_ethtool_stats = qca8k_get_ethtool_stats,
882 .get_sset_count = qca8k_get_sset_count,
883 .get_mac_eee = qca8k_get_mac_eee,
884 .set_mac_eee = qca8k_set_mac_eee,
885 .port_enable = qca8k_port_enable,
886 .port_disable = qca8k_port_disable,
887 .port_stp_state_set = qca8k_port_stp_state_set,
888 .port_bridge_join = qca8k_port_bridge_join,
889 .port_bridge_leave = qca8k_port_bridge_leave,
890 .port_fdb_add = qca8k_port_fdb_add,
891 .port_fdb_del = qca8k_port_fdb_del,
892 .port_fdb_dump = qca8k_port_fdb_dump,
893 };
894
895 static int
qca8k_sw_probe(struct mdio_device * mdiodev)896 qca8k_sw_probe(struct mdio_device *mdiodev)
897 {
898 struct qca8k_priv *priv;
899 u32 id;
900
901 /* allocate the private data struct so that we can probe the switches
902 * ID register
903 */
904 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL);
905 if (!priv)
906 return -ENOMEM;
907
908 priv->bus = mdiodev->bus;
909 priv->dev = &mdiodev->dev;
910
911 /* read the switches ID register */
912 id = qca8k_read(priv, QCA8K_REG_MASK_CTRL);
913 id >>= QCA8K_MASK_CTRL_ID_S;
914 id &= QCA8K_MASK_CTRL_ID_M;
915 if (id != QCA8K_ID_QCA8337)
916 return -ENODEV;
917
918 priv->ds = dsa_switch_alloc(&mdiodev->dev, DSA_MAX_PORTS);
919 if (!priv->ds)
920 return -ENOMEM;
921
922 priv->ds->priv = priv;
923 priv->ds->ops = &qca8k_switch_ops;
924 mutex_init(&priv->reg_mutex);
925 dev_set_drvdata(&mdiodev->dev, priv);
926
927 return dsa_register_switch(priv->ds);
928 }
929
930 static void
qca8k_sw_remove(struct mdio_device * mdiodev)931 qca8k_sw_remove(struct mdio_device *mdiodev)
932 {
933 struct qca8k_priv *priv = dev_get_drvdata(&mdiodev->dev);
934 int i;
935
936 for (i = 0; i < QCA8K_NUM_PORTS; i++)
937 qca8k_port_set_status(priv, i, 0);
938
939 dsa_unregister_switch(priv->ds);
940 }
941
942 #ifdef CONFIG_PM_SLEEP
943 static void
qca8k_set_pm(struct qca8k_priv * priv,int enable)944 qca8k_set_pm(struct qca8k_priv *priv, int enable)
945 {
946 int i;
947
948 for (i = 0; i < QCA8K_NUM_PORTS; i++) {
949 if (!priv->port_sts[i].enabled)
950 continue;
951
952 qca8k_port_set_status(priv, i, enable);
953 }
954 }
955
qca8k_suspend(struct device * dev)956 static int qca8k_suspend(struct device *dev)
957 {
958 struct platform_device *pdev = to_platform_device(dev);
959 struct qca8k_priv *priv = platform_get_drvdata(pdev);
960
961 qca8k_set_pm(priv, 0);
962
963 return dsa_switch_suspend(priv->ds);
964 }
965
qca8k_resume(struct device * dev)966 static int qca8k_resume(struct device *dev)
967 {
968 struct platform_device *pdev = to_platform_device(dev);
969 struct qca8k_priv *priv = platform_get_drvdata(pdev);
970
971 qca8k_set_pm(priv, 1);
972
973 return dsa_switch_resume(priv->ds);
974 }
975 #endif /* CONFIG_PM_SLEEP */
976
977 static SIMPLE_DEV_PM_OPS(qca8k_pm_ops,
978 qca8k_suspend, qca8k_resume);
979
980 static const struct of_device_id qca8k_of_match[] = {
981 { .compatible = "qca,qca8334" },
982 { .compatible = "qca,qca8337" },
983 { /* sentinel */ },
984 };
985
986 static struct mdio_driver qca8kmdio_driver = {
987 .probe = qca8k_sw_probe,
988 .remove = qca8k_sw_remove,
989 .mdiodrv.driver = {
990 .name = "qca8k",
991 .of_match_table = qca8k_of_match,
992 .pm = &qca8k_pm_ops,
993 },
994 };
995
996 mdio_module_driver(qca8kmdio_driver);
997
998 MODULE_AUTHOR("Mathieu Olivari, John Crispin <john@phrozen.org>");
999 MODULE_DESCRIPTION("Driver for QCA8K ethernet switch family");
1000 MODULE_LICENSE("GPL v2");
1001 MODULE_ALIAS("platform:qca8k");
1002
