1 /*
2 * Broadcom Starfighter 2 DSA switch driver
3 *
4 * Copyright (C) 2014, Broadcom Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 */
11
12 #include <linux/list.h>
13 #include <linux/module.h>
14 #include <linux/netdevice.h>
15 #include <linux/interrupt.h>
16 #include <linux/platform_device.h>
17 #include <linux/phy.h>
18 #include <linux/phy_fixed.h>
19 #include <linux/phylink.h>
20 #include <linux/mii.h>
21 #include <linux/of.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_address.h>
24 #include <linux/of_net.h>
25 #include <linux/of_mdio.h>
26 #include <net/dsa.h>
27 #include <linux/ethtool.h>
28 #include <linux/if_bridge.h>
29 #include <linux/brcmphy.h>
30 #include <linux/etherdevice.h>
31 #include <linux/platform_data/b53.h>
32
33 #include "bcm_sf2.h"
34 #include "bcm_sf2_regs.h"
35 #include "b53/b53_priv.h"
36 #include "b53/b53_regs.h"
37
bcm_sf2_imp_setup(struct dsa_switch * ds,int port)38 static void bcm_sf2_imp_setup(struct dsa_switch *ds, int port)
39 {
40 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
41 unsigned int i;
42 u32 reg, offset;
43
44 if (priv->type == BCM7445_DEVICE_ID)
45 offset = CORE_STS_OVERRIDE_IMP;
46 else
47 offset = CORE_STS_OVERRIDE_IMP2;
48
49 /* Enable the port memories */
50 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
51 reg &= ~P_TXQ_PSM_VDD(port);
52 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
53
54 /* Enable Broadcast, Multicast, Unicast forwarding to IMP port */
55 reg = core_readl(priv, CORE_IMP_CTL);
56 reg |= (RX_BCST_EN | RX_MCST_EN | RX_UCST_EN);
57 reg &= ~(RX_DIS | TX_DIS);
58 core_writel(priv, reg, CORE_IMP_CTL);
59
60 /* Enable forwarding */
61 core_writel(priv, SW_FWDG_EN, CORE_SWMODE);
62
63 /* Enable IMP port in dumb mode */
64 reg = core_readl(priv, CORE_SWITCH_CTRL);
65 reg |= MII_DUMB_FWDG_EN;
66 core_writel(priv, reg, CORE_SWITCH_CTRL);
67
68 /* Configure Traffic Class to QoS mapping, allow each priority to map
69 * to a different queue number
70 */
71 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
72 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
73 reg |= i << (PRT_TO_QID_SHIFT * i);
74 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
75
76 b53_brcm_hdr_setup(ds, port);
77
78 /* Force link status for IMP port */
79 reg = core_readl(priv, offset);
80 reg |= (MII_SW_OR | LINK_STS);
81 core_writel(priv, reg, offset);
82 }
83
bcm_sf2_gphy_enable_set(struct dsa_switch * ds,bool enable)84 static void bcm_sf2_gphy_enable_set(struct dsa_switch *ds, bool enable)
85 {
86 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
87 u32 reg;
88
89 reg = reg_readl(priv, REG_SPHY_CNTRL);
90 if (enable) {
91 reg |= PHY_RESET;
92 reg &= ~(EXT_PWR_DOWN | IDDQ_BIAS | IDDQ_GLOBAL_PWR | CK25_DIS);
93 reg_writel(priv, reg, REG_SPHY_CNTRL);
94 udelay(21);
95 reg = reg_readl(priv, REG_SPHY_CNTRL);
96 reg &= ~PHY_RESET;
97 } else {
98 reg |= EXT_PWR_DOWN | IDDQ_BIAS | PHY_RESET;
99 reg_writel(priv, reg, REG_SPHY_CNTRL);
100 mdelay(1);
101 reg |= CK25_DIS;
102 }
103 reg_writel(priv, reg, REG_SPHY_CNTRL);
104
105 /* Use PHY-driven LED signaling */
106 if (!enable) {
107 reg = reg_readl(priv, REG_LED_CNTRL(0));
108 reg |= SPDLNK_SRC_SEL;
109 reg_writel(priv, reg, REG_LED_CNTRL(0));
110 }
111 }
112
bcm_sf2_port_intr_enable(struct bcm_sf2_priv * priv,int port)113 static inline void bcm_sf2_port_intr_enable(struct bcm_sf2_priv *priv,
114 int port)
115 {
116 unsigned int off;
117
118 switch (port) {
119 case 7:
120 off = P7_IRQ_OFF;
121 break;
122 case 0:
123 /* Port 0 interrupts are located on the first bank */
124 intrl2_0_mask_clear(priv, P_IRQ_MASK(P0_IRQ_OFF));
125 return;
126 default:
127 off = P_IRQ_OFF(port);
128 break;
129 }
130
131 intrl2_1_mask_clear(priv, P_IRQ_MASK(off));
132 }
133
bcm_sf2_port_intr_disable(struct bcm_sf2_priv * priv,int port)134 static inline void bcm_sf2_port_intr_disable(struct bcm_sf2_priv *priv,
135 int port)
136 {
137 unsigned int off;
138
139 switch (port) {
140 case 7:
141 off = P7_IRQ_OFF;
142 break;
143 case 0:
144 /* Port 0 interrupts are located on the first bank */
145 intrl2_0_mask_set(priv, P_IRQ_MASK(P0_IRQ_OFF));
146 intrl2_0_writel(priv, P_IRQ_MASK(P0_IRQ_OFF), INTRL2_CPU_CLEAR);
147 return;
148 default:
149 off = P_IRQ_OFF(port);
150 break;
151 }
152
153 intrl2_1_mask_set(priv, P_IRQ_MASK(off));
154 intrl2_1_writel(priv, P_IRQ_MASK(off), INTRL2_CPU_CLEAR);
155 }
156
bcm_sf2_port_setup(struct dsa_switch * ds,int port,struct phy_device * phy)157 static int bcm_sf2_port_setup(struct dsa_switch *ds, int port,
158 struct phy_device *phy)
159 {
160 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
161 unsigned int i;
162 u32 reg;
163
164 /* Clear the memory power down */
165 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
166 reg &= ~P_TXQ_PSM_VDD(port);
167 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
168
169 /* Enable learning */
170 reg = core_readl(priv, CORE_DIS_LEARN);
171 reg &= ~BIT(port);
172 core_writel(priv, reg, CORE_DIS_LEARN);
173
174 /* Enable Broadcom tags for that port if requested */
175 if (priv->brcm_tag_mask & BIT(port))
176 b53_brcm_hdr_setup(ds, port);
177
178 /* Configure Traffic Class to QoS mapping, allow each priority to map
179 * to a different queue number
180 */
181 reg = core_readl(priv, CORE_PORT_TC2_QOS_MAP_PORT(port));
182 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++)
183 reg |= i << (PRT_TO_QID_SHIFT * i);
184 core_writel(priv, reg, CORE_PORT_TC2_QOS_MAP_PORT(port));
185
186 /* Re-enable the GPHY and re-apply workarounds */
187 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1) {
188 bcm_sf2_gphy_enable_set(ds, true);
189 if (phy) {
190 /* if phy_stop() has been called before, phy
191 * will be in halted state, and phy_start()
192 * will call resume.
193 *
194 * the resume path does not configure back
195 * autoneg settings, and since we hard reset
196 * the phy manually here, we need to reset the
197 * state machine also.
198 */
199 phy->state = PHY_READY;
200 phy_init_hw(phy);
201 }
202 }
203
204 /* Enable MoCA port interrupts to get notified */
205 if (port == priv->moca_port)
206 bcm_sf2_port_intr_enable(priv, port);
207
208 /* Set per-queue pause threshold to 32 */
209 core_writel(priv, 32, CORE_TXQ_THD_PAUSE_QN_PORT(port));
210
211 /* Set ACB threshold to 24 */
212 for (i = 0; i < SF2_NUM_EGRESS_QUEUES; i++) {
213 reg = acb_readl(priv, ACB_QUEUE_CFG(port *
214 SF2_NUM_EGRESS_QUEUES + i));
215 reg &= ~XOFF_THRESHOLD_MASK;
216 reg |= 24;
217 acb_writel(priv, reg, ACB_QUEUE_CFG(port *
218 SF2_NUM_EGRESS_QUEUES + i));
219 }
220
221 return b53_enable_port(ds, port, phy);
222 }
223
bcm_sf2_port_disable(struct dsa_switch * ds,int port,struct phy_device * phy)224 static void bcm_sf2_port_disable(struct dsa_switch *ds, int port,
225 struct phy_device *phy)
226 {
227 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
228 u32 reg;
229
230 /* Disable learning while in WoL mode */
231 if (priv->wol_ports_mask & (1 << port)) {
232 reg = core_readl(priv, CORE_DIS_LEARN);
233 reg |= BIT(port);
234 core_writel(priv, reg, CORE_DIS_LEARN);
235 return;
236 }
237
238 if (port == priv->moca_port)
239 bcm_sf2_port_intr_disable(priv, port);
240
241 if (priv->int_phy_mask & 1 << port && priv->hw_params.num_gphy == 1)
242 bcm_sf2_gphy_enable_set(ds, false);
243
244 b53_disable_port(ds, port, phy);
245
246 /* Power down the port memory */
247 reg = core_readl(priv, CORE_MEM_PSM_VDD_CTRL);
248 reg |= P_TXQ_PSM_VDD(port);
249 core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
250 }
251
252
bcm_sf2_sw_indir_rw(struct bcm_sf2_priv * priv,int op,int addr,int regnum,u16 val)253 static int bcm_sf2_sw_indir_rw(struct bcm_sf2_priv *priv, int op, int addr,
254 int regnum, u16 val)
255 {
256 int ret = 0;
257 u32 reg;
258
259 reg = reg_readl(priv, REG_SWITCH_CNTRL);
260 reg |= MDIO_MASTER_SEL;
261 reg_writel(priv, reg, REG_SWITCH_CNTRL);
262
263 /* Page << 8 | offset */
264 reg = 0x70;
265 reg <<= 2;
266 core_writel(priv, addr, reg);
267
268 /* Page << 8 | offset */
269 reg = 0x80 << 8 | regnum << 1;
270 reg <<= 2;
271
272 if (op)
273 ret = core_readl(priv, reg);
274 else
275 core_writel(priv, val, reg);
276
277 reg = reg_readl(priv, REG_SWITCH_CNTRL);
278 reg &= ~MDIO_MASTER_SEL;
279 reg_writel(priv, reg, REG_SWITCH_CNTRL);
280
281 return ret & 0xffff;
282 }
283
bcm_sf2_sw_mdio_read(struct mii_bus * bus,int addr,int regnum)284 static int bcm_sf2_sw_mdio_read(struct mii_bus *bus, int addr, int regnum)
285 {
286 struct bcm_sf2_priv *priv = bus->priv;
287
288 /* Intercept reads from Broadcom pseudo-PHY address, else, send
289 * them to our master MDIO bus controller
290 */
291 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
292 return bcm_sf2_sw_indir_rw(priv, 1, addr, regnum, 0);
293 else
294 return mdiobus_read_nested(priv->master_mii_bus, addr, regnum);
295 }
296
bcm_sf2_sw_mdio_write(struct mii_bus * bus,int addr,int regnum,u16 val)297 static int bcm_sf2_sw_mdio_write(struct mii_bus *bus, int addr, int regnum,
298 u16 val)
299 {
300 struct bcm_sf2_priv *priv = bus->priv;
301
302 /* Intercept writes to the Broadcom pseudo-PHY address, else,
303 * send them to our master MDIO bus controller
304 */
305 if (addr == BRCM_PSEUDO_PHY_ADDR && priv->indir_phy_mask & BIT(addr))
306 bcm_sf2_sw_indir_rw(priv, 0, addr, regnum, val);
307 else
308 mdiobus_write_nested(priv->master_mii_bus, addr, regnum, val);
309
310 return 0;
311 }
312
bcm_sf2_switch_0_isr(int irq,void * dev_id)313 static irqreturn_t bcm_sf2_switch_0_isr(int irq, void *dev_id)
314 {
315 struct dsa_switch *ds = dev_id;
316 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
317
318 priv->irq0_stat = intrl2_0_readl(priv, INTRL2_CPU_STATUS) &
319 ~priv->irq0_mask;
320 intrl2_0_writel(priv, priv->irq0_stat, INTRL2_CPU_CLEAR);
321
322 return IRQ_HANDLED;
323 }
324
bcm_sf2_switch_1_isr(int irq,void * dev_id)325 static irqreturn_t bcm_sf2_switch_1_isr(int irq, void *dev_id)
326 {
327 struct dsa_switch *ds = dev_id;
328 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
329
330 priv->irq1_stat = intrl2_1_readl(priv, INTRL2_CPU_STATUS) &
331 ~priv->irq1_mask;
332 intrl2_1_writel(priv, priv->irq1_stat, INTRL2_CPU_CLEAR);
333
334 if (priv->irq1_stat & P_LINK_UP_IRQ(P7_IRQ_OFF)) {
335 priv->port_sts[7].link = true;
336 dsa_port_phylink_mac_change(ds, 7, true);
337 }
338 if (priv->irq1_stat & P_LINK_DOWN_IRQ(P7_IRQ_OFF)) {
339 priv->port_sts[7].link = false;
340 dsa_port_phylink_mac_change(ds, 7, false);
341 }
342
343 return IRQ_HANDLED;
344 }
345
bcm_sf2_sw_rst(struct bcm_sf2_priv * priv)346 static int bcm_sf2_sw_rst(struct bcm_sf2_priv *priv)
347 {
348 unsigned int timeout = 1000;
349 u32 reg;
350
351 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
352 reg |= SOFTWARE_RESET | EN_CHIP_RST | EN_SW_RESET;
353 core_writel(priv, reg, CORE_WATCHDOG_CTRL);
354
355 do {
356 reg = core_readl(priv, CORE_WATCHDOG_CTRL);
357 if (!(reg & SOFTWARE_RESET))
358 break;
359
360 usleep_range(1000, 2000);
361 } while (timeout-- > 0);
362
363 if (timeout == 0)
364 return -ETIMEDOUT;
365
366 return 0;
367 }
368
bcm_sf2_intr_disable(struct bcm_sf2_priv * priv)369 static void bcm_sf2_intr_disable(struct bcm_sf2_priv *priv)
370 {
371 intrl2_0_mask_set(priv, 0xffffffff);
372 intrl2_0_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
373 intrl2_1_mask_set(priv, 0xffffffff);
374 intrl2_1_writel(priv, 0xffffffff, INTRL2_CPU_CLEAR);
375 }
376
bcm_sf2_identify_ports(struct bcm_sf2_priv * priv,struct device_node * dn)377 static void bcm_sf2_identify_ports(struct bcm_sf2_priv *priv,
378 struct device_node *dn)
379 {
380 struct device_node *port;
381 int mode;
382 unsigned int port_num;
383
384 priv->moca_port = -1;
385
386 for_each_available_child_of_node(dn, port) {
387 if (of_property_read_u32(port, "reg", &port_num))
388 continue;
389
390 /* Internal PHYs get assigned a specific 'phy-mode' property
391 * value: "internal" to help flag them before MDIO probing
392 * has completed, since they might be turned off at that
393 * time
394 */
395 mode = of_get_phy_mode(port);
396 if (mode < 0)
397 continue;
398
399 if (mode == PHY_INTERFACE_MODE_INTERNAL)
400 priv->int_phy_mask |= 1 << port_num;
401
402 if (mode == PHY_INTERFACE_MODE_MOCA)
403 priv->moca_port = port_num;
404
405 if (of_property_read_bool(port, "brcm,use-bcm-hdr"))
406 priv->brcm_tag_mask |= 1 << port_num;
407 }
408 }
409
bcm_sf2_mdio_register(struct dsa_switch * ds)410 static int bcm_sf2_mdio_register(struct dsa_switch *ds)
411 {
412 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
413 struct device_node *dn;
414 static int index;
415 int err;
416
417 /* Find our integrated MDIO bus node */
418 dn = of_find_compatible_node(NULL, NULL, "brcm,unimac-mdio");
419 priv->master_mii_bus = of_mdio_find_bus(dn);
420 if (!priv->master_mii_bus)
421 return -EPROBE_DEFER;
422
423 get_device(&priv->master_mii_bus->dev);
424 priv->master_mii_dn = dn;
425
426 priv->slave_mii_bus = devm_mdiobus_alloc(ds->dev);
427 if (!priv->slave_mii_bus)
428 return -ENOMEM;
429
430 priv->slave_mii_bus->priv = priv;
431 priv->slave_mii_bus->name = "sf2 slave mii";
432 priv->slave_mii_bus->read = bcm_sf2_sw_mdio_read;
433 priv->slave_mii_bus->write = bcm_sf2_sw_mdio_write;
434 snprintf(priv->slave_mii_bus->id, MII_BUS_ID_SIZE, "sf2-%d",
435 index++);
436 priv->slave_mii_bus->dev.of_node = dn;
437
438 /* Include the pseudo-PHY address to divert reads towards our
439 * workaround. This is only required for 7445D0, since 7445E0
440 * disconnects the internal switch pseudo-PHY such that we can use the
441 * regular SWITCH_MDIO master controller instead.
442 *
443 * Here we flag the pseudo PHY as needing special treatment and would
444 * otherwise make all other PHY read/writes go to the master MDIO bus
445 * controller that comes with this switch backed by the "mdio-unimac"
446 * driver.
447 */
448 if (of_machine_is_compatible("brcm,bcm7445d0"))
449 priv->indir_phy_mask |= (1 << BRCM_PSEUDO_PHY_ADDR);
450 else
451 priv->indir_phy_mask = 0;
452
453 ds->phys_mii_mask = priv->indir_phy_mask;
454 ds->slave_mii_bus = priv->slave_mii_bus;
455 priv->slave_mii_bus->parent = ds->dev->parent;
456 priv->slave_mii_bus->phy_mask = ~priv->indir_phy_mask;
457
458 err = of_mdiobus_register(priv->slave_mii_bus, dn);
459 if (err && dn)
460 of_node_put(dn);
461
462 return err;
463 }
464
bcm_sf2_mdio_unregister(struct bcm_sf2_priv * priv)465 static void bcm_sf2_mdio_unregister(struct bcm_sf2_priv *priv)
466 {
467 mdiobus_unregister(priv->slave_mii_bus);
468 if (priv->master_mii_dn)
469 of_node_put(priv->master_mii_dn);
470 }
471
bcm_sf2_sw_get_phy_flags(struct dsa_switch * ds,int port)472 static u32 bcm_sf2_sw_get_phy_flags(struct dsa_switch *ds, int port)
473 {
474 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
475
476 /* The BCM7xxx PHY driver expects to find the integrated PHY revision
477 * in bits 15:8 and the patch level in bits 7:0 which is exactly what
478 * the REG_PHY_REVISION register layout is.
479 */
480
481 return priv->hw_params.gphy_rev;
482 }
483
bcm_sf2_sw_validate(struct dsa_switch * ds,int port,unsigned long * supported,struct phylink_link_state * state)484 static void bcm_sf2_sw_validate(struct dsa_switch *ds, int port,
485 unsigned long *supported,
486 struct phylink_link_state *state)
487 {
488 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
489
490 if (!phy_interface_mode_is_rgmii(state->interface) &&
491 state->interface != PHY_INTERFACE_MODE_MII &&
492 state->interface != PHY_INTERFACE_MODE_REVMII &&
493 state->interface != PHY_INTERFACE_MODE_GMII &&
494 state->interface != PHY_INTERFACE_MODE_INTERNAL &&
495 state->interface != PHY_INTERFACE_MODE_MOCA) {
496 bitmap_zero(supported, __ETHTOOL_LINK_MODE_MASK_NBITS);
497 dev_err(ds->dev,
498 "Unsupported interface: %d\n", state->interface);
499 return;
500 }
501
502 /* Allow all the expected bits */
503 phylink_set(mask, Autoneg);
504 phylink_set_port_modes(mask);
505 phylink_set(mask, Pause);
506 phylink_set(mask, Asym_Pause);
507
508 /* With the exclusion of MII and Reverse MII, we support Gigabit,
509 * including Half duplex
510 */
511 if (state->interface != PHY_INTERFACE_MODE_MII &&
512 state->interface != PHY_INTERFACE_MODE_REVMII) {
513 phylink_set(mask, 1000baseT_Full);
514 phylink_set(mask, 1000baseT_Half);
515 }
516
517 phylink_set(mask, 10baseT_Half);
518 phylink_set(mask, 10baseT_Full);
519 phylink_set(mask, 100baseT_Half);
520 phylink_set(mask, 100baseT_Full);
521
522 bitmap_and(supported, supported, mask,
523 __ETHTOOL_LINK_MODE_MASK_NBITS);
524 bitmap_and(state->advertising, state->advertising, mask,
525 __ETHTOOL_LINK_MODE_MASK_NBITS);
526 }
527
bcm_sf2_sw_mac_config(struct dsa_switch * ds,int port,unsigned int mode,const struct phylink_link_state * state)528 static void bcm_sf2_sw_mac_config(struct dsa_switch *ds, int port,
529 unsigned int mode,
530 const struct phylink_link_state *state)
531 {
532 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
533 u32 id_mode_dis = 0, port_mode;
534 u32 reg, offset;
535
536 if (priv->type == BCM7445_DEVICE_ID)
537 offset = CORE_STS_OVERRIDE_GMIIP_PORT(port);
538 else
539 offset = CORE_STS_OVERRIDE_GMIIP2_PORT(port);
540
541 switch (state->interface) {
542 case PHY_INTERFACE_MODE_RGMII:
543 id_mode_dis = 1;
544 /* fallthrough */
545 case PHY_INTERFACE_MODE_RGMII_TXID:
546 port_mode = EXT_GPHY;
547 break;
548 case PHY_INTERFACE_MODE_MII:
549 port_mode = EXT_EPHY;
550 break;
551 case PHY_INTERFACE_MODE_REVMII:
552 port_mode = EXT_REVMII;
553 break;
554 default:
555 /* all other PHYs: internal and MoCA */
556 goto force_link;
557 }
558
559 /* Clear id_mode_dis bit, and the existing port mode, let
560 * RGMII_MODE_EN bet set by mac_link_{up,down}
561 */
562 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
563 reg &= ~ID_MODE_DIS;
564 reg &= ~(PORT_MODE_MASK << PORT_MODE_SHIFT);
565 reg &= ~(RX_PAUSE_EN | TX_PAUSE_EN);
566
567 reg |= port_mode;
568 if (id_mode_dis)
569 reg |= ID_MODE_DIS;
570
571 if (state->pause & MLO_PAUSE_TXRX_MASK) {
572 if (state->pause & MLO_PAUSE_TX)
573 reg |= TX_PAUSE_EN;
574 reg |= RX_PAUSE_EN;
575 }
576
577 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
578
579 force_link:
580 /* Force link settings detected from the PHY */
581 reg = SW_OVERRIDE;
582 switch (state->speed) {
583 case SPEED_1000:
584 reg |= SPDSTS_1000 << SPEED_SHIFT;
585 break;
586 case SPEED_100:
587 reg |= SPDSTS_100 << SPEED_SHIFT;
588 break;
589 }
590
591 if (state->link)
592 reg |= LINK_STS;
593 if (state->duplex == DUPLEX_FULL)
594 reg |= DUPLX_MODE;
595
596 core_writel(priv, reg, offset);
597 }
598
bcm_sf2_sw_mac_link_set(struct dsa_switch * ds,int port,phy_interface_t interface,bool link)599 static void bcm_sf2_sw_mac_link_set(struct dsa_switch *ds, int port,
600 phy_interface_t interface, bool link)
601 {
602 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
603 u32 reg;
604
605 if (!phy_interface_mode_is_rgmii(interface) &&
606 interface != PHY_INTERFACE_MODE_MII &&
607 interface != PHY_INTERFACE_MODE_REVMII)
608 return;
609
610 /* If the link is down, just disable the interface to conserve power */
611 reg = reg_readl(priv, REG_RGMII_CNTRL_P(port));
612 if (link)
613 reg |= RGMII_MODE_EN;
614 else
615 reg &= ~RGMII_MODE_EN;
616 reg_writel(priv, reg, REG_RGMII_CNTRL_P(port));
617 }
618
bcm_sf2_sw_mac_link_down(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface)619 static void bcm_sf2_sw_mac_link_down(struct dsa_switch *ds, int port,
620 unsigned int mode,
621 phy_interface_t interface)
622 {
623 bcm_sf2_sw_mac_link_set(ds, port, interface, false);
624 }
625
bcm_sf2_sw_mac_link_up(struct dsa_switch * ds,int port,unsigned int mode,phy_interface_t interface,struct phy_device * phydev)626 static void bcm_sf2_sw_mac_link_up(struct dsa_switch *ds, int port,
627 unsigned int mode,
628 phy_interface_t interface,
629 struct phy_device *phydev)
630 {
631 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
632 struct ethtool_eee *p = &priv->dev->ports[port].eee;
633
634 bcm_sf2_sw_mac_link_set(ds, port, interface, true);
635
636 if (mode == MLO_AN_PHY && phydev)
637 p->eee_enabled = b53_eee_init(ds, port, phydev);
638 }
639
bcm_sf2_sw_fixed_state(struct dsa_switch * ds,int port,struct phylink_link_state * status)640 static void bcm_sf2_sw_fixed_state(struct dsa_switch *ds, int port,
641 struct phylink_link_state *status)
642 {
643 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
644
645 status->link = false;
646
647 /* MoCA port is special as we do not get link status from CORE_LNKSTS,
648 * which means that we need to force the link at the port override
649 * level to get the data to flow. We do use what the interrupt handler
650 * did determine before.
651 *
652 * For the other ports, we just force the link status, since this is
653 * a fixed PHY device.
654 */
655 if (port == priv->moca_port) {
656 status->link = priv->port_sts[port].link;
657 /* For MoCA interfaces, also force a link down notification
658 * since some version of the user-space daemon (mocad) use
659 * cmd->autoneg to force the link, which messes up the PHY
660 * state machine and make it go in PHY_FORCING state instead.
661 */
662 if (!status->link)
663 netif_carrier_off(ds->ports[port].slave);
664 status->duplex = DUPLEX_FULL;
665 } else {
666 status->link = true;
667 }
668 }
669
bcm_sf2_enable_acb(struct dsa_switch * ds)670 static void bcm_sf2_enable_acb(struct dsa_switch *ds)
671 {
672 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
673 u32 reg;
674
675 /* Enable ACB globally */
676 reg = acb_readl(priv, ACB_CONTROL);
677 reg |= (ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
678 acb_writel(priv, reg, ACB_CONTROL);
679 reg &= ~(ACB_FLUSH_MASK << ACB_FLUSH_SHIFT);
680 reg |= ACB_EN | ACB_ALGORITHM;
681 acb_writel(priv, reg, ACB_CONTROL);
682 }
683
bcm_sf2_sw_suspend(struct dsa_switch * ds)684 static int bcm_sf2_sw_suspend(struct dsa_switch *ds)
685 {
686 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
687 unsigned int port;
688
689 bcm_sf2_intr_disable(priv);
690
691 /* Disable all ports physically present including the IMP
692 * port, the other ones have already been disabled during
693 * bcm_sf2_sw_setup
694 */
695 for (port = 0; port < DSA_MAX_PORTS; port++) {
696 if (dsa_is_user_port(ds, port) || dsa_is_cpu_port(ds, port))
697 bcm_sf2_port_disable(ds, port, NULL);
698 }
699
700 return 0;
701 }
702
bcm_sf2_sw_resume(struct dsa_switch * ds)703 static int bcm_sf2_sw_resume(struct dsa_switch *ds)
704 {
705 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
706 int ret;
707
708 ret = bcm_sf2_sw_rst(priv);
709 if (ret) {
710 pr_err("%s: failed to software reset switch\n", __func__);
711 return ret;
712 }
713
714 if (priv->hw_params.num_gphy == 1)
715 bcm_sf2_gphy_enable_set(ds, true);
716
717 ds->ops->setup(ds);
718
719 return 0;
720 }
721
bcm_sf2_sw_get_wol(struct dsa_switch * ds,int port,struct ethtool_wolinfo * wol)722 static void bcm_sf2_sw_get_wol(struct dsa_switch *ds, int port,
723 struct ethtool_wolinfo *wol)
724 {
725 struct net_device *p = ds->ports[port].cpu_dp->master;
726 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
727 struct ethtool_wolinfo pwol;
728
729 /* Get the parent device WoL settings */
730 p->ethtool_ops->get_wol(p, &pwol);
731
732 /* Advertise the parent device supported settings */
733 wol->supported = pwol.supported;
734 memset(&wol->sopass, 0, sizeof(wol->sopass));
735
736 if (pwol.wolopts & WAKE_MAGICSECURE)
737 memcpy(&wol->sopass, pwol.sopass, sizeof(wol->sopass));
738
739 if (priv->wol_ports_mask & (1 << port))
740 wol->wolopts = pwol.wolopts;
741 else
742 wol->wolopts = 0;
743 }
744
bcm_sf2_sw_set_wol(struct dsa_switch * ds,int port,struct ethtool_wolinfo * wol)745 static int bcm_sf2_sw_set_wol(struct dsa_switch *ds, int port,
746 struct ethtool_wolinfo *wol)
747 {
748 struct net_device *p = ds->ports[port].cpu_dp->master;
749 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
750 s8 cpu_port = ds->ports[port].cpu_dp->index;
751 struct ethtool_wolinfo pwol;
752
753 p->ethtool_ops->get_wol(p, &pwol);
754 if (wol->wolopts & ~pwol.supported)
755 return -EINVAL;
756
757 if (wol->wolopts)
758 priv->wol_ports_mask |= (1 << port);
759 else
760 priv->wol_ports_mask &= ~(1 << port);
761
762 /* If we have at least one port enabled, make sure the CPU port
763 * is also enabled. If the CPU port is the last one enabled, we disable
764 * it since this configuration does not make sense.
765 */
766 if (priv->wol_ports_mask && priv->wol_ports_mask != (1 << cpu_port))
767 priv->wol_ports_mask |= (1 << cpu_port);
768 else
769 priv->wol_ports_mask &= ~(1 << cpu_port);
770
771 return p->ethtool_ops->set_wol(p, wol);
772 }
773
bcm_sf2_sw_setup(struct dsa_switch * ds)774 static int bcm_sf2_sw_setup(struct dsa_switch *ds)
775 {
776 struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
777 unsigned int port;
778
779 /* Enable all valid ports and disable those unused */
780 for (port = 0; port < priv->hw_params.num_ports; port++) {
781 /* IMP port receives special treatment */
782 if (dsa_is_user_port(ds, port))
783 bcm_sf2_port_setup(ds, port, NULL);
784 else if (dsa_is_cpu_port(ds, port))
785 bcm_sf2_imp_setup(ds, port);
786 else
787 bcm_sf2_port_disable(ds, port, NULL);
788 }
789
790 b53_configure_vlan(ds);
791 bcm_sf2_enable_acb(ds);
792
793 return 0;
794 }
795
796 /* The SWITCH_CORE register space is managed by b53 but operates on a page +
797 * register basis so we need to translate that into an address that the
798 * bus-glue understands.
799 */
800 #define SF2_PAGE_REG_MKADDR(page, reg) ((page) << 10 | (reg) << 2)
801
bcm_sf2_core_read8(struct b53_device * dev,u8 page,u8 reg,u8 * val)802 static int bcm_sf2_core_read8(struct b53_device *dev, u8 page, u8 reg,
803 u8 *val)
804 {
805 struct bcm_sf2_priv *priv = dev->priv;
806
807 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
808
809 return 0;
810 }
811
bcm_sf2_core_read16(struct b53_device * dev,u8 page,u8 reg,u16 * val)812 static int bcm_sf2_core_read16(struct b53_device *dev, u8 page, u8 reg,
813 u16 *val)
814 {
815 struct bcm_sf2_priv *priv = dev->priv;
816
817 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
818
819 return 0;
820 }
821
bcm_sf2_core_read32(struct b53_device * dev,u8 page,u8 reg,u32 * val)822 static int bcm_sf2_core_read32(struct b53_device *dev, u8 page, u8 reg,
823 u32 *val)
824 {
825 struct bcm_sf2_priv *priv = dev->priv;
826
827 *val = core_readl(priv, SF2_PAGE_REG_MKADDR(page, reg));
828
829 return 0;
830 }
831
bcm_sf2_core_read64(struct b53_device * dev,u8 page,u8 reg,u64 * val)832 static int bcm_sf2_core_read64(struct b53_device *dev, u8 page, u8 reg,
833 u64 *val)
834 {
835 struct bcm_sf2_priv *priv = dev->priv;
836
837 *val = core_readq(priv, SF2_PAGE_REG_MKADDR(page, reg));
838
839 return 0;
840 }
841
bcm_sf2_core_write8(struct b53_device * dev,u8 page,u8 reg,u8 value)842 static int bcm_sf2_core_write8(struct b53_device *dev, u8 page, u8 reg,
843 u8 value)
844 {
845 struct bcm_sf2_priv *priv = dev->priv;
846
847 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
848
849 return 0;
850 }
851
bcm_sf2_core_write16(struct b53_device * dev,u8 page,u8 reg,u16 value)852 static int bcm_sf2_core_write16(struct b53_device *dev, u8 page, u8 reg,
853 u16 value)
854 {
855 struct bcm_sf2_priv *priv = dev->priv;
856
857 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
858
859 return 0;
860 }
861
bcm_sf2_core_write32(struct b53_device * dev,u8 page,u8 reg,u32 value)862 static int bcm_sf2_core_write32(struct b53_device *dev, u8 page, u8 reg,
863 u32 value)
864 {
865 struct bcm_sf2_priv *priv = dev->priv;
866
867 core_writel(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
868
869 return 0;
870 }
871
bcm_sf2_core_write64(struct b53_device * dev,u8 page,u8 reg,u64 value)872 static int bcm_sf2_core_write64(struct b53_device *dev, u8 page, u8 reg,
873 u64 value)
874 {
875 struct bcm_sf2_priv *priv = dev->priv;
876
877 core_writeq(priv, value, SF2_PAGE_REG_MKADDR(page, reg));
878
879 return 0;
880 }
881
882 static const struct b53_io_ops bcm_sf2_io_ops = {
883 .read8 = bcm_sf2_core_read8,
884 .read16 = bcm_sf2_core_read16,
885 .read32 = bcm_sf2_core_read32,
886 .read48 = bcm_sf2_core_read64,
887 .read64 = bcm_sf2_core_read64,
888 .write8 = bcm_sf2_core_write8,
889 .write16 = bcm_sf2_core_write16,
890 .write32 = bcm_sf2_core_write32,
891 .write48 = bcm_sf2_core_write64,
892 .write64 = bcm_sf2_core_write64,
893 };
894
895 static const struct dsa_switch_ops bcm_sf2_ops = {
896 .get_tag_protocol = b53_get_tag_protocol,
897 .setup = bcm_sf2_sw_setup,
898 .get_strings = b53_get_strings,
899 .get_ethtool_stats = b53_get_ethtool_stats,
900 .get_sset_count = b53_get_sset_count,
901 .get_ethtool_phy_stats = b53_get_ethtool_phy_stats,
902 .get_phy_flags = bcm_sf2_sw_get_phy_flags,
903 .phylink_validate = bcm_sf2_sw_validate,
904 .phylink_mac_config = bcm_sf2_sw_mac_config,
905 .phylink_mac_link_down = bcm_sf2_sw_mac_link_down,
906 .phylink_mac_link_up = bcm_sf2_sw_mac_link_up,
907 .phylink_fixed_state = bcm_sf2_sw_fixed_state,
908 .suspend = bcm_sf2_sw_suspend,
909 .resume = bcm_sf2_sw_resume,
910 .get_wol = bcm_sf2_sw_get_wol,
911 .set_wol = bcm_sf2_sw_set_wol,
912 .port_enable = bcm_sf2_port_setup,
913 .port_disable = bcm_sf2_port_disable,
914 .get_mac_eee = b53_get_mac_eee,
915 .set_mac_eee = b53_set_mac_eee,
916 .port_bridge_join = b53_br_join,
917 .port_bridge_leave = b53_br_leave,
918 .port_stp_state_set = b53_br_set_stp_state,
919 .port_fast_age = b53_br_fast_age,
920 .port_vlan_filtering = b53_vlan_filtering,
921 .port_vlan_prepare = b53_vlan_prepare,
922 .port_vlan_add = b53_vlan_add,
923 .port_vlan_del = b53_vlan_del,
924 .port_fdb_dump = b53_fdb_dump,
925 .port_fdb_add = b53_fdb_add,
926 .port_fdb_del = b53_fdb_del,
927 .get_rxnfc = bcm_sf2_get_rxnfc,
928 .set_rxnfc = bcm_sf2_set_rxnfc,
929 .port_mirror_add = b53_mirror_add,
930 .port_mirror_del = b53_mirror_del,
931 };
932
933 struct bcm_sf2_of_data {
934 u32 type;
935 const u16 *reg_offsets;
936 unsigned int core_reg_align;
937 unsigned int num_cfp_rules;
938 };
939
940 /* Register offsets for the SWITCH_REG_* block */
941 static const u16 bcm_sf2_7445_reg_offsets[] = {
942 [REG_SWITCH_CNTRL] = 0x00,
943 [REG_SWITCH_STATUS] = 0x04,
944 [REG_DIR_DATA_WRITE] = 0x08,
945 [REG_DIR_DATA_READ] = 0x0C,
946 [REG_SWITCH_REVISION] = 0x18,
947 [REG_PHY_REVISION] = 0x1C,
948 [REG_SPHY_CNTRL] = 0x2C,
949 [REG_RGMII_0_CNTRL] = 0x34,
950 [REG_RGMII_1_CNTRL] = 0x40,
951 [REG_RGMII_2_CNTRL] = 0x4c,
952 [REG_LED_0_CNTRL] = 0x90,
953 [REG_LED_1_CNTRL] = 0x94,
954 [REG_LED_2_CNTRL] = 0x98,
955 };
956
957 static const struct bcm_sf2_of_data bcm_sf2_7445_data = {
958 .type = BCM7445_DEVICE_ID,
959 .core_reg_align = 0,
960 .reg_offsets = bcm_sf2_7445_reg_offsets,
961 .num_cfp_rules = 256,
962 };
963
964 static const u16 bcm_sf2_7278_reg_offsets[] = {
965 [REG_SWITCH_CNTRL] = 0x00,
966 [REG_SWITCH_STATUS] = 0x04,
967 [REG_DIR_DATA_WRITE] = 0x08,
968 [REG_DIR_DATA_READ] = 0x0c,
969 [REG_SWITCH_REVISION] = 0x10,
970 [REG_PHY_REVISION] = 0x14,
971 [REG_SPHY_CNTRL] = 0x24,
972 [REG_RGMII_0_CNTRL] = 0xe0,
973 [REG_RGMII_1_CNTRL] = 0xec,
974 [REG_RGMII_2_CNTRL] = 0xf8,
975 [REG_LED_0_CNTRL] = 0x40,
976 [REG_LED_1_CNTRL] = 0x4c,
977 [REG_LED_2_CNTRL] = 0x58,
978 };
979
980 static const struct bcm_sf2_of_data bcm_sf2_7278_data = {
981 .type = BCM7278_DEVICE_ID,
982 .core_reg_align = 1,
983 .reg_offsets = bcm_sf2_7278_reg_offsets,
984 .num_cfp_rules = 128,
985 };
986
987 static const struct of_device_id bcm_sf2_of_match[] = {
988 { .compatible = "brcm,bcm7445-switch-v4.0",
989 .data = &bcm_sf2_7445_data
990 },
991 { .compatible = "brcm,bcm7278-switch-v4.0",
992 .data = &bcm_sf2_7278_data
993 },
994 { .compatible = "brcm,bcm7278-switch-v4.8",
995 .data = &bcm_sf2_7278_data
996 },
997 { /* sentinel */ },
998 };
999 MODULE_DEVICE_TABLE(of, bcm_sf2_of_match);
1000
bcm_sf2_sw_probe(struct platform_device * pdev)1001 static int bcm_sf2_sw_probe(struct platform_device *pdev)
1002 {
1003 const char *reg_names[BCM_SF2_REGS_NUM] = BCM_SF2_REGS_NAME;
1004 struct device_node *dn = pdev->dev.of_node;
1005 const struct of_device_id *of_id = NULL;
1006 const struct bcm_sf2_of_data *data;
1007 struct b53_platform_data *pdata;
1008 struct dsa_switch_ops *ops;
1009 struct bcm_sf2_priv *priv;
1010 struct b53_device *dev;
1011 struct dsa_switch *ds;
1012 void __iomem **base;
1013 struct resource *r;
1014 unsigned int i;
1015 u32 reg, rev;
1016 int ret;
1017
1018 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
1019 if (!priv)
1020 return -ENOMEM;
1021
1022 ops = devm_kzalloc(&pdev->dev, sizeof(*ops), GFP_KERNEL);
1023 if (!ops)
1024 return -ENOMEM;
1025
1026 dev = b53_switch_alloc(&pdev->dev, &bcm_sf2_io_ops, priv);
1027 if (!dev)
1028 return -ENOMEM;
1029
1030 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL);
1031 if (!pdata)
1032 return -ENOMEM;
1033
1034 of_id = of_match_node(bcm_sf2_of_match, dn);
1035 if (!of_id || !of_id->data)
1036 return -EINVAL;
1037
1038 data = of_id->data;
1039
1040 /* Set SWITCH_REG register offsets and SWITCH_CORE align factor */
1041 priv->type = data->type;
1042 priv->reg_offsets = data->reg_offsets;
1043 priv->core_reg_align = data->core_reg_align;
1044 priv->num_cfp_rules = data->num_cfp_rules;
1045
1046 /* Auto-detection using standard registers will not work, so
1047 * provide an indication of what kind of device we are for
1048 * b53_common to work with
1049 */
1050 pdata->chip_id = priv->type;
1051 dev->pdata = pdata;
1052
1053 priv->dev = dev;
1054 ds = dev->ds;
1055 ds->ops = &bcm_sf2_ops;
1056
1057 /* Advertise the 8 egress queues */
1058 ds->num_tx_queues = SF2_NUM_EGRESS_QUEUES;
1059
1060 dev_set_drvdata(&pdev->dev, priv);
1061
1062 spin_lock_init(&priv->indir_lock);
1063 mutex_init(&priv->stats_mutex);
1064 mutex_init(&priv->cfp.lock);
1065
1066 /* CFP rule #0 cannot be used for specific classifications, flag it as
1067 * permanently used
1068 */
1069 set_bit(0, priv->cfp.used);
1070 set_bit(0, priv->cfp.unique);
1071
1072 bcm_sf2_identify_ports(priv, dn->child);
1073
1074 priv->irq0 = irq_of_parse_and_map(dn, 0);
1075 priv->irq1 = irq_of_parse_and_map(dn, 1);
1076
1077 base = &priv->core;
1078 for (i = 0; i < BCM_SF2_REGS_NUM; i++) {
1079 r = platform_get_resource(pdev, IORESOURCE_MEM, i);
1080 *base = devm_ioremap_resource(&pdev->dev, r);
1081 if (IS_ERR(*base)) {
1082 pr_err("unable to find register: %s\n", reg_names[i]);
1083 return PTR_ERR(*base);
1084 }
1085 base++;
1086 }
1087
1088 ret = bcm_sf2_sw_rst(priv);
1089 if (ret) {
1090 pr_err("unable to software reset switch: %d\n", ret);
1091 return ret;
1092 }
1093
1094 ret = bcm_sf2_mdio_register(ds);
1095 if (ret) {
1096 pr_err("failed to register MDIO bus\n");
1097 return ret;
1098 }
1099
1100 ret = bcm_sf2_cfp_rst(priv);
1101 if (ret) {
1102 pr_err("failed to reset CFP\n");
1103 goto out_mdio;
1104 }
1105
1106 /* Disable all interrupts and request them */
1107 bcm_sf2_intr_disable(priv);
1108
1109 ret = devm_request_irq(&pdev->dev, priv->irq0, bcm_sf2_switch_0_isr, 0,
1110 "switch_0", ds);
1111 if (ret < 0) {
1112 pr_err("failed to request switch_0 IRQ\n");
1113 goto out_mdio;
1114 }
1115
1116 ret = devm_request_irq(&pdev->dev, priv->irq1, bcm_sf2_switch_1_isr, 0,
1117 "switch_1", ds);
1118 if (ret < 0) {
1119 pr_err("failed to request switch_1 IRQ\n");
1120 goto out_mdio;
1121 }
1122
1123 /* Reset the MIB counters */
1124 reg = core_readl(priv, CORE_GMNCFGCFG);
1125 reg |= RST_MIB_CNT;
1126 core_writel(priv, reg, CORE_GMNCFGCFG);
1127 reg &= ~RST_MIB_CNT;
1128 core_writel(priv, reg, CORE_GMNCFGCFG);
1129
1130 /* Get the maximum number of ports for this switch */
1131 priv->hw_params.num_ports = core_readl(priv, CORE_IMP0_PRT_ID) + 1;
1132 if (priv->hw_params.num_ports > DSA_MAX_PORTS)
1133 priv->hw_params.num_ports = DSA_MAX_PORTS;
1134
1135 /* Assume a single GPHY setup if we can't read that property */
1136 if (of_property_read_u32(dn, "brcm,num-gphy",
1137 &priv->hw_params.num_gphy))
1138 priv->hw_params.num_gphy = 1;
1139
1140 rev = reg_readl(priv, REG_SWITCH_REVISION);
1141 priv->hw_params.top_rev = (rev >> SWITCH_TOP_REV_SHIFT) &
1142 SWITCH_TOP_REV_MASK;
1143 priv->hw_params.core_rev = (rev & SF2_REV_MASK);
1144
1145 rev = reg_readl(priv, REG_PHY_REVISION);
1146 priv->hw_params.gphy_rev = rev & PHY_REVISION_MASK;
1147
1148 ret = b53_switch_register(dev);
1149 if (ret)
1150 goto out_mdio;
1151
1152 pr_info("Starfighter 2 top: %x.%02x, core: %x.%02x base: 0x%p, IRQs: %d, %d\n",
1153 priv->hw_params.top_rev >> 8, priv->hw_params.top_rev & 0xff,
1154 priv->hw_params.core_rev >> 8, priv->hw_params.core_rev & 0xff,
1155 priv->core, priv->irq0, priv->irq1);
1156
1157 return 0;
1158
1159 out_mdio:
1160 bcm_sf2_mdio_unregister(priv);
1161 return ret;
1162 }
1163
bcm_sf2_sw_remove(struct platform_device * pdev)1164 static int bcm_sf2_sw_remove(struct platform_device *pdev)
1165 {
1166 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1167
1168 priv->wol_ports_mask = 0;
1169 dsa_unregister_switch(priv->dev->ds);
1170 /* Disable all ports and interrupts */
1171 bcm_sf2_sw_suspend(priv->dev->ds);
1172 bcm_sf2_mdio_unregister(priv);
1173
1174 return 0;
1175 }
1176
bcm_sf2_sw_shutdown(struct platform_device * pdev)1177 static void bcm_sf2_sw_shutdown(struct platform_device *pdev)
1178 {
1179 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1180
1181 /* For a kernel about to be kexec'd we want to keep the GPHY on for a
1182 * successful MDIO bus scan to occur. If we did turn off the GPHY
1183 * before (e.g: port_disable), this will also power it back on.
1184 *
1185 * Do not rely on kexec_in_progress, just power the PHY on.
1186 */
1187 if (priv->hw_params.num_gphy == 1)
1188 bcm_sf2_gphy_enable_set(priv->dev->ds, true);
1189 }
1190
1191 #ifdef CONFIG_PM_SLEEP
bcm_sf2_suspend(struct device * dev)1192 static int bcm_sf2_suspend(struct device *dev)
1193 {
1194 struct platform_device *pdev = to_platform_device(dev);
1195 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1196
1197 return dsa_switch_suspend(priv->dev->ds);
1198 }
1199
bcm_sf2_resume(struct device * dev)1200 static int bcm_sf2_resume(struct device *dev)
1201 {
1202 struct platform_device *pdev = to_platform_device(dev);
1203 struct bcm_sf2_priv *priv = platform_get_drvdata(pdev);
1204
1205 return dsa_switch_resume(priv->dev->ds);
1206 }
1207 #endif /* CONFIG_PM_SLEEP */
1208
1209 static SIMPLE_DEV_PM_OPS(bcm_sf2_pm_ops,
1210 bcm_sf2_suspend, bcm_sf2_resume);
1211
1212
1213 static struct platform_driver bcm_sf2_driver = {
1214 .probe = bcm_sf2_sw_probe,
1215 .remove = bcm_sf2_sw_remove,
1216 .shutdown = bcm_sf2_sw_shutdown,
1217 .driver = {
1218 .name = "brcm-sf2",
1219 .of_match_table = bcm_sf2_of_match,
1220 .pm = &bcm_sf2_pm_ops,
1221 },
1222 };
1223 module_platform_driver(bcm_sf2_driver);
1224
1225 MODULE_AUTHOR("Broadcom Corporation");
1226 MODULE_DESCRIPTION("Driver for Broadcom Starfighter 2 ethernet switch chip");
1227 MODULE_LICENSE("GPL");
1228 MODULE_ALIAS("platform:brcm-sf2");
1229
