1 /*
2 * Driver for One Laptop Per Child ‘CAFÉ’ controller, aka Marvell 88ALP01
3 *
4 * The data sheet for this device can be found at:
5 * http://wiki.laptop.org/go/Datasheets
6 *
7 * Copyright © 2006 Red Hat, Inc.
8 * Copyright © 2006 David Woodhouse <dwmw2@infradead.org>
9 */
10
11 #define DEBUG
12
13 #include <linux/device.h>
14 #undef DEBUG
15 #include <linux/mtd/mtd.h>
16 #include <linux/mtd/rawnand.h>
17 #include <linux/mtd/partitions.h>
18 #include <linux/rslib.h>
19 #include <linux/pci.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/slab.h>
24 #include <linux/module.h>
25 #include <asm/io.h>
26
27 #define CAFE_NAND_CTRL1 0x00
28 #define CAFE_NAND_CTRL2 0x04
29 #define CAFE_NAND_CTRL3 0x08
30 #define CAFE_NAND_STATUS 0x0c
31 #define CAFE_NAND_IRQ 0x10
32 #define CAFE_NAND_IRQ_MASK 0x14
33 #define CAFE_NAND_DATA_LEN 0x18
34 #define CAFE_NAND_ADDR1 0x1c
35 #define CAFE_NAND_ADDR2 0x20
36 #define CAFE_NAND_TIMING1 0x24
37 #define CAFE_NAND_TIMING2 0x28
38 #define CAFE_NAND_TIMING3 0x2c
39 #define CAFE_NAND_NONMEM 0x30
40 #define CAFE_NAND_ECC_RESULT 0x3C
41 #define CAFE_NAND_DMA_CTRL 0x40
42 #define CAFE_NAND_DMA_ADDR0 0x44
43 #define CAFE_NAND_DMA_ADDR1 0x48
44 #define CAFE_NAND_ECC_SYN01 0x50
45 #define CAFE_NAND_ECC_SYN23 0x54
46 #define CAFE_NAND_ECC_SYN45 0x58
47 #define CAFE_NAND_ECC_SYN67 0x5c
48 #define CAFE_NAND_READ_DATA 0x1000
49 #define CAFE_NAND_WRITE_DATA 0x2000
50
51 #define CAFE_GLOBAL_CTRL 0x3004
52 #define CAFE_GLOBAL_IRQ 0x3008
53 #define CAFE_GLOBAL_IRQ_MASK 0x300c
54 #define CAFE_NAND_RESET 0x3034
55
56 /* Missing from the datasheet: bit 19 of CTRL1 sets CE0 vs. CE1 */
57 #define CTRL1_CHIPSELECT (1<<19)
58
59 struct cafe_priv {
60 struct nand_chip nand;
61 struct pci_dev *pdev;
62 void __iomem *mmio;
63 struct rs_control *rs;
64 uint32_t ctl1;
65 uint32_t ctl2;
66 int datalen;
67 int nr_data;
68 int data_pos;
69 int page_addr;
70 bool usedma;
71 dma_addr_t dmaaddr;
72 unsigned char *dmabuf;
73 };
74
75 static int usedma = 1;
76 module_param(usedma, int, 0644);
77
78 static int skipbbt = 0;
79 module_param(skipbbt, int, 0644);
80
81 static int debug = 0;
82 module_param(debug, int, 0644);
83
84 static int regdebug = 0;
85 module_param(regdebug, int, 0644);
86
87 static int checkecc = 1;
88 module_param(checkecc, int, 0644);
89
90 static unsigned int numtimings;
91 static int timing[3];
92 module_param_array(timing, int, &numtimings, 0644);
93
94 static const char *part_probes[] = { "cmdlinepart", "RedBoot", NULL };
95
96 /* Hrm. Why isn't this already conditional on something in the struct device? */
97 #define cafe_dev_dbg(dev, args...) do { if (debug) dev_dbg(dev, ##args); } while(0)
98
99 /* Make it easier to switch to PIO if we need to */
100 #define cafe_readl(cafe, addr) readl((cafe)->mmio + CAFE_##addr)
101 #define cafe_writel(cafe, datum, addr) writel(datum, (cafe)->mmio + CAFE_##addr)
102
cafe_device_ready(struct mtd_info * mtd)103 static int cafe_device_ready(struct mtd_info *mtd)
104 {
105 struct nand_chip *chip = mtd_to_nand(mtd);
106 struct cafe_priv *cafe = nand_get_controller_data(chip);
107 int result = !!(cafe_readl(cafe, NAND_STATUS) & 0x40000000);
108 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
109
110 cafe_writel(cafe, irqs, NAND_IRQ);
111
112 cafe_dev_dbg(&cafe->pdev->dev, "NAND device is%s ready, IRQ %x (%x) (%x,%x)\n",
113 result?"":" not", irqs, cafe_readl(cafe, NAND_IRQ),
114 cafe_readl(cafe, GLOBAL_IRQ), cafe_readl(cafe, GLOBAL_IRQ_MASK));
115
116 return result;
117 }
118
119
cafe_write_buf(struct mtd_info * mtd,const uint8_t * buf,int len)120 static void cafe_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
121 {
122 struct nand_chip *chip = mtd_to_nand(mtd);
123 struct cafe_priv *cafe = nand_get_controller_data(chip);
124
125 if (cafe->usedma)
126 memcpy(cafe->dmabuf + cafe->datalen, buf, len);
127 else
128 memcpy_toio(cafe->mmio + CAFE_NAND_WRITE_DATA + cafe->datalen, buf, len);
129
130 cafe->datalen += len;
131
132 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes to write buffer. datalen 0x%x\n",
133 len, cafe->datalen);
134 }
135
cafe_read_buf(struct mtd_info * mtd,uint8_t * buf,int len)136 static void cafe_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
137 {
138 struct nand_chip *chip = mtd_to_nand(mtd);
139 struct cafe_priv *cafe = nand_get_controller_data(chip);
140
141 if (cafe->usedma)
142 memcpy(buf, cafe->dmabuf + cafe->datalen, len);
143 else
144 memcpy_fromio(buf, cafe->mmio + CAFE_NAND_READ_DATA + cafe->datalen, len);
145
146 cafe_dev_dbg(&cafe->pdev->dev, "Copy 0x%x bytes from position 0x%x in read buffer.\n",
147 len, cafe->datalen);
148 cafe->datalen += len;
149 }
150
cafe_read_byte(struct mtd_info * mtd)151 static uint8_t cafe_read_byte(struct mtd_info *mtd)
152 {
153 struct nand_chip *chip = mtd_to_nand(mtd);
154 struct cafe_priv *cafe = nand_get_controller_data(chip);
155 uint8_t d;
156
157 cafe_read_buf(mtd, &d, 1);
158 cafe_dev_dbg(&cafe->pdev->dev, "Read %02x\n", d);
159
160 return d;
161 }
162
cafe_nand_cmdfunc(struct mtd_info * mtd,unsigned command,int column,int page_addr)163 static void cafe_nand_cmdfunc(struct mtd_info *mtd, unsigned command,
164 int column, int page_addr)
165 {
166 struct nand_chip *chip = mtd_to_nand(mtd);
167 struct cafe_priv *cafe = nand_get_controller_data(chip);
168 int adrbytes = 0;
169 uint32_t ctl1;
170 uint32_t doneint = 0x80000000;
171
172 cafe_dev_dbg(&cafe->pdev->dev, "cmdfunc %02x, 0x%x, 0x%x\n",
173 command, column, page_addr);
174
175 if (command == NAND_CMD_ERASE2 || command == NAND_CMD_PAGEPROG) {
176 /* Second half of a command we already calculated */
177 cafe_writel(cafe, cafe->ctl2 | 0x100 | command, NAND_CTRL2);
178 ctl1 = cafe->ctl1;
179 cafe->ctl2 &= ~(1<<30);
180 cafe_dev_dbg(&cafe->pdev->dev, "Continue command, ctl1 %08x, #data %d\n",
181 cafe->ctl1, cafe->nr_data);
182 goto do_command;
183 }
184 /* Reset ECC engine */
185 cafe_writel(cafe, 0, NAND_CTRL2);
186
187 /* Emulate NAND_CMD_READOOB on large-page chips */
188 if (mtd->writesize > 512 &&
189 command == NAND_CMD_READOOB) {
190 column += mtd->writesize;
191 command = NAND_CMD_READ0;
192 }
193
194 /* FIXME: Do we need to send read command before sending data
195 for small-page chips, to position the buffer correctly? */
196
197 if (column != -1) {
198 cafe_writel(cafe, column, NAND_ADDR1);
199 adrbytes = 2;
200 if (page_addr != -1)
201 goto write_adr2;
202 } else if (page_addr != -1) {
203 cafe_writel(cafe, page_addr & 0xffff, NAND_ADDR1);
204 page_addr >>= 16;
205 write_adr2:
206 cafe_writel(cafe, page_addr, NAND_ADDR2);
207 adrbytes += 2;
208 if (mtd->size > mtd->writesize << 16)
209 adrbytes++;
210 }
211
212 cafe->data_pos = cafe->datalen = 0;
213
214 /* Set command valid bit, mask in the chip select bit */
215 ctl1 = 0x80000000 | command | (cafe->ctl1 & CTRL1_CHIPSELECT);
216
217 /* Set RD or WR bits as appropriate */
218 if (command == NAND_CMD_READID || command == NAND_CMD_STATUS) {
219 ctl1 |= (1<<26); /* rd */
220 /* Always 5 bytes, for now */
221 cafe->datalen = 4;
222 /* And one address cycle -- even for STATUS, since the controller doesn't work without */
223 adrbytes = 1;
224 } else if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 ||
225 command == NAND_CMD_READOOB || command == NAND_CMD_RNDOUT) {
226 ctl1 |= 1<<26; /* rd */
227 /* For now, assume just read to end of page */
228 cafe->datalen = mtd->writesize + mtd->oobsize - column;
229 } else if (command == NAND_CMD_SEQIN)
230 ctl1 |= 1<<25; /* wr */
231
232 /* Set number of address bytes */
233 if (adrbytes)
234 ctl1 |= ((adrbytes-1)|8) << 27;
235
236 if (command == NAND_CMD_SEQIN || command == NAND_CMD_ERASE1) {
237 /* Ignore the first command of a pair; the hardware
238 deals with them both at once, later */
239 cafe->ctl1 = ctl1;
240 cafe_dev_dbg(&cafe->pdev->dev, "Setup for delayed command, ctl1 %08x, dlen %x\n",
241 cafe->ctl1, cafe->datalen);
242 return;
243 }
244 /* RNDOUT and READ0 commands need a following byte */
245 if (command == NAND_CMD_RNDOUT)
246 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_RNDOUTSTART, NAND_CTRL2);
247 else if (command == NAND_CMD_READ0 && mtd->writesize > 512)
248 cafe_writel(cafe, cafe->ctl2 | 0x100 | NAND_CMD_READSTART, NAND_CTRL2);
249
250 do_command:
251 cafe_dev_dbg(&cafe->pdev->dev, "dlen %x, ctl1 %x, ctl2 %x\n",
252 cafe->datalen, ctl1, cafe_readl(cafe, NAND_CTRL2));
253
254 /* NB: The datasheet lies -- we really should be subtracting 1 here */
255 cafe_writel(cafe, cafe->datalen, NAND_DATA_LEN);
256 cafe_writel(cafe, 0x90000000, NAND_IRQ);
257 if (cafe->usedma && (ctl1 & (3<<25))) {
258 uint32_t dmactl = 0xc0000000 + cafe->datalen;
259 /* If WR or RD bits set, set up DMA */
260 if (ctl1 & (1<<26)) {
261 /* It's a read */
262 dmactl |= (1<<29);
263 /* ... so it's done when the DMA is done, not just
264 the command. */
265 doneint = 0x10000000;
266 }
267 cafe_writel(cafe, dmactl, NAND_DMA_CTRL);
268 }
269 cafe->datalen = 0;
270
271 if (unlikely(regdebug)) {
272 int i;
273 printk("About to write command %08x to register 0\n", ctl1);
274 for (i=4; i< 0x5c; i+=4)
275 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
276 }
277
278 cafe_writel(cafe, ctl1, NAND_CTRL1);
279 /* Apply this short delay always to ensure that we do wait tWB in
280 * any case on any machine. */
281 ndelay(100);
282
283 if (1) {
284 int c;
285 uint32_t irqs;
286
287 for (c = 500000; c != 0; c--) {
288 irqs = cafe_readl(cafe, NAND_IRQ);
289 if (irqs & doneint)
290 break;
291 udelay(1);
292 if (!(c % 100000))
293 cafe_dev_dbg(&cafe->pdev->dev, "Wait for ready, IRQ %x\n", irqs);
294 cpu_relax();
295 }
296 cafe_writel(cafe, doneint, NAND_IRQ);
297 cafe_dev_dbg(&cafe->pdev->dev, "Command %x completed after %d usec, irqs %x (%x)\n",
298 command, 500000-c, irqs, cafe_readl(cafe, NAND_IRQ));
299 }
300
301 WARN_ON(cafe->ctl2 & (1<<30));
302
303 switch (command) {
304
305 case NAND_CMD_CACHEDPROG:
306 case NAND_CMD_PAGEPROG:
307 case NAND_CMD_ERASE1:
308 case NAND_CMD_ERASE2:
309 case NAND_CMD_SEQIN:
310 case NAND_CMD_RNDIN:
311 case NAND_CMD_STATUS:
312 case NAND_CMD_RNDOUT:
313 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
314 return;
315 }
316 nand_wait_ready(mtd);
317 cafe_writel(cafe, cafe->ctl2, NAND_CTRL2);
318 }
319
cafe_select_chip(struct mtd_info * mtd,int chipnr)320 static void cafe_select_chip(struct mtd_info *mtd, int chipnr)
321 {
322 struct nand_chip *chip = mtd_to_nand(mtd);
323 struct cafe_priv *cafe = nand_get_controller_data(chip);
324
325 cafe_dev_dbg(&cafe->pdev->dev, "select_chip %d\n", chipnr);
326
327 /* Mask the appropriate bit into the stored value of ctl1
328 which will be used by cafe_nand_cmdfunc() */
329 if (chipnr)
330 cafe->ctl1 |= CTRL1_CHIPSELECT;
331 else
332 cafe->ctl1 &= ~CTRL1_CHIPSELECT;
333 }
334
cafe_nand_interrupt(int irq,void * id)335 static irqreturn_t cafe_nand_interrupt(int irq, void *id)
336 {
337 struct mtd_info *mtd = id;
338 struct nand_chip *chip = mtd_to_nand(mtd);
339 struct cafe_priv *cafe = nand_get_controller_data(chip);
340 uint32_t irqs = cafe_readl(cafe, NAND_IRQ);
341 cafe_writel(cafe, irqs & ~0x90000000, NAND_IRQ);
342 if (!irqs)
343 return IRQ_NONE;
344
345 cafe_dev_dbg(&cafe->pdev->dev, "irq, bits %x (%x)\n", irqs, cafe_readl(cafe, NAND_IRQ));
346 return IRQ_HANDLED;
347 }
348
cafe_nand_write_oob(struct mtd_info * mtd,struct nand_chip * chip,int page)349 static int cafe_nand_write_oob(struct mtd_info *mtd,
350 struct nand_chip *chip, int page)
351 {
352 return nand_prog_page_op(chip, page, mtd->writesize, chip->oob_poi,
353 mtd->oobsize);
354 }
355
356 /* Don't use -- use nand_read_oob_std for now */
cafe_nand_read_oob(struct mtd_info * mtd,struct nand_chip * chip,int page)357 static int cafe_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
358 int page)
359 {
360 return nand_read_oob_op(chip, page, 0, chip->oob_poi, mtd->oobsize);
361 }
362 /**
363 * cafe_nand_read_page_syndrome - [REPLACEABLE] hardware ecc syndrome based page read
364 * @mtd: mtd info structure
365 * @chip: nand chip info structure
366 * @buf: buffer to store read data
367 * @oob_required: caller expects OOB data read to chip->oob_poi
368 *
369 * The hw generator calculates the error syndrome automatically. Therefore
370 * we need a special oob layout and handling.
371 */
cafe_nand_read_page(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)372 static int cafe_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
373 uint8_t *buf, int oob_required, int page)
374 {
375 struct cafe_priv *cafe = nand_get_controller_data(chip);
376 unsigned int max_bitflips = 0;
377
378 cafe_dev_dbg(&cafe->pdev->dev, "ECC result %08x SYN1,2 %08x\n",
379 cafe_readl(cafe, NAND_ECC_RESULT),
380 cafe_readl(cafe, NAND_ECC_SYN01));
381
382 nand_read_page_op(chip, page, 0, buf, mtd->writesize);
383 chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
384
385 if (checkecc && cafe_readl(cafe, NAND_ECC_RESULT) & (1<<18)) {
386 unsigned short syn[8], pat[4];
387 int pos[4];
388 u8 *oob = chip->oob_poi;
389 int i, n;
390
391 for (i=0; i<8; i+=2) {
392 uint32_t tmp = cafe_readl(cafe, NAND_ECC_SYN01 + (i*2));
393
394 syn[i] = cafe->rs->codec->index_of[tmp & 0xfff];
395 syn[i+1] = cafe->rs->codec->index_of[(tmp >> 16) & 0xfff];
396 }
397
398 n = decode_rs16(cafe->rs, NULL, NULL, 1367, syn, 0, pos, 0,
399 pat);
400
401 for (i = 0; i < n; i++) {
402 int p = pos[i];
403
404 /* The 12-bit symbols are mapped to bytes here */
405
406 if (p > 1374) {
407 /* out of range */
408 n = -1374;
409 } else if (p == 0) {
410 /* high four bits do not correspond to data */
411 if (pat[i] > 0xff)
412 n = -2048;
413 else
414 buf[0] ^= pat[i];
415 } else if (p == 1365) {
416 buf[2047] ^= pat[i] >> 4;
417 oob[0] ^= pat[i] << 4;
418 } else if (p > 1365) {
419 if ((p & 1) == 1) {
420 oob[3*p/2 - 2048] ^= pat[i] >> 4;
421 oob[3*p/2 - 2047] ^= pat[i] << 4;
422 } else {
423 oob[3*p/2 - 2049] ^= pat[i] >> 8;
424 oob[3*p/2 - 2048] ^= pat[i];
425 }
426 } else if ((p & 1) == 1) {
427 buf[3*p/2] ^= pat[i] >> 4;
428 buf[3*p/2 + 1] ^= pat[i] << 4;
429 } else {
430 buf[3*p/2 - 1] ^= pat[i] >> 8;
431 buf[3*p/2] ^= pat[i];
432 }
433 }
434
435 if (n < 0) {
436 dev_dbg(&cafe->pdev->dev, "Failed to correct ECC at %08x\n",
437 cafe_readl(cafe, NAND_ADDR2) * 2048);
438 for (i = 0; i < 0x5c; i += 4)
439 printk("Register %x: %08x\n", i, readl(cafe->mmio + i));
440 mtd->ecc_stats.failed++;
441 } else {
442 dev_dbg(&cafe->pdev->dev, "Corrected %d symbol errors\n", n);
443 mtd->ecc_stats.corrected += n;
444 max_bitflips = max_t(unsigned int, max_bitflips, n);
445 }
446 }
447
448 return max_bitflips;
449 }
450
cafe_ooblayout_ecc(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)451 static int cafe_ooblayout_ecc(struct mtd_info *mtd, int section,
452 struct mtd_oob_region *oobregion)
453 {
454 struct nand_chip *chip = mtd_to_nand(mtd);
455
456 if (section)
457 return -ERANGE;
458
459 oobregion->offset = 0;
460 oobregion->length = chip->ecc.total;
461
462 return 0;
463 }
464
cafe_ooblayout_free(struct mtd_info * mtd,int section,struct mtd_oob_region * oobregion)465 static int cafe_ooblayout_free(struct mtd_info *mtd, int section,
466 struct mtd_oob_region *oobregion)
467 {
468 struct nand_chip *chip = mtd_to_nand(mtd);
469
470 if (section)
471 return -ERANGE;
472
473 oobregion->offset = chip->ecc.total;
474 oobregion->length = mtd->oobsize - chip->ecc.total;
475
476 return 0;
477 }
478
479 static const struct mtd_ooblayout_ops cafe_ooblayout_ops = {
480 .ecc = cafe_ooblayout_ecc,
481 .free = cafe_ooblayout_free,
482 };
483
484 /* Ick. The BBT code really ought to be able to work this bit out
485 for itself from the above, at least for the 2KiB case */
486 static uint8_t cafe_bbt_pattern_2048[] = { 'B', 'b', 't', '0' };
487 static uint8_t cafe_mirror_pattern_2048[] = { '1', 't', 'b', 'B' };
488
489 static uint8_t cafe_bbt_pattern_512[] = { 0xBB };
490 static uint8_t cafe_mirror_pattern_512[] = { 0xBC };
491
492
493 static struct nand_bbt_descr cafe_bbt_main_descr_2048 = {
494 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
495 | NAND_BBT_2BIT | NAND_BBT_VERSION,
496 .offs = 14,
497 .len = 4,
498 .veroffs = 18,
499 .maxblocks = 4,
500 .pattern = cafe_bbt_pattern_2048
501 };
502
503 static struct nand_bbt_descr cafe_bbt_mirror_descr_2048 = {
504 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
505 | NAND_BBT_2BIT | NAND_BBT_VERSION,
506 .offs = 14,
507 .len = 4,
508 .veroffs = 18,
509 .maxblocks = 4,
510 .pattern = cafe_mirror_pattern_2048
511 };
512
513 static struct nand_bbt_descr cafe_bbt_main_descr_512 = {
514 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
515 | NAND_BBT_2BIT | NAND_BBT_VERSION,
516 .offs = 14,
517 .len = 1,
518 .veroffs = 15,
519 .maxblocks = 4,
520 .pattern = cafe_bbt_pattern_512
521 };
522
523 static struct nand_bbt_descr cafe_bbt_mirror_descr_512 = {
524 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
525 | NAND_BBT_2BIT | NAND_BBT_VERSION,
526 .offs = 14,
527 .len = 1,
528 .veroffs = 15,
529 .maxblocks = 4,
530 .pattern = cafe_mirror_pattern_512
531 };
532
533
cafe_nand_write_page_lowlevel(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)534 static int cafe_nand_write_page_lowlevel(struct mtd_info *mtd,
535 struct nand_chip *chip,
536 const uint8_t *buf, int oob_required,
537 int page)
538 {
539 struct cafe_priv *cafe = nand_get_controller_data(chip);
540
541 nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
542 chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
543
544 /* Set up ECC autogeneration */
545 cafe->ctl2 |= (1<<30);
546
547 return nand_prog_page_end_op(chip);
548 }
549
cafe_nand_block_bad(struct mtd_info * mtd,loff_t ofs)550 static int cafe_nand_block_bad(struct mtd_info *mtd, loff_t ofs)
551 {
552 return 0;
553 }
554
555 /* F_2[X]/(X**6+X+1) */
gf64_mul(u8 a,u8 b)556 static unsigned short gf64_mul(u8 a, u8 b)
557 {
558 u8 c;
559 unsigned int i;
560
561 c = 0;
562 for (i = 0; i < 6; i++) {
563 if (a & 1)
564 c ^= b;
565 a >>= 1;
566 b <<= 1;
567 if ((b & 0x40) != 0)
568 b ^= 0x43;
569 }
570
571 return c;
572 }
573
574 /* F_64[X]/(X**2+X+A**-1) with A the generator of F_64[X] */
gf4096_mul(u16 a,u16 b)575 static u16 gf4096_mul(u16 a, u16 b)
576 {
577 u8 ah, al, bh, bl, ch, cl;
578
579 ah = a >> 6;
580 al = a & 0x3f;
581 bh = b >> 6;
582 bl = b & 0x3f;
583
584 ch = gf64_mul(ah ^ al, bh ^ bl) ^ gf64_mul(al, bl);
585 cl = gf64_mul(gf64_mul(ah, bh), 0x21) ^ gf64_mul(al, bl);
586
587 return (ch << 6) ^ cl;
588 }
589
cafe_mul(int x)590 static int cafe_mul(int x)
591 {
592 if (x == 0)
593 return 1;
594 return gf4096_mul(x, 0xe01);
595 }
596
cafe_nand_attach_chip(struct nand_chip * chip)597 static int cafe_nand_attach_chip(struct nand_chip *chip)
598 {
599 struct mtd_info *mtd = nand_to_mtd(chip);
600 struct cafe_priv *cafe = nand_get_controller_data(chip);
601 int err = 0;
602
603 cafe->dmabuf = dma_alloc_coherent(&cafe->pdev->dev, 2112,
604 &cafe->dmaaddr, GFP_KERNEL);
605 if (!cafe->dmabuf)
606 return -ENOMEM;
607
608 /* Set up DMA address */
609 cafe_writel(cafe, lower_32_bits(cafe->dmaaddr), NAND_DMA_ADDR0);
610 cafe_writel(cafe, upper_32_bits(cafe->dmaaddr), NAND_DMA_ADDR1);
611
612 cafe_dev_dbg(&cafe->pdev->dev, "Set DMA address to %x (virt %p)\n",
613 cafe_readl(cafe, NAND_DMA_ADDR0), cafe->dmabuf);
614
615 /* Restore the DMA flag */
616 cafe->usedma = usedma;
617
618 cafe->ctl2 = BIT(27); /* Reed-Solomon ECC */
619 if (mtd->writesize == 2048)
620 cafe->ctl2 |= BIT(29); /* 2KiB page size */
621
622 /* Set up ECC according to the type of chip we found */
623 mtd_set_ooblayout(mtd, &cafe_ooblayout_ops);
624 if (mtd->writesize == 2048) {
625 cafe->nand.bbt_td = &cafe_bbt_main_descr_2048;
626 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_2048;
627 } else if (mtd->writesize == 512) {
628 cafe->nand.bbt_td = &cafe_bbt_main_descr_512;
629 cafe->nand.bbt_md = &cafe_bbt_mirror_descr_512;
630 } else {
631 dev_warn(&cafe->pdev->dev,
632 "Unexpected NAND flash writesize %d. Aborting\n",
633 mtd->writesize);
634 err = -ENOTSUPP;
635 goto out_free_dma;
636 }
637
638 cafe->nand.ecc.mode = NAND_ECC_HW_SYNDROME;
639 cafe->nand.ecc.size = mtd->writesize;
640 cafe->nand.ecc.bytes = 14;
641 cafe->nand.ecc.strength = 4;
642 cafe->nand.ecc.write_page = cafe_nand_write_page_lowlevel;
643 cafe->nand.ecc.write_oob = cafe_nand_write_oob;
644 cafe->nand.ecc.read_page = cafe_nand_read_page;
645 cafe->nand.ecc.read_oob = cafe_nand_read_oob;
646
647 return 0;
648
649 out_free_dma:
650 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
651
652 return err;
653 }
654
cafe_nand_detach_chip(struct nand_chip * chip)655 static void cafe_nand_detach_chip(struct nand_chip *chip)
656 {
657 struct cafe_priv *cafe = nand_get_controller_data(chip);
658
659 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
660 }
661
662 static const struct nand_controller_ops cafe_nand_controller_ops = {
663 .attach_chip = cafe_nand_attach_chip,
664 .detach_chip = cafe_nand_detach_chip,
665 };
666
cafe_nand_probe(struct pci_dev * pdev,const struct pci_device_id * ent)667 static int cafe_nand_probe(struct pci_dev *pdev,
668 const struct pci_device_id *ent)
669 {
670 struct mtd_info *mtd;
671 struct cafe_priv *cafe;
672 uint32_t ctrl;
673 int err = 0;
674
675 /* Very old versions shared the same PCI ident for all three
676 functions on the chip. Verify the class too... */
677 if ((pdev->class >> 8) != PCI_CLASS_MEMORY_FLASH)
678 return -ENODEV;
679
680 err = pci_enable_device(pdev);
681 if (err)
682 return err;
683
684 pci_set_master(pdev);
685
686 cafe = kzalloc(sizeof(*cafe), GFP_KERNEL);
687 if (!cafe)
688 return -ENOMEM;
689
690 mtd = nand_to_mtd(&cafe->nand);
691 mtd->dev.parent = &pdev->dev;
692 nand_set_controller_data(&cafe->nand, cafe);
693
694 cafe->pdev = pdev;
695 cafe->mmio = pci_iomap(pdev, 0, 0);
696 if (!cafe->mmio) {
697 dev_warn(&pdev->dev, "failed to iomap\n");
698 err = -ENOMEM;
699 goto out_free_mtd;
700 }
701
702 cafe->rs = init_rs_non_canonical(12, &cafe_mul, 0, 1, 8);
703 if (!cafe->rs) {
704 err = -ENOMEM;
705 goto out_ior;
706 }
707
708 cafe->nand.cmdfunc = cafe_nand_cmdfunc;
709 cafe->nand.dev_ready = cafe_device_ready;
710 cafe->nand.read_byte = cafe_read_byte;
711 cafe->nand.read_buf = cafe_read_buf;
712 cafe->nand.write_buf = cafe_write_buf;
713 cafe->nand.select_chip = cafe_select_chip;
714 cafe->nand.set_features = nand_get_set_features_notsupp;
715 cafe->nand.get_features = nand_get_set_features_notsupp;
716
717 cafe->nand.chip_delay = 0;
718
719 /* Enable the following for a flash based bad block table */
720 cafe->nand.bbt_options = NAND_BBT_USE_FLASH;
721
722 if (skipbbt) {
723 cafe->nand.options |= NAND_SKIP_BBTSCAN;
724 cafe->nand.block_bad = cafe_nand_block_bad;
725 }
726
727 if (numtimings && numtimings != 3) {
728 dev_warn(&cafe->pdev->dev, "%d timing register values ignored; precisely three are required\n", numtimings);
729 }
730
731 if (numtimings == 3) {
732 cafe_dev_dbg(&cafe->pdev->dev, "Using provided timings (%08x %08x %08x)\n",
733 timing[0], timing[1], timing[2]);
734 } else {
735 timing[0] = cafe_readl(cafe, NAND_TIMING1);
736 timing[1] = cafe_readl(cafe, NAND_TIMING2);
737 timing[2] = cafe_readl(cafe, NAND_TIMING3);
738
739 if (timing[0] | timing[1] | timing[2]) {
740 cafe_dev_dbg(&cafe->pdev->dev, "Timing registers already set (%08x %08x %08x)\n",
741 timing[0], timing[1], timing[2]);
742 } else {
743 dev_warn(&cafe->pdev->dev, "Timing registers unset; using most conservative defaults\n");
744 timing[0] = timing[1] = timing[2] = 0xffffffff;
745 }
746 }
747
748 /* Start off by resetting the NAND controller completely */
749 cafe_writel(cafe, 1, NAND_RESET);
750 cafe_writel(cafe, 0, NAND_RESET);
751
752 cafe_writel(cafe, timing[0], NAND_TIMING1);
753 cafe_writel(cafe, timing[1], NAND_TIMING2);
754 cafe_writel(cafe, timing[2], NAND_TIMING3);
755
756 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
757 err = request_irq(pdev->irq, &cafe_nand_interrupt, IRQF_SHARED,
758 "CAFE NAND", mtd);
759 if (err) {
760 dev_warn(&pdev->dev, "Could not register IRQ %d\n", pdev->irq);
761 goto out_ior;
762 }
763
764 /* Disable master reset, enable NAND clock */
765 ctrl = cafe_readl(cafe, GLOBAL_CTRL);
766 ctrl &= 0xffffeff0;
767 ctrl |= 0x00007000;
768 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
769 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
770 cafe_writel(cafe, 0, NAND_DMA_CTRL);
771
772 cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
773 cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
774
775 /* Enable NAND IRQ in global IRQ mask register */
776 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
777 cafe_dev_dbg(&cafe->pdev->dev, "Control %x, IRQ mask %x\n",
778 cafe_readl(cafe, GLOBAL_CTRL),
779 cafe_readl(cafe, GLOBAL_IRQ_MASK));
780
781 /* Do not use the DMA during the NAND identification */
782 cafe->usedma = 0;
783
784 /* Scan to find existence of the device */
785 cafe->nand.dummy_controller.ops = &cafe_nand_controller_ops;
786 err = nand_scan(mtd, 2);
787 if (err)
788 goto out_irq;
789
790 pci_set_drvdata(pdev, mtd);
791
792 mtd->name = "cafe_nand";
793 err = mtd_device_parse_register(mtd, part_probes, NULL, NULL, 0);
794 if (err)
795 goto out_cleanup_nand;
796
797 goto out;
798
799 out_cleanup_nand:
800 nand_cleanup(&cafe->nand);
801 out_irq:
802 /* Disable NAND IRQ in global IRQ mask register */
803 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
804 free_irq(pdev->irq, mtd);
805 out_ior:
806 pci_iounmap(pdev, cafe->mmio);
807 out_free_mtd:
808 kfree(cafe);
809 out:
810 return err;
811 }
812
cafe_nand_remove(struct pci_dev * pdev)813 static void cafe_nand_remove(struct pci_dev *pdev)
814 {
815 struct mtd_info *mtd = pci_get_drvdata(pdev);
816 struct nand_chip *chip = mtd_to_nand(mtd);
817 struct cafe_priv *cafe = nand_get_controller_data(chip);
818
819 /* Disable NAND IRQ in global IRQ mask register */
820 cafe_writel(cafe, ~1 & cafe_readl(cafe, GLOBAL_IRQ_MASK), GLOBAL_IRQ_MASK);
821 free_irq(pdev->irq, mtd);
822 nand_release(mtd);
823 free_rs(cafe->rs);
824 pci_iounmap(pdev, cafe->mmio);
825 dma_free_coherent(&cafe->pdev->dev, 2112, cafe->dmabuf, cafe->dmaaddr);
826 kfree(cafe);
827 }
828
829 static const struct pci_device_id cafe_nand_tbl[] = {
830 { PCI_VENDOR_ID_MARVELL, PCI_DEVICE_ID_MARVELL_88ALP01_NAND,
831 PCI_ANY_ID, PCI_ANY_ID },
832 { }
833 };
834
835 MODULE_DEVICE_TABLE(pci, cafe_nand_tbl);
836
cafe_nand_resume(struct pci_dev * pdev)837 static int cafe_nand_resume(struct pci_dev *pdev)
838 {
839 uint32_t ctrl;
840 struct mtd_info *mtd = pci_get_drvdata(pdev);
841 struct nand_chip *chip = mtd_to_nand(mtd);
842 struct cafe_priv *cafe = nand_get_controller_data(chip);
843
844 /* Start off by resetting the NAND controller completely */
845 cafe_writel(cafe, 1, NAND_RESET);
846 cafe_writel(cafe, 0, NAND_RESET);
847 cafe_writel(cafe, 0xffffffff, NAND_IRQ_MASK);
848
849 /* Restore timing configuration */
850 cafe_writel(cafe, timing[0], NAND_TIMING1);
851 cafe_writel(cafe, timing[1], NAND_TIMING2);
852 cafe_writel(cafe, timing[2], NAND_TIMING3);
853
854 /* Disable master reset, enable NAND clock */
855 ctrl = cafe_readl(cafe, GLOBAL_CTRL);
856 ctrl &= 0xffffeff0;
857 ctrl |= 0x00007000;
858 cafe_writel(cafe, ctrl | 0x05, GLOBAL_CTRL);
859 cafe_writel(cafe, ctrl | 0x0a, GLOBAL_CTRL);
860 cafe_writel(cafe, 0, NAND_DMA_CTRL);
861 cafe_writel(cafe, 0x7006, GLOBAL_CTRL);
862 cafe_writel(cafe, 0x700a, GLOBAL_CTRL);
863
864 /* Set up DMA address */
865 cafe_writel(cafe, cafe->dmaaddr & 0xffffffff, NAND_DMA_ADDR0);
866 if (sizeof(cafe->dmaaddr) > 4)
867 /* Shift in two parts to shut the compiler up */
868 cafe_writel(cafe, (cafe->dmaaddr >> 16) >> 16, NAND_DMA_ADDR1);
869 else
870 cafe_writel(cafe, 0, NAND_DMA_ADDR1);
871
872 /* Enable NAND IRQ in global IRQ mask register */
873 cafe_writel(cafe, 0x80000007, GLOBAL_IRQ_MASK);
874 return 0;
875 }
876
877 static struct pci_driver cafe_nand_pci_driver = {
878 .name = "CAFÉ NAND",
879 .id_table = cafe_nand_tbl,
880 .probe = cafe_nand_probe,
881 .remove = cafe_nand_remove,
882 .resume = cafe_nand_resume,
883 };
884
885 module_pci_driver(cafe_nand_pci_driver);
886
887 MODULE_LICENSE("GPL");
888 MODULE_AUTHOR("David Woodhouse <dwmw2@infradead.org>");
889 MODULE_DESCRIPTION("NAND flash driver for OLPC CAFÉ chip");
890
