1 /*
2 * linux/drivers/mmc/host/mmci.c - ARM PrimeCell MMCI PL180/1 driver
3 *
4 * Copyright (C) 2003 Deep Blue Solutions, Ltd, All Rights Reserved.
5 * Copyright (C) 2010 ST-Ericsson SA
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 */
11 #include <linux/module.h>
12 #include <linux/moduleparam.h>
13 #include <linux/init.h>
14 #include <linux/ioport.h>
15 #include <linux/device.h>
16 #include <linux/io.h>
17 #include <linux/interrupt.h>
18 #include <linux/kernel.h>
19 #include <linux/slab.h>
20 #include <linux/delay.h>
21 #include <linux/err.h>
22 #include <linux/highmem.h>
23 #include <linux/log2.h>
24 #include <linux/mmc/pm.h>
25 #include <linux/mmc/host.h>
26 #include <linux/mmc/card.h>
27 #include <linux/mmc/slot-gpio.h>
28 #include <linux/amba/bus.h>
29 #include <linux/clk.h>
30 #include <linux/scatterlist.h>
31 #include <linux/gpio.h>
32 #include <linux/of_gpio.h>
33 #include <linux/regulator/consumer.h>
34 #include <linux/dmaengine.h>
35 #include <linux/dma-mapping.h>
36 #include <linux/amba/mmci.h>
37 #include <linux/pm_runtime.h>
38 #include <linux/types.h>
39 #include <linux/pinctrl/consumer.h>
40
41 #include <asm/div64.h>
42 #include <asm/io.h>
43
44 #include "mmci.h"
45 #include "mmci_qcom_dml.h"
46
47 #define DRIVER_NAME "mmci-pl18x"
48
49 static unsigned int fmax = 515633;
50
51 static struct variant_data variant_arm = {
52 .fifosize = 16 * 4,
53 .fifohalfsize = 8 * 4,
54 .datalength_bits = 16,
55 .pwrreg_powerup = MCI_PWR_UP,
56 .f_max = 100000000,
57 .reversed_irq_handling = true,
58 .mmcimask1 = true,
59 .start_err = MCI_STARTBITERR,
60 .opendrain = MCI_ROD,
61 };
62
63 static struct variant_data variant_arm_extended_fifo = {
64 .fifosize = 128 * 4,
65 .fifohalfsize = 64 * 4,
66 .datalength_bits = 16,
67 .pwrreg_powerup = MCI_PWR_UP,
68 .f_max = 100000000,
69 .mmcimask1 = true,
70 .start_err = MCI_STARTBITERR,
71 .opendrain = MCI_ROD,
72 };
73
74 static struct variant_data variant_arm_extended_fifo_hwfc = {
75 .fifosize = 128 * 4,
76 .fifohalfsize = 64 * 4,
77 .clkreg_enable = MCI_ARM_HWFCEN,
78 .datalength_bits = 16,
79 .pwrreg_powerup = MCI_PWR_UP,
80 .f_max = 100000000,
81 .mmcimask1 = true,
82 .start_err = MCI_STARTBITERR,
83 .opendrain = MCI_ROD,
84 };
85
86 static struct variant_data variant_u300 = {
87 .fifosize = 16 * 4,
88 .fifohalfsize = 8 * 4,
89 .clkreg_enable = MCI_ST_U300_HWFCEN,
90 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
91 .datalength_bits = 16,
92 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
93 .st_sdio = true,
94 .pwrreg_powerup = MCI_PWR_ON,
95 .f_max = 100000000,
96 .signal_direction = true,
97 .pwrreg_clkgate = true,
98 .pwrreg_nopower = true,
99 .mmcimask1 = true,
100 .start_err = MCI_STARTBITERR,
101 .opendrain = MCI_OD,
102 };
103
104 static struct variant_data variant_nomadik = {
105 .fifosize = 16 * 4,
106 .fifohalfsize = 8 * 4,
107 .clkreg = MCI_CLK_ENABLE,
108 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
109 .datalength_bits = 24,
110 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
111 .st_sdio = true,
112 .st_clkdiv = true,
113 .pwrreg_powerup = MCI_PWR_ON,
114 .f_max = 100000000,
115 .signal_direction = true,
116 .pwrreg_clkgate = true,
117 .pwrreg_nopower = true,
118 .mmcimask1 = true,
119 .start_err = MCI_STARTBITERR,
120 .opendrain = MCI_OD,
121 };
122
123 static struct variant_data variant_ux500 = {
124 .fifosize = 30 * 4,
125 .fifohalfsize = 8 * 4,
126 .clkreg = MCI_CLK_ENABLE,
127 .clkreg_enable = MCI_ST_UX500_HWFCEN,
128 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
129 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
130 .datalength_bits = 24,
131 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
132 .st_sdio = true,
133 .st_clkdiv = true,
134 .pwrreg_powerup = MCI_PWR_ON,
135 .f_max = 100000000,
136 .signal_direction = true,
137 .pwrreg_clkgate = true,
138 .busy_detect = true,
139 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE,
140 .busy_detect_flag = MCI_ST_CARDBUSY,
141 .busy_detect_mask = MCI_ST_BUSYENDMASK,
142 .pwrreg_nopower = true,
143 .mmcimask1 = true,
144 .start_err = MCI_STARTBITERR,
145 .opendrain = MCI_OD,
146 };
147
148 static struct variant_data variant_ux500v2 = {
149 .fifosize = 30 * 4,
150 .fifohalfsize = 8 * 4,
151 .clkreg = MCI_CLK_ENABLE,
152 .clkreg_enable = MCI_ST_UX500_HWFCEN,
153 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
154 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
155 .datactrl_mask_ddrmode = MCI_DPSM_ST_DDRMODE,
156 .datalength_bits = 24,
157 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
158 .st_sdio = true,
159 .st_clkdiv = true,
160 .blksz_datactrl16 = true,
161 .pwrreg_powerup = MCI_PWR_ON,
162 .f_max = 100000000,
163 .signal_direction = true,
164 .pwrreg_clkgate = true,
165 .busy_detect = true,
166 .busy_dpsm_flag = MCI_DPSM_ST_BUSYMODE,
167 .busy_detect_flag = MCI_ST_CARDBUSY,
168 .busy_detect_mask = MCI_ST_BUSYENDMASK,
169 .pwrreg_nopower = true,
170 .mmcimask1 = true,
171 .start_err = MCI_STARTBITERR,
172 .opendrain = MCI_OD,
173 };
174
175 static struct variant_data variant_stm32 = {
176 .fifosize = 32 * 4,
177 .fifohalfsize = 8 * 4,
178 .clkreg = MCI_CLK_ENABLE,
179 .clkreg_enable = MCI_ST_UX500_HWFCEN,
180 .clkreg_8bit_bus_enable = MCI_ST_8BIT_BUS,
181 .clkreg_neg_edge_enable = MCI_ST_UX500_NEG_EDGE,
182 .datalength_bits = 24,
183 .datactrl_mask_sdio = MCI_DPSM_ST_SDIOEN,
184 .st_sdio = true,
185 .st_clkdiv = true,
186 .pwrreg_powerup = MCI_PWR_ON,
187 .f_max = 48000000,
188 .pwrreg_clkgate = true,
189 .pwrreg_nopower = true,
190 };
191
192 static struct variant_data variant_qcom = {
193 .fifosize = 16 * 4,
194 .fifohalfsize = 8 * 4,
195 .clkreg = MCI_CLK_ENABLE,
196 .clkreg_enable = MCI_QCOM_CLK_FLOWENA |
197 MCI_QCOM_CLK_SELECT_IN_FBCLK,
198 .clkreg_8bit_bus_enable = MCI_QCOM_CLK_WIDEBUS_8,
199 .datactrl_mask_ddrmode = MCI_QCOM_CLK_SELECT_IN_DDR_MODE,
200 .data_cmd_enable = MCI_CPSM_QCOM_DATCMD,
201 .blksz_datactrl4 = true,
202 .datalength_bits = 24,
203 .pwrreg_powerup = MCI_PWR_UP,
204 .f_max = 208000000,
205 .explicit_mclk_control = true,
206 .qcom_fifo = true,
207 .qcom_dml = true,
208 .mmcimask1 = true,
209 .start_err = MCI_STARTBITERR,
210 .opendrain = MCI_ROD,
211 .init = qcom_variant_init,
212 };
213
214 /* Busy detection for the ST Micro variant */
mmci_card_busy(struct mmc_host * mmc)215 static int mmci_card_busy(struct mmc_host *mmc)
216 {
217 struct mmci_host *host = mmc_priv(mmc);
218 unsigned long flags;
219 int busy = 0;
220
221 spin_lock_irqsave(&host->lock, flags);
222 if (readl(host->base + MMCISTATUS) & host->variant->busy_detect_flag)
223 busy = 1;
224 spin_unlock_irqrestore(&host->lock, flags);
225
226 return busy;
227 }
228
229 /*
230 * Validate mmc prerequisites
231 */
mmci_validate_data(struct mmci_host * host,struct mmc_data * data)232 static int mmci_validate_data(struct mmci_host *host,
233 struct mmc_data *data)
234 {
235 if (!data)
236 return 0;
237
238 if (!is_power_of_2(data->blksz)) {
239 dev_err(mmc_dev(host->mmc),
240 "unsupported block size (%d bytes)\n", data->blksz);
241 return -EINVAL;
242 }
243
244 return 0;
245 }
246
mmci_reg_delay(struct mmci_host * host)247 static void mmci_reg_delay(struct mmci_host *host)
248 {
249 /*
250 * According to the spec, at least three feedback clock cycles
251 * of max 52 MHz must pass between two writes to the MMCICLOCK reg.
252 * Three MCLK clock cycles must pass between two MMCIPOWER reg writes.
253 * Worst delay time during card init is at 100 kHz => 30 us.
254 * Worst delay time when up and running is at 25 MHz => 120 ns.
255 */
256 if (host->cclk < 25000000)
257 udelay(30);
258 else
259 ndelay(120);
260 }
261
262 /*
263 * This must be called with host->lock held
264 */
mmci_write_clkreg(struct mmci_host * host,u32 clk)265 static void mmci_write_clkreg(struct mmci_host *host, u32 clk)
266 {
267 if (host->clk_reg != clk) {
268 host->clk_reg = clk;
269 writel(clk, host->base + MMCICLOCK);
270 }
271 }
272
273 /*
274 * This must be called with host->lock held
275 */
mmci_write_pwrreg(struct mmci_host * host,u32 pwr)276 static void mmci_write_pwrreg(struct mmci_host *host, u32 pwr)
277 {
278 if (host->pwr_reg != pwr) {
279 host->pwr_reg = pwr;
280 writel(pwr, host->base + MMCIPOWER);
281 }
282 }
283
284 /*
285 * This must be called with host->lock held
286 */
mmci_write_datactrlreg(struct mmci_host * host,u32 datactrl)287 static void mmci_write_datactrlreg(struct mmci_host *host, u32 datactrl)
288 {
289 /* Keep busy mode in DPSM if enabled */
290 datactrl |= host->datactrl_reg & host->variant->busy_dpsm_flag;
291
292 if (host->datactrl_reg != datactrl) {
293 host->datactrl_reg = datactrl;
294 writel(datactrl, host->base + MMCIDATACTRL);
295 }
296 }
297
298 /*
299 * This must be called with host->lock held
300 */
mmci_set_clkreg(struct mmci_host * host,unsigned int desired)301 static void mmci_set_clkreg(struct mmci_host *host, unsigned int desired)
302 {
303 struct variant_data *variant = host->variant;
304 u32 clk = variant->clkreg;
305
306 /* Make sure cclk reflects the current calculated clock */
307 host->cclk = 0;
308
309 if (desired) {
310 if (variant->explicit_mclk_control) {
311 host->cclk = host->mclk;
312 } else if (desired >= host->mclk) {
313 clk = MCI_CLK_BYPASS;
314 if (variant->st_clkdiv)
315 clk |= MCI_ST_UX500_NEG_EDGE;
316 host->cclk = host->mclk;
317 } else if (variant->st_clkdiv) {
318 /*
319 * DB8500 TRM says f = mclk / (clkdiv + 2)
320 * => clkdiv = (mclk / f) - 2
321 * Round the divider up so we don't exceed the max
322 * frequency
323 */
324 clk = DIV_ROUND_UP(host->mclk, desired) - 2;
325 if (clk >= 256)
326 clk = 255;
327 host->cclk = host->mclk / (clk + 2);
328 } else {
329 /*
330 * PL180 TRM says f = mclk / (2 * (clkdiv + 1))
331 * => clkdiv = mclk / (2 * f) - 1
332 */
333 clk = host->mclk / (2 * desired) - 1;
334 if (clk >= 256)
335 clk = 255;
336 host->cclk = host->mclk / (2 * (clk + 1));
337 }
338
339 clk |= variant->clkreg_enable;
340 clk |= MCI_CLK_ENABLE;
341 /* This hasn't proven to be worthwhile */
342 /* clk |= MCI_CLK_PWRSAVE; */
343 }
344
345 /* Set actual clock for debug */
346 host->mmc->actual_clock = host->cclk;
347
348 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4)
349 clk |= MCI_4BIT_BUS;
350 if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_8)
351 clk |= variant->clkreg_8bit_bus_enable;
352
353 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
354 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
355 clk |= variant->clkreg_neg_edge_enable;
356
357 mmci_write_clkreg(host, clk);
358 }
359
360 static void
mmci_request_end(struct mmci_host * host,struct mmc_request * mrq)361 mmci_request_end(struct mmci_host *host, struct mmc_request *mrq)
362 {
363 writel(0, host->base + MMCICOMMAND);
364
365 BUG_ON(host->data);
366
367 host->mrq = NULL;
368 host->cmd = NULL;
369
370 mmc_request_done(host->mmc, mrq);
371 }
372
mmci_set_mask1(struct mmci_host * host,unsigned int mask)373 static void mmci_set_mask1(struct mmci_host *host, unsigned int mask)
374 {
375 void __iomem *base = host->base;
376 struct variant_data *variant = host->variant;
377
378 if (host->singleirq) {
379 unsigned int mask0 = readl(base + MMCIMASK0);
380
381 mask0 &= ~MCI_IRQ1MASK;
382 mask0 |= mask;
383
384 writel(mask0, base + MMCIMASK0);
385 }
386
387 if (variant->mmcimask1)
388 writel(mask, base + MMCIMASK1);
389
390 host->mask1_reg = mask;
391 }
392
mmci_stop_data(struct mmci_host * host)393 static void mmci_stop_data(struct mmci_host *host)
394 {
395 mmci_write_datactrlreg(host, 0);
396 mmci_set_mask1(host, 0);
397 host->data = NULL;
398 }
399
mmci_init_sg(struct mmci_host * host,struct mmc_data * data)400 static void mmci_init_sg(struct mmci_host *host, struct mmc_data *data)
401 {
402 unsigned int flags = SG_MITER_ATOMIC;
403
404 if (data->flags & MMC_DATA_READ)
405 flags |= SG_MITER_TO_SG;
406 else
407 flags |= SG_MITER_FROM_SG;
408
409 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags);
410 }
411
412 /*
413 * All the DMA operation mode stuff goes inside this ifdef.
414 * This assumes that you have a generic DMA device interface,
415 * no custom DMA interfaces are supported.
416 */
417 #ifdef CONFIG_DMA_ENGINE
mmci_dma_setup(struct mmci_host * host)418 static void mmci_dma_setup(struct mmci_host *host)
419 {
420 const char *rxname, *txname;
421
422 host->dma_rx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "rx");
423 host->dma_tx_channel = dma_request_slave_channel(mmc_dev(host->mmc), "tx");
424
425 /* initialize pre request cookie */
426 host->next_data.cookie = 1;
427
428 /*
429 * If only an RX channel is specified, the driver will
430 * attempt to use it bidirectionally, however if it is
431 * is specified but cannot be located, DMA will be disabled.
432 */
433 if (host->dma_rx_channel && !host->dma_tx_channel)
434 host->dma_tx_channel = host->dma_rx_channel;
435
436 if (host->dma_rx_channel)
437 rxname = dma_chan_name(host->dma_rx_channel);
438 else
439 rxname = "none";
440
441 if (host->dma_tx_channel)
442 txname = dma_chan_name(host->dma_tx_channel);
443 else
444 txname = "none";
445
446 dev_info(mmc_dev(host->mmc), "DMA channels RX %s, TX %s\n",
447 rxname, txname);
448
449 /*
450 * Limit the maximum segment size in any SG entry according to
451 * the parameters of the DMA engine device.
452 */
453 if (host->dma_tx_channel) {
454 struct device *dev = host->dma_tx_channel->device->dev;
455 unsigned int max_seg_size = dma_get_max_seg_size(dev);
456
457 if (max_seg_size < host->mmc->max_seg_size)
458 host->mmc->max_seg_size = max_seg_size;
459 }
460 if (host->dma_rx_channel) {
461 struct device *dev = host->dma_rx_channel->device->dev;
462 unsigned int max_seg_size = dma_get_max_seg_size(dev);
463
464 if (max_seg_size < host->mmc->max_seg_size)
465 host->mmc->max_seg_size = max_seg_size;
466 }
467
468 if (host->ops && host->ops->dma_setup)
469 host->ops->dma_setup(host);
470 }
471
472 /*
473 * This is used in or so inline it
474 * so it can be discarded.
475 */
mmci_dma_release(struct mmci_host * host)476 static inline void mmci_dma_release(struct mmci_host *host)
477 {
478 if (host->dma_rx_channel)
479 dma_release_channel(host->dma_rx_channel);
480 if (host->dma_tx_channel)
481 dma_release_channel(host->dma_tx_channel);
482 host->dma_rx_channel = host->dma_tx_channel = NULL;
483 }
484
mmci_dma_data_error(struct mmci_host * host)485 static void mmci_dma_data_error(struct mmci_host *host)
486 {
487 dev_err(mmc_dev(host->mmc), "error during DMA transfer!\n");
488 dmaengine_terminate_all(host->dma_current);
489 host->dma_in_progress = false;
490 host->dma_current = NULL;
491 host->dma_desc_current = NULL;
492 host->data->host_cookie = 0;
493 }
494
mmci_dma_unmap(struct mmci_host * host,struct mmc_data * data)495 static void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
496 {
497 struct dma_chan *chan;
498
499 if (data->flags & MMC_DATA_READ)
500 chan = host->dma_rx_channel;
501 else
502 chan = host->dma_tx_channel;
503
504 dma_unmap_sg(chan->device->dev, data->sg, data->sg_len,
505 mmc_get_dma_dir(data));
506 }
507
mmci_dma_finalize(struct mmci_host * host,struct mmc_data * data)508 static void mmci_dma_finalize(struct mmci_host *host, struct mmc_data *data)
509 {
510 u32 status;
511 int i;
512
513 /* Wait up to 1ms for the DMA to complete */
514 for (i = 0; ; i++) {
515 status = readl(host->base + MMCISTATUS);
516 if (!(status & MCI_RXDATAAVLBLMASK) || i >= 100)
517 break;
518 udelay(10);
519 }
520
521 /*
522 * Check to see whether we still have some data left in the FIFO -
523 * this catches DMA controllers which are unable to monitor the
524 * DMALBREQ and DMALSREQ signals while allowing us to DMA to non-
525 * contiguous buffers. On TX, we'll get a FIFO underrun error.
526 */
527 if (status & MCI_RXDATAAVLBLMASK) {
528 mmci_dma_data_error(host);
529 if (!data->error)
530 data->error = -EIO;
531 }
532
533 if (!data->host_cookie)
534 mmci_dma_unmap(host, data);
535
536 /*
537 * Use of DMA with scatter-gather is impossible.
538 * Give up with DMA and switch back to PIO mode.
539 */
540 if (status & MCI_RXDATAAVLBLMASK) {
541 dev_err(mmc_dev(host->mmc), "buggy DMA detected. Taking evasive action.\n");
542 mmci_dma_release(host);
543 }
544
545 host->dma_in_progress = false;
546 host->dma_current = NULL;
547 host->dma_desc_current = NULL;
548 }
549
550 /* prepares DMA channel and DMA descriptor, returns non-zero on failure */
__mmci_dma_prep_data(struct mmci_host * host,struct mmc_data * data,struct dma_chan ** dma_chan,struct dma_async_tx_descriptor ** dma_desc)551 static int __mmci_dma_prep_data(struct mmci_host *host, struct mmc_data *data,
552 struct dma_chan **dma_chan,
553 struct dma_async_tx_descriptor **dma_desc)
554 {
555 struct variant_data *variant = host->variant;
556 struct dma_slave_config conf = {
557 .src_addr = host->phybase + MMCIFIFO,
558 .dst_addr = host->phybase + MMCIFIFO,
559 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
560 .dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
561 .src_maxburst = variant->fifohalfsize >> 2, /* # of words */
562 .dst_maxburst = variant->fifohalfsize >> 2, /* # of words */
563 .device_fc = false,
564 };
565 struct dma_chan *chan;
566 struct dma_device *device;
567 struct dma_async_tx_descriptor *desc;
568 int nr_sg;
569 unsigned long flags = DMA_CTRL_ACK;
570
571 if (data->flags & MMC_DATA_READ) {
572 conf.direction = DMA_DEV_TO_MEM;
573 chan = host->dma_rx_channel;
574 } else {
575 conf.direction = DMA_MEM_TO_DEV;
576 chan = host->dma_tx_channel;
577 }
578
579 /* If there's no DMA channel, fall back to PIO */
580 if (!chan)
581 return -EINVAL;
582
583 /* If less than or equal to the fifo size, don't bother with DMA */
584 if (data->blksz * data->blocks <= variant->fifosize)
585 return -EINVAL;
586
587 device = chan->device;
588 nr_sg = dma_map_sg(device->dev, data->sg, data->sg_len,
589 mmc_get_dma_dir(data));
590 if (nr_sg == 0)
591 return -EINVAL;
592
593 if (host->variant->qcom_dml)
594 flags |= DMA_PREP_INTERRUPT;
595
596 dmaengine_slave_config(chan, &conf);
597 desc = dmaengine_prep_slave_sg(chan, data->sg, nr_sg,
598 conf.direction, flags);
599 if (!desc)
600 goto unmap_exit;
601
602 *dma_chan = chan;
603 *dma_desc = desc;
604
605 return 0;
606
607 unmap_exit:
608 dma_unmap_sg(device->dev, data->sg, data->sg_len,
609 mmc_get_dma_dir(data));
610 return -ENOMEM;
611 }
612
mmci_dma_prep_data(struct mmci_host * host,struct mmc_data * data)613 static inline int mmci_dma_prep_data(struct mmci_host *host,
614 struct mmc_data *data)
615 {
616 /* Check if next job is already prepared. */
617 if (host->dma_current && host->dma_desc_current)
618 return 0;
619
620 /* No job were prepared thus do it now. */
621 return __mmci_dma_prep_data(host, data, &host->dma_current,
622 &host->dma_desc_current);
623 }
624
mmci_dma_prep_next(struct mmci_host * host,struct mmc_data * data)625 static inline int mmci_dma_prep_next(struct mmci_host *host,
626 struct mmc_data *data)
627 {
628 struct mmci_host_next *nd = &host->next_data;
629 return __mmci_dma_prep_data(host, data, &nd->dma_chan, &nd->dma_desc);
630 }
631
mmci_dma_start_data(struct mmci_host * host,unsigned int datactrl)632 static int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
633 {
634 int ret;
635 struct mmc_data *data = host->data;
636
637 ret = mmci_dma_prep_data(host, host->data);
638 if (ret)
639 return ret;
640
641 /* Okay, go for it. */
642 dev_vdbg(mmc_dev(host->mmc),
643 "Submit MMCI DMA job, sglen %d blksz %04x blks %04x flags %08x\n",
644 data->sg_len, data->blksz, data->blocks, data->flags);
645 host->dma_in_progress = true;
646 dmaengine_submit(host->dma_desc_current);
647 dma_async_issue_pending(host->dma_current);
648
649 if (host->variant->qcom_dml)
650 dml_start_xfer(host, data);
651
652 datactrl |= MCI_DPSM_DMAENABLE;
653
654 /* Trigger the DMA transfer */
655 mmci_write_datactrlreg(host, datactrl);
656
657 /*
658 * Let the MMCI say when the data is ended and it's time
659 * to fire next DMA request. When that happens, MMCI will
660 * call mmci_data_end()
661 */
662 writel(readl(host->base + MMCIMASK0) | MCI_DATAENDMASK,
663 host->base + MMCIMASK0);
664 return 0;
665 }
666
mmci_get_next_data(struct mmci_host * host,struct mmc_data * data)667 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
668 {
669 struct mmci_host_next *next = &host->next_data;
670
671 WARN_ON(data->host_cookie && data->host_cookie != next->cookie);
672 WARN_ON(!data->host_cookie && (next->dma_desc || next->dma_chan));
673
674 host->dma_desc_current = next->dma_desc;
675 host->dma_current = next->dma_chan;
676 next->dma_desc = NULL;
677 next->dma_chan = NULL;
678 }
679
mmci_pre_request(struct mmc_host * mmc,struct mmc_request * mrq)680 static void mmci_pre_request(struct mmc_host *mmc, struct mmc_request *mrq)
681 {
682 struct mmci_host *host = mmc_priv(mmc);
683 struct mmc_data *data = mrq->data;
684 struct mmci_host_next *nd = &host->next_data;
685
686 if (!data)
687 return;
688
689 BUG_ON(data->host_cookie);
690
691 if (mmci_validate_data(host, data))
692 return;
693
694 if (!mmci_dma_prep_next(host, data))
695 data->host_cookie = ++nd->cookie < 0 ? 1 : nd->cookie;
696 }
697
mmci_post_request(struct mmc_host * mmc,struct mmc_request * mrq,int err)698 static void mmci_post_request(struct mmc_host *mmc, struct mmc_request *mrq,
699 int err)
700 {
701 struct mmci_host *host = mmc_priv(mmc);
702 struct mmc_data *data = mrq->data;
703
704 if (!data || !data->host_cookie)
705 return;
706
707 mmci_dma_unmap(host, data);
708
709 if (err) {
710 struct mmci_host_next *next = &host->next_data;
711 struct dma_chan *chan;
712 if (data->flags & MMC_DATA_READ)
713 chan = host->dma_rx_channel;
714 else
715 chan = host->dma_tx_channel;
716 dmaengine_terminate_all(chan);
717
718 if (host->dma_desc_current == next->dma_desc)
719 host->dma_desc_current = NULL;
720
721 if (host->dma_current == next->dma_chan) {
722 host->dma_in_progress = false;
723 host->dma_current = NULL;
724 }
725
726 next->dma_desc = NULL;
727 next->dma_chan = NULL;
728 data->host_cookie = 0;
729 }
730 }
731
732 #else
733 /* Blank functions if the DMA engine is not available */
mmci_get_next_data(struct mmci_host * host,struct mmc_data * data)734 static void mmci_get_next_data(struct mmci_host *host, struct mmc_data *data)
735 {
736 }
mmci_dma_setup(struct mmci_host * host)737 static inline void mmci_dma_setup(struct mmci_host *host)
738 {
739 }
740
mmci_dma_release(struct mmci_host * host)741 static inline void mmci_dma_release(struct mmci_host *host)
742 {
743 }
744
mmci_dma_unmap(struct mmci_host * host,struct mmc_data * data)745 static inline void mmci_dma_unmap(struct mmci_host *host, struct mmc_data *data)
746 {
747 }
748
mmci_dma_finalize(struct mmci_host * host,struct mmc_data * data)749 static inline void mmci_dma_finalize(struct mmci_host *host,
750 struct mmc_data *data)
751 {
752 }
753
mmci_dma_data_error(struct mmci_host * host)754 static inline void mmci_dma_data_error(struct mmci_host *host)
755 {
756 }
757
mmci_dma_start_data(struct mmci_host * host,unsigned int datactrl)758 static inline int mmci_dma_start_data(struct mmci_host *host, unsigned int datactrl)
759 {
760 return -ENOSYS;
761 }
762
763 #define mmci_pre_request NULL
764 #define mmci_post_request NULL
765
766 #endif
767
mmci_start_data(struct mmci_host * host,struct mmc_data * data)768 static void mmci_start_data(struct mmci_host *host, struct mmc_data *data)
769 {
770 struct variant_data *variant = host->variant;
771 unsigned int datactrl, timeout, irqmask;
772 unsigned long long clks;
773 void __iomem *base;
774 int blksz_bits;
775
776 dev_dbg(mmc_dev(host->mmc), "blksz %04x blks %04x flags %08x\n",
777 data->blksz, data->blocks, data->flags);
778
779 host->data = data;
780 host->size = data->blksz * data->blocks;
781 data->bytes_xfered = 0;
782
783 clks = (unsigned long long)data->timeout_ns * host->cclk;
784 do_div(clks, NSEC_PER_SEC);
785
786 timeout = data->timeout_clks + (unsigned int)clks;
787
788 base = host->base;
789 writel(timeout, base + MMCIDATATIMER);
790 writel(host->size, base + MMCIDATALENGTH);
791
792 blksz_bits = ffs(data->blksz) - 1;
793 BUG_ON(1 << blksz_bits != data->blksz);
794
795 if (variant->blksz_datactrl16)
796 datactrl = MCI_DPSM_ENABLE | (data->blksz << 16);
797 else if (variant->blksz_datactrl4)
798 datactrl = MCI_DPSM_ENABLE | (data->blksz << 4);
799 else
800 datactrl = MCI_DPSM_ENABLE | blksz_bits << 4;
801
802 if (data->flags & MMC_DATA_READ)
803 datactrl |= MCI_DPSM_DIRECTION;
804
805 if (host->mmc->card && mmc_card_sdio(host->mmc->card)) {
806 u32 clk;
807
808 datactrl |= variant->datactrl_mask_sdio;
809
810 /*
811 * The ST Micro variant for SDIO small write transfers
812 * needs to have clock H/W flow control disabled,
813 * otherwise the transfer will not start. The threshold
814 * depends on the rate of MCLK.
815 */
816 if (variant->st_sdio && data->flags & MMC_DATA_WRITE &&
817 (host->size < 8 ||
818 (host->size <= 8 && host->mclk > 50000000)))
819 clk = host->clk_reg & ~variant->clkreg_enable;
820 else
821 clk = host->clk_reg | variant->clkreg_enable;
822
823 mmci_write_clkreg(host, clk);
824 }
825
826 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 ||
827 host->mmc->ios.timing == MMC_TIMING_MMC_DDR52)
828 datactrl |= variant->datactrl_mask_ddrmode;
829
830 /*
831 * Attempt to use DMA operation mode, if this
832 * should fail, fall back to PIO mode
833 */
834 if (!mmci_dma_start_data(host, datactrl))
835 return;
836
837 /* IRQ mode, map the SG list for CPU reading/writing */
838 mmci_init_sg(host, data);
839
840 if (data->flags & MMC_DATA_READ) {
841 irqmask = MCI_RXFIFOHALFFULLMASK;
842
843 /*
844 * If we have less than the fifo 'half-full' threshold to
845 * transfer, trigger a PIO interrupt as soon as any data
846 * is available.
847 */
848 if (host->size < variant->fifohalfsize)
849 irqmask |= MCI_RXDATAAVLBLMASK;
850 } else {
851 /*
852 * We don't actually need to include "FIFO empty" here
853 * since its implicit in "FIFO half empty".
854 */
855 irqmask = MCI_TXFIFOHALFEMPTYMASK;
856 }
857
858 mmci_write_datactrlreg(host, datactrl);
859 writel(readl(base + MMCIMASK0) & ~MCI_DATAENDMASK, base + MMCIMASK0);
860 mmci_set_mask1(host, irqmask);
861 }
862
863 static void
mmci_start_command(struct mmci_host * host,struct mmc_command * cmd,u32 c)864 mmci_start_command(struct mmci_host *host, struct mmc_command *cmd, u32 c)
865 {
866 void __iomem *base = host->base;
867
868 dev_dbg(mmc_dev(host->mmc), "op %02x arg %08x flags %08x\n",
869 cmd->opcode, cmd->arg, cmd->flags);
870
871 if (readl(base + MMCICOMMAND) & MCI_CPSM_ENABLE) {
872 writel(0, base + MMCICOMMAND);
873 mmci_reg_delay(host);
874 }
875
876 c |= cmd->opcode | MCI_CPSM_ENABLE;
877 if (cmd->flags & MMC_RSP_PRESENT) {
878 if (cmd->flags & MMC_RSP_136)
879 c |= MCI_CPSM_LONGRSP;
880 c |= MCI_CPSM_RESPONSE;
881 }
882 if (/*interrupt*/0)
883 c |= MCI_CPSM_INTERRUPT;
884
885 if (mmc_cmd_type(cmd) == MMC_CMD_ADTC)
886 c |= host->variant->data_cmd_enable;
887
888 host->cmd = cmd;
889
890 writel(cmd->arg, base + MMCIARGUMENT);
891 writel(c, base + MMCICOMMAND);
892 }
893
894 static void
mmci_data_irq(struct mmci_host * host,struct mmc_data * data,unsigned int status)895 mmci_data_irq(struct mmci_host *host, struct mmc_data *data,
896 unsigned int status)
897 {
898 /* Make sure we have data to handle */
899 if (!data)
900 return;
901
902 /* First check for errors */
903 if (status & (MCI_DATACRCFAIL | MCI_DATATIMEOUT |
904 host->variant->start_err |
905 MCI_TXUNDERRUN | MCI_RXOVERRUN)) {
906 u32 remain, success;
907
908 /* Terminate the DMA transfer */
909 if (dma_inprogress(host)) {
910 mmci_dma_data_error(host);
911 mmci_dma_unmap(host, data);
912 }
913
914 /*
915 * Calculate how far we are into the transfer. Note that
916 * the data counter gives the number of bytes transferred
917 * on the MMC bus, not on the host side. On reads, this
918 * can be as much as a FIFO-worth of data ahead. This
919 * matters for FIFO overruns only.
920 */
921 remain = readl(host->base + MMCIDATACNT);
922 success = data->blksz * data->blocks - remain;
923
924 dev_dbg(mmc_dev(host->mmc), "MCI ERROR IRQ, status 0x%08x at 0x%08x\n",
925 status, success);
926 if (status & MCI_DATACRCFAIL) {
927 /* Last block was not successful */
928 success -= 1;
929 data->error = -EILSEQ;
930 } else if (status & MCI_DATATIMEOUT) {
931 data->error = -ETIMEDOUT;
932 } else if (status & MCI_STARTBITERR) {
933 data->error = -ECOMM;
934 } else if (status & MCI_TXUNDERRUN) {
935 data->error = -EIO;
936 } else if (status & MCI_RXOVERRUN) {
937 if (success > host->variant->fifosize)
938 success -= host->variant->fifosize;
939 else
940 success = 0;
941 data->error = -EIO;
942 }
943 data->bytes_xfered = round_down(success, data->blksz);
944 }
945
946 if (status & MCI_DATABLOCKEND)
947 dev_err(mmc_dev(host->mmc), "stray MCI_DATABLOCKEND interrupt\n");
948
949 if (status & MCI_DATAEND || data->error) {
950 if (dma_inprogress(host))
951 mmci_dma_finalize(host, data);
952 mmci_stop_data(host);
953
954 if (!data->error)
955 /* The error clause is handled above, success! */
956 data->bytes_xfered = data->blksz * data->blocks;
957
958 if (!data->stop || host->mrq->sbc) {
959 mmci_request_end(host, data->mrq);
960 } else {
961 mmci_start_command(host, data->stop, 0);
962 }
963 }
964 }
965
966 static void
mmci_cmd_irq(struct mmci_host * host,struct mmc_command * cmd,unsigned int status)967 mmci_cmd_irq(struct mmci_host *host, struct mmc_command *cmd,
968 unsigned int status)
969 {
970 void __iomem *base = host->base;
971 bool sbc;
972
973 if (!cmd)
974 return;
975
976 sbc = (cmd == host->mrq->sbc);
977
978 /*
979 * We need to be one of these interrupts to be considered worth
980 * handling. Note that we tag on any latent IRQs postponed
981 * due to waiting for busy status.
982 */
983 if (!((status|host->busy_status) &
984 (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT|MCI_CMDSENT|MCI_CMDRESPEND)))
985 return;
986
987 /*
988 * ST Micro variant: handle busy detection.
989 */
990 if (host->variant->busy_detect) {
991 bool busy_resp = !!(cmd->flags & MMC_RSP_BUSY);
992
993 /* We are busy with a command, return */
994 if (host->busy_status &&
995 (status & host->variant->busy_detect_flag))
996 return;
997
998 /*
999 * We were not busy, but we now got a busy response on
1000 * something that was not an error, and we double-check
1001 * that the special busy status bit is still set before
1002 * proceeding.
1003 */
1004 if (!host->busy_status && busy_resp &&
1005 !(status & (MCI_CMDCRCFAIL|MCI_CMDTIMEOUT)) &&
1006 (readl(base + MMCISTATUS) & host->variant->busy_detect_flag)) {
1007
1008 /* Clear the busy start IRQ */
1009 writel(host->variant->busy_detect_mask,
1010 host->base + MMCICLEAR);
1011
1012 /* Unmask the busy end IRQ */
1013 writel(readl(base + MMCIMASK0) |
1014 host->variant->busy_detect_mask,
1015 base + MMCIMASK0);
1016 /*
1017 * Now cache the last response status code (until
1018 * the busy bit goes low), and return.
1019 */
1020 host->busy_status =
1021 status & (MCI_CMDSENT|MCI_CMDRESPEND);
1022 return;
1023 }
1024
1025 /*
1026 * At this point we are not busy with a command, we have
1027 * not received a new busy request, clear and mask the busy
1028 * end IRQ and fall through to process the IRQ.
1029 */
1030 if (host->busy_status) {
1031
1032 writel(host->variant->busy_detect_mask,
1033 host->base + MMCICLEAR);
1034
1035 writel(readl(base + MMCIMASK0) &
1036 ~host->variant->busy_detect_mask,
1037 base + MMCIMASK0);
1038 host->busy_status = 0;
1039 }
1040 }
1041
1042 host->cmd = NULL;
1043
1044 if (status & MCI_CMDTIMEOUT) {
1045 cmd->error = -ETIMEDOUT;
1046 } else if (status & MCI_CMDCRCFAIL && cmd->flags & MMC_RSP_CRC) {
1047 cmd->error = -EILSEQ;
1048 } else {
1049 cmd->resp[0] = readl(base + MMCIRESPONSE0);
1050 cmd->resp[1] = readl(base + MMCIRESPONSE1);
1051 cmd->resp[2] = readl(base + MMCIRESPONSE2);
1052 cmd->resp[3] = readl(base + MMCIRESPONSE3);
1053 }
1054
1055 if ((!sbc && !cmd->data) || cmd->error) {
1056 if (host->data) {
1057 /* Terminate the DMA transfer */
1058 if (dma_inprogress(host)) {
1059 mmci_dma_data_error(host);
1060 mmci_dma_unmap(host, host->data);
1061 }
1062 mmci_stop_data(host);
1063 }
1064 mmci_request_end(host, host->mrq);
1065 } else if (sbc) {
1066 mmci_start_command(host, host->mrq->cmd, 0);
1067 } else if (!(cmd->data->flags & MMC_DATA_READ)) {
1068 mmci_start_data(host, cmd->data);
1069 }
1070 }
1071
mmci_get_rx_fifocnt(struct mmci_host * host,u32 status,int remain)1072 static int mmci_get_rx_fifocnt(struct mmci_host *host, u32 status, int remain)
1073 {
1074 return remain - (readl(host->base + MMCIFIFOCNT) << 2);
1075 }
1076
mmci_qcom_get_rx_fifocnt(struct mmci_host * host,u32 status,int r)1077 static int mmci_qcom_get_rx_fifocnt(struct mmci_host *host, u32 status, int r)
1078 {
1079 /*
1080 * on qcom SDCC4 only 8 words are used in each burst so only 8 addresses
1081 * from the fifo range should be used
1082 */
1083 if (status & MCI_RXFIFOHALFFULL)
1084 return host->variant->fifohalfsize;
1085 else if (status & MCI_RXDATAAVLBL)
1086 return 4;
1087
1088 return 0;
1089 }
1090
mmci_pio_read(struct mmci_host * host,char * buffer,unsigned int remain)1091 static int mmci_pio_read(struct mmci_host *host, char *buffer, unsigned int remain)
1092 {
1093 void __iomem *base = host->base;
1094 char *ptr = buffer;
1095 u32 status = readl(host->base + MMCISTATUS);
1096 int host_remain = host->size;
1097
1098 do {
1099 int count = host->get_rx_fifocnt(host, status, host_remain);
1100
1101 if (count > remain)
1102 count = remain;
1103
1104 if (count <= 0)
1105 break;
1106
1107 /*
1108 * SDIO especially may want to send something that is
1109 * not divisible by 4 (as opposed to card sectors
1110 * etc). Therefore make sure to always read the last bytes
1111 * while only doing full 32-bit reads towards the FIFO.
1112 */
1113 if (unlikely(count & 0x3)) {
1114 if (count < 4) {
1115 unsigned char buf[4];
1116 ioread32_rep(base + MMCIFIFO, buf, 1);
1117 memcpy(ptr, buf, count);
1118 } else {
1119 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
1120 count &= ~0x3;
1121 }
1122 } else {
1123 ioread32_rep(base + MMCIFIFO, ptr, count >> 2);
1124 }
1125
1126 ptr += count;
1127 remain -= count;
1128 host_remain -= count;
1129
1130 if (remain == 0)
1131 break;
1132
1133 status = readl(base + MMCISTATUS);
1134 } while (status & MCI_RXDATAAVLBL);
1135
1136 return ptr - buffer;
1137 }
1138
mmci_pio_write(struct mmci_host * host,char * buffer,unsigned int remain,u32 status)1139 static int mmci_pio_write(struct mmci_host *host, char *buffer, unsigned int remain, u32 status)
1140 {
1141 struct variant_data *variant = host->variant;
1142 void __iomem *base = host->base;
1143 char *ptr = buffer;
1144
1145 do {
1146 unsigned int count, maxcnt;
1147
1148 maxcnt = status & MCI_TXFIFOEMPTY ?
1149 variant->fifosize : variant->fifohalfsize;
1150 count = min(remain, maxcnt);
1151
1152 /*
1153 * SDIO especially may want to send something that is
1154 * not divisible by 4 (as opposed to card sectors
1155 * etc), and the FIFO only accept full 32-bit writes.
1156 * So compensate by adding +3 on the count, a single
1157 * byte become a 32bit write, 7 bytes will be two
1158 * 32bit writes etc.
1159 */
1160 iowrite32_rep(base + MMCIFIFO, ptr, (count + 3) >> 2);
1161
1162 ptr += count;
1163 remain -= count;
1164
1165 if (remain == 0)
1166 break;
1167
1168 status = readl(base + MMCISTATUS);
1169 } while (status & MCI_TXFIFOHALFEMPTY);
1170
1171 return ptr - buffer;
1172 }
1173
1174 /*
1175 * PIO data transfer IRQ handler.
1176 */
mmci_pio_irq(int irq,void * dev_id)1177 static irqreturn_t mmci_pio_irq(int irq, void *dev_id)
1178 {
1179 struct mmci_host *host = dev_id;
1180 struct sg_mapping_iter *sg_miter = &host->sg_miter;
1181 struct variant_data *variant = host->variant;
1182 void __iomem *base = host->base;
1183 u32 status;
1184
1185 status = readl(base + MMCISTATUS);
1186
1187 dev_dbg(mmc_dev(host->mmc), "irq1 (pio) %08x\n", status);
1188
1189 do {
1190 unsigned int remain, len;
1191 char *buffer;
1192
1193 /*
1194 * For write, we only need to test the half-empty flag
1195 * here - if the FIFO is completely empty, then by
1196 * definition it is more than half empty.
1197 *
1198 * For read, check for data available.
1199 */
1200 if (!(status & (MCI_TXFIFOHALFEMPTY|MCI_RXDATAAVLBL)))
1201 break;
1202
1203 if (!sg_miter_next(sg_miter))
1204 break;
1205
1206 buffer = sg_miter->addr;
1207 remain = sg_miter->length;
1208
1209 len = 0;
1210 if (status & MCI_RXACTIVE)
1211 len = mmci_pio_read(host, buffer, remain);
1212 if (status & MCI_TXACTIVE)
1213 len = mmci_pio_write(host, buffer, remain, status);
1214
1215 sg_miter->consumed = len;
1216
1217 host->size -= len;
1218 remain -= len;
1219
1220 if (remain)
1221 break;
1222
1223 status = readl(base + MMCISTATUS);
1224 } while (1);
1225
1226 sg_miter_stop(sg_miter);
1227
1228 /*
1229 * If we have less than the fifo 'half-full' threshold to transfer,
1230 * trigger a PIO interrupt as soon as any data is available.
1231 */
1232 if (status & MCI_RXACTIVE && host->size < variant->fifohalfsize)
1233 mmci_set_mask1(host, MCI_RXDATAAVLBLMASK);
1234
1235 /*
1236 * If we run out of data, disable the data IRQs; this
1237 * prevents a race where the FIFO becomes empty before
1238 * the chip itself has disabled the data path, and
1239 * stops us racing with our data end IRQ.
1240 */
1241 if (host->size == 0) {
1242 mmci_set_mask1(host, 0);
1243 writel(readl(base + MMCIMASK0) | MCI_DATAENDMASK, base + MMCIMASK0);
1244 }
1245
1246 return IRQ_HANDLED;
1247 }
1248
1249 /*
1250 * Handle completion of command and data transfers.
1251 */
mmci_irq(int irq,void * dev_id)1252 static irqreturn_t mmci_irq(int irq, void *dev_id)
1253 {
1254 struct mmci_host *host = dev_id;
1255 u32 status;
1256 int ret = 0;
1257
1258 spin_lock(&host->lock);
1259
1260 do {
1261 status = readl(host->base + MMCISTATUS);
1262
1263 if (host->singleirq) {
1264 if (status & host->mask1_reg)
1265 mmci_pio_irq(irq, dev_id);
1266
1267 status &= ~MCI_IRQ1MASK;
1268 }
1269
1270 /*
1271 * We intentionally clear the MCI_ST_CARDBUSY IRQ (if it's
1272 * enabled) in mmci_cmd_irq() function where ST Micro busy
1273 * detection variant is handled. Considering the HW seems to be
1274 * triggering the IRQ on both edges while monitoring DAT0 for
1275 * busy completion and that same status bit is used to monitor
1276 * start and end of busy detection, special care must be taken
1277 * to make sure that both start and end interrupts are always
1278 * cleared one after the other.
1279 */
1280 status &= readl(host->base + MMCIMASK0);
1281 if (host->variant->busy_detect)
1282 writel(status & ~host->variant->busy_detect_mask,
1283 host->base + MMCICLEAR);
1284 else
1285 writel(status, host->base + MMCICLEAR);
1286
1287 dev_dbg(mmc_dev(host->mmc), "irq0 (data+cmd) %08x\n", status);
1288
1289 if (host->variant->reversed_irq_handling) {
1290 mmci_data_irq(host, host->data, status);
1291 mmci_cmd_irq(host, host->cmd, status);
1292 } else {
1293 mmci_cmd_irq(host, host->cmd, status);
1294 mmci_data_irq(host, host->data, status);
1295 }
1296
1297 /*
1298 * Don't poll for busy completion in irq context.
1299 */
1300 if (host->variant->busy_detect && host->busy_status)
1301 status &= ~host->variant->busy_detect_flag;
1302
1303 ret = 1;
1304 } while (status);
1305
1306 spin_unlock(&host->lock);
1307
1308 return IRQ_RETVAL(ret);
1309 }
1310
mmci_request(struct mmc_host * mmc,struct mmc_request * mrq)1311 static void mmci_request(struct mmc_host *mmc, struct mmc_request *mrq)
1312 {
1313 struct mmci_host *host = mmc_priv(mmc);
1314 unsigned long flags;
1315
1316 WARN_ON(host->mrq != NULL);
1317
1318 mrq->cmd->error = mmci_validate_data(host, mrq->data);
1319 if (mrq->cmd->error) {
1320 mmc_request_done(mmc, mrq);
1321 return;
1322 }
1323
1324 spin_lock_irqsave(&host->lock, flags);
1325
1326 host->mrq = mrq;
1327
1328 if (mrq->data)
1329 mmci_get_next_data(host, mrq->data);
1330
1331 if (mrq->data && mrq->data->flags & MMC_DATA_READ)
1332 mmci_start_data(host, mrq->data);
1333
1334 if (mrq->sbc)
1335 mmci_start_command(host, mrq->sbc, 0);
1336 else
1337 mmci_start_command(host, mrq->cmd, 0);
1338
1339 spin_unlock_irqrestore(&host->lock, flags);
1340 }
1341
mmci_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)1342 static void mmci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1343 {
1344 struct mmci_host *host = mmc_priv(mmc);
1345 struct variant_data *variant = host->variant;
1346 u32 pwr = 0;
1347 unsigned long flags;
1348 int ret;
1349
1350 if (host->plat->ios_handler &&
1351 host->plat->ios_handler(mmc_dev(mmc), ios))
1352 dev_err(mmc_dev(mmc), "platform ios_handler failed\n");
1353
1354 switch (ios->power_mode) {
1355 case MMC_POWER_OFF:
1356 if (!IS_ERR(mmc->supply.vmmc))
1357 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
1358
1359 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) {
1360 regulator_disable(mmc->supply.vqmmc);
1361 host->vqmmc_enabled = false;
1362 }
1363
1364 break;
1365 case MMC_POWER_UP:
1366 if (!IS_ERR(mmc->supply.vmmc))
1367 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1368
1369 /*
1370 * The ST Micro variant doesn't have the PL180s MCI_PWR_UP
1371 * and instead uses MCI_PWR_ON so apply whatever value is
1372 * configured in the variant data.
1373 */
1374 pwr |= variant->pwrreg_powerup;
1375
1376 break;
1377 case MMC_POWER_ON:
1378 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) {
1379 ret = regulator_enable(mmc->supply.vqmmc);
1380 if (ret < 0)
1381 dev_err(mmc_dev(mmc),
1382 "failed to enable vqmmc regulator\n");
1383 else
1384 host->vqmmc_enabled = true;
1385 }
1386
1387 pwr |= MCI_PWR_ON;
1388 break;
1389 }
1390
1391 if (variant->signal_direction && ios->power_mode != MMC_POWER_OFF) {
1392 /*
1393 * The ST Micro variant has some additional bits
1394 * indicating signal direction for the signals in
1395 * the SD/MMC bus and feedback-clock usage.
1396 */
1397 pwr |= host->pwr_reg_add;
1398
1399 if (ios->bus_width == MMC_BUS_WIDTH_4)
1400 pwr &= ~MCI_ST_DATA74DIREN;
1401 else if (ios->bus_width == MMC_BUS_WIDTH_1)
1402 pwr &= (~MCI_ST_DATA74DIREN &
1403 ~MCI_ST_DATA31DIREN &
1404 ~MCI_ST_DATA2DIREN);
1405 }
1406
1407 if (variant->opendrain) {
1408 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1409 pwr |= variant->opendrain;
1410 } else {
1411 /*
1412 * If the variant cannot configure the pads by its own, then we
1413 * expect the pinctrl to be able to do that for us
1414 */
1415 if (ios->bus_mode == MMC_BUSMODE_OPENDRAIN)
1416 pinctrl_select_state(host->pinctrl, host->pins_opendrain);
1417 else
1418 pinctrl_select_state(host->pinctrl, host->pins_default);
1419 }
1420
1421 /*
1422 * If clock = 0 and the variant requires the MMCIPOWER to be used for
1423 * gating the clock, the MCI_PWR_ON bit is cleared.
1424 */
1425 if (!ios->clock && variant->pwrreg_clkgate)
1426 pwr &= ~MCI_PWR_ON;
1427
1428 if (host->variant->explicit_mclk_control &&
1429 ios->clock != host->clock_cache) {
1430 ret = clk_set_rate(host->clk, ios->clock);
1431 if (ret < 0)
1432 dev_err(mmc_dev(host->mmc),
1433 "Error setting clock rate (%d)\n", ret);
1434 else
1435 host->mclk = clk_get_rate(host->clk);
1436 }
1437 host->clock_cache = ios->clock;
1438
1439 spin_lock_irqsave(&host->lock, flags);
1440
1441 mmci_set_clkreg(host, ios->clock);
1442 mmci_write_pwrreg(host, pwr);
1443 mmci_reg_delay(host);
1444
1445 spin_unlock_irqrestore(&host->lock, flags);
1446 }
1447
mmci_get_cd(struct mmc_host * mmc)1448 static int mmci_get_cd(struct mmc_host *mmc)
1449 {
1450 struct mmci_host *host = mmc_priv(mmc);
1451 struct mmci_platform_data *plat = host->plat;
1452 unsigned int status = mmc_gpio_get_cd(mmc);
1453
1454 if (status == -ENOSYS) {
1455 if (!plat->status)
1456 return 1; /* Assume always present */
1457
1458 status = plat->status(mmc_dev(host->mmc));
1459 }
1460 return status;
1461 }
1462
mmci_sig_volt_switch(struct mmc_host * mmc,struct mmc_ios * ios)1463 static int mmci_sig_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios)
1464 {
1465 int ret = 0;
1466
1467 if (!IS_ERR(mmc->supply.vqmmc)) {
1468
1469 switch (ios->signal_voltage) {
1470 case MMC_SIGNAL_VOLTAGE_330:
1471 ret = regulator_set_voltage(mmc->supply.vqmmc,
1472 2700000, 3600000);
1473 break;
1474 case MMC_SIGNAL_VOLTAGE_180:
1475 ret = regulator_set_voltage(mmc->supply.vqmmc,
1476 1700000, 1950000);
1477 break;
1478 case MMC_SIGNAL_VOLTAGE_120:
1479 ret = regulator_set_voltage(mmc->supply.vqmmc,
1480 1100000, 1300000);
1481 break;
1482 }
1483
1484 if (ret)
1485 dev_warn(mmc_dev(mmc), "Voltage switch failed\n");
1486 }
1487
1488 return ret;
1489 }
1490
1491 static struct mmc_host_ops mmci_ops = {
1492 .request = mmci_request,
1493 .pre_req = mmci_pre_request,
1494 .post_req = mmci_post_request,
1495 .set_ios = mmci_set_ios,
1496 .get_ro = mmc_gpio_get_ro,
1497 .get_cd = mmci_get_cd,
1498 .start_signal_voltage_switch = mmci_sig_volt_switch,
1499 };
1500
mmci_of_parse(struct device_node * np,struct mmc_host * mmc)1501 static int mmci_of_parse(struct device_node *np, struct mmc_host *mmc)
1502 {
1503 struct mmci_host *host = mmc_priv(mmc);
1504 int ret = mmc_of_parse(mmc);
1505
1506 if (ret)
1507 return ret;
1508
1509 if (of_get_property(np, "st,sig-dir-dat0", NULL))
1510 host->pwr_reg_add |= MCI_ST_DATA0DIREN;
1511 if (of_get_property(np, "st,sig-dir-dat2", NULL))
1512 host->pwr_reg_add |= MCI_ST_DATA2DIREN;
1513 if (of_get_property(np, "st,sig-dir-dat31", NULL))
1514 host->pwr_reg_add |= MCI_ST_DATA31DIREN;
1515 if (of_get_property(np, "st,sig-dir-dat74", NULL))
1516 host->pwr_reg_add |= MCI_ST_DATA74DIREN;
1517 if (of_get_property(np, "st,sig-dir-cmd", NULL))
1518 host->pwr_reg_add |= MCI_ST_CMDDIREN;
1519 if (of_get_property(np, "st,sig-pin-fbclk", NULL))
1520 host->pwr_reg_add |= MCI_ST_FBCLKEN;
1521
1522 if (of_get_property(np, "mmc-cap-mmc-highspeed", NULL))
1523 mmc->caps |= MMC_CAP_MMC_HIGHSPEED;
1524 if (of_get_property(np, "mmc-cap-sd-highspeed", NULL))
1525 mmc->caps |= MMC_CAP_SD_HIGHSPEED;
1526
1527 return 0;
1528 }
1529
mmci_probe(struct amba_device * dev,const struct amba_id * id)1530 static int mmci_probe(struct amba_device *dev,
1531 const struct amba_id *id)
1532 {
1533 struct mmci_platform_data *plat = dev->dev.platform_data;
1534 struct device_node *np = dev->dev.of_node;
1535 struct variant_data *variant = id->data;
1536 struct mmci_host *host;
1537 struct mmc_host *mmc;
1538 int ret;
1539
1540 /* Must have platform data or Device Tree. */
1541 if (!plat && !np) {
1542 dev_err(&dev->dev, "No plat data or DT found\n");
1543 return -EINVAL;
1544 }
1545
1546 if (!plat) {
1547 plat = devm_kzalloc(&dev->dev, sizeof(*plat), GFP_KERNEL);
1548 if (!plat)
1549 return -ENOMEM;
1550 }
1551
1552 mmc = mmc_alloc_host(sizeof(struct mmci_host), &dev->dev);
1553 if (!mmc)
1554 return -ENOMEM;
1555
1556 ret = mmci_of_parse(np, mmc);
1557 if (ret)
1558 goto host_free;
1559
1560 host = mmc_priv(mmc);
1561 host->mmc = mmc;
1562
1563 /*
1564 * Some variant (STM32) doesn't have opendrain bit, nevertheless
1565 * pins can be set accordingly using pinctrl
1566 */
1567 if (!variant->opendrain) {
1568 host->pinctrl = devm_pinctrl_get(&dev->dev);
1569 if (IS_ERR(host->pinctrl)) {
1570 dev_err(&dev->dev, "failed to get pinctrl");
1571 ret = PTR_ERR(host->pinctrl);
1572 goto host_free;
1573 }
1574
1575 host->pins_default = pinctrl_lookup_state(host->pinctrl,
1576 PINCTRL_STATE_DEFAULT);
1577 if (IS_ERR(host->pins_default)) {
1578 dev_err(mmc_dev(mmc), "Can't select default pins\n");
1579 ret = PTR_ERR(host->pins_default);
1580 goto host_free;
1581 }
1582
1583 host->pins_opendrain = pinctrl_lookup_state(host->pinctrl,
1584 MMCI_PINCTRL_STATE_OPENDRAIN);
1585 if (IS_ERR(host->pins_opendrain)) {
1586 dev_err(mmc_dev(mmc), "Can't select opendrain pins\n");
1587 ret = PTR_ERR(host->pins_opendrain);
1588 goto host_free;
1589 }
1590 }
1591
1592 host->hw_designer = amba_manf(dev);
1593 host->hw_revision = amba_rev(dev);
1594 dev_dbg(mmc_dev(mmc), "designer ID = 0x%02x\n", host->hw_designer);
1595 dev_dbg(mmc_dev(mmc), "revision = 0x%01x\n", host->hw_revision);
1596
1597 host->clk = devm_clk_get(&dev->dev, NULL);
1598 if (IS_ERR(host->clk)) {
1599 ret = PTR_ERR(host->clk);
1600 goto host_free;
1601 }
1602
1603 ret = clk_prepare_enable(host->clk);
1604 if (ret)
1605 goto host_free;
1606
1607 if (variant->qcom_fifo)
1608 host->get_rx_fifocnt = mmci_qcom_get_rx_fifocnt;
1609 else
1610 host->get_rx_fifocnt = mmci_get_rx_fifocnt;
1611
1612 host->plat = plat;
1613 host->variant = variant;
1614 host->mclk = clk_get_rate(host->clk);
1615 /*
1616 * According to the spec, mclk is max 100 MHz,
1617 * so we try to adjust the clock down to this,
1618 * (if possible).
1619 */
1620 if (host->mclk > variant->f_max) {
1621 ret = clk_set_rate(host->clk, variant->f_max);
1622 if (ret < 0)
1623 goto clk_disable;
1624 host->mclk = clk_get_rate(host->clk);
1625 dev_dbg(mmc_dev(mmc), "eventual mclk rate: %u Hz\n",
1626 host->mclk);
1627 }
1628
1629 host->phybase = dev->res.start;
1630 host->base = devm_ioremap_resource(&dev->dev, &dev->res);
1631 if (IS_ERR(host->base)) {
1632 ret = PTR_ERR(host->base);
1633 goto clk_disable;
1634 }
1635
1636 if (variant->init)
1637 variant->init(host);
1638
1639 /*
1640 * The ARM and ST versions of the block have slightly different
1641 * clock divider equations which means that the minimum divider
1642 * differs too.
1643 * on Qualcomm like controllers get the nearest minimum clock to 100Khz
1644 */
1645 if (variant->st_clkdiv)
1646 mmc->f_min = DIV_ROUND_UP(host->mclk, 257);
1647 else if (variant->explicit_mclk_control)
1648 mmc->f_min = clk_round_rate(host->clk, 100000);
1649 else
1650 mmc->f_min = DIV_ROUND_UP(host->mclk, 512);
1651 /*
1652 * If no maximum operating frequency is supplied, fall back to use
1653 * the module parameter, which has a (low) default value in case it
1654 * is not specified. Either value must not exceed the clock rate into
1655 * the block, of course.
1656 */
1657 if (mmc->f_max)
1658 mmc->f_max = variant->explicit_mclk_control ?
1659 min(variant->f_max, mmc->f_max) :
1660 min(host->mclk, mmc->f_max);
1661 else
1662 mmc->f_max = variant->explicit_mclk_control ?
1663 fmax : min(host->mclk, fmax);
1664
1665
1666 dev_dbg(mmc_dev(mmc), "clocking block at %u Hz\n", mmc->f_max);
1667
1668 /* Get regulators and the supported OCR mask */
1669 ret = mmc_regulator_get_supply(mmc);
1670 if (ret)
1671 goto clk_disable;
1672
1673 if (!mmc->ocr_avail)
1674 mmc->ocr_avail = plat->ocr_mask;
1675 else if (plat->ocr_mask)
1676 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
1677
1678 /* DT takes precedence over platform data. */
1679 if (!np) {
1680 if (!plat->cd_invert)
1681 mmc->caps2 |= MMC_CAP2_CD_ACTIVE_HIGH;
1682 mmc->caps2 |= MMC_CAP2_RO_ACTIVE_HIGH;
1683 }
1684
1685 /* We support these capabilities. */
1686 mmc->caps |= MMC_CAP_CMD23;
1687
1688 /*
1689 * Enable busy detection.
1690 */
1691 if (variant->busy_detect) {
1692 mmci_ops.card_busy = mmci_card_busy;
1693 /*
1694 * Not all variants have a flag to enable busy detection
1695 * in the DPSM, but if they do, set it here.
1696 */
1697 if (variant->busy_dpsm_flag)
1698 mmci_write_datactrlreg(host,
1699 host->variant->busy_dpsm_flag);
1700 mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY;
1701 mmc->max_busy_timeout = 0;
1702 }
1703
1704 mmc->ops = &mmci_ops;
1705
1706 /* We support these PM capabilities. */
1707 mmc->pm_caps |= MMC_PM_KEEP_POWER;
1708
1709 /*
1710 * We can do SGIO
1711 */
1712 mmc->max_segs = NR_SG;
1713
1714 /*
1715 * Since only a certain number of bits are valid in the data length
1716 * register, we must ensure that we don't exceed 2^num-1 bytes in a
1717 * single request.
1718 */
1719 mmc->max_req_size = (1 << variant->datalength_bits) - 1;
1720
1721 /*
1722 * Set the maximum segment size. Since we aren't doing DMA
1723 * (yet) we are only limited by the data length register.
1724 */
1725 mmc->max_seg_size = mmc->max_req_size;
1726
1727 /*
1728 * Block size can be up to 2048 bytes, but must be a power of two.
1729 */
1730 mmc->max_blk_size = 1 << 11;
1731
1732 /*
1733 * Limit the number of blocks transferred so that we don't overflow
1734 * the maximum request size.
1735 */
1736 mmc->max_blk_count = mmc->max_req_size >> 11;
1737
1738 spin_lock_init(&host->lock);
1739
1740 writel(0, host->base + MMCIMASK0);
1741
1742 if (variant->mmcimask1)
1743 writel(0, host->base + MMCIMASK1);
1744
1745 writel(0xfff, host->base + MMCICLEAR);
1746
1747 /*
1748 * If:
1749 * - not using DT but using a descriptor table, or
1750 * - using a table of descriptors ALONGSIDE DT, or
1751 * look up these descriptors named "cd" and "wp" right here, fail
1752 * silently of these do not exist and proceed to try platform data
1753 */
1754 if (!np) {
1755 ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL);
1756 if (ret < 0) {
1757 if (ret == -EPROBE_DEFER)
1758 goto clk_disable;
1759 else if (gpio_is_valid(plat->gpio_cd)) {
1760 ret = mmc_gpio_request_cd(mmc, plat->gpio_cd, 0);
1761 if (ret)
1762 goto clk_disable;
1763 }
1764 }
1765
1766 ret = mmc_gpiod_request_ro(mmc, "wp", 0, false, 0, NULL);
1767 if (ret < 0) {
1768 if (ret == -EPROBE_DEFER)
1769 goto clk_disable;
1770 else if (gpio_is_valid(plat->gpio_wp)) {
1771 ret = mmc_gpio_request_ro(mmc, plat->gpio_wp);
1772 if (ret)
1773 goto clk_disable;
1774 }
1775 }
1776 }
1777
1778 ret = devm_request_irq(&dev->dev, dev->irq[0], mmci_irq, IRQF_SHARED,
1779 DRIVER_NAME " (cmd)", host);
1780 if (ret)
1781 goto clk_disable;
1782
1783 if (!dev->irq[1])
1784 host->singleirq = true;
1785 else {
1786 ret = devm_request_irq(&dev->dev, dev->irq[1], mmci_pio_irq,
1787 IRQF_SHARED, DRIVER_NAME " (pio)", host);
1788 if (ret)
1789 goto clk_disable;
1790 }
1791
1792 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1793
1794 amba_set_drvdata(dev, mmc);
1795
1796 dev_info(&dev->dev, "%s: PL%03x manf %x rev%u at 0x%08llx irq %d,%d (pio)\n",
1797 mmc_hostname(mmc), amba_part(dev), amba_manf(dev),
1798 amba_rev(dev), (unsigned long long)dev->res.start,
1799 dev->irq[0], dev->irq[1]);
1800
1801 mmci_dma_setup(host);
1802
1803 pm_runtime_set_autosuspend_delay(&dev->dev, 50);
1804 pm_runtime_use_autosuspend(&dev->dev);
1805
1806 mmc_add_host(mmc);
1807
1808 pm_runtime_put(&dev->dev);
1809 return 0;
1810
1811 clk_disable:
1812 clk_disable_unprepare(host->clk);
1813 host_free:
1814 mmc_free_host(mmc);
1815 return ret;
1816 }
1817
mmci_remove(struct amba_device * dev)1818 static int mmci_remove(struct amba_device *dev)
1819 {
1820 struct mmc_host *mmc = amba_get_drvdata(dev);
1821
1822 if (mmc) {
1823 struct mmci_host *host = mmc_priv(mmc);
1824 struct variant_data *variant = host->variant;
1825
1826 /*
1827 * Undo pm_runtime_put() in probe. We use the _sync
1828 * version here so that we can access the primecell.
1829 */
1830 pm_runtime_get_sync(&dev->dev);
1831
1832 mmc_remove_host(mmc);
1833
1834 writel(0, host->base + MMCIMASK0);
1835
1836 if (variant->mmcimask1)
1837 writel(0, host->base + MMCIMASK1);
1838
1839 writel(0, host->base + MMCICOMMAND);
1840 writel(0, host->base + MMCIDATACTRL);
1841
1842 mmci_dma_release(host);
1843 clk_disable_unprepare(host->clk);
1844 mmc_free_host(mmc);
1845 }
1846
1847 return 0;
1848 }
1849
1850 #ifdef CONFIG_PM
mmci_save(struct mmci_host * host)1851 static void mmci_save(struct mmci_host *host)
1852 {
1853 unsigned long flags;
1854
1855 spin_lock_irqsave(&host->lock, flags);
1856
1857 writel(0, host->base + MMCIMASK0);
1858 if (host->variant->pwrreg_nopower) {
1859 writel(0, host->base + MMCIDATACTRL);
1860 writel(0, host->base + MMCIPOWER);
1861 writel(0, host->base + MMCICLOCK);
1862 }
1863 mmci_reg_delay(host);
1864
1865 spin_unlock_irqrestore(&host->lock, flags);
1866 }
1867
mmci_restore(struct mmci_host * host)1868 static void mmci_restore(struct mmci_host *host)
1869 {
1870 unsigned long flags;
1871
1872 spin_lock_irqsave(&host->lock, flags);
1873
1874 if (host->variant->pwrreg_nopower) {
1875 writel(host->clk_reg, host->base + MMCICLOCK);
1876 writel(host->datactrl_reg, host->base + MMCIDATACTRL);
1877 writel(host->pwr_reg, host->base + MMCIPOWER);
1878 }
1879 writel(MCI_IRQENABLE, host->base + MMCIMASK0);
1880 mmci_reg_delay(host);
1881
1882 spin_unlock_irqrestore(&host->lock, flags);
1883 }
1884
mmci_runtime_suspend(struct device * dev)1885 static int mmci_runtime_suspend(struct device *dev)
1886 {
1887 struct amba_device *adev = to_amba_device(dev);
1888 struct mmc_host *mmc = amba_get_drvdata(adev);
1889
1890 if (mmc) {
1891 struct mmci_host *host = mmc_priv(mmc);
1892 pinctrl_pm_select_sleep_state(dev);
1893 mmci_save(host);
1894 clk_disable_unprepare(host->clk);
1895 }
1896
1897 return 0;
1898 }
1899
mmci_runtime_resume(struct device * dev)1900 static int mmci_runtime_resume(struct device *dev)
1901 {
1902 struct amba_device *adev = to_amba_device(dev);
1903 struct mmc_host *mmc = amba_get_drvdata(adev);
1904
1905 if (mmc) {
1906 struct mmci_host *host = mmc_priv(mmc);
1907 clk_prepare_enable(host->clk);
1908 mmci_restore(host);
1909 pinctrl_pm_select_default_state(dev);
1910 }
1911
1912 return 0;
1913 }
1914 #endif
1915
1916 static const struct dev_pm_ops mmci_dev_pm_ops = {
1917 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
1918 pm_runtime_force_resume)
1919 SET_RUNTIME_PM_OPS(mmci_runtime_suspend, mmci_runtime_resume, NULL)
1920 };
1921
1922 static const struct amba_id mmci_ids[] = {
1923 {
1924 .id = 0x00041180,
1925 .mask = 0xff0fffff,
1926 .data = &variant_arm,
1927 },
1928 {
1929 .id = 0x01041180,
1930 .mask = 0xff0fffff,
1931 .data = &variant_arm_extended_fifo,
1932 },
1933 {
1934 .id = 0x02041180,
1935 .mask = 0xff0fffff,
1936 .data = &variant_arm_extended_fifo_hwfc,
1937 },
1938 {
1939 .id = 0x00041181,
1940 .mask = 0x000fffff,
1941 .data = &variant_arm,
1942 },
1943 /* ST Micro variants */
1944 {
1945 .id = 0x00180180,
1946 .mask = 0x00ffffff,
1947 .data = &variant_u300,
1948 },
1949 {
1950 .id = 0x10180180,
1951 .mask = 0xf0ffffff,
1952 .data = &variant_nomadik,
1953 },
1954 {
1955 .id = 0x00280180,
1956 .mask = 0x00ffffff,
1957 .data = &variant_nomadik,
1958 },
1959 {
1960 .id = 0x00480180,
1961 .mask = 0xf0ffffff,
1962 .data = &variant_ux500,
1963 },
1964 {
1965 .id = 0x10480180,
1966 .mask = 0xf0ffffff,
1967 .data = &variant_ux500v2,
1968 },
1969 {
1970 .id = 0x00880180,
1971 .mask = 0x00ffffff,
1972 .data = &variant_stm32,
1973 },
1974 /* Qualcomm variants */
1975 {
1976 .id = 0x00051180,
1977 .mask = 0x000fffff,
1978 .data = &variant_qcom,
1979 },
1980 { 0, 0 },
1981 };
1982
1983 MODULE_DEVICE_TABLE(amba, mmci_ids);
1984
1985 static struct amba_driver mmci_driver = {
1986 .drv = {
1987 .name = DRIVER_NAME,
1988 .pm = &mmci_dev_pm_ops,
1989 },
1990 .probe = mmci_probe,
1991 .remove = mmci_remove,
1992 .id_table = mmci_ids,
1993 };
1994
1995 module_amba_driver(mmci_driver);
1996
1997 module_param(fmax, uint, 0444);
1998
1999 MODULE_DESCRIPTION("ARM PrimeCell PL180/181 Multimedia Card Interface driver");
2000 MODULE_LICENSE("GPL");
2001
