1 /*
2 * Driver for the CS5535/CS5536 Multi-Function General Purpose Timers (MFGPT)
3 *
4 * Copyright (C) 2006, Advanced Micro Devices, Inc.
5 * Copyright (C) 2007 Andres Salomon <dilinger@debian.org>
6 * Copyright (C) 2009 Andres Salomon <dilinger@collabora.co.uk>
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of version 2 of the GNU General Public License
10 * as published by the Free Software Foundation.
11 *
12 * The MFGPTs are documented in AMD Geode CS5536 Companion Device Data Book.
13 */
14
15 #include <linux/kernel.h>
16 #include <linux/spinlock.h>
17 #include <linux/interrupt.h>
18 #include <linux/module.h>
19 #include <linux/platform_device.h>
20 #include <linux/cs5535.h>
21 #include <linux/slab.h>
22
23 #define DRV_NAME "cs5535-mfgpt"
24
25 static int mfgpt_reset_timers;
26 module_param_named(mfgptfix, mfgpt_reset_timers, int, 0644);
27 MODULE_PARM_DESC(mfgptfix, "Try to reset the MFGPT timers during init; "
28 "required by some broken BIOSes (ie, TinyBIOS < 0.99) or kexec "
29 "(1 = reset the MFGPT using an undocumented bit, "
30 "2 = perform a soft reset by unconfiguring all timers); "
31 "use what works best for you.");
32
33 struct cs5535_mfgpt_timer {
34 struct cs5535_mfgpt_chip *chip;
35 int nr;
36 };
37
38 static struct cs5535_mfgpt_chip {
39 DECLARE_BITMAP(avail, MFGPT_MAX_TIMERS);
40 resource_size_t base;
41
42 struct platform_device *pdev;
43 spinlock_t lock;
44 int initialized;
45 } cs5535_mfgpt_chip;
46
cs5535_mfgpt_toggle_event(struct cs5535_mfgpt_timer * timer,int cmp,int event,int enable)47 int cs5535_mfgpt_toggle_event(struct cs5535_mfgpt_timer *timer, int cmp,
48 int event, int enable)
49 {
50 uint32_t msr, mask, value, dummy;
51 int shift = (cmp == MFGPT_CMP1) ? 0 : 8;
52
53 if (!timer) {
54 WARN_ON(1);
55 return -EIO;
56 }
57
58 /*
59 * The register maps for these are described in sections 6.17.1.x of
60 * the AMD Geode CS5536 Companion Device Data Book.
61 */
62 switch (event) {
63 case MFGPT_EVENT_RESET:
64 /*
65 * XXX: According to the docs, we cannot reset timers above
66 * 6; that is, resets for 7 and 8 will be ignored. Is this
67 * a problem? -dilinger
68 */
69 msr = MSR_MFGPT_NR;
70 mask = 1 << (timer->nr + 24);
71 break;
72
73 case MFGPT_EVENT_NMI:
74 msr = MSR_MFGPT_NR;
75 mask = 1 << (timer->nr + shift);
76 break;
77
78 case MFGPT_EVENT_IRQ:
79 msr = MSR_MFGPT_IRQ;
80 mask = 1 << (timer->nr + shift);
81 break;
82
83 default:
84 return -EIO;
85 }
86
87 rdmsr(msr, value, dummy);
88
89 if (enable)
90 value |= mask;
91 else
92 value &= ~mask;
93
94 wrmsr(msr, value, dummy);
95 return 0;
96 }
97 EXPORT_SYMBOL_GPL(cs5535_mfgpt_toggle_event);
98
cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer * timer,int cmp,int * irq,int enable)99 int cs5535_mfgpt_set_irq(struct cs5535_mfgpt_timer *timer, int cmp, int *irq,
100 int enable)
101 {
102 uint32_t zsel, lpc, dummy;
103 int shift;
104
105 if (!timer) {
106 WARN_ON(1);
107 return -EIO;
108 }
109
110 /*
111 * Unfortunately, MFGPTs come in pairs sharing their IRQ lines. If VSA
112 * is using the same CMP of the timer's Siamese twin, the IRQ is set to
113 * 2, and we mustn't use nor change it.
114 * XXX: Likewise, 2 Linux drivers might clash if the 2nd overwrites the
115 * IRQ of the 1st. This can only happen if forcing an IRQ, calling this
116 * with *irq==0 is safe. Currently there _are_ no 2 drivers.
117 */
118 rdmsr(MSR_PIC_ZSEL_LOW, zsel, dummy);
119 shift = ((cmp == MFGPT_CMP1 ? 0 : 4) + timer->nr % 4) * 4;
120 if (((zsel >> shift) & 0xF) == 2)
121 return -EIO;
122
123 /* Choose IRQ: if none supplied, keep IRQ already set or use default */
124 if (!*irq)
125 *irq = (zsel >> shift) & 0xF;
126 if (!*irq)
127 *irq = CONFIG_CS5535_MFGPT_DEFAULT_IRQ;
128
129 /* Can't use IRQ if it's 0 (=disabled), 2, or routed to LPC */
130 if (*irq < 1 || *irq == 2 || *irq > 15)
131 return -EIO;
132 rdmsr(MSR_PIC_IRQM_LPC, lpc, dummy);
133 if (lpc & (1 << *irq))
134 return -EIO;
135
136 /* All chosen and checked - go for it */
137 if (cs5535_mfgpt_toggle_event(timer, cmp, MFGPT_EVENT_IRQ, enable))
138 return -EIO;
139 if (enable) {
140 zsel = (zsel & ~(0xF << shift)) | (*irq << shift);
141 wrmsr(MSR_PIC_ZSEL_LOW, zsel, dummy);
142 }
143
144 return 0;
145 }
146 EXPORT_SYMBOL_GPL(cs5535_mfgpt_set_irq);
147
cs5535_mfgpt_alloc_timer(int timer_nr,int domain)148 struct cs5535_mfgpt_timer *cs5535_mfgpt_alloc_timer(int timer_nr, int domain)
149 {
150 struct cs5535_mfgpt_chip *mfgpt = &cs5535_mfgpt_chip;
151 struct cs5535_mfgpt_timer *timer = NULL;
152 unsigned long flags;
153 int max;
154
155 if (!mfgpt->initialized)
156 goto done;
157
158 /* only allocate timers from the working domain if requested */
159 if (domain == MFGPT_DOMAIN_WORKING)
160 max = 6;
161 else
162 max = MFGPT_MAX_TIMERS;
163
164 if (timer_nr >= max) {
165 /* programmer error. silly programmers! */
166 WARN_ON(1);
167 goto done;
168 }
169
170 spin_lock_irqsave(&mfgpt->lock, flags);
171 if (timer_nr < 0) {
172 unsigned long t;
173
174 /* try to find any available timer */
175 t = find_first_bit(mfgpt->avail, max);
176 /* set timer_nr to -1 if no timers available */
177 timer_nr = t < max ? (int) t : -1;
178 } else {
179 /* check if the requested timer's available */
180 if (!test_bit(timer_nr, mfgpt->avail))
181 timer_nr = -1;
182 }
183
184 if (timer_nr >= 0)
185 /* if timer_nr is not -1, it's an available timer */
186 __clear_bit(timer_nr, mfgpt->avail);
187 spin_unlock_irqrestore(&mfgpt->lock, flags);
188
189 if (timer_nr < 0)
190 goto done;
191
192 timer = kmalloc(sizeof(*timer), GFP_KERNEL);
193 if (!timer) {
194 /* aw hell */
195 spin_lock_irqsave(&mfgpt->lock, flags);
196 __set_bit(timer_nr, mfgpt->avail);
197 spin_unlock_irqrestore(&mfgpt->lock, flags);
198 goto done;
199 }
200 timer->chip = mfgpt;
201 timer->nr = timer_nr;
202 dev_info(&mfgpt->pdev->dev, "registered timer %d\n", timer_nr);
203
204 done:
205 return timer;
206 }
207 EXPORT_SYMBOL_GPL(cs5535_mfgpt_alloc_timer);
208
209 /*
210 * XXX: This frees the timer memory, but never resets the actual hardware
211 * timer. The old geode_mfgpt code did this; it would be good to figure
212 * out a way to actually release the hardware timer. See comments below.
213 */
cs5535_mfgpt_free_timer(struct cs5535_mfgpt_timer * timer)214 void cs5535_mfgpt_free_timer(struct cs5535_mfgpt_timer *timer)
215 {
216 unsigned long flags;
217 uint16_t val;
218
219 /* timer can be made available again only if never set up */
220 val = cs5535_mfgpt_read(timer, MFGPT_REG_SETUP);
221 if (!(val & MFGPT_SETUP_SETUP)) {
222 spin_lock_irqsave(&timer->chip->lock, flags);
223 __set_bit(timer->nr, timer->chip->avail);
224 spin_unlock_irqrestore(&timer->chip->lock, flags);
225 }
226
227 kfree(timer);
228 }
229 EXPORT_SYMBOL_GPL(cs5535_mfgpt_free_timer);
230
cs5535_mfgpt_read(struct cs5535_mfgpt_timer * timer,uint16_t reg)231 uint16_t cs5535_mfgpt_read(struct cs5535_mfgpt_timer *timer, uint16_t reg)
232 {
233 return inw(timer->chip->base + reg + (timer->nr * 8));
234 }
235 EXPORT_SYMBOL_GPL(cs5535_mfgpt_read);
236
cs5535_mfgpt_write(struct cs5535_mfgpt_timer * timer,uint16_t reg,uint16_t value)237 void cs5535_mfgpt_write(struct cs5535_mfgpt_timer *timer, uint16_t reg,
238 uint16_t value)
239 {
240 outw(value, timer->chip->base + reg + (timer->nr * 8));
241 }
242 EXPORT_SYMBOL_GPL(cs5535_mfgpt_write);
243
244 /*
245 * This is a sledgehammer that resets all MFGPT timers. This is required by
246 * some broken BIOSes which leave the system in an unstable state
247 * (TinyBIOS 0.98, for example; fixed in 0.99). It's uncertain as to
248 * whether or not this secret MSR can be used to release individual timers.
249 * Jordan tells me that he and Mitch once played w/ it, but it's unclear
250 * what the results of that were (and they experienced some instability).
251 */
reset_all_timers(void)252 static void reset_all_timers(void)
253 {
254 uint32_t val, dummy;
255
256 /* The following undocumented bit resets the MFGPT timers */
257 val = 0xFF; dummy = 0;
258 wrmsr(MSR_MFGPT_SETUP, val, dummy);
259 }
260
261 /*
262 * This is another sledgehammer to reset all MFGPT timers.
263 * Instead of using the undocumented bit method it clears
264 * IRQ, NMI and RESET settings.
265 */
soft_reset(void)266 static void soft_reset(void)
267 {
268 int i;
269 struct cs5535_mfgpt_timer t;
270
271 for (i = 0; i < MFGPT_MAX_TIMERS; i++) {
272 t.nr = i;
273
274 cs5535_mfgpt_toggle_event(&t, MFGPT_CMP1, MFGPT_EVENT_RESET, 0);
275 cs5535_mfgpt_toggle_event(&t, MFGPT_CMP2, MFGPT_EVENT_RESET, 0);
276 cs5535_mfgpt_toggle_event(&t, MFGPT_CMP1, MFGPT_EVENT_NMI, 0);
277 cs5535_mfgpt_toggle_event(&t, MFGPT_CMP2, MFGPT_EVENT_NMI, 0);
278 cs5535_mfgpt_toggle_event(&t, MFGPT_CMP1, MFGPT_EVENT_IRQ, 0);
279 cs5535_mfgpt_toggle_event(&t, MFGPT_CMP2, MFGPT_EVENT_IRQ, 0);
280 }
281 }
282
283 /*
284 * Check whether any MFGPTs are available for the kernel to use. In most
285 * cases, firmware that uses AMD's VSA code will claim all timers during
286 * bootup; we certainly don't want to take them if they're already in use.
287 * In other cases (such as with VSAless OpenFirmware), the system firmware
288 * leaves timers available for us to use.
289 */
scan_timers(struct cs5535_mfgpt_chip * mfgpt)290 static int scan_timers(struct cs5535_mfgpt_chip *mfgpt)
291 {
292 struct cs5535_mfgpt_timer timer = { .chip = mfgpt };
293 unsigned long flags;
294 int timers = 0;
295 uint16_t val;
296 int i;
297
298 /* bios workaround */
299 if (mfgpt_reset_timers == 1)
300 reset_all_timers();
301 else if (mfgpt_reset_timers == 2)
302 soft_reset();
303
304 /* just to be safe, protect this section w/ lock */
305 spin_lock_irqsave(&mfgpt->lock, flags);
306 for (i = 0; i < MFGPT_MAX_TIMERS; i++) {
307 timer.nr = i;
308 val = cs5535_mfgpt_read(&timer, MFGPT_REG_SETUP);
309 if (!(val & MFGPT_SETUP_SETUP) || mfgpt_reset_timers == 2) {
310 __set_bit(i, mfgpt->avail);
311 timers++;
312 }
313 }
314 spin_unlock_irqrestore(&mfgpt->lock, flags);
315
316 return timers;
317 }
318
cs5535_mfgpt_probe(struct platform_device * pdev)319 static int cs5535_mfgpt_probe(struct platform_device *pdev)
320 {
321 struct resource *res;
322 int err = -EIO, t;
323
324 if (mfgpt_reset_timers < 0 || mfgpt_reset_timers > 2) {
325 dev_err(&pdev->dev, "Bad mfgpt_reset_timers value: %i\n",
326 mfgpt_reset_timers);
327 goto done;
328 }
329
330 /* There are two ways to get the MFGPT base address; one is by
331 * fetching it from MSR_LBAR_MFGPT, the other is by reading the
332 * PCI BAR info. The latter method is easier (especially across
333 * different architectures), so we'll stick with that for now. If
334 * it turns out to be unreliable in the face of crappy BIOSes, we
335 * can always go back to using MSRs.. */
336
337 res = platform_get_resource(pdev, IORESOURCE_IO, 0);
338 if (!res) {
339 dev_err(&pdev->dev, "can't fetch device resource info\n");
340 goto done;
341 }
342
343 if (!request_region(res->start, resource_size(res), pdev->name)) {
344 dev_err(&pdev->dev, "can't request region\n");
345 goto done;
346 }
347
348 /* set up the driver-specific struct */
349 cs5535_mfgpt_chip.base = res->start;
350 cs5535_mfgpt_chip.pdev = pdev;
351 spin_lock_init(&cs5535_mfgpt_chip.lock);
352
353 dev_info(&pdev->dev, "reserved resource region %pR\n", res);
354
355 /* detect the available timers */
356 t = scan_timers(&cs5535_mfgpt_chip);
357 dev_info(&pdev->dev, "%d MFGPT timers available\n", t);
358 cs5535_mfgpt_chip.initialized = 1;
359 return 0;
360
361 done:
362 return err;
363 }
364
365 static struct platform_driver cs5535_mfgpt_driver = {
366 .driver = {
367 .name = DRV_NAME,
368 },
369 .probe = cs5535_mfgpt_probe,
370 };
371
372
cs5535_mfgpt_init(void)373 static int __init cs5535_mfgpt_init(void)
374 {
375 return platform_driver_register(&cs5535_mfgpt_driver);
376 }
377
378 module_init(cs5535_mfgpt_init);
379
380 MODULE_AUTHOR("Andres Salomon <dilinger@queued.net>");
381 MODULE_DESCRIPTION("CS5535/CS5536 MFGPT timer driver");
382 MODULE_LICENSE("GPL");
383 MODULE_ALIAS("platform:" DRV_NAME);
384
