1 /*
2 * driver/mfd/asic3.c
3 *
4 * Compaq ASIC3 support.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 *
10 * Copyright 2001 Compaq Computer Corporation.
11 * Copyright 2004-2005 Phil Blundell
12 * Copyright 2007-2008 OpenedHand Ltd.
13 *
14 * Authors: Phil Blundell <pb@handhelds.org>,
15 * Samuel Ortiz <sameo@openedhand.com>
16 *
17 */
18
19 #include <linux/kernel.h>
20 #include <linux/delay.h>
21 #include <linux/irq.h>
22 #include <linux/gpio.h>
23 #include <linux/export.h>
24 #include <linux/io.h>
25 #include <linux/slab.h>
26 #include <linux/spinlock.h>
27 #include <linux/platform_device.h>
28
29 #include <linux/mfd/asic3.h>
30 #include <linux/mfd/core.h>
31 #include <linux/mfd/ds1wm.h>
32 #include <linux/mfd/tmio.h>
33
34 #include <linux/mmc/host.h>
35
36 enum {
37 ASIC3_CLOCK_SPI,
38 ASIC3_CLOCK_OWM,
39 ASIC3_CLOCK_PWM0,
40 ASIC3_CLOCK_PWM1,
41 ASIC3_CLOCK_LED0,
42 ASIC3_CLOCK_LED1,
43 ASIC3_CLOCK_LED2,
44 ASIC3_CLOCK_SD_HOST,
45 ASIC3_CLOCK_SD_BUS,
46 ASIC3_CLOCK_SMBUS,
47 ASIC3_CLOCK_EX0,
48 ASIC3_CLOCK_EX1,
49 };
50
51 struct asic3_clk {
52 int enabled;
53 unsigned int cdex;
54 unsigned long rate;
55 };
56
57 #define INIT_CDEX(_name, _rate) \
58 [ASIC3_CLOCK_##_name] = { \
59 .cdex = CLOCK_CDEX_##_name, \
60 .rate = _rate, \
61 }
62
63 static struct asic3_clk asic3_clk_init[] __initdata = {
64 INIT_CDEX(SPI, 0),
65 INIT_CDEX(OWM, 5000000),
66 INIT_CDEX(PWM0, 0),
67 INIT_CDEX(PWM1, 0),
68 INIT_CDEX(LED0, 0),
69 INIT_CDEX(LED1, 0),
70 INIT_CDEX(LED2, 0),
71 INIT_CDEX(SD_HOST, 24576000),
72 INIT_CDEX(SD_BUS, 12288000),
73 INIT_CDEX(SMBUS, 0),
74 INIT_CDEX(EX0, 32768),
75 INIT_CDEX(EX1, 24576000),
76 };
77
78 struct asic3 {
79 void __iomem *mapping;
80 unsigned int bus_shift;
81 unsigned int irq_nr;
82 unsigned int irq_base;
83 raw_spinlock_t lock;
84 u16 irq_bothedge[4];
85 struct gpio_chip gpio;
86 struct device *dev;
87 void __iomem *tmio_cnf;
88
89 struct asic3_clk clocks[ARRAY_SIZE(asic3_clk_init)];
90 };
91
92 static int asic3_gpio_get(struct gpio_chip *chip, unsigned offset);
93
asic3_write_register(struct asic3 * asic,unsigned int reg,u32 value)94 void asic3_write_register(struct asic3 *asic, unsigned int reg, u32 value)
95 {
96 iowrite16(value, asic->mapping +
97 (reg >> asic->bus_shift));
98 }
99 EXPORT_SYMBOL_GPL(asic3_write_register);
100
asic3_read_register(struct asic3 * asic,unsigned int reg)101 u32 asic3_read_register(struct asic3 *asic, unsigned int reg)
102 {
103 return ioread16(asic->mapping +
104 (reg >> asic->bus_shift));
105 }
106 EXPORT_SYMBOL_GPL(asic3_read_register);
107
asic3_set_register(struct asic3 * asic,u32 reg,u32 bits,bool set)108 static void asic3_set_register(struct asic3 *asic, u32 reg, u32 bits, bool set)
109 {
110 unsigned long flags;
111 u32 val;
112
113 raw_spin_lock_irqsave(&asic->lock, flags);
114 val = asic3_read_register(asic, reg);
115 if (set)
116 val |= bits;
117 else
118 val &= ~bits;
119 asic3_write_register(asic, reg, val);
120 raw_spin_unlock_irqrestore(&asic->lock, flags);
121 }
122
123 /* IRQs */
124 #define MAX_ASIC_ISR_LOOPS 20
125 #define ASIC3_GPIO_BASE_INCR \
126 (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE)
127
asic3_irq_flip_edge(struct asic3 * asic,u32 base,int bit)128 static void asic3_irq_flip_edge(struct asic3 *asic,
129 u32 base, int bit)
130 {
131 u16 edge;
132 unsigned long flags;
133
134 raw_spin_lock_irqsave(&asic->lock, flags);
135 edge = asic3_read_register(asic,
136 base + ASIC3_GPIO_EDGE_TRIGGER);
137 edge ^= bit;
138 asic3_write_register(asic,
139 base + ASIC3_GPIO_EDGE_TRIGGER, edge);
140 raw_spin_unlock_irqrestore(&asic->lock, flags);
141 }
142
asic3_irq_demux(struct irq_desc * desc)143 static void asic3_irq_demux(struct irq_desc *desc)
144 {
145 struct asic3 *asic = irq_desc_get_handler_data(desc);
146 struct irq_data *data = irq_desc_get_irq_data(desc);
147 int iter, i;
148 unsigned long flags;
149
150 data->chip->irq_ack(data);
151
152 for (iter = 0 ; iter < MAX_ASIC_ISR_LOOPS; iter++) {
153 u32 status;
154 int bank;
155
156 raw_spin_lock_irqsave(&asic->lock, flags);
157 status = asic3_read_register(asic,
158 ASIC3_OFFSET(INTR, P_INT_STAT));
159 raw_spin_unlock_irqrestore(&asic->lock, flags);
160
161 /* Check all ten register bits */
162 if ((status & 0x3ff) == 0)
163 break;
164
165 /* Handle GPIO IRQs */
166 for (bank = 0; bank < ASIC3_NUM_GPIO_BANKS; bank++) {
167 if (status & (1 << bank)) {
168 unsigned long base, istat;
169
170 base = ASIC3_GPIO_A_BASE
171 + bank * ASIC3_GPIO_BASE_INCR;
172 raw_spin_lock_irqsave(&asic->lock, flags);
173 istat = asic3_read_register(asic,
174 base +
175 ASIC3_GPIO_INT_STATUS);
176 /* Clearing IntStatus */
177 asic3_write_register(asic,
178 base +
179 ASIC3_GPIO_INT_STATUS, 0);
180 raw_spin_unlock_irqrestore(&asic->lock, flags);
181
182 for (i = 0; i < ASIC3_GPIOS_PER_BANK; i++) {
183 int bit = (1 << i);
184 unsigned int irqnr;
185
186 if (!(istat & bit))
187 continue;
188
189 irqnr = asic->irq_base +
190 (ASIC3_GPIOS_PER_BANK * bank)
191 + i;
192 generic_handle_irq(irqnr);
193 if (asic->irq_bothedge[bank] & bit)
194 asic3_irq_flip_edge(asic, base,
195 bit);
196 }
197 }
198 }
199
200 /* Handle remaining IRQs in the status register */
201 for (i = ASIC3_NUM_GPIOS; i < ASIC3_NR_IRQS; i++) {
202 /* They start at bit 4 and go up */
203 if (status & (1 << (i - ASIC3_NUM_GPIOS + 4)))
204 generic_handle_irq(asic->irq_base + i);
205 }
206 }
207
208 if (iter >= MAX_ASIC_ISR_LOOPS)
209 dev_err(asic->dev, "interrupt processing overrun\n");
210 }
211
asic3_irq_to_bank(struct asic3 * asic,int irq)212 static inline int asic3_irq_to_bank(struct asic3 *asic, int irq)
213 {
214 int n;
215
216 n = (irq - asic->irq_base) >> 4;
217
218 return (n * (ASIC3_GPIO_B_BASE - ASIC3_GPIO_A_BASE));
219 }
220
asic3_irq_to_index(struct asic3 * asic,int irq)221 static inline int asic3_irq_to_index(struct asic3 *asic, int irq)
222 {
223 return (irq - asic->irq_base) & 0xf;
224 }
225
asic3_mask_gpio_irq(struct irq_data * data)226 static void asic3_mask_gpio_irq(struct irq_data *data)
227 {
228 struct asic3 *asic = irq_data_get_irq_chip_data(data);
229 u32 val, bank, index;
230 unsigned long flags;
231
232 bank = asic3_irq_to_bank(asic, data->irq);
233 index = asic3_irq_to_index(asic, data->irq);
234
235 raw_spin_lock_irqsave(&asic->lock, flags);
236 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
237 val |= 1 << index;
238 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
239 raw_spin_unlock_irqrestore(&asic->lock, flags);
240 }
241
asic3_mask_irq(struct irq_data * data)242 static void asic3_mask_irq(struct irq_data *data)
243 {
244 struct asic3 *asic = irq_data_get_irq_chip_data(data);
245 int regval;
246 unsigned long flags;
247
248 raw_spin_lock_irqsave(&asic->lock, flags);
249 regval = asic3_read_register(asic,
250 ASIC3_INTR_BASE +
251 ASIC3_INTR_INT_MASK);
252
253 regval &= ~(ASIC3_INTMASK_MASK0 <<
254 (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
255
256 asic3_write_register(asic,
257 ASIC3_INTR_BASE +
258 ASIC3_INTR_INT_MASK,
259 regval);
260 raw_spin_unlock_irqrestore(&asic->lock, flags);
261 }
262
asic3_unmask_gpio_irq(struct irq_data * data)263 static void asic3_unmask_gpio_irq(struct irq_data *data)
264 {
265 struct asic3 *asic = irq_data_get_irq_chip_data(data);
266 u32 val, bank, index;
267 unsigned long flags;
268
269 bank = asic3_irq_to_bank(asic, data->irq);
270 index = asic3_irq_to_index(asic, data->irq);
271
272 raw_spin_lock_irqsave(&asic->lock, flags);
273 val = asic3_read_register(asic, bank + ASIC3_GPIO_MASK);
274 val &= ~(1 << index);
275 asic3_write_register(asic, bank + ASIC3_GPIO_MASK, val);
276 raw_spin_unlock_irqrestore(&asic->lock, flags);
277 }
278
asic3_unmask_irq(struct irq_data * data)279 static void asic3_unmask_irq(struct irq_data *data)
280 {
281 struct asic3 *asic = irq_data_get_irq_chip_data(data);
282 int regval;
283 unsigned long flags;
284
285 raw_spin_lock_irqsave(&asic->lock, flags);
286 regval = asic3_read_register(asic,
287 ASIC3_INTR_BASE +
288 ASIC3_INTR_INT_MASK);
289
290 regval |= (ASIC3_INTMASK_MASK0 <<
291 (data->irq - (asic->irq_base + ASIC3_NUM_GPIOS)));
292
293 asic3_write_register(asic,
294 ASIC3_INTR_BASE +
295 ASIC3_INTR_INT_MASK,
296 regval);
297 raw_spin_unlock_irqrestore(&asic->lock, flags);
298 }
299
asic3_gpio_irq_type(struct irq_data * data,unsigned int type)300 static int asic3_gpio_irq_type(struct irq_data *data, unsigned int type)
301 {
302 struct asic3 *asic = irq_data_get_irq_chip_data(data);
303 u32 bank, index;
304 u16 trigger, level, edge, bit;
305 unsigned long flags;
306
307 bank = asic3_irq_to_bank(asic, data->irq);
308 index = asic3_irq_to_index(asic, data->irq);
309 bit = 1<<index;
310
311 raw_spin_lock_irqsave(&asic->lock, flags);
312 level = asic3_read_register(asic,
313 bank + ASIC3_GPIO_LEVEL_TRIGGER);
314 edge = asic3_read_register(asic,
315 bank + ASIC3_GPIO_EDGE_TRIGGER);
316 trigger = asic3_read_register(asic,
317 bank + ASIC3_GPIO_TRIGGER_TYPE);
318 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] &= ~bit;
319
320 if (type == IRQ_TYPE_EDGE_RISING) {
321 trigger |= bit;
322 edge |= bit;
323 } else if (type == IRQ_TYPE_EDGE_FALLING) {
324 trigger |= bit;
325 edge &= ~bit;
326 } else if (type == IRQ_TYPE_EDGE_BOTH) {
327 trigger |= bit;
328 if (asic3_gpio_get(&asic->gpio, data->irq - asic->irq_base))
329 edge &= ~bit;
330 else
331 edge |= bit;
332 asic->irq_bothedge[(data->irq - asic->irq_base) >> 4] |= bit;
333 } else if (type == IRQ_TYPE_LEVEL_LOW) {
334 trigger &= ~bit;
335 level &= ~bit;
336 } else if (type == IRQ_TYPE_LEVEL_HIGH) {
337 trigger &= ~bit;
338 level |= bit;
339 } else {
340 /*
341 * if type == IRQ_TYPE_NONE, we should mask interrupts, but
342 * be careful to not unmask them if mask was also called.
343 * Probably need internal state for mask.
344 */
345 dev_notice(asic->dev, "irq type not changed\n");
346 }
347 asic3_write_register(asic, bank + ASIC3_GPIO_LEVEL_TRIGGER,
348 level);
349 asic3_write_register(asic, bank + ASIC3_GPIO_EDGE_TRIGGER,
350 edge);
351 asic3_write_register(asic, bank + ASIC3_GPIO_TRIGGER_TYPE,
352 trigger);
353 raw_spin_unlock_irqrestore(&asic->lock, flags);
354 return 0;
355 }
356
asic3_gpio_irq_set_wake(struct irq_data * data,unsigned int on)357 static int asic3_gpio_irq_set_wake(struct irq_data *data, unsigned int on)
358 {
359 struct asic3 *asic = irq_data_get_irq_chip_data(data);
360 u32 bank, index;
361 u16 bit;
362
363 bank = asic3_irq_to_bank(asic, data->irq);
364 index = asic3_irq_to_index(asic, data->irq);
365 bit = 1<<index;
366
367 asic3_set_register(asic, bank + ASIC3_GPIO_SLEEP_MASK, bit, !on);
368
369 return 0;
370 }
371
372 static struct irq_chip asic3_gpio_irq_chip = {
373 .name = "ASIC3-GPIO",
374 .irq_ack = asic3_mask_gpio_irq,
375 .irq_mask = asic3_mask_gpio_irq,
376 .irq_unmask = asic3_unmask_gpio_irq,
377 .irq_set_type = asic3_gpio_irq_type,
378 .irq_set_wake = asic3_gpio_irq_set_wake,
379 };
380
381 static struct irq_chip asic3_irq_chip = {
382 .name = "ASIC3",
383 .irq_ack = asic3_mask_irq,
384 .irq_mask = asic3_mask_irq,
385 .irq_unmask = asic3_unmask_irq,
386 };
387
asic3_irq_probe(struct platform_device * pdev)388 static int __init asic3_irq_probe(struct platform_device *pdev)
389 {
390 struct asic3 *asic = platform_get_drvdata(pdev);
391 unsigned long clksel = 0;
392 unsigned int irq, irq_base;
393 int ret;
394
395 ret = platform_get_irq(pdev, 0);
396 if (ret < 0)
397 return ret;
398 asic->irq_nr = ret;
399
400 /* turn on clock to IRQ controller */
401 clksel |= CLOCK_SEL_CX;
402 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
403 clksel);
404
405 irq_base = asic->irq_base;
406
407 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
408 if (irq < asic->irq_base + ASIC3_NUM_GPIOS)
409 irq_set_chip(irq, &asic3_gpio_irq_chip);
410 else
411 irq_set_chip(irq, &asic3_irq_chip);
412
413 irq_set_chip_data(irq, asic);
414 irq_set_handler(irq, handle_level_irq);
415 irq_clear_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
416 }
417
418 asic3_write_register(asic, ASIC3_OFFSET(INTR, INT_MASK),
419 ASIC3_INTMASK_GINTMASK);
420
421 irq_set_chained_handler_and_data(asic->irq_nr, asic3_irq_demux, asic);
422 irq_set_irq_type(asic->irq_nr, IRQ_TYPE_EDGE_RISING);
423
424 return 0;
425 }
426
asic3_irq_remove(struct platform_device * pdev)427 static void asic3_irq_remove(struct platform_device *pdev)
428 {
429 struct asic3 *asic = platform_get_drvdata(pdev);
430 unsigned int irq, irq_base;
431
432 irq_base = asic->irq_base;
433
434 for (irq = irq_base; irq < irq_base + ASIC3_NR_IRQS; irq++) {
435 irq_set_status_flags(irq, IRQ_NOREQUEST | IRQ_NOPROBE);
436 irq_set_chip_and_handler(irq, NULL, NULL);
437 irq_set_chip_data(irq, NULL);
438 }
439 irq_set_chained_handler(asic->irq_nr, NULL);
440 }
441
442 /* GPIOs */
asic3_gpio_direction(struct gpio_chip * chip,unsigned offset,int out)443 static int asic3_gpio_direction(struct gpio_chip *chip,
444 unsigned offset, int out)
445 {
446 u32 mask = ASIC3_GPIO_TO_MASK(offset), out_reg;
447 unsigned int gpio_base;
448 unsigned long flags;
449 struct asic3 *asic;
450
451 asic = gpiochip_get_data(chip);
452 gpio_base = ASIC3_GPIO_TO_BASE(offset);
453
454 if (gpio_base > ASIC3_GPIO_D_BASE) {
455 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
456 gpio_base, offset);
457 return -EINVAL;
458 }
459
460 raw_spin_lock_irqsave(&asic->lock, flags);
461
462 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_DIRECTION);
463
464 /* Input is 0, Output is 1 */
465 if (out)
466 out_reg |= mask;
467 else
468 out_reg &= ~mask;
469
470 asic3_write_register(asic, gpio_base + ASIC3_GPIO_DIRECTION, out_reg);
471
472 raw_spin_unlock_irqrestore(&asic->lock, flags);
473
474 return 0;
475
476 }
477
asic3_gpio_direction_input(struct gpio_chip * chip,unsigned offset)478 static int asic3_gpio_direction_input(struct gpio_chip *chip,
479 unsigned offset)
480 {
481 return asic3_gpio_direction(chip, offset, 0);
482 }
483
asic3_gpio_direction_output(struct gpio_chip * chip,unsigned offset,int value)484 static int asic3_gpio_direction_output(struct gpio_chip *chip,
485 unsigned offset, int value)
486 {
487 return asic3_gpio_direction(chip, offset, 1);
488 }
489
asic3_gpio_get(struct gpio_chip * chip,unsigned offset)490 static int asic3_gpio_get(struct gpio_chip *chip,
491 unsigned offset)
492 {
493 unsigned int gpio_base;
494 u32 mask = ASIC3_GPIO_TO_MASK(offset);
495 struct asic3 *asic;
496
497 asic = gpiochip_get_data(chip);
498 gpio_base = ASIC3_GPIO_TO_BASE(offset);
499
500 if (gpio_base > ASIC3_GPIO_D_BASE) {
501 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
502 gpio_base, offset);
503 return -EINVAL;
504 }
505
506 return !!(asic3_read_register(asic,
507 gpio_base + ASIC3_GPIO_STATUS) & mask);
508 }
509
asic3_gpio_set(struct gpio_chip * chip,unsigned offset,int value)510 static void asic3_gpio_set(struct gpio_chip *chip,
511 unsigned offset, int value)
512 {
513 u32 mask, out_reg;
514 unsigned int gpio_base;
515 unsigned long flags;
516 struct asic3 *asic;
517
518 asic = gpiochip_get_data(chip);
519 gpio_base = ASIC3_GPIO_TO_BASE(offset);
520
521 if (gpio_base > ASIC3_GPIO_D_BASE) {
522 dev_err(asic->dev, "Invalid base (0x%x) for gpio %d\n",
523 gpio_base, offset);
524 return;
525 }
526
527 mask = ASIC3_GPIO_TO_MASK(offset);
528
529 raw_spin_lock_irqsave(&asic->lock, flags);
530
531 out_reg = asic3_read_register(asic, gpio_base + ASIC3_GPIO_OUT);
532
533 if (value)
534 out_reg |= mask;
535 else
536 out_reg &= ~mask;
537
538 asic3_write_register(asic, gpio_base + ASIC3_GPIO_OUT, out_reg);
539
540 raw_spin_unlock_irqrestore(&asic->lock, flags);
541 }
542
asic3_gpio_to_irq(struct gpio_chip * chip,unsigned offset)543 static int asic3_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
544 {
545 struct asic3 *asic = gpiochip_get_data(chip);
546
547 return asic->irq_base + offset;
548 }
549
asic3_gpio_probe(struct platform_device * pdev,u16 * gpio_config,int num)550 static __init int asic3_gpio_probe(struct platform_device *pdev,
551 u16 *gpio_config, int num)
552 {
553 struct asic3 *asic = platform_get_drvdata(pdev);
554 u16 alt_reg[ASIC3_NUM_GPIO_BANKS];
555 u16 out_reg[ASIC3_NUM_GPIO_BANKS];
556 u16 dir_reg[ASIC3_NUM_GPIO_BANKS];
557 int i;
558
559 memset(alt_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
560 memset(out_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
561 memset(dir_reg, 0, ASIC3_NUM_GPIO_BANKS * sizeof(u16));
562
563 /* Enable all GPIOs */
564 asic3_write_register(asic, ASIC3_GPIO_OFFSET(A, MASK), 0xffff);
565 asic3_write_register(asic, ASIC3_GPIO_OFFSET(B, MASK), 0xffff);
566 asic3_write_register(asic, ASIC3_GPIO_OFFSET(C, MASK), 0xffff);
567 asic3_write_register(asic, ASIC3_GPIO_OFFSET(D, MASK), 0xffff);
568
569 for (i = 0; i < num; i++) {
570 u8 alt, pin, dir, init, bank_num, bit_num;
571 u16 config = gpio_config[i];
572
573 pin = ASIC3_CONFIG_GPIO_PIN(config);
574 alt = ASIC3_CONFIG_GPIO_ALT(config);
575 dir = ASIC3_CONFIG_GPIO_DIR(config);
576 init = ASIC3_CONFIG_GPIO_INIT(config);
577
578 bank_num = ASIC3_GPIO_TO_BANK(pin);
579 bit_num = ASIC3_GPIO_TO_BIT(pin);
580
581 alt_reg[bank_num] |= (alt << bit_num);
582 out_reg[bank_num] |= (init << bit_num);
583 dir_reg[bank_num] |= (dir << bit_num);
584 }
585
586 for (i = 0; i < ASIC3_NUM_GPIO_BANKS; i++) {
587 asic3_write_register(asic,
588 ASIC3_BANK_TO_BASE(i) +
589 ASIC3_GPIO_DIRECTION,
590 dir_reg[i]);
591 asic3_write_register(asic,
592 ASIC3_BANK_TO_BASE(i) + ASIC3_GPIO_OUT,
593 out_reg[i]);
594 asic3_write_register(asic,
595 ASIC3_BANK_TO_BASE(i) +
596 ASIC3_GPIO_ALT_FUNCTION,
597 alt_reg[i]);
598 }
599
600 return gpiochip_add_data(&asic->gpio, asic);
601 }
602
asic3_gpio_remove(struct platform_device * pdev)603 static int asic3_gpio_remove(struct platform_device *pdev)
604 {
605 struct asic3 *asic = platform_get_drvdata(pdev);
606
607 gpiochip_remove(&asic->gpio);
608 return 0;
609 }
610
asic3_clk_enable(struct asic3 * asic,struct asic3_clk * clk)611 static void asic3_clk_enable(struct asic3 *asic, struct asic3_clk *clk)
612 {
613 unsigned long flags;
614 u32 cdex;
615
616 raw_spin_lock_irqsave(&asic->lock, flags);
617 if (clk->enabled++ == 0) {
618 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
619 cdex |= clk->cdex;
620 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
621 }
622 raw_spin_unlock_irqrestore(&asic->lock, flags);
623 }
624
asic3_clk_disable(struct asic3 * asic,struct asic3_clk * clk)625 static void asic3_clk_disable(struct asic3 *asic, struct asic3_clk *clk)
626 {
627 unsigned long flags;
628 u32 cdex;
629
630 WARN_ON(clk->enabled == 0);
631
632 raw_spin_lock_irqsave(&asic->lock, flags);
633 if (--clk->enabled == 0) {
634 cdex = asic3_read_register(asic, ASIC3_OFFSET(CLOCK, CDEX));
635 cdex &= ~clk->cdex;
636 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, CDEX), cdex);
637 }
638 raw_spin_unlock_irqrestore(&asic->lock, flags);
639 }
640
641 /* MFD cells (SPI, PWM, LED, DS1WM, MMC) */
642 static struct ds1wm_driver_data ds1wm_pdata = {
643 .active_high = 1,
644 .reset_recover_delay = 1,
645 };
646
647 static struct resource ds1wm_resources[] = {
648 {
649 .start = ASIC3_OWM_BASE,
650 .end = ASIC3_OWM_BASE + 0x13,
651 .flags = IORESOURCE_MEM,
652 },
653 {
654 .start = ASIC3_IRQ_OWM,
655 .end = ASIC3_IRQ_OWM,
656 .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE,
657 },
658 };
659
ds1wm_enable(struct platform_device * pdev)660 static int ds1wm_enable(struct platform_device *pdev)
661 {
662 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
663
664 /* Turn on external clocks and the OWM clock */
665 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
666 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
667 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
668 usleep_range(1000, 5000);
669
670 /* Reset and enable DS1WM */
671 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
672 ASIC3_EXTCF_OWM_RESET, 1);
673 usleep_range(1000, 5000);
674 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, RESET),
675 ASIC3_EXTCF_OWM_RESET, 0);
676 usleep_range(1000, 5000);
677 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
678 ASIC3_EXTCF_OWM_EN, 1);
679 usleep_range(1000, 5000);
680
681 return 0;
682 }
683
ds1wm_disable(struct platform_device * pdev)684 static int ds1wm_disable(struct platform_device *pdev)
685 {
686 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
687
688 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
689 ASIC3_EXTCF_OWM_EN, 0);
690
691 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_OWM]);
692 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
693 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
694
695 return 0;
696 }
697
698 static const struct mfd_cell asic3_cell_ds1wm = {
699 .name = "ds1wm",
700 .enable = ds1wm_enable,
701 .disable = ds1wm_disable,
702 .platform_data = &ds1wm_pdata,
703 .pdata_size = sizeof(ds1wm_pdata),
704 .num_resources = ARRAY_SIZE(ds1wm_resources),
705 .resources = ds1wm_resources,
706 };
707
asic3_mmc_pwr(struct platform_device * pdev,int state)708 static void asic3_mmc_pwr(struct platform_device *pdev, int state)
709 {
710 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
711
712 tmio_core_mmc_pwr(asic->tmio_cnf, 1 - asic->bus_shift, state);
713 }
714
asic3_mmc_clk_div(struct platform_device * pdev,int state)715 static void asic3_mmc_clk_div(struct platform_device *pdev, int state)
716 {
717 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
718
719 tmio_core_mmc_clk_div(asic->tmio_cnf, 1 - asic->bus_shift, state);
720 }
721
722 static struct tmio_mmc_data asic3_mmc_data = {
723 .hclk = 24576000,
724 .ocr_mask = MMC_VDD_32_33 | MMC_VDD_33_34,
725 .set_pwr = asic3_mmc_pwr,
726 .set_clk_div = asic3_mmc_clk_div,
727 };
728
729 static struct resource asic3_mmc_resources[] = {
730 {
731 .start = ASIC3_SD_CTRL_BASE,
732 .end = ASIC3_SD_CTRL_BASE + 0x3ff,
733 .flags = IORESOURCE_MEM,
734 },
735 {
736 .start = 0,
737 .end = 0,
738 .flags = IORESOURCE_IRQ,
739 },
740 };
741
asic3_mmc_enable(struct platform_device * pdev)742 static int asic3_mmc_enable(struct platform_device *pdev)
743 {
744 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
745
746 /* Not sure if it must be done bit by bit, but leaving as-is */
747 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
748 ASIC3_SDHWCTRL_LEVCD, 1);
749 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
750 ASIC3_SDHWCTRL_LEVWP, 1);
751 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
752 ASIC3_SDHWCTRL_SUSPEND, 0);
753 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
754 ASIC3_SDHWCTRL_PCLR, 0);
755
756 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
757 /* CLK32 used for card detection and for interruption detection
758 * when HCLK is stopped.
759 */
760 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
761 usleep_range(1000, 5000);
762
763 /* HCLK 24.576 MHz, BCLK 12.288 MHz: */
764 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL),
765 CLOCK_SEL_CX | CLOCK_SEL_SD_HCLK_SEL);
766
767 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
768 asic3_clk_enable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
769 usleep_range(1000, 5000);
770
771 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
772 ASIC3_EXTCF_SD_MEM_ENABLE, 1);
773
774 /* Enable SD card slot 3.3V power supply */
775 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
776 ASIC3_SDHWCTRL_SDPWR, 1);
777
778 /* ASIC3_SD_CTRL_BASE assumes 32-bit addressing, TMIO is 16-bit */
779 tmio_core_mmc_enable(asic->tmio_cnf, 1 - asic->bus_shift,
780 ASIC3_SD_CTRL_BASE >> 1);
781
782 return 0;
783 }
784
asic3_mmc_disable(struct platform_device * pdev)785 static int asic3_mmc_disable(struct platform_device *pdev)
786 {
787 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
788
789 /* Put in suspend mode */
790 asic3_set_register(asic, ASIC3_OFFSET(SDHWCTRL, SDCONF),
791 ASIC3_SDHWCTRL_SUSPEND, 1);
792
793 /* Disable clocks */
794 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_HOST]);
795 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_SD_BUS]);
796 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX0]);
797 asic3_clk_disable(asic, &asic->clocks[ASIC3_CLOCK_EX1]);
798 return 0;
799 }
800
801 static const struct mfd_cell asic3_cell_mmc = {
802 .name = "tmio-mmc",
803 .enable = asic3_mmc_enable,
804 .disable = asic3_mmc_disable,
805 .suspend = asic3_mmc_disable,
806 .resume = asic3_mmc_enable,
807 .platform_data = &asic3_mmc_data,
808 .pdata_size = sizeof(asic3_mmc_data),
809 .num_resources = ARRAY_SIZE(asic3_mmc_resources),
810 .resources = asic3_mmc_resources,
811 };
812
813 static const int clock_ledn[ASIC3_NUM_LEDS] = {
814 [0] = ASIC3_CLOCK_LED0,
815 [1] = ASIC3_CLOCK_LED1,
816 [2] = ASIC3_CLOCK_LED2,
817 };
818
asic3_leds_enable(struct platform_device * pdev)819 static int asic3_leds_enable(struct platform_device *pdev)
820 {
821 const struct mfd_cell *cell = mfd_get_cell(pdev);
822 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
823
824 asic3_clk_enable(asic, &asic->clocks[clock_ledn[cell->id]]);
825
826 return 0;
827 }
828
asic3_leds_disable(struct platform_device * pdev)829 static int asic3_leds_disable(struct platform_device *pdev)
830 {
831 const struct mfd_cell *cell = mfd_get_cell(pdev);
832 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
833
834 asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]);
835
836 return 0;
837 }
838
asic3_leds_suspend(struct platform_device * pdev)839 static int asic3_leds_suspend(struct platform_device *pdev)
840 {
841 const struct mfd_cell *cell = mfd_get_cell(pdev);
842 struct asic3 *asic = dev_get_drvdata(pdev->dev.parent);
843
844 while (asic3_gpio_get(&asic->gpio, ASIC3_GPIO(C, cell->id)) != 0)
845 usleep_range(1000, 5000);
846
847 asic3_clk_disable(asic, &asic->clocks[clock_ledn[cell->id]]);
848
849 return 0;
850 }
851
852 static struct mfd_cell asic3_cell_leds[ASIC3_NUM_LEDS] = {
853 [0] = {
854 .name = "leds-asic3",
855 .id = 0,
856 .enable = asic3_leds_enable,
857 .disable = asic3_leds_disable,
858 .suspend = asic3_leds_suspend,
859 .resume = asic3_leds_enable,
860 },
861 [1] = {
862 .name = "leds-asic3",
863 .id = 1,
864 .enable = asic3_leds_enable,
865 .disable = asic3_leds_disable,
866 .suspend = asic3_leds_suspend,
867 .resume = asic3_leds_enable,
868 },
869 [2] = {
870 .name = "leds-asic3",
871 .id = 2,
872 .enable = asic3_leds_enable,
873 .disable = asic3_leds_disable,
874 .suspend = asic3_leds_suspend,
875 .resume = asic3_leds_enable,
876 },
877 };
878
asic3_mfd_probe(struct platform_device * pdev,struct asic3_platform_data * pdata,struct resource * mem)879 static int __init asic3_mfd_probe(struct platform_device *pdev,
880 struct asic3_platform_data *pdata,
881 struct resource *mem)
882 {
883 struct asic3 *asic = platform_get_drvdata(pdev);
884 struct resource *mem_sdio;
885 int irq, ret;
886
887 mem_sdio = platform_get_resource(pdev, IORESOURCE_MEM, 1);
888 if (!mem_sdio)
889 dev_dbg(asic->dev, "no SDIO MEM resource\n");
890
891 irq = platform_get_irq(pdev, 1);
892 if (irq < 0)
893 dev_dbg(asic->dev, "no SDIO IRQ resource\n");
894
895 /* DS1WM */
896 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
897 ASIC3_EXTCF_OWM_SMB, 0);
898
899 ds1wm_resources[0].start >>= asic->bus_shift;
900 ds1wm_resources[0].end >>= asic->bus_shift;
901
902 /* MMC */
903 if (mem_sdio) {
904 asic->tmio_cnf = ioremap((ASIC3_SD_CONFIG_BASE >>
905 asic->bus_shift) + mem_sdio->start,
906 ASIC3_SD_CONFIG_SIZE >> asic->bus_shift);
907 if (!asic->tmio_cnf) {
908 ret = -ENOMEM;
909 dev_dbg(asic->dev, "Couldn't ioremap SD_CONFIG\n");
910 goto out;
911 }
912 }
913 asic3_mmc_resources[0].start >>= asic->bus_shift;
914 asic3_mmc_resources[0].end >>= asic->bus_shift;
915
916 if (pdata->clock_rate) {
917 ds1wm_pdata.clock_rate = pdata->clock_rate;
918 ret = mfd_add_devices(&pdev->dev, pdev->id,
919 &asic3_cell_ds1wm, 1, mem, asic->irq_base, NULL);
920 if (ret < 0)
921 goto out;
922 }
923
924 if (mem_sdio && (irq >= 0)) {
925 ret = mfd_add_devices(&pdev->dev, pdev->id,
926 &asic3_cell_mmc, 1, mem_sdio, irq, NULL);
927 if (ret < 0)
928 goto out;
929 }
930
931 ret = 0;
932 if (pdata->leds) {
933 int i;
934
935 for (i = 0; i < ASIC3_NUM_LEDS; ++i) {
936 asic3_cell_leds[i].platform_data = &pdata->leds[i];
937 asic3_cell_leds[i].pdata_size = sizeof(pdata->leds[i]);
938 }
939 ret = mfd_add_devices(&pdev->dev, 0,
940 asic3_cell_leds, ASIC3_NUM_LEDS, NULL, 0, NULL);
941 }
942
943 out:
944 return ret;
945 }
946
asic3_mfd_remove(struct platform_device * pdev)947 static void asic3_mfd_remove(struct platform_device *pdev)
948 {
949 struct asic3 *asic = platform_get_drvdata(pdev);
950
951 mfd_remove_devices(&pdev->dev);
952 iounmap(asic->tmio_cnf);
953 }
954
955 /* Core */
asic3_probe(struct platform_device * pdev)956 static int __init asic3_probe(struct platform_device *pdev)
957 {
958 struct asic3_platform_data *pdata = dev_get_platdata(&pdev->dev);
959 struct asic3 *asic;
960 struct resource *mem;
961 unsigned long clksel;
962 int ret = 0;
963
964 asic = devm_kzalloc(&pdev->dev,
965 sizeof(struct asic3), GFP_KERNEL);
966 if (!asic)
967 return -ENOMEM;
968
969 raw_spin_lock_init(&asic->lock);
970 platform_set_drvdata(pdev, asic);
971 asic->dev = &pdev->dev;
972
973 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
974 if (!mem) {
975 dev_err(asic->dev, "no MEM resource\n");
976 return -ENOMEM;
977 }
978
979 asic->mapping = ioremap(mem->start, resource_size(mem));
980 if (!asic->mapping) {
981 dev_err(asic->dev, "Couldn't ioremap\n");
982 return -ENOMEM;
983 }
984
985 asic->irq_base = pdata->irq_base;
986
987 /* calculate bus shift from mem resource */
988 asic->bus_shift = 2 - (resource_size(mem) >> 12);
989
990 clksel = 0;
991 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), clksel);
992
993 ret = asic3_irq_probe(pdev);
994 if (ret < 0) {
995 dev_err(asic->dev, "Couldn't probe IRQs\n");
996 goto out_unmap;
997 }
998
999 asic->gpio.label = "asic3";
1000 asic->gpio.base = pdata->gpio_base;
1001 asic->gpio.ngpio = ASIC3_NUM_GPIOS;
1002 asic->gpio.get = asic3_gpio_get;
1003 asic->gpio.set = asic3_gpio_set;
1004 asic->gpio.direction_input = asic3_gpio_direction_input;
1005 asic->gpio.direction_output = asic3_gpio_direction_output;
1006 asic->gpio.to_irq = asic3_gpio_to_irq;
1007
1008 ret = asic3_gpio_probe(pdev,
1009 pdata->gpio_config,
1010 pdata->gpio_config_num);
1011 if (ret < 0) {
1012 dev_err(asic->dev, "GPIO probe failed\n");
1013 goto out_irq;
1014 }
1015
1016 /* Making a per-device copy is only needed for the
1017 * theoretical case of multiple ASIC3s on one board:
1018 */
1019 memcpy(asic->clocks, asic3_clk_init, sizeof(asic3_clk_init));
1020
1021 asic3_mfd_probe(pdev, pdata, mem);
1022
1023 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
1024 (ASIC3_EXTCF_CF0_BUF_EN|ASIC3_EXTCF_CF0_PWAIT_EN), 1);
1025
1026 dev_info(asic->dev, "ASIC3 Core driver\n");
1027
1028 return 0;
1029
1030 out_irq:
1031 asic3_irq_remove(pdev);
1032
1033 out_unmap:
1034 iounmap(asic->mapping);
1035
1036 return ret;
1037 }
1038
asic3_remove(struct platform_device * pdev)1039 static int asic3_remove(struct platform_device *pdev)
1040 {
1041 int ret;
1042 struct asic3 *asic = platform_get_drvdata(pdev);
1043
1044 asic3_set_register(asic, ASIC3_OFFSET(EXTCF, SELECT),
1045 (ASIC3_EXTCF_CF0_BUF_EN|ASIC3_EXTCF_CF0_PWAIT_EN), 0);
1046
1047 asic3_mfd_remove(pdev);
1048
1049 ret = asic3_gpio_remove(pdev);
1050 if (ret < 0)
1051 return ret;
1052 asic3_irq_remove(pdev);
1053
1054 asic3_write_register(asic, ASIC3_OFFSET(CLOCK, SEL), 0);
1055
1056 iounmap(asic->mapping);
1057
1058 return 0;
1059 }
1060
asic3_shutdown(struct platform_device * pdev)1061 static void asic3_shutdown(struct platform_device *pdev)
1062 {
1063 }
1064
1065 static struct platform_driver asic3_device_driver = {
1066 .driver = {
1067 .name = "asic3",
1068 },
1069 .remove = asic3_remove,
1070 .shutdown = asic3_shutdown,
1071 };
1072
asic3_init(void)1073 static int __init asic3_init(void)
1074 {
1075 int retval = 0;
1076
1077 retval = platform_driver_probe(&asic3_device_driver, asic3_probe);
1078
1079 return retval;
1080 }
1081
1082 subsys_initcall(asic3_init);
1083
