1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * vsp1_drm.c -- R-Car VSP1 DRM/KMS Interface
4 *
5 * Copyright (C) 2015 Renesas Electronics Corporation
6 *
7 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
8 */
9
10 #include <linux/device.h>
11 #include <linux/dma-mapping.h>
12 #include <linux/slab.h>
13
14 #include <media/media-entity.h>
15 #include <media/v4l2-subdev.h>
16 #include <media/vsp1.h>
17
18 #include "vsp1.h"
19 #include "vsp1_brx.h"
20 #include "vsp1_dl.h"
21 #include "vsp1_drm.h"
22 #include "vsp1_lif.h"
23 #include "vsp1_pipe.h"
24 #include "vsp1_rwpf.h"
25 #include "vsp1_uif.h"
26
27 #define BRX_NAME(e) (e)->type == VSP1_ENTITY_BRU ? "BRU" : "BRS"
28
29 /* -----------------------------------------------------------------------------
30 * Interrupt Handling
31 */
32
vsp1_du_pipeline_frame_end(struct vsp1_pipeline * pipe,unsigned int completion)33 static void vsp1_du_pipeline_frame_end(struct vsp1_pipeline *pipe,
34 unsigned int completion)
35 {
36 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
37 bool complete = completion == VSP1_DL_FRAME_END_COMPLETED;
38
39 if (drm_pipe->du_complete) {
40 struct vsp1_entity *uif = drm_pipe->uif;
41 u32 crc;
42
43 crc = uif ? vsp1_uif_get_crc(to_uif(&uif->subdev)) : 0;
44 drm_pipe->du_complete(drm_pipe->du_private, complete, crc);
45 }
46
47 if (completion & VSP1_DL_FRAME_END_INTERNAL) {
48 drm_pipe->force_brx_release = false;
49 wake_up(&drm_pipe->wait_queue);
50 }
51 }
52
53 /* -----------------------------------------------------------------------------
54 * Pipeline Configuration
55 */
56
57 /*
58 * Insert the UIF in the pipeline between the prev and next entities. If no UIF
59 * is available connect the two entities directly.
60 */
vsp1_du_insert_uif(struct vsp1_device * vsp1,struct vsp1_pipeline * pipe,struct vsp1_entity * uif,struct vsp1_entity * prev,unsigned int prev_pad,struct vsp1_entity * next,unsigned int next_pad)61 static int vsp1_du_insert_uif(struct vsp1_device *vsp1,
62 struct vsp1_pipeline *pipe,
63 struct vsp1_entity *uif,
64 struct vsp1_entity *prev, unsigned int prev_pad,
65 struct vsp1_entity *next, unsigned int next_pad)
66 {
67 struct v4l2_subdev_format format;
68 int ret;
69
70 if (!uif) {
71 /*
72 * If there's no UIF to be inserted, connect the previous and
73 * next entities directly.
74 */
75 prev->sink = next;
76 prev->sink_pad = next_pad;
77 return 0;
78 }
79
80 prev->sink = uif;
81 prev->sink_pad = UIF_PAD_SINK;
82
83 memset(&format, 0, sizeof(format));
84 format.which = V4L2_SUBDEV_FORMAT_ACTIVE;
85 format.pad = prev_pad;
86
87 ret = v4l2_subdev_call(&prev->subdev, pad, get_fmt, NULL, &format);
88 if (ret < 0)
89 return ret;
90
91 format.pad = UIF_PAD_SINK;
92
93 ret = v4l2_subdev_call(&uif->subdev, pad, set_fmt, NULL, &format);
94 if (ret < 0)
95 return ret;
96
97 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on UIF sink\n",
98 __func__, format.format.width, format.format.height,
99 format.format.code);
100
101 /*
102 * The UIF doesn't mangle the format between its sink and source pads,
103 * so there is no need to retrieve the format on its source pad.
104 */
105
106 uif->sink = next;
107 uif->sink_pad = next_pad;
108
109 return 0;
110 }
111
112 /* Setup one RPF and the connected BRx sink pad. */
vsp1_du_pipeline_setup_rpf(struct vsp1_device * vsp1,struct vsp1_pipeline * pipe,struct vsp1_rwpf * rpf,struct vsp1_entity * uif,unsigned int brx_input)113 static int vsp1_du_pipeline_setup_rpf(struct vsp1_device *vsp1,
114 struct vsp1_pipeline *pipe,
115 struct vsp1_rwpf *rpf,
116 struct vsp1_entity *uif,
117 unsigned int brx_input)
118 {
119 struct v4l2_subdev_selection sel;
120 struct v4l2_subdev_format format;
121 const struct v4l2_rect *crop;
122 int ret;
123
124 /*
125 * Configure the format on the RPF sink pad and propagate it up to the
126 * BRx sink pad.
127 */
128 crop = &vsp1->drm->inputs[rpf->entity.index].crop;
129
130 memset(&format, 0, sizeof(format));
131 format.which = V4L2_SUBDEV_FORMAT_ACTIVE;
132 format.pad = RWPF_PAD_SINK;
133 format.format.width = crop->width + crop->left;
134 format.format.height = crop->height + crop->top;
135 format.format.code = rpf->fmtinfo->mbus;
136 format.format.field = V4L2_FIELD_NONE;
137
138 ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_fmt, NULL,
139 &format);
140 if (ret < 0)
141 return ret;
142
143 dev_dbg(vsp1->dev,
144 "%s: set format %ux%u (%x) on RPF%u sink\n",
145 __func__, format.format.width, format.format.height,
146 format.format.code, rpf->entity.index);
147
148 memset(&sel, 0, sizeof(sel));
149 sel.which = V4L2_SUBDEV_FORMAT_ACTIVE;
150 sel.pad = RWPF_PAD_SINK;
151 sel.target = V4L2_SEL_TGT_CROP;
152 sel.r = *crop;
153
154 ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_selection, NULL,
155 &sel);
156 if (ret < 0)
157 return ret;
158
159 dev_dbg(vsp1->dev,
160 "%s: set selection (%u,%u)/%ux%u on RPF%u sink\n",
161 __func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height,
162 rpf->entity.index);
163
164 /*
165 * RPF source, hardcode the format to ARGB8888 to turn on format
166 * conversion if needed.
167 */
168 format.pad = RWPF_PAD_SOURCE;
169
170 ret = v4l2_subdev_call(&rpf->entity.subdev, pad, get_fmt, NULL,
171 &format);
172 if (ret < 0)
173 return ret;
174
175 dev_dbg(vsp1->dev,
176 "%s: got format %ux%u (%x) on RPF%u source\n",
177 __func__, format.format.width, format.format.height,
178 format.format.code, rpf->entity.index);
179
180 format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;
181
182 ret = v4l2_subdev_call(&rpf->entity.subdev, pad, set_fmt, NULL,
183 &format);
184 if (ret < 0)
185 return ret;
186
187 /* Insert and configure the UIF if available. */
188 ret = vsp1_du_insert_uif(vsp1, pipe, uif, &rpf->entity, RWPF_PAD_SOURCE,
189 pipe->brx, brx_input);
190 if (ret < 0)
191 return ret;
192
193 /* BRx sink, propagate the format from the RPF source. */
194 format.pad = brx_input;
195
196 ret = v4l2_subdev_call(&pipe->brx->subdev, pad, set_fmt, NULL,
197 &format);
198 if (ret < 0)
199 return ret;
200
201 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n",
202 __func__, format.format.width, format.format.height,
203 format.format.code, BRX_NAME(pipe->brx), format.pad);
204
205 sel.pad = brx_input;
206 sel.target = V4L2_SEL_TGT_COMPOSE;
207 sel.r = vsp1->drm->inputs[rpf->entity.index].compose;
208
209 ret = v4l2_subdev_call(&pipe->brx->subdev, pad, set_selection, NULL,
210 &sel);
211 if (ret < 0)
212 return ret;
213
214 dev_dbg(vsp1->dev, "%s: set selection (%u,%u)/%ux%u on %s pad %u\n",
215 __func__, sel.r.left, sel.r.top, sel.r.width, sel.r.height,
216 BRX_NAME(pipe->brx), sel.pad);
217
218 return 0;
219 }
220
221 /* Setup the BRx source pad. */
222 static int vsp1_du_pipeline_setup_inputs(struct vsp1_device *vsp1,
223 struct vsp1_pipeline *pipe);
224 static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe);
225
vsp1_du_pipeline_setup_brx(struct vsp1_device * vsp1,struct vsp1_pipeline * pipe)226 static int vsp1_du_pipeline_setup_brx(struct vsp1_device *vsp1,
227 struct vsp1_pipeline *pipe)
228 {
229 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
230 struct v4l2_subdev_format format = {
231 .which = V4L2_SUBDEV_FORMAT_ACTIVE,
232 };
233 struct vsp1_entity *brx;
234 int ret;
235
236 /*
237 * Pick a BRx:
238 * - If we need more than two inputs, use the BRU.
239 * - Otherwise, if we are not forced to release our BRx, keep it.
240 * - Else, use any free BRx (randomly starting with the BRU).
241 */
242 if (pipe->num_inputs > 2)
243 brx = &vsp1->bru->entity;
244 else if (pipe->brx && !drm_pipe->force_brx_release)
245 brx = pipe->brx;
246 else if (!vsp1->bru->entity.pipe)
247 brx = &vsp1->bru->entity;
248 else
249 brx = &vsp1->brs->entity;
250
251 /* Switch BRx if needed. */
252 if (brx != pipe->brx) {
253 struct vsp1_entity *released_brx = NULL;
254
255 /* Release our BRx if we have one. */
256 if (pipe->brx) {
257 dev_dbg(vsp1->dev, "%s: pipe %u: releasing %s\n",
258 __func__, pipe->lif->index,
259 BRX_NAME(pipe->brx));
260
261 /*
262 * The BRx might be acquired by the other pipeline in
263 * the next step. We must thus remove it from the list
264 * of entities for this pipeline. The other pipeline's
265 * hardware configuration will reconfigure the BRx
266 * routing.
267 *
268 * However, if the other pipeline doesn't acquire our
269 * BRx, we need to keep it in the list, otherwise the
270 * hardware configuration step won't disconnect it from
271 * the pipeline. To solve this, store the released BRx
272 * pointer to add it back to the list of entities later
273 * if it isn't acquired by the other pipeline.
274 */
275 released_brx = pipe->brx;
276
277 list_del(&pipe->brx->list_pipe);
278 pipe->brx->sink = NULL;
279 pipe->brx->pipe = NULL;
280 pipe->brx = NULL;
281 }
282
283 /*
284 * If the BRx we need is in use, force the owner pipeline to
285 * switch to the other BRx and wait until the switch completes.
286 */
287 if (brx->pipe) {
288 struct vsp1_drm_pipeline *owner_pipe;
289
290 dev_dbg(vsp1->dev, "%s: pipe %u: waiting for %s\n",
291 __func__, pipe->lif->index, BRX_NAME(brx));
292
293 owner_pipe = to_vsp1_drm_pipeline(brx->pipe);
294 owner_pipe->force_brx_release = true;
295
296 vsp1_du_pipeline_setup_inputs(vsp1, &owner_pipe->pipe);
297 vsp1_du_pipeline_configure(&owner_pipe->pipe);
298
299 ret = wait_event_timeout(owner_pipe->wait_queue,
300 !owner_pipe->force_brx_release,
301 msecs_to_jiffies(500));
302 if (ret == 0)
303 dev_warn(vsp1->dev,
304 "DRM pipeline %u reconfiguration timeout\n",
305 owner_pipe->pipe.lif->index);
306 }
307
308 /*
309 * If the BRx we have released previously hasn't been acquired
310 * by the other pipeline, add it back to the entities list (with
311 * the pipe pointer NULL) to let vsp1_du_pipeline_configure()
312 * disconnect it from the hardware pipeline.
313 */
314 if (released_brx && !released_brx->pipe)
315 list_add_tail(&released_brx->list_pipe,
316 &pipe->entities);
317
318 /* Add the BRx to the pipeline. */
319 dev_dbg(vsp1->dev, "%s: pipe %u: acquired %s\n",
320 __func__, pipe->lif->index, BRX_NAME(brx));
321
322 pipe->brx = brx;
323 pipe->brx->pipe = pipe;
324 pipe->brx->sink = &pipe->output->entity;
325 pipe->brx->sink_pad = 0;
326
327 list_add_tail(&pipe->brx->list_pipe, &pipe->entities);
328 }
329
330 /*
331 * Configure the format on the BRx source and verify that it matches the
332 * requested format. We don't set the media bus code as it is configured
333 * on the BRx sink pad 0 and propagated inside the entity, not on the
334 * source pad.
335 */
336 format.pad = pipe->brx->source_pad;
337 format.format.width = drm_pipe->width;
338 format.format.height = drm_pipe->height;
339 format.format.field = V4L2_FIELD_NONE;
340
341 ret = v4l2_subdev_call(&pipe->brx->subdev, pad, set_fmt, NULL,
342 &format);
343 if (ret < 0)
344 return ret;
345
346 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on %s pad %u\n",
347 __func__, format.format.width, format.format.height,
348 format.format.code, BRX_NAME(pipe->brx), pipe->brx->source_pad);
349
350 if (format.format.width != drm_pipe->width ||
351 format.format.height != drm_pipe->height) {
352 dev_dbg(vsp1->dev, "%s: format mismatch\n", __func__);
353 return -EPIPE;
354 }
355
356 return 0;
357 }
358
rpf_zpos(struct vsp1_device * vsp1,struct vsp1_rwpf * rpf)359 static unsigned int rpf_zpos(struct vsp1_device *vsp1, struct vsp1_rwpf *rpf)
360 {
361 return vsp1->drm->inputs[rpf->entity.index].zpos;
362 }
363
364 /* Setup the input side of the pipeline (RPFs and BRx). */
vsp1_du_pipeline_setup_inputs(struct vsp1_device * vsp1,struct vsp1_pipeline * pipe)365 static int vsp1_du_pipeline_setup_inputs(struct vsp1_device *vsp1,
366 struct vsp1_pipeline *pipe)
367 {
368 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
369 struct vsp1_rwpf *inputs[VSP1_MAX_RPF] = { NULL, };
370 struct vsp1_entity *uif;
371 bool use_uif = false;
372 struct vsp1_brx *brx;
373 unsigned int i;
374 int ret;
375
376 /* Count the number of enabled inputs and sort them by Z-order. */
377 pipe->num_inputs = 0;
378
379 for (i = 0; i < vsp1->info->rpf_count; ++i) {
380 struct vsp1_rwpf *rpf = vsp1->rpf[i];
381 unsigned int j;
382
383 if (!pipe->inputs[i])
384 continue;
385
386 /* Insert the RPF in the sorted RPFs array. */
387 for (j = pipe->num_inputs++; j > 0; --j) {
388 if (rpf_zpos(vsp1, inputs[j-1]) <= rpf_zpos(vsp1, rpf))
389 break;
390 inputs[j] = inputs[j-1];
391 }
392
393 inputs[j] = rpf;
394 }
395
396 /*
397 * Setup the BRx. This must be done before setting up the RPF input
398 * pipelines as the BRx sink compose rectangles depend on the BRx source
399 * format.
400 */
401 ret = vsp1_du_pipeline_setup_brx(vsp1, pipe);
402 if (ret < 0) {
403 dev_err(vsp1->dev, "%s: failed to setup %s source\n", __func__,
404 BRX_NAME(pipe->brx));
405 return ret;
406 }
407
408 brx = to_brx(&pipe->brx->subdev);
409
410 /* Setup the RPF input pipeline for every enabled input. */
411 for (i = 0; i < pipe->brx->source_pad; ++i) {
412 struct vsp1_rwpf *rpf = inputs[i];
413
414 if (!rpf) {
415 brx->inputs[i].rpf = NULL;
416 continue;
417 }
418
419 if (!rpf->entity.pipe) {
420 rpf->entity.pipe = pipe;
421 list_add_tail(&rpf->entity.list_pipe, &pipe->entities);
422 }
423
424 brx->inputs[i].rpf = rpf;
425 rpf->brx_input = i;
426 rpf->entity.sink = pipe->brx;
427 rpf->entity.sink_pad = i;
428
429 dev_dbg(vsp1->dev, "%s: connecting RPF.%u to %s:%u\n",
430 __func__, rpf->entity.index, BRX_NAME(pipe->brx), i);
431
432 uif = drm_pipe->crc.source == VSP1_DU_CRC_PLANE &&
433 drm_pipe->crc.index == i ? drm_pipe->uif : NULL;
434 if (uif)
435 use_uif = true;
436 ret = vsp1_du_pipeline_setup_rpf(vsp1, pipe, rpf, uif, i);
437 if (ret < 0) {
438 dev_err(vsp1->dev,
439 "%s: failed to setup RPF.%u\n",
440 __func__, rpf->entity.index);
441 return ret;
442 }
443 }
444
445 /* Insert and configure the UIF at the BRx output if available. */
446 uif = drm_pipe->crc.source == VSP1_DU_CRC_OUTPUT ? drm_pipe->uif : NULL;
447 if (uif)
448 use_uif = true;
449 ret = vsp1_du_insert_uif(vsp1, pipe, uif,
450 pipe->brx, pipe->brx->source_pad,
451 &pipe->output->entity, 0);
452 if (ret < 0)
453 dev_err(vsp1->dev, "%s: failed to setup UIF after %s\n",
454 __func__, BRX_NAME(pipe->brx));
455
456 /*
457 * If the UIF is not in use schedule it for removal by setting its pipe
458 * pointer to NULL, vsp1_du_pipeline_configure() will remove it from the
459 * hardware pipeline and from the pipeline's list of entities. Otherwise
460 * make sure it is present in the pipeline's list of entities if it
461 * wasn't already.
462 */
463 if (!use_uif) {
464 drm_pipe->uif->pipe = NULL;
465 } else if (!drm_pipe->uif->pipe) {
466 drm_pipe->uif->pipe = pipe;
467 list_add_tail(&drm_pipe->uif->list_pipe, &pipe->entities);
468 }
469
470 return 0;
471 }
472
473 /* Setup the output side of the pipeline (WPF and LIF). */
vsp1_du_pipeline_setup_output(struct vsp1_device * vsp1,struct vsp1_pipeline * pipe)474 static int vsp1_du_pipeline_setup_output(struct vsp1_device *vsp1,
475 struct vsp1_pipeline *pipe)
476 {
477 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
478 struct v4l2_subdev_format format = { 0, };
479 int ret;
480
481 format.which = V4L2_SUBDEV_FORMAT_ACTIVE;
482 format.pad = RWPF_PAD_SINK;
483 format.format.width = drm_pipe->width;
484 format.format.height = drm_pipe->height;
485 format.format.code = MEDIA_BUS_FMT_ARGB8888_1X32;
486 format.format.field = V4L2_FIELD_NONE;
487
488 ret = v4l2_subdev_call(&pipe->output->entity.subdev, pad, set_fmt, NULL,
489 &format);
490 if (ret < 0)
491 return ret;
492
493 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on WPF%u sink\n",
494 __func__, format.format.width, format.format.height,
495 format.format.code, pipe->output->entity.index);
496
497 format.pad = RWPF_PAD_SOURCE;
498 ret = v4l2_subdev_call(&pipe->output->entity.subdev, pad, get_fmt, NULL,
499 &format);
500 if (ret < 0)
501 return ret;
502
503 dev_dbg(vsp1->dev, "%s: got format %ux%u (%x) on WPF%u source\n",
504 __func__, format.format.width, format.format.height,
505 format.format.code, pipe->output->entity.index);
506
507 format.pad = LIF_PAD_SINK;
508 ret = v4l2_subdev_call(&pipe->lif->subdev, pad, set_fmt, NULL,
509 &format);
510 if (ret < 0)
511 return ret;
512
513 dev_dbg(vsp1->dev, "%s: set format %ux%u (%x) on LIF%u sink\n",
514 __func__, format.format.width, format.format.height,
515 format.format.code, pipe->lif->index);
516
517 /*
518 * Verify that the format at the output of the pipeline matches the
519 * requested frame size and media bus code.
520 */
521 if (format.format.width != drm_pipe->width ||
522 format.format.height != drm_pipe->height ||
523 format.format.code != MEDIA_BUS_FMT_ARGB8888_1X32) {
524 dev_dbg(vsp1->dev, "%s: format mismatch on LIF%u\n", __func__,
525 pipe->lif->index);
526 return -EPIPE;
527 }
528
529 return 0;
530 }
531
532 /* Configure all entities in the pipeline. */
vsp1_du_pipeline_configure(struct vsp1_pipeline * pipe)533 static void vsp1_du_pipeline_configure(struct vsp1_pipeline *pipe)
534 {
535 struct vsp1_drm_pipeline *drm_pipe = to_vsp1_drm_pipeline(pipe);
536 struct vsp1_entity *entity;
537 struct vsp1_entity *next;
538 struct vsp1_dl_list *dl;
539 struct vsp1_dl_body *dlb;
540
541 dl = vsp1_dl_list_get(pipe->output->dlm);
542 dlb = vsp1_dl_list_get_body0(dl);
543
544 list_for_each_entry_safe(entity, next, &pipe->entities, list_pipe) {
545 /* Disconnect unused entities from the pipeline. */
546 if (!entity->pipe) {
547 vsp1_dl_body_write(dlb, entity->route->reg,
548 VI6_DPR_NODE_UNUSED);
549
550 entity->sink = NULL;
551 list_del(&entity->list_pipe);
552
553 continue;
554 }
555
556 vsp1_entity_route_setup(entity, pipe, dlb);
557 vsp1_entity_configure_stream(entity, pipe, dlb);
558 vsp1_entity_configure_frame(entity, pipe, dl, dlb);
559 vsp1_entity_configure_partition(entity, pipe, dl, dlb);
560 }
561
562 vsp1_dl_list_commit(dl, drm_pipe->force_brx_release);
563 }
564
565 /* -----------------------------------------------------------------------------
566 * DU Driver API
567 */
568
vsp1_du_init(struct device * dev)569 int vsp1_du_init(struct device *dev)
570 {
571 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
572
573 if (!vsp1)
574 return -EPROBE_DEFER;
575
576 return 0;
577 }
578 EXPORT_SYMBOL_GPL(vsp1_du_init);
579
580 /**
581 * vsp1_du_setup_lif - Setup the output part of the VSP pipeline
582 * @dev: the VSP device
583 * @pipe_index: the DRM pipeline index
584 * @cfg: the LIF configuration
585 *
586 * Configure the output part of VSP DRM pipeline for the given frame @cfg.width
587 * and @cfg.height. This sets up formats on the BRx source pad, the WPF sink and
588 * source pads, and the LIF sink pad.
589 *
590 * The @pipe_index argument selects which DRM pipeline to setup. The number of
591 * available pipelines depend on the VSP instance.
592 *
593 * As the media bus code on the blend unit source pad is conditioned by the
594 * configuration of its sink 0 pad, we also set up the formats on all blend unit
595 * sinks, even if the configuration will be overwritten later by
596 * vsp1_du_setup_rpf(). This ensures that the blend unit configuration is set to
597 * a well defined state.
598 *
599 * Return 0 on success or a negative error code on failure.
600 */
vsp1_du_setup_lif(struct device * dev,unsigned int pipe_index,const struct vsp1_du_lif_config * cfg)601 int vsp1_du_setup_lif(struct device *dev, unsigned int pipe_index,
602 const struct vsp1_du_lif_config *cfg)
603 {
604 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
605 struct vsp1_drm_pipeline *drm_pipe;
606 struct vsp1_pipeline *pipe;
607 unsigned long flags;
608 unsigned int i;
609 int ret;
610
611 if (pipe_index >= vsp1->info->lif_count)
612 return -EINVAL;
613
614 drm_pipe = &vsp1->drm->pipe[pipe_index];
615 pipe = &drm_pipe->pipe;
616
617 if (!cfg) {
618 struct vsp1_brx *brx;
619
620 mutex_lock(&vsp1->drm->lock);
621
622 brx = to_brx(&pipe->brx->subdev);
623
624 /*
625 * NULL configuration means the CRTC is being disabled, stop
626 * the pipeline and turn the light off.
627 */
628 ret = vsp1_pipeline_stop(pipe);
629 if (ret == -ETIMEDOUT)
630 dev_err(vsp1->dev, "DRM pipeline stop timeout\n");
631
632 for (i = 0; i < ARRAY_SIZE(pipe->inputs); ++i) {
633 struct vsp1_rwpf *rpf = pipe->inputs[i];
634
635 if (!rpf)
636 continue;
637
638 /*
639 * Remove the RPF from the pipe and the list of BRx
640 * inputs.
641 */
642 WARN_ON(!rpf->entity.pipe);
643 rpf->entity.pipe = NULL;
644 list_del(&rpf->entity.list_pipe);
645 pipe->inputs[i] = NULL;
646
647 brx->inputs[rpf->brx_input].rpf = NULL;
648 }
649
650 drm_pipe->du_complete = NULL;
651 pipe->num_inputs = 0;
652
653 dev_dbg(vsp1->dev, "%s: pipe %u: releasing %s\n",
654 __func__, pipe->lif->index,
655 BRX_NAME(pipe->brx));
656
657 list_del(&pipe->brx->list_pipe);
658 pipe->brx->pipe = NULL;
659 pipe->brx = NULL;
660
661 mutex_unlock(&vsp1->drm->lock);
662
663 vsp1_dlm_reset(pipe->output->dlm);
664 vsp1_device_put(vsp1);
665
666 dev_dbg(vsp1->dev, "%s: pipeline disabled\n", __func__);
667
668 return 0;
669 }
670
671 drm_pipe->width = cfg->width;
672 drm_pipe->height = cfg->height;
673 pipe->interlaced = cfg->interlaced;
674
675 dev_dbg(vsp1->dev, "%s: configuring LIF%u with format %ux%u%s\n",
676 __func__, pipe_index, cfg->width, cfg->height,
677 pipe->interlaced ? "i" : "");
678
679 mutex_lock(&vsp1->drm->lock);
680
681 /* Setup formats through the pipeline. */
682 ret = vsp1_du_pipeline_setup_inputs(vsp1, pipe);
683 if (ret < 0)
684 goto unlock;
685
686 ret = vsp1_du_pipeline_setup_output(vsp1, pipe);
687 if (ret < 0)
688 goto unlock;
689
690 /* Enable the VSP1. */
691 ret = vsp1_device_get(vsp1);
692 if (ret < 0)
693 goto unlock;
694
695 /*
696 * Register a callback to allow us to notify the DRM driver of frame
697 * completion events.
698 */
699 drm_pipe->du_complete = cfg->callback;
700 drm_pipe->du_private = cfg->callback_data;
701
702 /* Disable the display interrupts. */
703 vsp1_write(vsp1, VI6_DISP_IRQ_STA, 0);
704 vsp1_write(vsp1, VI6_DISP_IRQ_ENB, 0);
705
706 /* Configure all entities in the pipeline. */
707 vsp1_du_pipeline_configure(pipe);
708
709 unlock:
710 mutex_unlock(&vsp1->drm->lock);
711
712 if (ret < 0)
713 return ret;
714
715 /* Start the pipeline. */
716 spin_lock_irqsave(&pipe->irqlock, flags);
717 vsp1_pipeline_run(pipe);
718 spin_unlock_irqrestore(&pipe->irqlock, flags);
719
720 dev_dbg(vsp1->dev, "%s: pipeline enabled\n", __func__);
721
722 return 0;
723 }
724 EXPORT_SYMBOL_GPL(vsp1_du_setup_lif);
725
726 /**
727 * vsp1_du_atomic_begin - Prepare for an atomic update
728 * @dev: the VSP device
729 * @pipe_index: the DRM pipeline index
730 */
vsp1_du_atomic_begin(struct device * dev,unsigned int pipe_index)731 void vsp1_du_atomic_begin(struct device *dev, unsigned int pipe_index)
732 {
733 }
734 EXPORT_SYMBOL_GPL(vsp1_du_atomic_begin);
735
736 /**
737 * vsp1_du_atomic_update - Setup one RPF input of the VSP pipeline
738 * @dev: the VSP device
739 * @pipe_index: the DRM pipeline index
740 * @rpf_index: index of the RPF to setup (0-based)
741 * @cfg: the RPF configuration
742 *
743 * Configure the VSP to perform image composition through RPF @rpf_index as
744 * described by the @cfg configuration. The image to compose is referenced by
745 * @cfg.mem and composed using the @cfg.src crop rectangle and the @cfg.dst
746 * composition rectangle. The Z-order is configurable with higher @zpos values
747 * displayed on top.
748 *
749 * If the @cfg configuration is NULL, the RPF will be disabled. Calling the
750 * function on a disabled RPF is allowed.
751 *
752 * Image format as stored in memory is expressed as a V4L2 @cfg.pixelformat
753 * value. The memory pitch is configurable to allow for padding at end of lines,
754 * or simply for images that extend beyond the crop rectangle boundaries. The
755 * @cfg.pitch value is expressed in bytes and applies to all planes for
756 * multiplanar formats.
757 *
758 * The source memory buffer is referenced by the DMA address of its planes in
759 * the @cfg.mem array. Up to two planes are supported. The second plane DMA
760 * address is ignored for formats using a single plane.
761 *
762 * This function isn't reentrant, the caller needs to serialize calls.
763 *
764 * Return 0 on success or a negative error code on failure.
765 */
vsp1_du_atomic_update(struct device * dev,unsigned int pipe_index,unsigned int rpf_index,const struct vsp1_du_atomic_config * cfg)766 int vsp1_du_atomic_update(struct device *dev, unsigned int pipe_index,
767 unsigned int rpf_index,
768 const struct vsp1_du_atomic_config *cfg)
769 {
770 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
771 struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index];
772 const struct vsp1_format_info *fmtinfo;
773 struct vsp1_rwpf *rpf;
774
775 if (rpf_index >= vsp1->info->rpf_count)
776 return -EINVAL;
777
778 rpf = vsp1->rpf[rpf_index];
779
780 if (!cfg) {
781 dev_dbg(vsp1->dev, "%s: RPF%u: disable requested\n", __func__,
782 rpf_index);
783
784 /*
785 * Remove the RPF from the pipeline's inputs. Keep it in the
786 * pipeline's entity list to let vsp1_du_pipeline_configure()
787 * remove it from the hardware pipeline.
788 */
789 rpf->entity.pipe = NULL;
790 drm_pipe->pipe.inputs[rpf_index] = NULL;
791 return 0;
792 }
793
794 dev_dbg(vsp1->dev,
795 "%s: RPF%u: (%u,%u)/%ux%u -> (%u,%u)/%ux%u (%08x), pitch %u dma { %pad, %pad, %pad } zpos %u\n",
796 __func__, rpf_index,
797 cfg->src.left, cfg->src.top, cfg->src.width, cfg->src.height,
798 cfg->dst.left, cfg->dst.top, cfg->dst.width, cfg->dst.height,
799 cfg->pixelformat, cfg->pitch, &cfg->mem[0], &cfg->mem[1],
800 &cfg->mem[2], cfg->zpos);
801
802 /*
803 * Store the format, stride, memory buffer address, crop and compose
804 * rectangles and Z-order position and for the input.
805 */
806 fmtinfo = vsp1_get_format_info(vsp1, cfg->pixelformat);
807 if (!fmtinfo) {
808 dev_dbg(vsp1->dev, "Unsupported pixel format %08x for RPF\n",
809 cfg->pixelformat);
810 return -EINVAL;
811 }
812
813 rpf->fmtinfo = fmtinfo;
814 rpf->format.num_planes = fmtinfo->planes;
815 rpf->format.plane_fmt[0].bytesperline = cfg->pitch;
816 rpf->format.plane_fmt[1].bytesperline = cfg->pitch;
817 rpf->alpha = cfg->alpha;
818
819 rpf->mem.addr[0] = cfg->mem[0];
820 rpf->mem.addr[1] = cfg->mem[1];
821 rpf->mem.addr[2] = cfg->mem[2];
822
823 vsp1->drm->inputs[rpf_index].crop = cfg->src;
824 vsp1->drm->inputs[rpf_index].compose = cfg->dst;
825 vsp1->drm->inputs[rpf_index].zpos = cfg->zpos;
826
827 drm_pipe->pipe.inputs[rpf_index] = rpf;
828
829 return 0;
830 }
831 EXPORT_SYMBOL_GPL(vsp1_du_atomic_update);
832
833 /**
834 * vsp1_du_atomic_flush - Commit an atomic update
835 * @dev: the VSP device
836 * @pipe_index: the DRM pipeline index
837 * @cfg: atomic pipe configuration
838 */
vsp1_du_atomic_flush(struct device * dev,unsigned int pipe_index,const struct vsp1_du_atomic_pipe_config * cfg)839 void vsp1_du_atomic_flush(struct device *dev, unsigned int pipe_index,
840 const struct vsp1_du_atomic_pipe_config *cfg)
841 {
842 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
843 struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[pipe_index];
844 struct vsp1_pipeline *pipe = &drm_pipe->pipe;
845
846 drm_pipe->crc = cfg->crc;
847
848 mutex_lock(&vsp1->drm->lock);
849 vsp1_du_pipeline_setup_inputs(vsp1, pipe);
850 vsp1_du_pipeline_configure(pipe);
851 mutex_unlock(&vsp1->drm->lock);
852 }
853 EXPORT_SYMBOL_GPL(vsp1_du_atomic_flush);
854
vsp1_du_map_sg(struct device * dev,struct sg_table * sgt)855 int vsp1_du_map_sg(struct device *dev, struct sg_table *sgt)
856 {
857 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
858
859 /*
860 * As all the buffers allocated by the DU driver are coherent, we can
861 * skip cache sync. This will need to be revisited when support for
862 * non-coherent buffers will be added to the DU driver.
863 */
864 return dma_map_sg_attrs(vsp1->bus_master, sgt->sgl, sgt->nents,
865 DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
866 }
867 EXPORT_SYMBOL_GPL(vsp1_du_map_sg);
868
vsp1_du_unmap_sg(struct device * dev,struct sg_table * sgt)869 void vsp1_du_unmap_sg(struct device *dev, struct sg_table *sgt)
870 {
871 struct vsp1_device *vsp1 = dev_get_drvdata(dev);
872
873 dma_unmap_sg_attrs(vsp1->bus_master, sgt->sgl, sgt->nents,
874 DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
875 }
876 EXPORT_SYMBOL_GPL(vsp1_du_unmap_sg);
877
878 /* -----------------------------------------------------------------------------
879 * Initialization
880 */
881
vsp1_drm_init(struct vsp1_device * vsp1)882 int vsp1_drm_init(struct vsp1_device *vsp1)
883 {
884 unsigned int i;
885
886 vsp1->drm = devm_kzalloc(vsp1->dev, sizeof(*vsp1->drm), GFP_KERNEL);
887 if (!vsp1->drm)
888 return -ENOMEM;
889
890 mutex_init(&vsp1->drm->lock);
891
892 /* Create one DRM pipeline per LIF. */
893 for (i = 0; i < vsp1->info->lif_count; ++i) {
894 struct vsp1_drm_pipeline *drm_pipe = &vsp1->drm->pipe[i];
895 struct vsp1_pipeline *pipe = &drm_pipe->pipe;
896
897 init_waitqueue_head(&drm_pipe->wait_queue);
898
899 vsp1_pipeline_init(pipe);
900
901 pipe->frame_end = vsp1_du_pipeline_frame_end;
902
903 /*
904 * The output side of the DRM pipeline is static, add the
905 * corresponding entities manually.
906 */
907 pipe->output = vsp1->wpf[i];
908 pipe->lif = &vsp1->lif[i]->entity;
909
910 pipe->output->entity.pipe = pipe;
911 pipe->output->entity.sink = pipe->lif;
912 pipe->output->entity.sink_pad = 0;
913 list_add_tail(&pipe->output->entity.list_pipe, &pipe->entities);
914
915 pipe->lif->pipe = pipe;
916 list_add_tail(&pipe->lif->list_pipe, &pipe->entities);
917
918 /*
919 * CRC computation is initially disabled, don't add the UIF to
920 * the pipeline.
921 */
922 if (i < vsp1->info->uif_count)
923 drm_pipe->uif = &vsp1->uif[i]->entity;
924 }
925
926 /* Disable all RPFs initially. */
927 for (i = 0; i < vsp1->info->rpf_count; ++i) {
928 struct vsp1_rwpf *input = vsp1->rpf[i];
929
930 INIT_LIST_HEAD(&input->entity.list_pipe);
931 }
932
933 return 0;
934 }
935
vsp1_drm_cleanup(struct vsp1_device * vsp1)936 void vsp1_drm_cleanup(struct vsp1_device *vsp1)
937 {
938 mutex_destroy(&vsp1->drm->lock);
939 }
940
