1 /* 2 * Tegra CEC register definitions 3 * 4 * The original 3.10 CEC driver using a custom API: 5 * 6 * Copyright (c) 2012-2015, NVIDIA CORPORATION. All rights reserved. 7 * 8 * Conversion to the CEC framework and to the mainline kernel: 9 * 10 * Copyright 2016-2017 Cisco Systems, Inc. and/or its affiliates. All rights reserved. 11 * 12 * This program is free software; you can redistribute it and/or modify it 13 * under the terms and conditions of the GNU General Public License, 14 * version 2, as published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope it will be useful, but WITHOUT 17 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 18 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 19 * more details. 20 * 21 * You should have received a copy of the GNU General Public License 22 * along with this program. If not, see <http://www.gnu.org/licenses/>. 23 */ 24 25 #ifndef TEGRA_CEC_H 26 #define TEGRA_CEC_H 27 28 /* CEC registers */ 29 #define TEGRA_CEC_SW_CONTROL 0x000 30 #define TEGRA_CEC_HW_CONTROL 0x004 31 #define TEGRA_CEC_INPUT_FILTER 0x008 32 #define TEGRA_CEC_TX_REGISTER 0x010 33 #define TEGRA_CEC_RX_REGISTER 0x014 34 #define TEGRA_CEC_RX_TIMING_0 0x018 35 #define TEGRA_CEC_RX_TIMING_1 0x01c 36 #define TEGRA_CEC_RX_TIMING_2 0x020 37 #define TEGRA_CEC_TX_TIMING_0 0x024 38 #define TEGRA_CEC_TX_TIMING_1 0x028 39 #define TEGRA_CEC_TX_TIMING_2 0x02c 40 #define TEGRA_CEC_INT_STAT 0x030 41 #define TEGRA_CEC_INT_MASK 0x034 42 #define TEGRA_CEC_HW_DEBUG_RX 0x038 43 #define TEGRA_CEC_HW_DEBUG_TX 0x03c 44 45 #define TEGRA_CEC_HWCTRL_RX_LADDR_MASK 0x7fff 46 #define TEGRA_CEC_HWCTRL_RX_LADDR(x) \ 47 ((x) & TEGRA_CEC_HWCTRL_RX_LADDR_MASK) 48 #define TEGRA_CEC_HWCTRL_RX_SNOOP (1 << 15) 49 #define TEGRA_CEC_HWCTRL_RX_NAK_MODE (1 << 16) 50 #define TEGRA_CEC_HWCTRL_TX_NAK_MODE (1 << 24) 51 #define TEGRA_CEC_HWCTRL_FAST_SIM_MODE (1 << 30) 52 #define TEGRA_CEC_HWCTRL_TX_RX_MODE (1 << 31) 53 54 #define TEGRA_CEC_INPUT_FILTER_MODE (1 << 31) 55 #define TEGRA_CEC_INPUT_FILTER_FIFO_LENGTH_SHIFT 0 56 57 #define TEGRA_CEC_TX_REG_DATA_SHIFT 0 58 #define TEGRA_CEC_TX_REG_EOM (1 << 8) 59 #define TEGRA_CEC_TX_REG_BCAST (1 << 12) 60 #define TEGRA_CEC_TX_REG_START_BIT (1 << 16) 61 #define TEGRA_CEC_TX_REG_RETRY (1 << 17) 62 63 #define TEGRA_CEC_RX_REGISTER_SHIFT 0 64 #define TEGRA_CEC_RX_REGISTER_EOM (1 << 8) 65 #define TEGRA_CEC_RX_REGISTER_ACK (1 << 9) 66 67 #define TEGRA_CEC_RX_TIM0_START_BIT_MAX_LO_TIME_SHIFT 0 68 #define TEGRA_CEC_RX_TIM0_START_BIT_MIN_LO_TIME_SHIFT 8 69 #define TEGRA_CEC_RX_TIM0_START_BIT_MAX_DURATION_SHIFT 16 70 #define TEGRA_CEC_RX_TIM0_START_BIT_MIN_DURATION_SHIFT 24 71 72 #define TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_LO_TIME_SHIFT 0 73 #define TEGRA_CEC_RX_TIM1_DATA_BIT_SAMPLE_TIME_SHIFT 8 74 #define TEGRA_CEC_RX_TIM1_DATA_BIT_MAX_DURATION_SHIFT 16 75 #define TEGRA_CEC_RX_TIM1_DATA_BIT_MIN_DURATION_SHIFT 24 76 77 #define TEGRA_CEC_RX_TIM2_END_OF_BLOCK_TIME_SHIFT 0 78 79 #define TEGRA_CEC_TX_TIM0_START_BIT_LO_TIME_SHIFT 0 80 #define TEGRA_CEC_TX_TIM0_START_BIT_DURATION_SHIFT 8 81 #define TEGRA_CEC_TX_TIM0_BUS_XITION_TIME_SHIFT 16 82 #define TEGRA_CEC_TX_TIM0_BUS_ERROR_LO_TIME_SHIFT 24 83 84 #define TEGRA_CEC_TX_TIM1_LO_DATA_BIT_LO_TIME_SHIFT 0 85 #define TEGRA_CEC_TX_TIM1_HI_DATA_BIT_LO_TIME_SHIFT 8 86 #define TEGRA_CEC_TX_TIM1_DATA_BIT_DURATION_SHIFT 16 87 #define TEGRA_CEC_TX_TIM1_ACK_NAK_BIT_SAMPLE_TIME_SHIFT 24 88 89 #define TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_ADDITIONAL_FRAME_SHIFT 0 90 #define TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_NEW_FRAME_SHIFT 4 91 #define TEGRA_CEC_TX_TIM2_BUS_IDLE_TIME_RETRY_FRAME_SHIFT 8 92 93 #define TEGRA_CEC_INT_STAT_TX_REGISTER_EMPTY (1 << 0) 94 #define TEGRA_CEC_INT_STAT_TX_REGISTER_UNDERRUN (1 << 1) 95 #define TEGRA_CEC_INT_STAT_TX_FRAME_OR_BLOCK_NAKD (1 << 2) 96 #define TEGRA_CEC_INT_STAT_TX_ARBITRATION_FAILED (1 << 3) 97 #define TEGRA_CEC_INT_STAT_TX_BUS_ANOMALY_DETECTED (1 << 4) 98 #define TEGRA_CEC_INT_STAT_TX_FRAME_TRANSMITTED (1 << 5) 99 #define TEGRA_CEC_INT_STAT_RX_REGISTER_FULL (1 << 8) 100 #define TEGRA_CEC_INT_STAT_RX_REGISTER_OVERRUN (1 << 9) 101 #define TEGRA_CEC_INT_STAT_RX_START_BIT_DETECTED (1 << 10) 102 #define TEGRA_CEC_INT_STAT_RX_BUS_ANOMALY_DETECTED (1 << 11) 103 #define TEGRA_CEC_INT_STAT_RX_BUS_ERROR_DETECTED (1 << 12) 104 #define TEGRA_CEC_INT_STAT_FILTERED_RX_DATA_PIN_TRANSITION_H2L (1 << 13) 105 #define TEGRA_CEC_INT_STAT_FILTERED_RX_DATA_PIN_TRANSITION_L2H (1 << 14) 106 107 #define TEGRA_CEC_INT_MASK_TX_REGISTER_EMPTY (1 << 0) 108 #define TEGRA_CEC_INT_MASK_TX_REGISTER_UNDERRUN (1 << 1) 109 #define TEGRA_CEC_INT_MASK_TX_FRAME_OR_BLOCK_NAKD (1 << 2) 110 #define TEGRA_CEC_INT_MASK_TX_ARBITRATION_FAILED (1 << 3) 111 #define TEGRA_CEC_INT_MASK_TX_BUS_ANOMALY_DETECTED (1 << 4) 112 #define TEGRA_CEC_INT_MASK_TX_FRAME_TRANSMITTED (1 << 5) 113 #define TEGRA_CEC_INT_MASK_RX_REGISTER_FULL (1 << 8) 114 #define TEGRA_CEC_INT_MASK_RX_REGISTER_OVERRUN (1 << 9) 115 #define TEGRA_CEC_INT_MASK_RX_START_BIT_DETECTED (1 << 10) 116 #define TEGRA_CEC_INT_MASK_RX_BUS_ANOMALY_DETECTED (1 << 11) 117 #define TEGRA_CEC_INT_MASK_RX_BUS_ERROR_DETECTED (1 << 12) 118 #define TEGRA_CEC_INT_MASK_FILTERED_RX_DATA_PIN_TRANSITION_H2L (1 << 13) 119 #define TEGRA_CEC_INT_MASK_FILTERED_RX_DATA_PIN_TRANSITION_L2H (1 << 14) 120 121 #define TEGRA_CEC_HW_DEBUG_TX_DURATION_COUNT_SHIFT 0 122 #define TEGRA_CEC_HW_DEBUG_TX_TXBIT_COUNT_SHIFT 17 123 #define TEGRA_CEC_HW_DEBUG_TX_STATE_SHIFT 21 124 #define TEGRA_CEC_HW_DEBUG_TX_FORCELOOUT (1 << 25) 125 #define TEGRA_CEC_HW_DEBUG_TX_TXDATABIT_SAMPLE_TIMER (1 << 26) 126 127 #endif /* TEGRA_CEC_H */ 128
