1 /*
2 * Samsung S5P Multi Format Codec v 5.1
3 *
4 * Copyright (c) 2011 Samsung Electronics Co., Ltd.
5 * Kamil Debski, <k.debski@samsung.com>
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License, or
10 * (at your option) any later version.
11 */
12
13 #include <linux/clk.h>
14 #include <linux/delay.h>
15 #include <linux/interrupt.h>
16 #include <linux/io.h>
17 #include <linux/module.h>
18 #include <linux/platform_device.h>
19 #include <linux/sched.h>
20 #include <linux/slab.h>
21 #include <linux/videodev2.h>
22 #include <media/v4l2-event.h>
23 #include <linux/workqueue.h>
24 #include <linux/of.h>
25 #include <linux/of_device.h>
26 #include <linux/of_reserved_mem.h>
27 #include <media/videobuf2-v4l2.h>
28 #include "s5p_mfc_common.h"
29 #include "s5p_mfc_ctrl.h"
30 #include "s5p_mfc_debug.h"
31 #include "s5p_mfc_dec.h"
32 #include "s5p_mfc_enc.h"
33 #include "s5p_mfc_intr.h"
34 #include "s5p_mfc_iommu.h"
35 #include "s5p_mfc_opr.h"
36 #include "s5p_mfc_cmd.h"
37 #include "s5p_mfc_pm.h"
38
39 #define S5P_MFC_DEC_NAME "s5p-mfc-dec"
40 #define S5P_MFC_ENC_NAME "s5p-mfc-enc"
41
42 int mfc_debug_level;
43 module_param_named(debug, mfc_debug_level, int, S_IRUGO | S_IWUSR);
44 MODULE_PARM_DESC(debug, "Debug level - higher value produces more verbose messages");
45
46 static char *mfc_mem_size;
47 module_param_named(mem, mfc_mem_size, charp, 0644);
48 MODULE_PARM_DESC(mem, "Preallocated memory size for the firmware and context buffers");
49
50 /* Helper functions for interrupt processing */
51
52 /* Remove from hw execution round robin */
clear_work_bit(struct s5p_mfc_ctx * ctx)53 void clear_work_bit(struct s5p_mfc_ctx *ctx)
54 {
55 struct s5p_mfc_dev *dev = ctx->dev;
56
57 spin_lock(&dev->condlock);
58 __clear_bit(ctx->num, &dev->ctx_work_bits);
59 spin_unlock(&dev->condlock);
60 }
61
62 /* Add to hw execution round robin */
set_work_bit(struct s5p_mfc_ctx * ctx)63 void set_work_bit(struct s5p_mfc_ctx *ctx)
64 {
65 struct s5p_mfc_dev *dev = ctx->dev;
66
67 spin_lock(&dev->condlock);
68 __set_bit(ctx->num, &dev->ctx_work_bits);
69 spin_unlock(&dev->condlock);
70 }
71
72 /* Remove from hw execution round robin */
clear_work_bit_irqsave(struct s5p_mfc_ctx * ctx)73 void clear_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
74 {
75 struct s5p_mfc_dev *dev = ctx->dev;
76 unsigned long flags;
77
78 spin_lock_irqsave(&dev->condlock, flags);
79 __clear_bit(ctx->num, &dev->ctx_work_bits);
80 spin_unlock_irqrestore(&dev->condlock, flags);
81 }
82
83 /* Add to hw execution round robin */
set_work_bit_irqsave(struct s5p_mfc_ctx * ctx)84 void set_work_bit_irqsave(struct s5p_mfc_ctx *ctx)
85 {
86 struct s5p_mfc_dev *dev = ctx->dev;
87 unsigned long flags;
88
89 spin_lock_irqsave(&dev->condlock, flags);
90 __set_bit(ctx->num, &dev->ctx_work_bits);
91 spin_unlock_irqrestore(&dev->condlock, flags);
92 }
93
s5p_mfc_get_new_ctx(struct s5p_mfc_dev * dev)94 int s5p_mfc_get_new_ctx(struct s5p_mfc_dev *dev)
95 {
96 unsigned long flags;
97 int ctx;
98
99 spin_lock_irqsave(&dev->condlock, flags);
100 ctx = dev->curr_ctx;
101 do {
102 ctx = (ctx + 1) % MFC_NUM_CONTEXTS;
103 if (ctx == dev->curr_ctx) {
104 if (!test_bit(ctx, &dev->ctx_work_bits))
105 ctx = -EAGAIN;
106 break;
107 }
108 } while (!test_bit(ctx, &dev->ctx_work_bits));
109 spin_unlock_irqrestore(&dev->condlock, flags);
110
111 return ctx;
112 }
113
114 /* Wake up context wait_queue */
wake_up_ctx(struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)115 static void wake_up_ctx(struct s5p_mfc_ctx *ctx, unsigned int reason,
116 unsigned int err)
117 {
118 ctx->int_cond = 1;
119 ctx->int_type = reason;
120 ctx->int_err = err;
121 wake_up(&ctx->queue);
122 }
123
124 /* Wake up device wait_queue */
wake_up_dev(struct s5p_mfc_dev * dev,unsigned int reason,unsigned int err)125 static void wake_up_dev(struct s5p_mfc_dev *dev, unsigned int reason,
126 unsigned int err)
127 {
128 dev->int_cond = 1;
129 dev->int_type = reason;
130 dev->int_err = err;
131 wake_up(&dev->queue);
132 }
133
s5p_mfc_cleanup_queue(struct list_head * lh,struct vb2_queue * vq)134 void s5p_mfc_cleanup_queue(struct list_head *lh, struct vb2_queue *vq)
135 {
136 struct s5p_mfc_buf *b;
137 int i;
138
139 while (!list_empty(lh)) {
140 b = list_entry(lh->next, struct s5p_mfc_buf, list);
141 for (i = 0; i < b->b->vb2_buf.num_planes; i++)
142 vb2_set_plane_payload(&b->b->vb2_buf, i, 0);
143 vb2_buffer_done(&b->b->vb2_buf, VB2_BUF_STATE_ERROR);
144 list_del(&b->list);
145 }
146 }
147
s5p_mfc_watchdog(struct timer_list * t)148 static void s5p_mfc_watchdog(struct timer_list *t)
149 {
150 struct s5p_mfc_dev *dev = from_timer(dev, t, watchdog_timer);
151
152 if (test_bit(0, &dev->hw_lock))
153 atomic_inc(&dev->watchdog_cnt);
154 if (atomic_read(&dev->watchdog_cnt) >= MFC_WATCHDOG_CNT) {
155 /* This means that hw is busy and no interrupts were
156 * generated by hw for the Nth time of running this
157 * watchdog timer. This usually means a serious hw
158 * error. Now it is time to kill all instances and
159 * reset the MFC. */
160 mfc_err("Time out during waiting for HW\n");
161 schedule_work(&dev->watchdog_work);
162 }
163 dev->watchdog_timer.expires = jiffies +
164 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
165 add_timer(&dev->watchdog_timer);
166 }
167
s5p_mfc_watchdog_worker(struct work_struct * work)168 static void s5p_mfc_watchdog_worker(struct work_struct *work)
169 {
170 struct s5p_mfc_dev *dev;
171 struct s5p_mfc_ctx *ctx;
172 unsigned long flags;
173 int mutex_locked;
174 int i, ret;
175
176 dev = container_of(work, struct s5p_mfc_dev, watchdog_work);
177
178 mfc_err("Driver timeout error handling\n");
179 /* Lock the mutex that protects open and release.
180 * This is necessary as they may load and unload firmware. */
181 mutex_locked = mutex_trylock(&dev->mfc_mutex);
182 if (!mutex_locked)
183 mfc_err("Error: some instance may be closing/opening\n");
184 spin_lock_irqsave(&dev->irqlock, flags);
185
186 s5p_mfc_clock_off();
187
188 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
189 ctx = dev->ctx[i];
190 if (!ctx)
191 continue;
192 ctx->state = MFCINST_ERROR;
193 s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
194 s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
195 clear_work_bit(ctx);
196 wake_up_ctx(ctx, S5P_MFC_R2H_CMD_ERR_RET, 0);
197 }
198 clear_bit(0, &dev->hw_lock);
199 spin_unlock_irqrestore(&dev->irqlock, flags);
200
201 /* De-init MFC */
202 s5p_mfc_deinit_hw(dev);
203
204 /* Double check if there is at least one instance running.
205 * If no instance is in memory than no firmware should be present */
206 if (dev->num_inst > 0) {
207 ret = s5p_mfc_load_firmware(dev);
208 if (ret) {
209 mfc_err("Failed to reload FW\n");
210 goto unlock;
211 }
212 s5p_mfc_clock_on();
213 ret = s5p_mfc_init_hw(dev);
214 s5p_mfc_clock_off();
215 if (ret)
216 mfc_err("Failed to reinit FW\n");
217 }
218 unlock:
219 if (mutex_locked)
220 mutex_unlock(&dev->mfc_mutex);
221 }
222
s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx * ctx)223 static void s5p_mfc_handle_frame_all_extracted(struct s5p_mfc_ctx *ctx)
224 {
225 struct s5p_mfc_buf *dst_buf;
226 struct s5p_mfc_dev *dev = ctx->dev;
227
228 ctx->state = MFCINST_FINISHED;
229 ctx->sequence++;
230 while (!list_empty(&ctx->dst_queue)) {
231 dst_buf = list_entry(ctx->dst_queue.next,
232 struct s5p_mfc_buf, list);
233 mfc_debug(2, "Cleaning up buffer: %d\n",
234 dst_buf->b->vb2_buf.index);
235 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0, 0);
236 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1, 0);
237 list_del(&dst_buf->list);
238 dst_buf->flags |= MFC_BUF_FLAG_EOS;
239 ctx->dst_queue_cnt--;
240 dst_buf->b->sequence = (ctx->sequence++);
241
242 if (s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_top, ctx) ==
243 s5p_mfc_hw_call(dev->mfc_ops, get_pic_type_bot, ctx))
244 dst_buf->b->field = V4L2_FIELD_NONE;
245 else
246 dst_buf->b->field = V4L2_FIELD_INTERLACED;
247 dst_buf->b->flags |= V4L2_BUF_FLAG_LAST;
248
249 ctx->dec_dst_flag &= ~(1 << dst_buf->b->vb2_buf.index);
250 vb2_buffer_done(&dst_buf->b->vb2_buf, VB2_BUF_STATE_DONE);
251 }
252 }
253
s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx * ctx)254 static void s5p_mfc_handle_frame_copy_time(struct s5p_mfc_ctx *ctx)
255 {
256 struct s5p_mfc_dev *dev = ctx->dev;
257 struct s5p_mfc_buf *dst_buf, *src_buf;
258 u32 dec_y_addr;
259 unsigned int frame_type;
260
261 /* Make sure we actually have a new frame before continuing. */
262 frame_type = s5p_mfc_hw_call(dev->mfc_ops, get_dec_frame_type, dev);
263 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED)
264 return;
265 dec_y_addr = (u32)s5p_mfc_hw_call(dev->mfc_ops, get_dec_y_adr, dev);
266
267 /* Copy timestamp / timecode from decoded src to dst and set
268 appropriate flags. */
269 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf, list);
270 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
271 u32 addr = (u32)vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0);
272
273 if (addr == dec_y_addr) {
274 dst_buf->b->timecode = src_buf->b->timecode;
275 dst_buf->b->vb2_buf.timestamp =
276 src_buf->b->vb2_buf.timestamp;
277 dst_buf->b->flags &=
278 ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
279 dst_buf->b->flags |=
280 src_buf->b->flags
281 & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
282 switch (frame_type) {
283 case S5P_FIMV_DECODE_FRAME_I_FRAME:
284 dst_buf->b->flags |=
285 V4L2_BUF_FLAG_KEYFRAME;
286 break;
287 case S5P_FIMV_DECODE_FRAME_P_FRAME:
288 dst_buf->b->flags |=
289 V4L2_BUF_FLAG_PFRAME;
290 break;
291 case S5P_FIMV_DECODE_FRAME_B_FRAME:
292 dst_buf->b->flags |=
293 V4L2_BUF_FLAG_BFRAME;
294 break;
295 default:
296 /* Don't know how to handle
297 S5P_FIMV_DECODE_FRAME_OTHER_FRAME. */
298 mfc_debug(2, "Unexpected frame type: %d\n",
299 frame_type);
300 }
301 break;
302 }
303 }
304 }
305
s5p_mfc_handle_frame_new(struct s5p_mfc_ctx * ctx,unsigned int err)306 static void s5p_mfc_handle_frame_new(struct s5p_mfc_ctx *ctx, unsigned int err)
307 {
308 struct s5p_mfc_dev *dev = ctx->dev;
309 struct s5p_mfc_buf *dst_buf;
310 u32 dspl_y_addr;
311 unsigned int frame_type;
312
313 dspl_y_addr = (u32)s5p_mfc_hw_call(dev->mfc_ops, get_dspl_y_adr, dev);
314 if (IS_MFCV6_PLUS(dev))
315 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
316 get_disp_frame_type, ctx);
317 else
318 frame_type = s5p_mfc_hw_call(dev->mfc_ops,
319 get_dec_frame_type, dev);
320
321 /* If frame is same as previous then skip and do not dequeue */
322 if (frame_type == S5P_FIMV_DECODE_FRAME_SKIPPED) {
323 if (!ctx->after_packed_pb)
324 ctx->sequence++;
325 ctx->after_packed_pb = 0;
326 return;
327 }
328 ctx->sequence++;
329 /* The MFC returns address of the buffer, now we have to
330 * check which videobuf does it correspond to */
331 list_for_each_entry(dst_buf, &ctx->dst_queue, list) {
332 u32 addr = (u32)vb2_dma_contig_plane_dma_addr(&dst_buf->b->vb2_buf, 0);
333
334 /* Check if this is the buffer we're looking for */
335 if (addr == dspl_y_addr) {
336 list_del(&dst_buf->list);
337 ctx->dst_queue_cnt--;
338 dst_buf->b->sequence = ctx->sequence;
339 if (s5p_mfc_hw_call(dev->mfc_ops,
340 get_pic_type_top, ctx) ==
341 s5p_mfc_hw_call(dev->mfc_ops,
342 get_pic_type_bot, ctx))
343 dst_buf->b->field = V4L2_FIELD_NONE;
344 else
345 dst_buf->b->field =
346 V4L2_FIELD_INTERLACED;
347 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 0,
348 ctx->luma_size);
349 vb2_set_plane_payload(&dst_buf->b->vb2_buf, 1,
350 ctx->chroma_size);
351 clear_bit(dst_buf->b->vb2_buf.index,
352 &ctx->dec_dst_flag);
353
354 vb2_buffer_done(&dst_buf->b->vb2_buf, err ?
355 VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
356
357 break;
358 }
359 }
360 }
361
362 /* Handle frame decoding interrupt */
s5p_mfc_handle_frame(struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)363 static void s5p_mfc_handle_frame(struct s5p_mfc_ctx *ctx,
364 unsigned int reason, unsigned int err)
365 {
366 struct s5p_mfc_dev *dev = ctx->dev;
367 unsigned int dst_frame_status;
368 unsigned int dec_frame_status;
369 struct s5p_mfc_buf *src_buf;
370 unsigned int res_change;
371
372 dst_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
373 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
374 dec_frame_status = s5p_mfc_hw_call(dev->mfc_ops, get_dec_status, dev)
375 & S5P_FIMV_DEC_STATUS_DECODING_STATUS_MASK;
376 res_change = (s5p_mfc_hw_call(dev->mfc_ops, get_dspl_status, dev)
377 & S5P_FIMV_DEC_STATUS_RESOLUTION_MASK)
378 >> S5P_FIMV_DEC_STATUS_RESOLUTION_SHIFT;
379 mfc_debug(2, "Frame Status: %x\n", dst_frame_status);
380 if (ctx->state == MFCINST_RES_CHANGE_INIT)
381 ctx->state = MFCINST_RES_CHANGE_FLUSH;
382 if (res_change == S5P_FIMV_RES_INCREASE ||
383 res_change == S5P_FIMV_RES_DECREASE) {
384 ctx->state = MFCINST_RES_CHANGE_INIT;
385 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
386 wake_up_ctx(ctx, reason, err);
387 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
388 s5p_mfc_clock_off();
389 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
390 return;
391 }
392 if (ctx->dpb_flush_flag)
393 ctx->dpb_flush_flag = 0;
394
395 /* All frames remaining in the buffer have been extracted */
396 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_EMPTY) {
397 if (ctx->state == MFCINST_RES_CHANGE_FLUSH) {
398 static const struct v4l2_event ev_src_ch = {
399 .type = V4L2_EVENT_SOURCE_CHANGE,
400 .u.src_change.changes =
401 V4L2_EVENT_SRC_CH_RESOLUTION,
402 };
403
404 s5p_mfc_handle_frame_all_extracted(ctx);
405 ctx->state = MFCINST_RES_CHANGE_END;
406 v4l2_event_queue_fh(&ctx->fh, &ev_src_ch);
407
408 goto leave_handle_frame;
409 } else {
410 s5p_mfc_handle_frame_all_extracted(ctx);
411 }
412 }
413
414 if (dec_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY)
415 s5p_mfc_handle_frame_copy_time(ctx);
416
417 /* A frame has been decoded and is in the buffer */
418 if (dst_frame_status == S5P_FIMV_DEC_STATUS_DISPLAY_ONLY ||
419 dst_frame_status == S5P_FIMV_DEC_STATUS_DECODING_DISPLAY) {
420 s5p_mfc_handle_frame_new(ctx, err);
421 } else {
422 mfc_debug(2, "No frame decode\n");
423 }
424 /* Mark source buffer as complete */
425 if (dst_frame_status != S5P_FIMV_DEC_STATUS_DISPLAY_ONLY
426 && !list_empty(&ctx->src_queue)) {
427 src_buf = list_entry(ctx->src_queue.next, struct s5p_mfc_buf,
428 list);
429 ctx->consumed_stream += s5p_mfc_hw_call(dev->mfc_ops,
430 get_consumed_stream, dev);
431 if (ctx->codec_mode != S5P_MFC_CODEC_H264_DEC &&
432 ctx->codec_mode != S5P_MFC_CODEC_VP8_DEC &&
433 ctx->consumed_stream + STUFF_BYTE <
434 src_buf->b->vb2_buf.planes[0].bytesused) {
435 /* Run MFC again on the same buffer */
436 mfc_debug(2, "Running again the same buffer\n");
437 ctx->after_packed_pb = 1;
438 } else {
439 mfc_debug(2, "MFC needs next buffer\n");
440 ctx->consumed_stream = 0;
441 if (src_buf->flags & MFC_BUF_FLAG_EOS)
442 ctx->state = MFCINST_FINISHING;
443 list_del(&src_buf->list);
444 ctx->src_queue_cnt--;
445 if (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) > 0)
446 vb2_buffer_done(&src_buf->b->vb2_buf,
447 VB2_BUF_STATE_ERROR);
448 else
449 vb2_buffer_done(&src_buf->b->vb2_buf,
450 VB2_BUF_STATE_DONE);
451 }
452 }
453 leave_handle_frame:
454 if ((ctx->src_queue_cnt == 0 && ctx->state != MFCINST_FINISHING)
455 || ctx->dst_queue_cnt < ctx->pb_count)
456 clear_work_bit(ctx);
457 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
458 wake_up_ctx(ctx, reason, err);
459 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
460 s5p_mfc_clock_off();
461 /* if suspending, wake up device and do not try_run again*/
462 if (test_bit(0, &dev->enter_suspend))
463 wake_up_dev(dev, reason, err);
464 else
465 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
466 }
467
468 /* Error handling for interrupt */
s5p_mfc_handle_error(struct s5p_mfc_dev * dev,struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)469 static void s5p_mfc_handle_error(struct s5p_mfc_dev *dev,
470 struct s5p_mfc_ctx *ctx, unsigned int reason, unsigned int err)
471 {
472 mfc_err("Interrupt Error: %08x\n", err);
473
474 if (ctx) {
475 /* Error recovery is dependent on the state of context */
476 switch (ctx->state) {
477 case MFCINST_RES_CHANGE_INIT:
478 case MFCINST_RES_CHANGE_FLUSH:
479 case MFCINST_RES_CHANGE_END:
480 case MFCINST_FINISHING:
481 case MFCINST_FINISHED:
482 case MFCINST_RUNNING:
483 /* It is highly probable that an error occurred
484 * while decoding a frame */
485 clear_work_bit(ctx);
486 ctx->state = MFCINST_ERROR;
487 /* Mark all dst buffers as having an error */
488 s5p_mfc_cleanup_queue(&ctx->dst_queue, &ctx->vq_dst);
489 /* Mark all src buffers as having an error */
490 s5p_mfc_cleanup_queue(&ctx->src_queue, &ctx->vq_src);
491 wake_up_ctx(ctx, reason, err);
492 break;
493 default:
494 clear_work_bit(ctx);
495 ctx->state = MFCINST_ERROR;
496 wake_up_ctx(ctx, reason, err);
497 break;
498 }
499 }
500 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
501 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
502 s5p_mfc_clock_off();
503 wake_up_dev(dev, reason, err);
504 }
505
506 /* Header parsing interrupt handling */
s5p_mfc_handle_seq_done(struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)507 static void s5p_mfc_handle_seq_done(struct s5p_mfc_ctx *ctx,
508 unsigned int reason, unsigned int err)
509 {
510 struct s5p_mfc_dev *dev;
511
512 if (!ctx)
513 return;
514 dev = ctx->dev;
515 if (ctx->c_ops->post_seq_start) {
516 if (ctx->c_ops->post_seq_start(ctx))
517 mfc_err("post_seq_start() failed\n");
518 } else {
519 ctx->img_width = s5p_mfc_hw_call(dev->mfc_ops, get_img_width,
520 dev);
521 ctx->img_height = s5p_mfc_hw_call(dev->mfc_ops, get_img_height,
522 dev);
523
524 s5p_mfc_hw_call(dev->mfc_ops, dec_calc_dpb_size, ctx);
525
526 ctx->pb_count = s5p_mfc_hw_call(dev->mfc_ops, get_dpb_count,
527 dev);
528 ctx->mv_count = s5p_mfc_hw_call(dev->mfc_ops, get_mv_count,
529 dev);
530 ctx->scratch_buf_size = s5p_mfc_hw_call(dev->mfc_ops,
531 get_min_scratch_buf_size, dev);
532 if (ctx->img_width == 0 || ctx->img_height == 0)
533 ctx->state = MFCINST_ERROR;
534 else
535 ctx->state = MFCINST_HEAD_PARSED;
536
537 if ((ctx->codec_mode == S5P_MFC_CODEC_H264_DEC ||
538 ctx->codec_mode == S5P_MFC_CODEC_H264_MVC_DEC) &&
539 !list_empty(&ctx->src_queue)) {
540 struct s5p_mfc_buf *src_buf;
541 src_buf = list_entry(ctx->src_queue.next,
542 struct s5p_mfc_buf, list);
543 if (s5p_mfc_hw_call(dev->mfc_ops, get_consumed_stream,
544 dev) <
545 src_buf->b->vb2_buf.planes[0].bytesused)
546 ctx->head_processed = 0;
547 else
548 ctx->head_processed = 1;
549 } else {
550 ctx->head_processed = 1;
551 }
552 }
553 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
554 clear_work_bit(ctx);
555 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
556 s5p_mfc_clock_off();
557 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
558 wake_up_ctx(ctx, reason, err);
559 }
560
561 /* Header parsing interrupt handling */
s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx * ctx,unsigned int reason,unsigned int err)562 static void s5p_mfc_handle_init_buffers(struct s5p_mfc_ctx *ctx,
563 unsigned int reason, unsigned int err)
564 {
565 struct s5p_mfc_buf *src_buf;
566 struct s5p_mfc_dev *dev;
567
568 if (!ctx)
569 return;
570 dev = ctx->dev;
571 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
572 ctx->int_type = reason;
573 ctx->int_err = err;
574 ctx->int_cond = 1;
575 clear_work_bit(ctx);
576 if (err == 0) {
577 ctx->state = MFCINST_RUNNING;
578 if (!ctx->dpb_flush_flag && ctx->head_processed) {
579 if (!list_empty(&ctx->src_queue)) {
580 src_buf = list_entry(ctx->src_queue.next,
581 struct s5p_mfc_buf, list);
582 list_del(&src_buf->list);
583 ctx->src_queue_cnt--;
584 vb2_buffer_done(&src_buf->b->vb2_buf,
585 VB2_BUF_STATE_DONE);
586 }
587 } else {
588 ctx->dpb_flush_flag = 0;
589 }
590 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
591
592 s5p_mfc_clock_off();
593
594 wake_up(&ctx->queue);
595 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
596 } else {
597 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
598
599 s5p_mfc_clock_off();
600
601 wake_up(&ctx->queue);
602 }
603 }
604
s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx * ctx)605 static void s5p_mfc_handle_stream_complete(struct s5p_mfc_ctx *ctx)
606 {
607 struct s5p_mfc_dev *dev = ctx->dev;
608 struct s5p_mfc_buf *mb_entry;
609
610 mfc_debug(2, "Stream completed\n");
611
612 ctx->state = MFCINST_FINISHED;
613
614 if (!list_empty(&ctx->dst_queue)) {
615 mb_entry = list_entry(ctx->dst_queue.next, struct s5p_mfc_buf,
616 list);
617 list_del(&mb_entry->list);
618 ctx->dst_queue_cnt--;
619 vb2_set_plane_payload(&mb_entry->b->vb2_buf, 0, 0);
620 vb2_buffer_done(&mb_entry->b->vb2_buf, VB2_BUF_STATE_DONE);
621 }
622
623 clear_work_bit(ctx);
624
625 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
626
627 s5p_mfc_clock_off();
628 wake_up(&ctx->queue);
629 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
630 }
631
632 /* Interrupt processing */
s5p_mfc_irq(int irq,void * priv)633 static irqreturn_t s5p_mfc_irq(int irq, void *priv)
634 {
635 struct s5p_mfc_dev *dev = priv;
636 struct s5p_mfc_ctx *ctx;
637 unsigned int reason;
638 unsigned int err;
639
640 mfc_debug_enter();
641 /* Reset the timeout watchdog */
642 atomic_set(&dev->watchdog_cnt, 0);
643 spin_lock(&dev->irqlock);
644 ctx = dev->ctx[dev->curr_ctx];
645 /* Get the reason of interrupt and the error code */
646 reason = s5p_mfc_hw_call(dev->mfc_ops, get_int_reason, dev);
647 err = s5p_mfc_hw_call(dev->mfc_ops, get_int_err, dev);
648 mfc_debug(1, "Int reason: %d (err: %08x)\n", reason, err);
649 switch (reason) {
650 case S5P_MFC_R2H_CMD_ERR_RET:
651 /* An error has occurred */
652 if (ctx->state == MFCINST_RUNNING &&
653 (s5p_mfc_hw_call(dev->mfc_ops, err_dec, err) >=
654 dev->warn_start ||
655 err == S5P_FIMV_ERR_NO_VALID_SEQ_HDR ||
656 err == S5P_FIMV_ERR_INCOMPLETE_FRAME ||
657 err == S5P_FIMV_ERR_TIMEOUT))
658 s5p_mfc_handle_frame(ctx, reason, err);
659 else
660 s5p_mfc_handle_error(dev, ctx, reason, err);
661 clear_bit(0, &dev->enter_suspend);
662 break;
663
664 case S5P_MFC_R2H_CMD_SLICE_DONE_RET:
665 case S5P_MFC_R2H_CMD_FIELD_DONE_RET:
666 case S5P_MFC_R2H_CMD_FRAME_DONE_RET:
667 if (ctx->c_ops->post_frame_start) {
668 if (ctx->c_ops->post_frame_start(ctx))
669 mfc_err("post_frame_start() failed\n");
670
671 if (ctx->state == MFCINST_FINISHING &&
672 list_empty(&ctx->ref_queue)) {
673 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
674 s5p_mfc_handle_stream_complete(ctx);
675 break;
676 }
677 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
678 WARN_ON(test_and_clear_bit(0, &dev->hw_lock) == 0);
679 s5p_mfc_clock_off();
680 wake_up_ctx(ctx, reason, err);
681 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
682 } else {
683 s5p_mfc_handle_frame(ctx, reason, err);
684 }
685 break;
686
687 case S5P_MFC_R2H_CMD_SEQ_DONE_RET:
688 s5p_mfc_handle_seq_done(ctx, reason, err);
689 break;
690
691 case S5P_MFC_R2H_CMD_OPEN_INSTANCE_RET:
692 ctx->inst_no = s5p_mfc_hw_call(dev->mfc_ops, get_inst_no, dev);
693 ctx->state = MFCINST_GOT_INST;
694 goto irq_cleanup_hw;
695
696 case S5P_MFC_R2H_CMD_CLOSE_INSTANCE_RET:
697 ctx->inst_no = MFC_NO_INSTANCE_SET;
698 ctx->state = MFCINST_FREE;
699 goto irq_cleanup_hw;
700
701 case S5P_MFC_R2H_CMD_SYS_INIT_RET:
702 case S5P_MFC_R2H_CMD_FW_STATUS_RET:
703 case S5P_MFC_R2H_CMD_SLEEP_RET:
704 case S5P_MFC_R2H_CMD_WAKEUP_RET:
705 if (ctx)
706 clear_work_bit(ctx);
707 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
708 clear_bit(0, &dev->hw_lock);
709 clear_bit(0, &dev->enter_suspend);
710 wake_up_dev(dev, reason, err);
711 break;
712
713 case S5P_MFC_R2H_CMD_INIT_BUFFERS_RET:
714 s5p_mfc_handle_init_buffers(ctx, reason, err);
715 break;
716
717 case S5P_MFC_R2H_CMD_COMPLETE_SEQ_RET:
718 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
719 ctx->int_type = reason;
720 ctx->int_err = err;
721 s5p_mfc_handle_stream_complete(ctx);
722 break;
723
724 case S5P_MFC_R2H_CMD_DPB_FLUSH_RET:
725 ctx->state = MFCINST_RUNNING;
726 goto irq_cleanup_hw;
727
728 default:
729 mfc_debug(2, "Unknown int reason\n");
730 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
731 }
732 spin_unlock(&dev->irqlock);
733 mfc_debug_leave();
734 return IRQ_HANDLED;
735 irq_cleanup_hw:
736 s5p_mfc_hw_call(dev->mfc_ops, clear_int_flags, dev);
737 ctx->int_type = reason;
738 ctx->int_err = err;
739 ctx->int_cond = 1;
740 if (test_and_clear_bit(0, &dev->hw_lock) == 0)
741 mfc_err("Failed to unlock hw\n");
742
743 s5p_mfc_clock_off();
744 clear_work_bit(ctx);
745 wake_up(&ctx->queue);
746
747 s5p_mfc_hw_call(dev->mfc_ops, try_run, dev);
748 spin_unlock(&dev->irqlock);
749 mfc_debug(2, "Exit via irq_cleanup_hw\n");
750 return IRQ_HANDLED;
751 }
752
753 /* Open an MFC node */
s5p_mfc_open(struct file * file)754 static int s5p_mfc_open(struct file *file)
755 {
756 struct video_device *vdev = video_devdata(file);
757 struct s5p_mfc_dev *dev = video_drvdata(file);
758 struct s5p_mfc_ctx *ctx = NULL;
759 struct vb2_queue *q;
760 int ret = 0;
761
762 mfc_debug_enter();
763 if (mutex_lock_interruptible(&dev->mfc_mutex))
764 return -ERESTARTSYS;
765 dev->num_inst++; /* It is guarded by mfc_mutex in vfd */
766 /* Allocate memory for context */
767 ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
768 if (!ctx) {
769 ret = -ENOMEM;
770 goto err_alloc;
771 }
772 init_waitqueue_head(&ctx->queue);
773 v4l2_fh_init(&ctx->fh, vdev);
774 file->private_data = &ctx->fh;
775 v4l2_fh_add(&ctx->fh);
776 ctx->dev = dev;
777 INIT_LIST_HEAD(&ctx->src_queue);
778 INIT_LIST_HEAD(&ctx->dst_queue);
779 ctx->src_queue_cnt = 0;
780 ctx->dst_queue_cnt = 0;
781 /* Get context number */
782 ctx->num = 0;
783 while (dev->ctx[ctx->num]) {
784 ctx->num++;
785 if (ctx->num >= MFC_NUM_CONTEXTS) {
786 mfc_debug(2, "Too many open contexts\n");
787 ret = -EBUSY;
788 goto err_no_ctx;
789 }
790 }
791 /* Mark context as idle */
792 clear_work_bit_irqsave(ctx);
793 dev->ctx[ctx->num] = ctx;
794 if (vdev == dev->vfd_dec) {
795 ctx->type = MFCINST_DECODER;
796 ctx->c_ops = get_dec_codec_ops();
797 s5p_mfc_dec_init(ctx);
798 /* Setup ctrl handler */
799 ret = s5p_mfc_dec_ctrls_setup(ctx);
800 if (ret) {
801 mfc_err("Failed to setup mfc controls\n");
802 goto err_ctrls_setup;
803 }
804 } else if (vdev == dev->vfd_enc) {
805 ctx->type = MFCINST_ENCODER;
806 ctx->c_ops = get_enc_codec_ops();
807 /* only for encoder */
808 INIT_LIST_HEAD(&ctx->ref_queue);
809 ctx->ref_queue_cnt = 0;
810 s5p_mfc_enc_init(ctx);
811 /* Setup ctrl handler */
812 ret = s5p_mfc_enc_ctrls_setup(ctx);
813 if (ret) {
814 mfc_err("Failed to setup mfc controls\n");
815 goto err_ctrls_setup;
816 }
817 } else {
818 ret = -ENOENT;
819 goto err_bad_node;
820 }
821 ctx->fh.ctrl_handler = &ctx->ctrl_handler;
822 ctx->inst_no = MFC_NO_INSTANCE_SET;
823 /* Load firmware if this is the first instance */
824 if (dev->num_inst == 1) {
825 dev->watchdog_timer.expires = jiffies +
826 msecs_to_jiffies(MFC_WATCHDOG_INTERVAL);
827 add_timer(&dev->watchdog_timer);
828 ret = s5p_mfc_power_on();
829 if (ret < 0) {
830 mfc_err("power on failed\n");
831 goto err_pwr_enable;
832 }
833 s5p_mfc_clock_on();
834 ret = s5p_mfc_load_firmware(dev);
835 if (ret) {
836 s5p_mfc_clock_off();
837 goto err_load_fw;
838 }
839 /* Init the FW */
840 ret = s5p_mfc_init_hw(dev);
841 s5p_mfc_clock_off();
842 if (ret)
843 goto err_init_hw;
844 }
845 /* Init videobuf2 queue for CAPTURE */
846 q = &ctx->vq_dst;
847 q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
848 q->drv_priv = &ctx->fh;
849 q->lock = &dev->mfc_mutex;
850 if (vdev == dev->vfd_dec) {
851 q->io_modes = VB2_MMAP;
852 q->ops = get_dec_queue_ops();
853 } else if (vdev == dev->vfd_enc) {
854 q->io_modes = VB2_MMAP | VB2_USERPTR;
855 q->ops = get_enc_queue_ops();
856 } else {
857 ret = -ENOENT;
858 goto err_queue_init;
859 }
860 /*
861 * We'll do mostly sequential access, so sacrifice TLB efficiency for
862 * faster allocation.
863 */
864 q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
865 q->mem_ops = &vb2_dma_contig_memops;
866 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
867 ret = vb2_queue_init(q);
868 if (ret) {
869 mfc_err("Failed to initialize videobuf2 queue(capture)\n");
870 goto err_queue_init;
871 }
872 /* Init videobuf2 queue for OUTPUT */
873 q = &ctx->vq_src;
874 q->type = V4L2_BUF_TYPE_VIDEO_OUTPUT_MPLANE;
875 q->drv_priv = &ctx->fh;
876 q->lock = &dev->mfc_mutex;
877 if (vdev == dev->vfd_dec) {
878 q->io_modes = VB2_MMAP;
879 q->ops = get_dec_queue_ops();
880 } else if (vdev == dev->vfd_enc) {
881 q->io_modes = VB2_MMAP | VB2_USERPTR;
882 q->ops = get_enc_queue_ops();
883 } else {
884 ret = -ENOENT;
885 goto err_queue_init;
886 }
887 /* One way to indicate end-of-stream for MFC is to set the
888 * bytesused == 0. However by default videobuf2 handles bytesused
889 * equal to 0 as a special case and changes its value to the size
890 * of the buffer. Set the allow_zero_bytesused flag so that videobuf2
891 * will keep the value of bytesused intact.
892 */
893 q->allow_zero_bytesused = 1;
894
895 /*
896 * We'll do mostly sequential access, so sacrifice TLB efficiency for
897 * faster allocation.
898 */
899 q->dma_attrs = DMA_ATTR_ALLOC_SINGLE_PAGES;
900 q->mem_ops = &vb2_dma_contig_memops;
901 q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
902 ret = vb2_queue_init(q);
903 if (ret) {
904 mfc_err("Failed to initialize videobuf2 queue(output)\n");
905 goto err_queue_init;
906 }
907 mutex_unlock(&dev->mfc_mutex);
908 mfc_debug_leave();
909 return ret;
910 /* Deinit when failure occurred */
911 err_queue_init:
912 if (dev->num_inst == 1)
913 s5p_mfc_deinit_hw(dev);
914 err_init_hw:
915 err_load_fw:
916 err_pwr_enable:
917 if (dev->num_inst == 1) {
918 if (s5p_mfc_power_off() < 0)
919 mfc_err("power off failed\n");
920 del_timer_sync(&dev->watchdog_timer);
921 }
922 err_ctrls_setup:
923 s5p_mfc_dec_ctrls_delete(ctx);
924 err_bad_node:
925 dev->ctx[ctx->num] = NULL;
926 err_no_ctx:
927 v4l2_fh_del(&ctx->fh);
928 v4l2_fh_exit(&ctx->fh);
929 kfree(ctx);
930 err_alloc:
931 dev->num_inst--;
932 mutex_unlock(&dev->mfc_mutex);
933 mfc_debug_leave();
934 return ret;
935 }
936
937 /* Release MFC context */
s5p_mfc_release(struct file * file)938 static int s5p_mfc_release(struct file *file)
939 {
940 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
941 struct s5p_mfc_dev *dev = ctx->dev;
942
943 /* if dev is null, do cleanup that doesn't need dev */
944 mfc_debug_enter();
945 if (dev)
946 mutex_lock(&dev->mfc_mutex);
947 vb2_queue_release(&ctx->vq_src);
948 vb2_queue_release(&ctx->vq_dst);
949 if (dev) {
950 s5p_mfc_clock_on();
951
952 /* Mark context as idle */
953 clear_work_bit_irqsave(ctx);
954 /*
955 * If instance was initialised and not yet freed,
956 * return instance and free resources
957 */
958 if (ctx->state != MFCINST_FREE && ctx->state != MFCINST_INIT) {
959 mfc_debug(2, "Has to free instance\n");
960 s5p_mfc_close_mfc_inst(dev, ctx);
961 }
962 /* hardware locking scheme */
963 if (dev->curr_ctx == ctx->num)
964 clear_bit(0, &dev->hw_lock);
965 dev->num_inst--;
966 if (dev->num_inst == 0) {
967 mfc_debug(2, "Last instance\n");
968 s5p_mfc_deinit_hw(dev);
969 del_timer_sync(&dev->watchdog_timer);
970 s5p_mfc_clock_off();
971 if (s5p_mfc_power_off() < 0)
972 mfc_err("Power off failed\n");
973 } else {
974 mfc_debug(2, "Shutting down clock\n");
975 s5p_mfc_clock_off();
976 }
977 }
978 if (dev)
979 dev->ctx[ctx->num] = NULL;
980 s5p_mfc_dec_ctrls_delete(ctx);
981 v4l2_fh_del(&ctx->fh);
982 /* vdev is gone if dev is null */
983 if (dev)
984 v4l2_fh_exit(&ctx->fh);
985 kfree(ctx);
986 mfc_debug_leave();
987 if (dev)
988 mutex_unlock(&dev->mfc_mutex);
989
990 return 0;
991 }
992
993 /* Poll */
s5p_mfc_poll(struct file * file,struct poll_table_struct * wait)994 static __poll_t s5p_mfc_poll(struct file *file,
995 struct poll_table_struct *wait)
996 {
997 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
998 struct s5p_mfc_dev *dev = ctx->dev;
999 struct vb2_queue *src_q, *dst_q;
1000 struct vb2_buffer *src_vb = NULL, *dst_vb = NULL;
1001 __poll_t rc = 0;
1002 unsigned long flags;
1003
1004 mutex_lock(&dev->mfc_mutex);
1005 src_q = &ctx->vq_src;
1006 dst_q = &ctx->vq_dst;
1007 /*
1008 * There has to be at least one buffer queued on each queued_list, which
1009 * means either in driver already or waiting for driver to claim it
1010 * and start processing.
1011 */
1012 if ((!src_q->streaming || list_empty(&src_q->queued_list))
1013 && (!dst_q->streaming || list_empty(&dst_q->queued_list))) {
1014 rc = EPOLLERR;
1015 goto end;
1016 }
1017 mutex_unlock(&dev->mfc_mutex);
1018 poll_wait(file, &ctx->fh.wait, wait);
1019 poll_wait(file, &src_q->done_wq, wait);
1020 poll_wait(file, &dst_q->done_wq, wait);
1021 mutex_lock(&dev->mfc_mutex);
1022 if (v4l2_event_pending(&ctx->fh))
1023 rc |= EPOLLPRI;
1024 spin_lock_irqsave(&src_q->done_lock, flags);
1025 if (!list_empty(&src_q->done_list))
1026 src_vb = list_first_entry(&src_q->done_list, struct vb2_buffer,
1027 done_entry);
1028 if (src_vb && (src_vb->state == VB2_BUF_STATE_DONE
1029 || src_vb->state == VB2_BUF_STATE_ERROR))
1030 rc |= EPOLLOUT | EPOLLWRNORM;
1031 spin_unlock_irqrestore(&src_q->done_lock, flags);
1032 spin_lock_irqsave(&dst_q->done_lock, flags);
1033 if (!list_empty(&dst_q->done_list))
1034 dst_vb = list_first_entry(&dst_q->done_list, struct vb2_buffer,
1035 done_entry);
1036 if (dst_vb && (dst_vb->state == VB2_BUF_STATE_DONE
1037 || dst_vb->state == VB2_BUF_STATE_ERROR))
1038 rc |= EPOLLIN | EPOLLRDNORM;
1039 spin_unlock_irqrestore(&dst_q->done_lock, flags);
1040 end:
1041 mutex_unlock(&dev->mfc_mutex);
1042 return rc;
1043 }
1044
1045 /* Mmap */
s5p_mfc_mmap(struct file * file,struct vm_area_struct * vma)1046 static int s5p_mfc_mmap(struct file *file, struct vm_area_struct *vma)
1047 {
1048 struct s5p_mfc_ctx *ctx = fh_to_ctx(file->private_data);
1049 unsigned long offset = vma->vm_pgoff << PAGE_SHIFT;
1050 int ret;
1051
1052 if (offset < DST_QUEUE_OFF_BASE) {
1053 mfc_debug(2, "mmaping source\n");
1054 ret = vb2_mmap(&ctx->vq_src, vma);
1055 } else { /* capture */
1056 mfc_debug(2, "mmaping destination\n");
1057 vma->vm_pgoff -= (DST_QUEUE_OFF_BASE >> PAGE_SHIFT);
1058 ret = vb2_mmap(&ctx->vq_dst, vma);
1059 }
1060 return ret;
1061 }
1062
1063 /* v4l2 ops */
1064 static const struct v4l2_file_operations s5p_mfc_fops = {
1065 .owner = THIS_MODULE,
1066 .open = s5p_mfc_open,
1067 .release = s5p_mfc_release,
1068 .poll = s5p_mfc_poll,
1069 .unlocked_ioctl = video_ioctl2,
1070 .mmap = s5p_mfc_mmap,
1071 };
1072
1073 /* DMA memory related helper functions */
s5p_mfc_memdev_release(struct device * dev)1074 static void s5p_mfc_memdev_release(struct device *dev)
1075 {
1076 of_reserved_mem_device_release(dev);
1077 }
1078
s5p_mfc_alloc_memdev(struct device * dev,const char * name,unsigned int idx)1079 static struct device *s5p_mfc_alloc_memdev(struct device *dev,
1080 const char *name, unsigned int idx)
1081 {
1082 struct device *child;
1083 int ret;
1084
1085 child = devm_kzalloc(dev, sizeof(*child), GFP_KERNEL);
1086 if (!child)
1087 return NULL;
1088
1089 device_initialize(child);
1090 dev_set_name(child, "%s:%s", dev_name(dev), name);
1091 child->parent = dev;
1092 child->bus = dev->bus;
1093 child->coherent_dma_mask = dev->coherent_dma_mask;
1094 child->dma_mask = dev->dma_mask;
1095 child->release = s5p_mfc_memdev_release;
1096
1097 if (device_add(child) == 0) {
1098 ret = of_reserved_mem_device_init_by_idx(child, dev->of_node,
1099 idx);
1100 if (ret == 0)
1101 return child;
1102 device_del(child);
1103 }
1104
1105 put_device(child);
1106 return NULL;
1107 }
1108
s5p_mfc_configure_2port_memory(struct s5p_mfc_dev * mfc_dev)1109 static int s5p_mfc_configure_2port_memory(struct s5p_mfc_dev *mfc_dev)
1110 {
1111 struct device *dev = &mfc_dev->plat_dev->dev;
1112 void *bank2_virt;
1113 dma_addr_t bank2_dma_addr;
1114 unsigned long align_size = 1 << MFC_BASE_ALIGN_ORDER;
1115 int ret;
1116
1117 /*
1118 * Create and initialize virtual devices for accessing
1119 * reserved memory regions.
1120 */
1121 mfc_dev->mem_dev[BANK_L_CTX] = s5p_mfc_alloc_memdev(dev, "left",
1122 BANK_L_CTX);
1123 if (!mfc_dev->mem_dev[BANK_L_CTX])
1124 return -ENODEV;
1125 mfc_dev->mem_dev[BANK_R_CTX] = s5p_mfc_alloc_memdev(dev, "right",
1126 BANK_R_CTX);
1127 if (!mfc_dev->mem_dev[BANK_R_CTX]) {
1128 device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1129 return -ENODEV;
1130 }
1131
1132 /* Allocate memory for firmware and initialize both banks addresses */
1133 ret = s5p_mfc_alloc_firmware(mfc_dev);
1134 if (ret) {
1135 device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);
1136 device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1137 return ret;
1138 }
1139
1140 mfc_dev->dma_base[BANK_L_CTX] = mfc_dev->fw_buf.dma;
1141
1142 bank2_virt = dma_alloc_coherent(mfc_dev->mem_dev[BANK_R_CTX],
1143 align_size, &bank2_dma_addr, GFP_KERNEL);
1144 if (!bank2_virt) {
1145 mfc_err("Allocating bank2 base failed\n");
1146 s5p_mfc_release_firmware(mfc_dev);
1147 device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);
1148 device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1149 return -ENOMEM;
1150 }
1151
1152 /* Valid buffers passed to MFC encoder with LAST_FRAME command
1153 * should not have address of bank2 - MFC will treat it as a null frame.
1154 * To avoid such situation we set bank2 address below the pool address.
1155 */
1156 mfc_dev->dma_base[BANK_R_CTX] = bank2_dma_addr - align_size;
1157
1158 dma_free_coherent(mfc_dev->mem_dev[BANK_R_CTX], align_size, bank2_virt,
1159 bank2_dma_addr);
1160
1161 vb2_dma_contig_set_max_seg_size(mfc_dev->mem_dev[BANK_L_CTX],
1162 DMA_BIT_MASK(32));
1163 vb2_dma_contig_set_max_seg_size(mfc_dev->mem_dev[BANK_R_CTX],
1164 DMA_BIT_MASK(32));
1165
1166 return 0;
1167 }
1168
s5p_mfc_unconfigure_2port_memory(struct s5p_mfc_dev * mfc_dev)1169 static void s5p_mfc_unconfigure_2port_memory(struct s5p_mfc_dev *mfc_dev)
1170 {
1171 device_unregister(mfc_dev->mem_dev[BANK_L_CTX]);
1172 device_unregister(mfc_dev->mem_dev[BANK_R_CTX]);
1173 vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK_L_CTX]);
1174 vb2_dma_contig_clear_max_seg_size(mfc_dev->mem_dev[BANK_R_CTX]);
1175 }
1176
s5p_mfc_configure_common_memory(struct s5p_mfc_dev * mfc_dev)1177 static int s5p_mfc_configure_common_memory(struct s5p_mfc_dev *mfc_dev)
1178 {
1179 struct device *dev = &mfc_dev->plat_dev->dev;
1180 unsigned long mem_size = SZ_4M;
1181 unsigned int bitmap_size;
1182
1183 if (IS_ENABLED(CONFIG_DMA_CMA) || exynos_is_iommu_available(dev))
1184 mem_size = SZ_8M;
1185
1186 if (mfc_mem_size)
1187 mem_size = memparse(mfc_mem_size, NULL);
1188
1189 bitmap_size = BITS_TO_LONGS(mem_size >> PAGE_SHIFT) * sizeof(long);
1190
1191 mfc_dev->mem_bitmap = kzalloc(bitmap_size, GFP_KERNEL);
1192 if (!mfc_dev->mem_bitmap)
1193 return -ENOMEM;
1194
1195 mfc_dev->mem_virt = dma_alloc_coherent(dev, mem_size,
1196 &mfc_dev->mem_base, GFP_KERNEL);
1197 if (!mfc_dev->mem_virt) {
1198 kfree(mfc_dev->mem_bitmap);
1199 dev_err(dev, "failed to preallocate %ld MiB for the firmware and context buffers\n",
1200 (mem_size / SZ_1M));
1201 return -ENOMEM;
1202 }
1203 mfc_dev->mem_size = mem_size;
1204 mfc_dev->dma_base[BANK_L_CTX] = mfc_dev->mem_base;
1205 mfc_dev->dma_base[BANK_R_CTX] = mfc_dev->mem_base;
1206
1207 /*
1208 * MFC hardware cannot handle 0 as a base address, so mark first 128K
1209 * as used (to keep required base alignment) and adjust base address
1210 */
1211 if (mfc_dev->mem_base == (dma_addr_t)0) {
1212 unsigned int offset = 1 << MFC_BASE_ALIGN_ORDER;
1213
1214 bitmap_set(mfc_dev->mem_bitmap, 0, offset >> PAGE_SHIFT);
1215 mfc_dev->dma_base[BANK_L_CTX] += offset;
1216 mfc_dev->dma_base[BANK_R_CTX] += offset;
1217 }
1218
1219 /* Firmware allocation cannot fail in this case */
1220 s5p_mfc_alloc_firmware(mfc_dev);
1221
1222 mfc_dev->mem_dev[BANK_L_CTX] = mfc_dev->mem_dev[BANK_R_CTX] = dev;
1223 vb2_dma_contig_set_max_seg_size(dev, DMA_BIT_MASK(32));
1224
1225 dev_info(dev, "preallocated %ld MiB buffer for the firmware and context buffers\n",
1226 (mem_size / SZ_1M));
1227
1228 return 0;
1229 }
1230
s5p_mfc_unconfigure_common_memory(struct s5p_mfc_dev * mfc_dev)1231 static void s5p_mfc_unconfigure_common_memory(struct s5p_mfc_dev *mfc_dev)
1232 {
1233 struct device *dev = &mfc_dev->plat_dev->dev;
1234
1235 dma_free_coherent(dev, mfc_dev->mem_size, mfc_dev->mem_virt,
1236 mfc_dev->mem_base);
1237 kfree(mfc_dev->mem_bitmap);
1238 vb2_dma_contig_clear_max_seg_size(dev);
1239 }
1240
s5p_mfc_configure_dma_memory(struct s5p_mfc_dev * mfc_dev)1241 static int s5p_mfc_configure_dma_memory(struct s5p_mfc_dev *mfc_dev)
1242 {
1243 struct device *dev = &mfc_dev->plat_dev->dev;
1244
1245 if (exynos_is_iommu_available(dev) || !IS_TWOPORT(mfc_dev))
1246 return s5p_mfc_configure_common_memory(mfc_dev);
1247 else
1248 return s5p_mfc_configure_2port_memory(mfc_dev);
1249 }
1250
s5p_mfc_unconfigure_dma_memory(struct s5p_mfc_dev * mfc_dev)1251 static void s5p_mfc_unconfigure_dma_memory(struct s5p_mfc_dev *mfc_dev)
1252 {
1253 struct device *dev = &mfc_dev->plat_dev->dev;
1254
1255 s5p_mfc_release_firmware(mfc_dev);
1256 if (exynos_is_iommu_available(dev) || !IS_TWOPORT(mfc_dev))
1257 s5p_mfc_unconfigure_common_memory(mfc_dev);
1258 else
1259 s5p_mfc_unconfigure_2port_memory(mfc_dev);
1260 }
1261
1262 /* MFC probe function */
s5p_mfc_probe(struct platform_device * pdev)1263 static int s5p_mfc_probe(struct platform_device *pdev)
1264 {
1265 struct s5p_mfc_dev *dev;
1266 struct video_device *vfd;
1267 struct resource *res;
1268 int ret;
1269
1270 pr_debug("%s++\n", __func__);
1271 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
1272 if (!dev)
1273 return -ENOMEM;
1274
1275 spin_lock_init(&dev->irqlock);
1276 spin_lock_init(&dev->condlock);
1277 dev->plat_dev = pdev;
1278 if (!dev->plat_dev) {
1279 dev_err(&pdev->dev, "No platform data specified\n");
1280 return -ENODEV;
1281 }
1282
1283 dev->variant = of_device_get_match_data(&pdev->dev);
1284
1285 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1286 dev->regs_base = devm_ioremap_resource(&pdev->dev, res);
1287 if (IS_ERR(dev->regs_base))
1288 return PTR_ERR(dev->regs_base);
1289
1290 res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
1291 if (!res) {
1292 dev_err(&pdev->dev, "failed to get irq resource\n");
1293 return -ENOENT;
1294 }
1295 dev->irq = res->start;
1296 ret = devm_request_irq(&pdev->dev, dev->irq, s5p_mfc_irq,
1297 0, pdev->name, dev);
1298 if (ret) {
1299 dev_err(&pdev->dev, "Failed to install irq (%d)\n", ret);
1300 return ret;
1301 }
1302
1303 ret = s5p_mfc_configure_dma_memory(dev);
1304 if (ret < 0) {
1305 dev_err(&pdev->dev, "failed to configure DMA memory\n");
1306 return ret;
1307 }
1308
1309 ret = s5p_mfc_init_pm(dev);
1310 if (ret < 0) {
1311 dev_err(&pdev->dev, "failed to get mfc clock source\n");
1312 goto err_dma;
1313 }
1314
1315 /*
1316 * Load fails if fs isn't mounted. Try loading anyway.
1317 * _open() will load it, it it fails now. Ignore failure.
1318 */
1319 s5p_mfc_load_firmware(dev);
1320
1321 mutex_init(&dev->mfc_mutex);
1322 init_waitqueue_head(&dev->queue);
1323 dev->hw_lock = 0;
1324 INIT_WORK(&dev->watchdog_work, s5p_mfc_watchdog_worker);
1325 atomic_set(&dev->watchdog_cnt, 0);
1326 timer_setup(&dev->watchdog_timer, s5p_mfc_watchdog, 0);
1327
1328 ret = v4l2_device_register(&pdev->dev, &dev->v4l2_dev);
1329 if (ret)
1330 goto err_v4l2_dev_reg;
1331
1332 /* decoder */
1333 vfd = video_device_alloc();
1334 if (!vfd) {
1335 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1336 ret = -ENOMEM;
1337 goto err_dec_alloc;
1338 }
1339 vfd->fops = &s5p_mfc_fops;
1340 vfd->ioctl_ops = get_dec_v4l2_ioctl_ops();
1341 vfd->release = video_device_release;
1342 vfd->lock = &dev->mfc_mutex;
1343 vfd->v4l2_dev = &dev->v4l2_dev;
1344 vfd->vfl_dir = VFL_DIR_M2M;
1345 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_DEC_NAME);
1346 dev->vfd_dec = vfd;
1347 video_set_drvdata(vfd, dev);
1348
1349 /* encoder */
1350 vfd = video_device_alloc();
1351 if (!vfd) {
1352 v4l2_err(&dev->v4l2_dev, "Failed to allocate video device\n");
1353 ret = -ENOMEM;
1354 goto err_enc_alloc;
1355 }
1356 vfd->fops = &s5p_mfc_fops;
1357 vfd->ioctl_ops = get_enc_v4l2_ioctl_ops();
1358 vfd->release = video_device_release;
1359 vfd->lock = &dev->mfc_mutex;
1360 vfd->v4l2_dev = &dev->v4l2_dev;
1361 vfd->vfl_dir = VFL_DIR_M2M;
1362 snprintf(vfd->name, sizeof(vfd->name), "%s", S5P_MFC_ENC_NAME);
1363 dev->vfd_enc = vfd;
1364 video_set_drvdata(vfd, dev);
1365 platform_set_drvdata(pdev, dev);
1366
1367 /* Initialize HW ops and commands based on MFC version */
1368 s5p_mfc_init_hw_ops(dev);
1369 s5p_mfc_init_hw_cmds(dev);
1370 s5p_mfc_init_regs(dev);
1371
1372 /* Register decoder and encoder */
1373 ret = video_register_device(dev->vfd_dec, VFL_TYPE_GRABBER, 0);
1374 if (ret) {
1375 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1376 goto err_dec_reg;
1377 }
1378 v4l2_info(&dev->v4l2_dev,
1379 "decoder registered as /dev/video%d\n", dev->vfd_dec->num);
1380
1381 ret = video_register_device(dev->vfd_enc, VFL_TYPE_GRABBER, 0);
1382 if (ret) {
1383 v4l2_err(&dev->v4l2_dev, "Failed to register video device\n");
1384 goto err_enc_reg;
1385 }
1386 v4l2_info(&dev->v4l2_dev,
1387 "encoder registered as /dev/video%d\n", dev->vfd_enc->num);
1388
1389 pr_debug("%s--\n", __func__);
1390 return 0;
1391
1392 /* Deinit MFC if probe had failed */
1393 err_enc_reg:
1394 video_unregister_device(dev->vfd_dec);
1395 err_dec_reg:
1396 video_device_release(dev->vfd_enc);
1397 err_enc_alloc:
1398 video_device_release(dev->vfd_dec);
1399 err_dec_alloc:
1400 v4l2_device_unregister(&dev->v4l2_dev);
1401 err_v4l2_dev_reg:
1402 s5p_mfc_final_pm(dev);
1403 err_dma:
1404 s5p_mfc_unconfigure_dma_memory(dev);
1405
1406 pr_debug("%s-- with error\n", __func__);
1407 return ret;
1408
1409 }
1410
1411 /* Remove the driver */
s5p_mfc_remove(struct platform_device * pdev)1412 static int s5p_mfc_remove(struct platform_device *pdev)
1413 {
1414 struct s5p_mfc_dev *dev = platform_get_drvdata(pdev);
1415 struct s5p_mfc_ctx *ctx;
1416 int i;
1417
1418 v4l2_info(&dev->v4l2_dev, "Removing %s\n", pdev->name);
1419
1420 /*
1421 * Clear ctx dev pointer to avoid races between s5p_mfc_remove()
1422 * and s5p_mfc_release() and s5p_mfc_release() accessing ctx->dev
1423 * after s5p_mfc_remove() is run during unbind.
1424 */
1425 mutex_lock(&dev->mfc_mutex);
1426 for (i = 0; i < MFC_NUM_CONTEXTS; i++) {
1427 ctx = dev->ctx[i];
1428 if (!ctx)
1429 continue;
1430 /* clear ctx->dev */
1431 ctx->dev = NULL;
1432 }
1433 mutex_unlock(&dev->mfc_mutex);
1434
1435 del_timer_sync(&dev->watchdog_timer);
1436 flush_work(&dev->watchdog_work);
1437
1438 video_unregister_device(dev->vfd_enc);
1439 video_unregister_device(dev->vfd_dec);
1440 video_device_release(dev->vfd_enc);
1441 video_device_release(dev->vfd_dec);
1442 v4l2_device_unregister(&dev->v4l2_dev);
1443 s5p_mfc_unconfigure_dma_memory(dev);
1444
1445 s5p_mfc_final_pm(dev);
1446 return 0;
1447 }
1448
1449 #ifdef CONFIG_PM_SLEEP
1450
s5p_mfc_suspend(struct device * dev)1451 static int s5p_mfc_suspend(struct device *dev)
1452 {
1453 struct s5p_mfc_dev *m_dev = dev_get_drvdata(dev);
1454 int ret;
1455
1456 if (m_dev->num_inst == 0)
1457 return 0;
1458
1459 if (test_and_set_bit(0, &m_dev->enter_suspend) != 0) {
1460 mfc_err("Error: going to suspend for a second time\n");
1461 return -EIO;
1462 }
1463
1464 /* Check if we're processing then wait if it necessary. */
1465 while (test_and_set_bit(0, &m_dev->hw_lock) != 0) {
1466 /* Try and lock the HW */
1467 /* Wait on the interrupt waitqueue */
1468 ret = wait_event_interruptible_timeout(m_dev->queue,
1469 m_dev->int_cond, msecs_to_jiffies(MFC_INT_TIMEOUT));
1470 if (ret == 0) {
1471 mfc_err("Waiting for hardware to finish timed out\n");
1472 clear_bit(0, &m_dev->enter_suspend);
1473 return -EIO;
1474 }
1475 }
1476
1477 ret = s5p_mfc_sleep(m_dev);
1478 if (ret) {
1479 clear_bit(0, &m_dev->enter_suspend);
1480 clear_bit(0, &m_dev->hw_lock);
1481 }
1482 return ret;
1483 }
1484
s5p_mfc_resume(struct device * dev)1485 static int s5p_mfc_resume(struct device *dev)
1486 {
1487 struct s5p_mfc_dev *m_dev = dev_get_drvdata(dev);
1488
1489 if (m_dev->num_inst == 0)
1490 return 0;
1491 return s5p_mfc_wakeup(m_dev);
1492 }
1493 #endif
1494
1495 /* Power management */
1496 static const struct dev_pm_ops s5p_mfc_pm_ops = {
1497 SET_SYSTEM_SLEEP_PM_OPS(s5p_mfc_suspend, s5p_mfc_resume)
1498 };
1499
1500 static struct s5p_mfc_buf_size_v5 mfc_buf_size_v5 = {
1501 .h264_ctx = MFC_H264_CTX_BUF_SIZE,
1502 .non_h264_ctx = MFC_CTX_BUF_SIZE,
1503 .dsc = DESC_BUF_SIZE,
1504 .shm = SHARED_BUF_SIZE,
1505 };
1506
1507 static struct s5p_mfc_buf_size buf_size_v5 = {
1508 .fw = MAX_FW_SIZE,
1509 .cpb = MAX_CPB_SIZE,
1510 .priv = &mfc_buf_size_v5,
1511 };
1512
1513 static struct s5p_mfc_variant mfc_drvdata_v5 = {
1514 .version = MFC_VERSION,
1515 .version_bit = MFC_V5_BIT,
1516 .port_num = MFC_NUM_PORTS,
1517 .buf_size = &buf_size_v5,
1518 .fw_name[0] = "s5p-mfc.fw",
1519 .clk_names = {"mfc", "sclk_mfc"},
1520 .num_clocks = 2,
1521 .use_clock_gating = true,
1522 };
1523
1524 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v6 = {
1525 .dev_ctx = MFC_CTX_BUF_SIZE_V6,
1526 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V6,
1527 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V6,
1528 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V6,
1529 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V6,
1530 };
1531
1532 static struct s5p_mfc_buf_size buf_size_v6 = {
1533 .fw = MAX_FW_SIZE_V6,
1534 .cpb = MAX_CPB_SIZE_V6,
1535 .priv = &mfc_buf_size_v6,
1536 };
1537
1538 static struct s5p_mfc_variant mfc_drvdata_v6 = {
1539 .version = MFC_VERSION_V6,
1540 .version_bit = MFC_V6_BIT,
1541 .port_num = MFC_NUM_PORTS_V6,
1542 .buf_size = &buf_size_v6,
1543 .fw_name[0] = "s5p-mfc-v6.fw",
1544 /*
1545 * v6-v2 firmware contains bug fixes and interface change
1546 * for init buffer command
1547 */
1548 .fw_name[1] = "s5p-mfc-v6-v2.fw",
1549 .clk_names = {"mfc"},
1550 .num_clocks = 1,
1551 };
1552
1553 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v7 = {
1554 .dev_ctx = MFC_CTX_BUF_SIZE_V7,
1555 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V7,
1556 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V7,
1557 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V7,
1558 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V7,
1559 };
1560
1561 static struct s5p_mfc_buf_size buf_size_v7 = {
1562 .fw = MAX_FW_SIZE_V7,
1563 .cpb = MAX_CPB_SIZE_V7,
1564 .priv = &mfc_buf_size_v7,
1565 };
1566
1567 static struct s5p_mfc_variant mfc_drvdata_v7 = {
1568 .version = MFC_VERSION_V7,
1569 .version_bit = MFC_V7_BIT,
1570 .port_num = MFC_NUM_PORTS_V7,
1571 .buf_size = &buf_size_v7,
1572 .fw_name[0] = "s5p-mfc-v7.fw",
1573 .clk_names = {"mfc", "sclk_mfc"},
1574 .num_clocks = 2,
1575 };
1576
1577 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v8 = {
1578 .dev_ctx = MFC_CTX_BUF_SIZE_V8,
1579 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V8,
1580 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V8,
1581 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V8,
1582 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V8,
1583 };
1584
1585 static struct s5p_mfc_buf_size buf_size_v8 = {
1586 .fw = MAX_FW_SIZE_V8,
1587 .cpb = MAX_CPB_SIZE_V8,
1588 .priv = &mfc_buf_size_v8,
1589 };
1590
1591 static struct s5p_mfc_variant mfc_drvdata_v8 = {
1592 .version = MFC_VERSION_V8,
1593 .version_bit = MFC_V8_BIT,
1594 .port_num = MFC_NUM_PORTS_V8,
1595 .buf_size = &buf_size_v8,
1596 .fw_name[0] = "s5p-mfc-v8.fw",
1597 .clk_names = {"mfc"},
1598 .num_clocks = 1,
1599 };
1600
1601 static struct s5p_mfc_variant mfc_drvdata_v8_5433 = {
1602 .version = MFC_VERSION_V8,
1603 .version_bit = MFC_V8_BIT,
1604 .port_num = MFC_NUM_PORTS_V8,
1605 .buf_size = &buf_size_v8,
1606 .fw_name[0] = "s5p-mfc-v8.fw",
1607 .clk_names = {"pclk", "aclk", "aclk_xiu"},
1608 .num_clocks = 3,
1609 };
1610
1611 static struct s5p_mfc_buf_size_v6 mfc_buf_size_v10 = {
1612 .dev_ctx = MFC_CTX_BUF_SIZE_V10,
1613 .h264_dec_ctx = MFC_H264_DEC_CTX_BUF_SIZE_V10,
1614 .other_dec_ctx = MFC_OTHER_DEC_CTX_BUF_SIZE_V10,
1615 .h264_enc_ctx = MFC_H264_ENC_CTX_BUF_SIZE_V10,
1616 .hevc_enc_ctx = MFC_HEVC_ENC_CTX_BUF_SIZE_V10,
1617 .other_enc_ctx = MFC_OTHER_ENC_CTX_BUF_SIZE_V10,
1618 };
1619
1620 static struct s5p_mfc_buf_size buf_size_v10 = {
1621 .fw = MAX_FW_SIZE_V10,
1622 .cpb = MAX_CPB_SIZE_V10,
1623 .priv = &mfc_buf_size_v10,
1624 };
1625
1626 static struct s5p_mfc_variant mfc_drvdata_v10 = {
1627 .version = MFC_VERSION_V10,
1628 .version_bit = MFC_V10_BIT,
1629 .port_num = MFC_NUM_PORTS_V10,
1630 .buf_size = &buf_size_v10,
1631 .fw_name[0] = "s5p-mfc-v10.fw",
1632 };
1633
1634 static const struct of_device_id exynos_mfc_match[] = {
1635 {
1636 .compatible = "samsung,mfc-v5",
1637 .data = &mfc_drvdata_v5,
1638 }, {
1639 .compatible = "samsung,mfc-v6",
1640 .data = &mfc_drvdata_v6,
1641 }, {
1642 .compatible = "samsung,mfc-v7",
1643 .data = &mfc_drvdata_v7,
1644 }, {
1645 .compatible = "samsung,mfc-v8",
1646 .data = &mfc_drvdata_v8,
1647 }, {
1648 .compatible = "samsung,exynos5433-mfc",
1649 .data = &mfc_drvdata_v8_5433,
1650 }, {
1651 .compatible = "samsung,mfc-v10",
1652 .data = &mfc_drvdata_v10,
1653 },
1654 {},
1655 };
1656 MODULE_DEVICE_TABLE(of, exynos_mfc_match);
1657
1658 static struct platform_driver s5p_mfc_driver = {
1659 .probe = s5p_mfc_probe,
1660 .remove = s5p_mfc_remove,
1661 .driver = {
1662 .name = S5P_MFC_NAME,
1663 .pm = &s5p_mfc_pm_ops,
1664 .of_match_table = exynos_mfc_match,
1665 },
1666 };
1667
1668 module_platform_driver(s5p_mfc_driver);
1669
1670 MODULE_LICENSE("GPL");
1671 MODULE_AUTHOR("Kamil Debski <k.debski@samsung.com>");
1672 MODULE_DESCRIPTION("Samsung S5P Multi Format Codec V4L2 driver");
1673
1674
