1 /* 2 * Copyright (C) 2005-2009 Texas Instruments Inc 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License as published by 6 * the Free Software Foundation; either version 2 of the License, or 7 * (at your option) any later version. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 #ifndef _DM355_CCDC_REGS_H 15 #define _DM355_CCDC_REGS_H 16 17 /**************************************************************************\ 18 * Register OFFSET Definitions 19 \**************************************************************************/ 20 #define SYNCEN 0x00 21 #define MODESET 0x04 22 #define HDWIDTH 0x08 23 #define VDWIDTH 0x0c 24 #define PPLN 0x10 25 #define LPFR 0x14 26 #define SPH 0x18 27 #define NPH 0x1c 28 #define SLV0 0x20 29 #define SLV1 0x24 30 #define NLV 0x28 31 #define CULH 0x2c 32 #define CULV 0x30 33 #define HSIZE 0x34 34 #define SDOFST 0x38 35 #define STADRH 0x3c 36 #define STADRL 0x40 37 #define CLAMP 0x44 38 #define DCSUB 0x48 39 #define COLPTN 0x4c 40 #define BLKCMP0 0x50 41 #define BLKCMP1 0x54 42 #define MEDFILT 0x58 43 #define RYEGAIN 0x5c 44 #define GRCYGAIN 0x60 45 #define GBGGAIN 0x64 46 #define BMGGAIN 0x68 47 #define OFFSET 0x6c 48 #define OUTCLIP 0x70 49 #define VDINT0 0x74 50 #define VDINT1 0x78 51 #define RSV0 0x7c 52 #define GAMMAWD 0x80 53 #define REC656IF 0x84 54 #define CCDCFG 0x88 55 #define FMTCFG 0x8c 56 #define FMTPLEN 0x90 57 #define FMTSPH 0x94 58 #define FMTLNH 0x98 59 #define FMTSLV 0x9c 60 #define FMTLNV 0xa0 61 #define FMTRLEN 0xa4 62 #define FMTHCNT 0xa8 63 #define FMT_ADDR_PTR_B 0xac 64 #define FMT_ADDR_PTR(i) (FMT_ADDR_PTR_B + (i * 4)) 65 #define FMTPGM_VF0 0xcc 66 #define FMTPGM_VF1 0xd0 67 #define FMTPGM_AP0 0xd4 68 #define FMTPGM_AP1 0xd8 69 #define FMTPGM_AP2 0xdc 70 #define FMTPGM_AP3 0xe0 71 #define FMTPGM_AP4 0xe4 72 #define FMTPGM_AP5 0xe8 73 #define FMTPGM_AP6 0xec 74 #define FMTPGM_AP7 0xf0 75 #define LSCCFG1 0xf4 76 #define LSCCFG2 0xf8 77 #define LSCH0 0xfc 78 #define LSCV0 0x100 79 #define LSCKH 0x104 80 #define LSCKV 0x108 81 #define LSCMEMCTL 0x10c 82 #define LSCMEMD 0x110 83 #define LSCMEMQ 0x114 84 #define DFCCTL 0x118 85 #define DFCVSAT 0x11c 86 #define DFCMEMCTL 0x120 87 #define DFCMEM0 0x124 88 #define DFCMEM1 0x128 89 #define DFCMEM2 0x12c 90 #define DFCMEM3 0x130 91 #define DFCMEM4 0x134 92 #define CSCCTL 0x138 93 #define CSCM0 0x13c 94 #define CSCM1 0x140 95 #define CSCM2 0x144 96 #define CSCM3 0x148 97 #define CSCM4 0x14c 98 #define CSCM5 0x150 99 #define CSCM6 0x154 100 #define CSCM7 0x158 101 #define DATAOFST 0x15c 102 #define CCDC_REG_LAST DATAOFST 103 /************************************************************** 104 * Define for various register bit mask and shifts for CCDC 105 * 106 **************************************************************/ 107 #define CCDC_RAW_IP_MODE 0 108 #define CCDC_VDHDOUT_INPUT 0 109 #define CCDC_YCINSWP_RAW (0 << 4) 110 #define CCDC_EXWEN_DISABLE 0 111 #define CCDC_DATAPOL_NORMAL 0 112 #define CCDC_CCDCFG_FIDMD_LATCH_VSYNC 0 113 #define CCDC_CCDCFG_FIDMD_NO_LATCH_VSYNC (1 << 6) 114 #define CCDC_CCDCFG_WENLOG_AND 0 115 #define CCDC_CCDCFG_TRGSEL_WEN 0 116 #define CCDC_CCDCFG_EXTRG_DISABLE 0 117 #define CCDC_CFA_MOSAIC 0 118 #define CCDC_Y8POS_SHIFT 11 119 120 #define CCDC_VDC_DFCVSAT_MASK 0x3fff 121 #define CCDC_DATAOFST_MASK 0x0ff 122 #define CCDC_DATAOFST_H_SHIFT 0 123 #define CCDC_DATAOFST_V_SHIFT 8 124 #define CCDC_GAMMAWD_CFA_MASK 1 125 #define CCDC_GAMMAWD_CFA_SHIFT 5 126 #define CCDC_GAMMAWD_INPUT_SHIFT 2 127 #define CCDC_FID_POL_MASK 1 128 #define CCDC_FID_POL_SHIFT 4 129 #define CCDC_HD_POL_MASK 1 130 #define CCDC_HD_POL_SHIFT 3 131 #define CCDC_VD_POL_MASK 1 132 #define CCDC_VD_POL_SHIFT 2 133 #define CCDC_VD_POL_NEGATIVE (1 << 2) 134 #define CCDC_FRM_FMT_MASK 1 135 #define CCDC_FRM_FMT_SHIFT 7 136 #define CCDC_DATA_SZ_MASK 7 137 #define CCDC_DATA_SZ_SHIFT 8 138 #define CCDC_VDHDOUT_MASK 1 139 #define CCDC_VDHDOUT_SHIFT 0 140 #define CCDC_EXWEN_MASK 1 141 #define CCDC_EXWEN_SHIFT 5 142 #define CCDC_INPUT_MODE_MASK 3 143 #define CCDC_INPUT_MODE_SHIFT 12 144 #define CCDC_PIX_FMT_MASK 3 145 #define CCDC_PIX_FMT_SHIFT 12 146 #define CCDC_DATAPOL_MASK 1 147 #define CCDC_DATAPOL_SHIFT 6 148 #define CCDC_WEN_ENABLE (1 << 1) 149 #define CCDC_VDHDEN_ENABLE (1 << 16) 150 #define CCDC_LPF_ENABLE (1 << 14) 151 #define CCDC_ALAW_ENABLE 1 152 #define CCDC_ALAW_GAMMA_WD_MASK 7 153 #define CCDC_REC656IF_BT656_EN 3 154 155 #define CCDC_FMTCFG_FMTMODE_MASK 3 156 #define CCDC_FMTCFG_FMTMODE_SHIFT 1 157 #define CCDC_FMTCFG_LNUM_MASK 3 158 #define CCDC_FMTCFG_LNUM_SHIFT 4 159 #define CCDC_FMTCFG_ADDRINC_MASK 7 160 #define CCDC_FMTCFG_ADDRINC_SHIFT 8 161 162 #define CCDC_CCDCFG_FIDMD_SHIFT 6 163 #define CCDC_CCDCFG_WENLOG_SHIFT 8 164 #define CCDC_CCDCFG_TRGSEL_SHIFT 9 165 #define CCDC_CCDCFG_EXTRG_SHIFT 10 166 #define CCDC_CCDCFG_MSBINVI_SHIFT 13 167 168 #define CCDC_HSIZE_FLIP_SHIFT 12 169 #define CCDC_HSIZE_FLIP_MASK 1 170 #define CCDC_HSIZE_VAL_MASK 0xFFF 171 #define CCDC_SDOFST_FIELD_INTERLEAVED 0x249 172 #define CCDC_SDOFST_INTERLACE_INVERSE 0x4B6D 173 #define CCDC_SDOFST_INTERLACE_NORMAL 0x0B6D 174 #define CCDC_SDOFST_PROGRESSIVE_INVERSE 0x4000 175 #define CCDC_SDOFST_PROGRESSIVE_NORMAL 0 176 #define CCDC_START_PX_HOR_MASK 0x7FFF 177 #define CCDC_NUM_PX_HOR_MASK 0x7FFF 178 #define CCDC_START_VER_ONE_MASK 0x7FFF 179 #define CCDC_START_VER_TWO_MASK 0x7FFF 180 #define CCDC_NUM_LINES_VER 0x7FFF 181 182 #define CCDC_BLK_CLAMP_ENABLE (1 << 15) 183 #define CCDC_BLK_SGAIN_MASK 0x1F 184 #define CCDC_BLK_ST_PXL_MASK 0x1FFF 185 #define CCDC_BLK_SAMPLE_LN_MASK 3 186 #define CCDC_BLK_SAMPLE_LN_SHIFT 13 187 188 #define CCDC_NUM_LINE_CALC_MASK 3 189 #define CCDC_NUM_LINE_CALC_SHIFT 14 190 191 #define CCDC_BLK_DC_SUB_MASK 0x3FFF 192 #define CCDC_BLK_COMP_MASK 0xFF 193 #define CCDC_BLK_COMP_GB_COMP_SHIFT 8 194 #define CCDC_BLK_COMP_GR_COMP_SHIFT 0 195 #define CCDC_BLK_COMP_R_COMP_SHIFT 8 196 #define CCDC_LATCH_ON_VSYNC_DISABLE (1 << 15) 197 #define CCDC_LATCH_ON_VSYNC_ENABLE (0 << 15) 198 #define CCDC_FPC_ENABLE (1 << 15) 199 #define CCDC_FPC_FPC_NUM_MASK 0x7FFF 200 #define CCDC_DATA_PACK_ENABLE (1 << 11) 201 #define CCDC_FMT_HORZ_FMTLNH_MASK 0x1FFF 202 #define CCDC_FMT_HORZ_FMTSPH_MASK 0x1FFF 203 #define CCDC_FMT_HORZ_FMTSPH_SHIFT 16 204 #define CCDC_FMT_VERT_FMTLNV_MASK 0x1FFF 205 #define CCDC_FMT_VERT_FMTSLV_MASK 0x1FFF 206 #define CCDC_FMT_VERT_FMTSLV_SHIFT 16 207 #define CCDC_VP_OUT_VERT_NUM_MASK 0x3FFF 208 #define CCDC_VP_OUT_VERT_NUM_SHIFT 17 209 #define CCDC_VP_OUT_HORZ_NUM_MASK 0x1FFF 210 #define CCDC_VP_OUT_HORZ_NUM_SHIFT 4 211 #define CCDC_VP_OUT_HORZ_ST_MASK 0xF 212 213 #define CCDC_CSC_COEF_INTEG_MASK 7 214 #define CCDC_CSC_COEF_DECIMAL_MASK 0x1f 215 #define CCDC_CSC_COEF_INTEG_SHIFT 5 216 #define CCDC_CSCM_MSB_SHIFT 8 217 #define CCDC_CSC_ENABLE 1 218 #define CCDC_CSC_DEC_MAX 32 219 220 #define CCDC_MFILT1_SHIFT 10 221 #define CCDC_MFILT2_SHIFT 8 222 #define CCDC_MED_FILT_THRESH 0x3FFF 223 #define CCDC_LPF_MASK 1 224 #define CCDC_LPF_SHIFT 14 225 #define CCDC_OFFSET_MASK 0x3FF 226 #define CCDC_DATASFT_MASK 7 227 #define CCDC_DATASFT_SHIFT 8 228 229 #define CCDC_DF_ENABLE 1 230 231 #define CCDC_FMTPLEN_P0_MASK 0xF 232 #define CCDC_FMTPLEN_P1_MASK 0xF 233 #define CCDC_FMTPLEN_P2_MASK 7 234 #define CCDC_FMTPLEN_P3_MASK 7 235 #define CCDC_FMTPLEN_P0_SHIFT 0 236 #define CCDC_FMTPLEN_P1_SHIFT 4 237 #define CCDC_FMTPLEN_P2_SHIFT 8 238 #define CCDC_FMTPLEN_P3_SHIFT 12 239 240 #define CCDC_FMTSPH_MASK 0x1FFF 241 #define CCDC_FMTLNH_MASK 0x1FFF 242 #define CCDC_FMTSLV_MASK 0x1FFF 243 #define CCDC_FMTLNV_MASK 0x7FFF 244 #define CCDC_FMTRLEN_MASK 0x1FFF 245 #define CCDC_FMTHCNT_MASK 0x1FFF 246 247 #define CCDC_ADP_INIT_MASK 0x1FFF 248 #define CCDC_ADP_LINE_SHIFT 13 249 #define CCDC_ADP_LINE_MASK 3 250 #define CCDC_FMTPGN_APTR_MASK 7 251 252 #define CCDC_DFCCTL_GDFCEN_MASK 1 253 #define CCDC_DFCCTL_VDFCEN_MASK 1 254 #define CCDC_DFCCTL_VDFC_DISABLE (0 << 4) 255 #define CCDC_DFCCTL_VDFCEN_SHIFT 4 256 #define CCDC_DFCCTL_VDFCSL_MASK 3 257 #define CCDC_DFCCTL_VDFCSL_SHIFT 5 258 #define CCDC_DFCCTL_VDFCUDA_MASK 1 259 #define CCDC_DFCCTL_VDFCUDA_SHIFT 7 260 #define CCDC_DFCCTL_VDFLSFT_MASK 3 261 #define CCDC_DFCCTL_VDFLSFT_SHIFT 8 262 #define CCDC_DFCMEMCTL_DFCMARST_MASK 1 263 #define CCDC_DFCMEMCTL_DFCMARST_SHIFT 2 264 #define CCDC_DFCMEMCTL_DFCMWR_MASK 1 265 #define CCDC_DFCMEMCTL_DFCMWR_SHIFT 0 266 #define CCDC_DFCMEMCTL_INC_ADDR (0 << 2) 267 268 #define CCDC_LSCCFG_GFTSF_MASK 7 269 #define CCDC_LSCCFG_GFTSF_SHIFT 1 270 #define CCDC_LSCCFG_GFTINV_MASK 0xf 271 #define CCDC_LSCCFG_GFTINV_SHIFT 4 272 #define CCDC_LSC_GFTABLE_SEL_MASK 3 273 #define CCDC_LSC_GFTABLE_EPEL_SHIFT 8 274 #define CCDC_LSC_GFTABLE_OPEL_SHIFT 10 275 #define CCDC_LSC_GFTABLE_EPOL_SHIFT 12 276 #define CCDC_LSC_GFTABLE_OPOL_SHIFT 14 277 #define CCDC_LSC_GFMODE_MASK 3 278 #define CCDC_LSC_GFMODE_SHIFT 4 279 #define CCDC_LSC_DISABLE 0 280 #define CCDC_LSC_ENABLE 1 281 #define CCDC_LSC_TABLE1_SLC 0 282 #define CCDC_LSC_TABLE2_SLC 1 283 #define CCDC_LSC_TABLE3_SLC 2 284 #define CCDC_LSC_MEMADDR_RESET (1 << 2) 285 #define CCDC_LSC_MEMADDR_INCR (0 << 2) 286 #define CCDC_LSC_FRAC_MASK_T1 0xFF 287 #define CCDC_LSC_INT_MASK 3 288 #define CCDC_LSC_FRAC_MASK 0x3FFF 289 #define CCDC_LSC_CENTRE_MASK 0x3FFF 290 #define CCDC_LSC_COEF_MASK 0xff 291 #define CCDC_LSC_COEFL_SHIFT 0 292 #define CCDC_LSC_COEFU_SHIFT 8 293 #define CCDC_GAIN_MASK 0x7FF 294 #define CCDC_SYNCEN_VDHDEN_MASK (1 << 0) 295 #define CCDC_SYNCEN_WEN_MASK (1 << 1) 296 #define CCDC_SYNCEN_WEN_SHIFT 1 297 298 /* Power on Defaults in hardware */ 299 #define MODESET_DEFAULT 0x200 300 #define CULH_DEFAULT 0xFFFF 301 #define CULV_DEFAULT 0xFF 302 #define GAIN_DEFAULT 256 303 #define OUTCLIP_DEFAULT 0x3FFF 304 #define LSCCFG2_DEFAULT 0xE 305 306 #endif 307
