1 /* 2 * ngene.h: nGene PCIe bridge driver 3 * 4 * Copyright (C) 2005-2007 Micronas 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License 8 * version 2 only, as published by the Free Software Foundation. 9 * 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 * 16 * To obtain the license, point your browser to 17 * http://www.gnu.org/copyleft/gpl.html 18 */ 19 20 #ifndef _NGENE_H_ 21 #define _NGENE_H_ 22 23 #include <linux/types.h> 24 #include <linux/sched.h> 25 #include <linux/interrupt.h> 26 #include <linux/i2c.h> 27 #include <asm/dma.h> 28 #include <linux/scatterlist.h> 29 30 #include <linux/dvb/frontend.h> 31 32 #include <media/dmxdev.h> 33 #include <media/dvbdev.h> 34 #include <media/dvb_demux.h> 35 #include <media/dvb_ca_en50221.h> 36 #include <media/dvb_frontend.h> 37 #include <media/dvb_ringbuffer.h> 38 #include <media/dvb_net.h> 39 #include "cxd2099.h" 40 41 #define DEVICE_NAME "ngene" 42 43 #define NGENE_VID 0x18c3 44 #define NGENE_PID 0x0720 45 46 #ifndef VIDEO_CAP_VC1 47 #define VIDEO_CAP_AVC 128 48 #define VIDEO_CAP_H264 128 49 #define VIDEO_CAP_VC1 256 50 #define VIDEO_CAP_WMV9 256 51 #define VIDEO_CAP_MPEG4 512 52 #endif 53 54 #define DEMOD_TYPE_STV090X 0 55 #define DEMOD_TYPE_DRXK 1 56 #define DEMOD_TYPE_STV0367 2 57 58 #define DEMOD_TYPE_XO2 32 59 #define DEMOD_TYPE_STV0910 (DEMOD_TYPE_XO2 + 0) 60 #define DEMOD_TYPE_SONY_CT2 (DEMOD_TYPE_XO2 + 1) 61 #define DEMOD_TYPE_SONY_ISDBT (DEMOD_TYPE_XO2 + 2) 62 #define DEMOD_TYPE_SONY_C2T2 (DEMOD_TYPE_XO2 + 3) 63 #define DEMOD_TYPE_ST_ATSC (DEMOD_TYPE_XO2 + 4) 64 #define DEMOD_TYPE_SONY_C2T2I (DEMOD_TYPE_XO2 + 5) 65 66 #define NGENE_XO2_TYPE_NONE 0 67 #define NGENE_XO2_TYPE_DUOFLEX 1 68 #define NGENE_XO2_TYPE_CI 2 69 70 enum STREAM { 71 STREAM_VIDEOIN1 = 0, /* ITU656 or TS Input */ 72 STREAM_VIDEOIN2, 73 STREAM_AUDIOIN1, /* I2S or SPI Input */ 74 STREAM_AUDIOIN2, 75 STREAM_AUDIOOUT, 76 MAX_STREAM 77 }; 78 79 enum SMODE_BITS { 80 SMODE_AUDIO_SPDIF = 0x20, 81 SMODE_AVSYNC = 0x10, 82 SMODE_TRANSPORT_STREAM = 0x08, 83 SMODE_AUDIO_CAPTURE = 0x04, 84 SMODE_VBI_CAPTURE = 0x02, 85 SMODE_VIDEO_CAPTURE = 0x01 86 }; 87 88 enum STREAM_FLAG_BITS { 89 SFLAG_CHROMA_FORMAT_2COMP = 0x01, /* Chroma Format : 2's complement */ 90 SFLAG_CHROMA_FORMAT_OFFSET = 0x00, /* Chroma Format : Binary offset */ 91 SFLAG_ORDER_LUMA_CHROMA = 0x02, /* Byte order: Y,Cb,Y,Cr */ 92 SFLAG_ORDER_CHROMA_LUMA = 0x00, /* Byte order: Cb,Y,Cr,Y */ 93 SFLAG_COLORBAR = 0x04, /* Select colorbar */ 94 }; 95 96 #define PROGRAM_ROM 0x0000 97 #define PROGRAM_SRAM 0x1000 98 #define PERIPHERALS0 0x8000 99 #define PERIPHERALS1 0x9000 100 #define SHARED_BUFFER 0xC000 101 102 #define HOST_TO_NGENE (SHARED_BUFFER+0x0000) 103 #define NGENE_TO_HOST (SHARED_BUFFER+0x0100) 104 #define NGENE_COMMAND (SHARED_BUFFER+0x0200) 105 #define NGENE_COMMAND_HI (SHARED_BUFFER+0x0204) 106 #define NGENE_STATUS (SHARED_BUFFER+0x0208) 107 #define NGENE_STATUS_HI (SHARED_BUFFER+0x020C) 108 #define NGENE_EVENT (SHARED_BUFFER+0x0210) 109 #define NGENE_EVENT_HI (SHARED_BUFFER+0x0214) 110 #define VARIABLES (SHARED_BUFFER+0x0210) 111 112 #define NGENE_INT_COUNTS (SHARED_BUFFER+0x0260) 113 #define NGENE_INT_ENABLE (SHARED_BUFFER+0x0264) 114 #define NGENE_VBI_LINE_COUNT (SHARED_BUFFER+0x0268) 115 116 #define BUFFER_GP_XMIT (SHARED_BUFFER+0x0800) 117 #define BUFFER_GP_RECV (SHARED_BUFFER+0x0900) 118 #define EEPROM_AREA (SHARED_BUFFER+0x0A00) 119 120 #define SG_V_IN_1 (SHARED_BUFFER+0x0A80) 121 #define SG_VBI_1 (SHARED_BUFFER+0x0B00) 122 #define SG_A_IN_1 (SHARED_BUFFER+0x0B80) 123 #define SG_V_IN_2 (SHARED_BUFFER+0x0C00) 124 #define SG_VBI_2 (SHARED_BUFFER+0x0C80) 125 #define SG_A_IN_2 (SHARED_BUFFER+0x0D00) 126 #define SG_V_OUT (SHARED_BUFFER+0x0D80) 127 #define SG_A_OUT2 (SHARED_BUFFER+0x0E00) 128 129 #define DATA_A_IN_1 (SHARED_BUFFER+0x0E80) 130 #define DATA_A_IN_2 (SHARED_BUFFER+0x0F00) 131 #define DATA_A_OUT (SHARED_BUFFER+0x0F80) 132 #define DATA_V_IN_1 (SHARED_BUFFER+0x1000) 133 #define DATA_V_IN_2 (SHARED_BUFFER+0x2000) 134 #define DATA_V_OUT (SHARED_BUFFER+0x3000) 135 136 #define DATA_FIFO_AREA (SHARED_BUFFER+0x1000) 137 138 #define TIMESTAMPS 0xA000 139 #define SCRATCHPAD 0xA080 140 #define FORCE_INT 0xA088 141 #define FORCE_NMI 0xA090 142 #define INT_STATUS 0xA0A0 143 144 #define DEV_VER 0x9004 145 146 #define FW_DEBUG_DEFAULT (PROGRAM_SRAM+0x00FF) 147 148 struct SG_ADDR { 149 u64 start; 150 u64 curr; 151 u16 curr_ptr; 152 u16 elements; 153 u32 pad[3]; 154 } __attribute__ ((__packed__)); 155 156 struct SHARED_MEMORY { 157 /* C000 */ 158 u32 HostToNgene[64]; 159 160 /* C100 */ 161 u32 NgeneToHost[64]; 162 163 /* C200 */ 164 u64 NgeneCommand; 165 u64 NgeneStatus; 166 u64 NgeneEvent; 167 168 /* C210 */ 169 u8 pad1[0xc260 - 0xc218]; 170 171 /* C260 */ 172 u32 IntCounts; 173 u32 IntEnable; 174 175 /* C268 */ 176 u8 pad2[0xd000 - 0xc268]; 177 178 } __attribute__ ((__packed__)); 179 180 struct BUFFER_STREAM_RESULTS { 181 u32 Clock; /* Stream time in 100ns units */ 182 u16 RemainingLines; /* Remaining lines in this field. 183 0 for complete field */ 184 u8 FieldCount; /* Video field number */ 185 u8 Flags; /* Bit 7 = Done, Bit 6 = seen, Bit 5 = overflow, 186 Bit 0 = FieldID */ 187 u16 BlockCount; /* Audio block count (unused) */ 188 u8 Reserved[2]; 189 u32 DTOUpdate; 190 } __attribute__ ((__packed__)); 191 192 struct HW_SCATTER_GATHER_ELEMENT { 193 u64 Address; 194 u32 Length; 195 u32 Reserved; 196 } __attribute__ ((__packed__)); 197 198 struct BUFFER_HEADER { 199 u64 Next; 200 struct BUFFER_STREAM_RESULTS SR; 201 202 u32 Number_of_entries_1; 203 u32 Reserved5; 204 u64 Address_of_first_entry_1; 205 206 u32 Number_of_entries_2; 207 u32 Reserved7; 208 u64 Address_of_first_entry_2; 209 } __attribute__ ((__packed__)); 210 211 struct EVENT_BUFFER { 212 u32 TimeStamp; 213 u8 GPIOStatus; 214 u8 UARTStatus; 215 u8 RXCharacter; 216 u8 EventStatus; 217 u32 Reserved[2]; 218 } __attribute__ ((__packed__)); 219 220 /* Firmware commands. */ 221 222 enum OPCODES { 223 CMD_NOP = 0, 224 CMD_FWLOAD_PREPARE = 0x01, 225 CMD_FWLOAD_FINISH = 0x02, 226 CMD_I2C_READ = 0x03, 227 CMD_I2C_WRITE = 0x04, 228 229 CMD_I2C_WRITE_NOSTOP = 0x05, 230 CMD_I2C_CONTINUE_WRITE = 0x06, 231 CMD_I2C_CONTINUE_WRITE_NOSTOP = 0x07, 232 233 CMD_DEBUG_OUTPUT = 0x09, 234 235 CMD_CONTROL = 0x10, 236 CMD_CONFIGURE_BUFFER = 0x11, 237 CMD_CONFIGURE_FREE_BUFFER = 0x12, 238 239 CMD_SPI_READ = 0x13, 240 CMD_SPI_WRITE = 0x14, 241 242 CMD_MEM_READ = 0x20, 243 CMD_MEM_WRITE = 0x21, 244 CMD_SFR_READ = 0x22, 245 CMD_SFR_WRITE = 0x23, 246 CMD_IRAM_READ = 0x24, 247 CMD_IRAM_WRITE = 0x25, 248 CMD_SET_GPIO_PIN = 0x26, 249 CMD_SET_GPIO_INT = 0x27, 250 CMD_CONFIGURE_UART = 0x28, 251 CMD_WRITE_UART = 0x29, 252 MAX_CMD 253 }; 254 255 enum RESPONSES { 256 OK = 0, 257 ERROR = 1 258 }; 259 260 struct FW_HEADER { 261 u8 Opcode; 262 u8 Length; 263 } __attribute__ ((__packed__)); 264 265 struct FW_I2C_WRITE { 266 struct FW_HEADER hdr; 267 u8 Device; 268 u8 Data[250]; 269 } __attribute__ ((__packed__)); 270 271 struct FW_I2C_CONTINUE_WRITE { 272 struct FW_HEADER hdr; 273 u8 Data[250]; 274 } __attribute__ ((__packed__)); 275 276 struct FW_I2C_READ { 277 struct FW_HEADER hdr; 278 u8 Device; 279 u8 Data[252]; /* followed by two bytes of read data count */ 280 } __attribute__ ((__packed__)); 281 282 struct FW_SPI_WRITE { 283 struct FW_HEADER hdr; 284 u8 ModeSelect; 285 u8 Data[250]; 286 } __attribute__ ((__packed__)); 287 288 struct FW_SPI_READ { 289 struct FW_HEADER hdr; 290 u8 ModeSelect; 291 u8 Data[252]; /* followed by two bytes of read data count */ 292 } __attribute__ ((__packed__)); 293 294 struct FW_FWLOAD_PREPARE { 295 struct FW_HEADER hdr; 296 } __attribute__ ((__packed__)); 297 298 struct FW_FWLOAD_FINISH { 299 struct FW_HEADER hdr; 300 u16 Address; /* address of final block */ 301 u16 Length; 302 } __attribute__ ((__packed__)); 303 304 /* 305 * Meaning of FW_STREAM_CONTROL::Mode bits: 306 * Bit 7: Loopback PEXin to PEXout using TVOut channel 307 * Bit 6: AVLOOP 308 * Bit 5: Audio select; 0=I2S, 1=SPDIF 309 * Bit 4: AVSYNC 310 * Bit 3: Enable transport stream 311 * Bit 2: Enable audio capture 312 * Bit 1: Enable ITU-Video VBI capture 313 * Bit 0: Enable ITU-Video capture 314 * 315 * Meaning of FW_STREAM_CONTROL::Control bits (see UVI1_CTL) 316 * Bit 7: continuous capture 317 * Bit 6: capture one field 318 * Bit 5: capture one frame 319 * Bit 4: unused 320 * Bit 3: starting field; 0=odd, 1=even 321 * Bit 2: sample size; 0=8-bit, 1=10-bit 322 * Bit 1: data format; 0=UYVY, 1=YUY2 323 * Bit 0: resets buffer pointers 324 */ 325 326 enum FSC_MODE_BITS { 327 SMODE_LOOPBACK = 0x80, 328 SMODE_AVLOOP = 0x40, 329 _SMODE_AUDIO_SPDIF = 0x20, 330 _SMODE_AVSYNC = 0x10, 331 _SMODE_TRANSPORT_STREAM = 0x08, 332 _SMODE_AUDIO_CAPTURE = 0x04, 333 _SMODE_VBI_CAPTURE = 0x02, 334 _SMODE_VIDEO_CAPTURE = 0x01 335 }; 336 337 338 /* Meaning of FW_STREAM_CONTROL::Stream bits: 339 * Bit 3: Audio sample count: 0 = relative, 1 = absolute 340 * Bit 2: color bar select; 1=color bars, 0=CV3 decoder 341 * Bits 1-0: stream select, UVI1, UVI2, TVOUT 342 */ 343 344 struct FW_STREAM_CONTROL { 345 struct FW_HEADER hdr; 346 u8 Stream; /* Stream number (UVI1, UVI2, TVOUT) */ 347 u8 Control; /* Value written to UVI1_CTL */ 348 u8 Mode; /* Controls clock source */ 349 u8 SetupDataLen; /* Length of setup data, MSB=1 write 350 backwards */ 351 u16 CaptureBlockCount; /* Blocks (a 256 Bytes) to capture per buffer 352 for TS and Audio */ 353 u64 Buffer_Address; /* Address of first buffer header */ 354 u16 BytesPerVideoLine; 355 u16 MaxLinesPerField; 356 u16 MinLinesPerField; 357 u16 Reserved_1; 358 u16 BytesPerVBILine; 359 u16 MaxVBILinesPerField; 360 u16 MinVBILinesPerField; 361 u16 SetupDataAddr; /* ngene relative address of setup data */ 362 u8 SetupData[32]; /* setup data */ 363 } __attribute__((__packed__)); 364 365 #define AUDIO_BLOCK_SIZE 256 366 #define TS_BLOCK_SIZE 256 367 368 struct FW_MEM_READ { 369 struct FW_HEADER hdr; 370 u16 address; 371 } __attribute__ ((__packed__)); 372 373 struct FW_MEM_WRITE { 374 struct FW_HEADER hdr; 375 u16 address; 376 u8 data; 377 } __attribute__ ((__packed__)); 378 379 struct FW_SFR_IRAM_READ { 380 struct FW_HEADER hdr; 381 u8 address; 382 } __attribute__ ((__packed__)); 383 384 struct FW_SFR_IRAM_WRITE { 385 struct FW_HEADER hdr; 386 u8 address; 387 u8 data; 388 } __attribute__ ((__packed__)); 389 390 struct FW_SET_GPIO_PIN { 391 struct FW_HEADER hdr; 392 u8 select; 393 } __attribute__ ((__packed__)); 394 395 struct FW_SET_GPIO_INT { 396 struct FW_HEADER hdr; 397 u8 select; 398 } __attribute__ ((__packed__)); 399 400 struct FW_SET_DEBUGMODE { 401 struct FW_HEADER hdr; 402 u8 debug_flags; 403 } __attribute__ ((__packed__)); 404 405 struct FW_CONFIGURE_BUFFERS { 406 struct FW_HEADER hdr; 407 u8 config; 408 } __attribute__ ((__packed__)); 409 410 enum _BUFFER_CONFIGS { 411 /* 4k UVI1, 4k UVI2, 2k AUD1, 2k AUD2 (standard usage) */ 412 BUFFER_CONFIG_4422 = 0, 413 /* 3k UVI1, 3k UVI2, 3k AUD1, 3k AUD2 (4x TS input usage) */ 414 BUFFER_CONFIG_3333 = 1, 415 /* 8k UVI1, 0k UVI2, 2k AUD1, 2k I2SOut (HDTV decoder usage) */ 416 BUFFER_CONFIG_8022 = 2, 417 BUFFER_CONFIG_FW17 = 255, /* Use new FW 17 command */ 418 }; 419 420 struct FW_CONFIGURE_FREE_BUFFERS { 421 struct FW_HEADER hdr; 422 u8 UVI1_BufferLength; 423 u8 UVI2_BufferLength; 424 u8 TVO_BufferLength; 425 u8 AUD1_BufferLength; 426 u8 AUD2_BufferLength; 427 u8 TVA_BufferLength; 428 } __attribute__ ((__packed__)); 429 430 struct FW_CONFIGURE_UART { 431 struct FW_HEADER hdr; 432 u8 UartControl; 433 } __attribute__ ((__packed__)); 434 435 enum _UART_CONFIG { 436 _UART_BAUDRATE_19200 = 0, 437 _UART_BAUDRATE_9600 = 1, 438 _UART_BAUDRATE_4800 = 2, 439 _UART_BAUDRATE_2400 = 3, 440 _UART_RX_ENABLE = 0x40, 441 _UART_TX_ENABLE = 0x80, 442 }; 443 444 struct FW_WRITE_UART { 445 struct FW_HEADER hdr; 446 u8 Data[252]; 447 } __attribute__ ((__packed__)); 448 449 450 struct ngene_command { 451 u32 in_len; 452 u32 out_len; 453 union { 454 u32 raw[64]; 455 u8 raw8[256]; 456 struct FW_HEADER hdr; 457 struct FW_I2C_WRITE I2CWrite; 458 struct FW_I2C_CONTINUE_WRITE I2CContinueWrite; 459 struct FW_I2C_READ I2CRead; 460 struct FW_STREAM_CONTROL StreamControl; 461 struct FW_FWLOAD_PREPARE FWLoadPrepare; 462 struct FW_FWLOAD_FINISH FWLoadFinish; 463 struct FW_MEM_READ MemoryRead; 464 struct FW_MEM_WRITE MemoryWrite; 465 struct FW_SFR_IRAM_READ SfrIramRead; 466 struct FW_SFR_IRAM_WRITE SfrIramWrite; 467 struct FW_SPI_WRITE SPIWrite; 468 struct FW_SPI_READ SPIRead; 469 struct FW_SET_GPIO_PIN SetGpioPin; 470 struct FW_SET_GPIO_INT SetGpioInt; 471 struct FW_SET_DEBUGMODE SetDebugMode; 472 struct FW_CONFIGURE_BUFFERS ConfigureBuffers; 473 struct FW_CONFIGURE_FREE_BUFFERS ConfigureFreeBuffers; 474 struct FW_CONFIGURE_UART ConfigureUart; 475 struct FW_WRITE_UART WriteUart; 476 } cmd; 477 } __attribute__ ((__packed__)); 478 479 #define NGENE_INTERFACE_VERSION 0x103 480 #define MAX_VIDEO_BUFFER_SIZE (417792) /* 288*1440 rounded up to next page */ 481 #define MAX_AUDIO_BUFFER_SIZE (8192) /* Gives room for about 23msec@48KHz */ 482 #define MAX_VBI_BUFFER_SIZE (28672) /* 1144*18 rounded up to next page */ 483 #define MAX_TS_BUFFER_SIZE (98304) /* 512*188 rounded up to next page */ 484 #define MAX_HDTV_BUFFER_SIZE (2080768) /* 541*1920*2 rounded up to next page 485 Max: (1920x1080i60) */ 486 487 #define OVERFLOW_BUFFER_SIZE (8192) 488 489 #define RING_SIZE_VIDEO 4 490 #define RING_SIZE_AUDIO 8 491 #define RING_SIZE_TS 8 492 493 #define NUM_SCATTER_GATHER_ENTRIES 8 494 495 #define MAX_DMA_LENGTH (((MAX_VIDEO_BUFFER_SIZE + MAX_VBI_BUFFER_SIZE) * \ 496 RING_SIZE_VIDEO * 2) + \ 497 (MAX_AUDIO_BUFFER_SIZE * RING_SIZE_AUDIO * 2) + \ 498 (MAX_TS_BUFFER_SIZE * RING_SIZE_TS * 4) + \ 499 (RING_SIZE_VIDEO * PAGE_SIZE * 2) + \ 500 (RING_SIZE_AUDIO * PAGE_SIZE * 2) + \ 501 (RING_SIZE_TS * PAGE_SIZE * 4) + \ 502 8 * PAGE_SIZE + OVERFLOW_BUFFER_SIZE + PAGE_SIZE) 503 504 #define EVENT_QUEUE_SIZE 16 505 506 /* Gathers the current state of a single channel. */ 507 508 struct SBufferHeader { 509 struct BUFFER_HEADER ngeneBuffer; /* Physical descriptor */ 510 struct SBufferHeader *Next; 511 void *Buffer1; 512 struct HW_SCATTER_GATHER_ELEMENT *scList1; 513 void *Buffer2; 514 struct HW_SCATTER_GATHER_ELEMENT *scList2; 515 }; 516 517 /* Sizeof SBufferHeader aligned to next 64 Bit boundary (hw restriction) */ 518 #define SIZEOF_SBufferHeader ((sizeof(struct SBufferHeader) + 63) & ~63) 519 520 enum HWSTATE { 521 HWSTATE_STOP, 522 HWSTATE_STARTUP, 523 HWSTATE_RUN, 524 HWSTATE_PAUSE, 525 }; 526 527 enum KSSTATE { 528 KSSTATE_STOP, 529 KSSTATE_ACQUIRE, 530 KSSTATE_PAUSE, 531 KSSTATE_RUN, 532 }; 533 534 struct SRingBufferDescriptor { 535 struct SBufferHeader *Head; /* Points to first buffer in ring buffer 536 structure*/ 537 u64 PAHead; /* Physical address of first buffer */ 538 u32 MemSize; /* Memory size of allocated ring buffers 539 (needed for freeing) */ 540 u32 NumBuffers; /* Number of buffers in the ring */ 541 u32 Buffer1Length; /* Allocated length of Buffer 1 */ 542 u32 Buffer2Length; /* Allocated length of Buffer 2 */ 543 void *SCListMem; /* Memory to hold scatter gather lists for this 544 ring */ 545 u64 PASCListMem; /* Physical address .. */ 546 u32 SCListMemSize; /* Size of this memory */ 547 }; 548 549 enum STREAMMODEFLAGS { 550 StreamMode_NONE = 0, /* Stream not used */ 551 StreamMode_ANALOG = 1, /* Analog: Stream 0,1 = Video, 2,3 = Audio */ 552 StreamMode_TSIN = 2, /* Transport stream input (all) */ 553 StreamMode_HDTV = 4, /* HDTV: Maximum 1920x1080p30,1920x1080i60 554 (only stream 0) */ 555 StreamMode_TSOUT = 8, /* Transport stream output (only stream 3) */ 556 }; 557 558 559 enum BufferExchangeFlags { 560 BEF_EVEN_FIELD = 0x00000001, 561 BEF_CONTINUATION = 0x00000002, 562 BEF_MORE_DATA = 0x00000004, 563 BEF_OVERFLOW = 0x00000008, 564 DF_SWAP32 = 0x00010000, 565 }; 566 567 typedef void *(IBufferExchange)(void *, void *, u32, u32, u32); 568 569 struct MICI_STREAMINFO { 570 IBufferExchange *pExchange; 571 IBufferExchange *pExchangeVBI; /* Secondary (VBI, ancillary) */ 572 u8 Stream; 573 u8 Flags; 574 u8 Mode; 575 u8 Reserved; 576 u16 nLinesVideo; 577 u16 nBytesPerLineVideo; 578 u16 nLinesVBI; 579 u16 nBytesPerLineVBI; 580 u32 CaptureLength; /* Used for audio and transport stream */ 581 }; 582 583 /****************************************************************************/ 584 /* STRUCTS ******************************************************************/ 585 /****************************************************************************/ 586 587 /* sound hardware definition */ 588 #define MIXER_ADDR_TVTUNER 0 589 #define MIXER_ADDR_LAST 0 590 591 struct ngene_channel; 592 593 /*struct sound chip*/ 594 595 struct mychip { 596 struct ngene_channel *chan; 597 struct snd_card *card; 598 struct pci_dev *pci; 599 struct snd_pcm_substream *substream; 600 struct snd_pcm *pcm; 601 unsigned long port; 602 int irq; 603 spinlock_t mixer_lock; 604 spinlock_t lock; 605 int mixer_volume[MIXER_ADDR_LAST + 1][2]; 606 int capture_source[MIXER_ADDR_LAST + 1][2]; 607 }; 608 609 #ifdef NGENE_V4L 610 struct ngene_overlay { 611 int tvnorm; 612 struct v4l2_rect w; 613 enum v4l2_field field; 614 struct v4l2_clip *clips; 615 int nclips; 616 int setup_ok; 617 }; 618 619 struct ngene_tvnorm { 620 int v4l2_id; 621 char *name; 622 u16 swidth, sheight; /* scaled standard width, height */ 623 int tuner_norm; 624 int soundstd; 625 }; 626 627 struct ngene_vopen { 628 struct ngene_channel *ch; 629 enum v4l2_priority prio; 630 int width; 631 int height; 632 int depth; 633 struct videobuf_queue vbuf_q; 634 struct videobuf_queue vbi; 635 int fourcc; 636 int picxcount; 637 int resources; 638 enum v4l2_buf_type type; 639 const struct ngene_format *fmt; 640 641 const struct ngene_format *ovfmt; 642 struct ngene_overlay ov; 643 }; 644 #endif 645 646 struct ngene_channel { 647 struct device device; 648 struct i2c_adapter i2c_adapter; 649 struct i2c_client *i2c_client[1]; 650 int i2c_client_fe; 651 652 struct ngene *dev; 653 int number; 654 int type; 655 int mode; 656 bool has_adapter; 657 bool has_demux; 658 int demod_type; 659 int (*gate_ctrl)(struct dvb_frontend *, int); 660 661 struct dvb_frontend *fe; 662 struct dvb_frontend *fe2; 663 struct dmxdev dmxdev; 664 struct dvb_demux demux; 665 struct dvb_net dvbnet; 666 struct dmx_frontend hw_frontend; 667 struct dmx_frontend mem_frontend; 668 int users; 669 struct video_device *v4l_dev; 670 struct dvb_device *ci_dev; 671 struct tasklet_struct demux_tasklet; 672 673 struct SBufferHeader *nextBuffer; 674 enum KSSTATE State; 675 enum HWSTATE HWState; 676 u8 Stream; 677 u8 Flags; 678 u8 Mode; 679 IBufferExchange *pBufferExchange; 680 IBufferExchange *pBufferExchange2; 681 682 spinlock_t state_lock; 683 u16 nLines; 684 u16 nBytesPerLine; 685 u16 nVBILines; 686 u16 nBytesPerVBILine; 687 u16 itumode; 688 u32 Capture1Length; 689 u32 Capture2Length; 690 struct SRingBufferDescriptor RingBuffer; 691 struct SRingBufferDescriptor TSRingBuffer; 692 struct SRingBufferDescriptor TSIdleBuffer; 693 694 u32 DataFormatFlags; 695 696 int AudioDTOUpdated; 697 u32 AudioDTOValue; 698 699 int (*set_tone)(struct dvb_frontend *, enum fe_sec_tone_mode); 700 u8 lnbh; 701 702 /* stuff from analog driver */ 703 704 int minor; 705 struct mychip *mychip; 706 struct snd_card *soundcard; 707 u8 *evenbuffer; 708 u8 dma_on; 709 int soundstreamon; 710 int audiomute; 711 int soundbuffisallocated; 712 int sndbuffflag; 713 int tun_rdy; 714 int dec_rdy; 715 int tun_dec_rdy; 716 int lastbufferflag; 717 718 struct ngene_tvnorm *tvnorms; 719 int tvnorm_num; 720 int tvnorm; 721 722 #ifdef NGENE_V4L 723 int videousers; 724 struct v4l2_prio_state prio; 725 struct ngene_vopen init; 726 int resources; 727 struct v4l2_framebuffer fbuf; 728 struct ngene_buffer *screen; /* overlay */ 729 struct list_head capture; /* video capture queue */ 730 spinlock_t s_lock; 731 struct semaphore reslock; 732 #endif 733 734 int running; 735 736 int tsin_offset; 737 u8 tsin_buffer[188]; 738 }; 739 740 741 struct ngene_ci { 742 struct device device; 743 struct i2c_adapter i2c_adapter; 744 745 struct ngene *dev; 746 struct dvb_ca_en50221 *en; 747 }; 748 749 struct ngene; 750 751 typedef void (rx_cb_t)(struct ngene *, u32, u8); 752 typedef void (tx_cb_t)(struct ngene *, u32); 753 754 struct ngene { 755 int nr; 756 struct pci_dev *pci_dev; 757 unsigned char __iomem *iomem; 758 759 /*struct i2c_adapter i2c_adapter;*/ 760 761 u32 device_version; 762 u32 fw_interface_version; 763 u32 icounts; 764 bool msi_enabled; 765 bool cmd_timeout_workaround; 766 767 u8 *CmdDoneByte; 768 int BootFirmware; 769 void *OverflowBuffer; 770 dma_addr_t PAOverflowBuffer; 771 void *FWInterfaceBuffer; 772 dma_addr_t PAFWInterfaceBuffer; 773 u8 *ngenetohost; 774 u8 *hosttongene; 775 776 struct EVENT_BUFFER EventQueue[EVENT_QUEUE_SIZE]; 777 int EventQueueOverflowCount; 778 int EventQueueOverflowFlag; 779 struct tasklet_struct event_tasklet; 780 struct EVENT_BUFFER *EventBuffer; 781 int EventQueueWriteIndex; 782 int EventQueueReadIndex; 783 784 wait_queue_head_t cmd_wq; 785 int cmd_done; 786 struct mutex cmd_mutex; 787 struct mutex stream_mutex; 788 struct semaphore pll_mutex; 789 struct mutex i2c_switch_mutex; 790 int i2c_current_channel; 791 int i2c_current_bus; 792 spinlock_t cmd_lock; 793 794 struct dvb_adapter adapter[MAX_STREAM]; 795 struct dvb_adapter *first_adapter; /* "one_adapter" modprobe opt */ 796 struct ngene_channel channel[MAX_STREAM]; 797 798 struct ngene_info *card_info; 799 800 tx_cb_t *TxEventNotify; 801 rx_cb_t *RxEventNotify; 802 int tx_busy; 803 wait_queue_head_t tx_wq; 804 wait_queue_head_t rx_wq; 805 #define UART_RBUF_LEN 4096 806 u8 uart_rbuf[UART_RBUF_LEN]; 807 int uart_rp, uart_wp; 808 809 #define TS_FILLER 0x6f 810 811 u8 *tsout_buf; 812 #define TSOUT_BUF_SIZE (512*188*8) 813 struct dvb_ringbuffer tsout_rbuf; 814 815 u8 *tsin_buf; 816 #define TSIN_BUF_SIZE (512*188*8) 817 struct dvb_ringbuffer tsin_rbuf; 818 819 u8 *ain_buf; 820 #define AIN_BUF_SIZE (128*1024) 821 struct dvb_ringbuffer ain_rbuf; 822 823 824 u8 *vin_buf; 825 #define VIN_BUF_SIZE (4*1920*1080) 826 struct dvb_ringbuffer vin_rbuf; 827 828 unsigned long exp_val; 829 int prev_cmd; 830 831 struct ngene_ci ci; 832 }; 833 834 struct ngene_info { 835 int type; 836 #define NGENE_APP 0 837 #define NGENE_TERRATEC 1 838 #define NGENE_SIDEWINDER 2 839 #define NGENE_RACER 3 840 #define NGENE_VIPER 4 841 #define NGENE_PYTHON 5 842 #define NGENE_VBOX_V1 6 843 #define NGENE_VBOX_V2 7 844 845 int fw_version; 846 bool msi_supported; 847 char *name; 848 849 int io_type[MAX_STREAM]; 850 #define NGENE_IO_NONE 0 851 #define NGENE_IO_TV 1 852 #define NGENE_IO_HDTV 2 853 #define NGENE_IO_TSIN 4 854 #define NGENE_IO_TSOUT 8 855 #define NGENE_IO_AIN 16 856 857 void *fe_config[4]; 858 void *tuner_config[4]; 859 860 int (*demod_attach[4])(struct ngene_channel *); 861 int (*tuner_attach[4])(struct ngene_channel *); 862 863 u8 avf[4]; 864 u8 msp[4]; 865 u8 demoda[4]; 866 u8 lnb[4]; 867 int i2c_access; 868 u8 ntsc; 869 u8 tsf[4]; 870 u8 i2s[4]; 871 872 int (*gate_ctrl)(struct dvb_frontend *, int); 873 int (*switch_ctrl)(struct ngene_channel *, int, int); 874 }; 875 876 #ifdef NGENE_V4L 877 struct ngene_format { 878 char *name; 879 int fourcc; /* video4linux 2 */ 880 int btformat; /* BT848_COLOR_FMT_* */ 881 int format; 882 int btswap; /* BT848_COLOR_CTL_* */ 883 int depth; /* bit/pixel */ 884 int flags; 885 int hshift, vshift; /* for planar modes */ 886 int palette; 887 }; 888 889 #define RESOURCE_OVERLAY 1 890 #define RESOURCE_VIDEO 2 891 #define RESOURCE_VBI 4 892 893 struct ngene_buffer { 894 /* common v4l buffer stuff -- must be first */ 895 struct videobuf_buffer vb; 896 897 /* ngene specific */ 898 const struct ngene_format *fmt; 899 int tvnorm; 900 int btformat; 901 int btswap; 902 }; 903 #endif 904 905 906 /* Provided by ngene-core.c */ 907 int ngene_probe(struct pci_dev *pci_dev, const struct pci_device_id *id); 908 void ngene_remove(struct pci_dev *pdev); 909 void ngene_shutdown(struct pci_dev *pdev); 910 int ngene_command(struct ngene *dev, struct ngene_command *com); 911 int ngene_command_gpio_set(struct ngene *dev, u8 select, u8 level); 912 void set_transfer(struct ngene_channel *chan, int state); 913 void FillTSBuffer(void *Buffer, int Length, u32 Flags); 914 915 /* Provided by ngene-cards.c */ 916 int ngene_port_has_cxd2099(struct i2c_adapter *i2c, u8 *type); 917 918 /* Provided by ngene-i2c.c */ 919 int ngene_i2c_init(struct ngene *dev, int dev_nr); 920 921 /* Provided by ngene-dvb.c */ 922 extern struct dvb_device ngene_dvbdev_ci; 923 void *tsout_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags); 924 void *tsin_exchange(void *priv, void *buf, u32 len, u32 clock, u32 flags); 925 int ngene_start_feed(struct dvb_demux_feed *dvbdmxfeed); 926 int ngene_stop_feed(struct dvb_demux_feed *dvbdmxfeed); 927 int my_dvb_dmx_ts_card_init(struct dvb_demux *dvbdemux, char *id, 928 int (*start_feed)(struct dvb_demux_feed *), 929 int (*stop_feed)(struct dvb_demux_feed *), 930 void *priv); 931 int my_dvb_dmxdev_ts_card_init(struct dmxdev *dmxdev, 932 struct dvb_demux *dvbdemux, 933 struct dmx_frontend *hw_frontend, 934 struct dmx_frontend *mem_frontend, 935 struct dvb_adapter *dvb_adapter); 936 937 #endif 938 939 /* LocalWords: Endif 940 */ 941
