1 /* This file is part of the Emulex RoCE Device Driver for
2 * RoCE (RDMA over Converged Ethernet) adapters.
3 * Copyright (C) 2012-2015 Emulex. All rights reserved.
4 * EMULEX and SLI are trademarks of Emulex.
5 * www.emulex.com
6 *
7 * This software is available to you under a choice of one of two licenses.
8 * You may choose to be licensed under the terms of the GNU General Public
9 * License (GPL) Version 2, available from the file COPYING in the main
10 * directory of this source tree, or the BSD license below:
11 *
12 * Redistribution and use in source and binary forms, with or without
13 * modification, are permitted provided that the following conditions
14 * are met:
15 *
16 * - Redistributions of source code must retain the above copyright notice,
17 * this list of conditions and the following disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in
21 * the documentation and/or other materials provided with the distribution.
22 *
23 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
24 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,THE
25 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
26 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
27 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
30 * BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
31 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
32 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
33 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 * Contact Information:
36 * linux-drivers@emulex.com
37 *
38 * Emulex
39 * 3333 Susan Street
40 * Costa Mesa, CA 92626
41 */
42
43 #include <linux/sched.h>
44 #include <linux/interrupt.h>
45 #include <linux/log2.h>
46 #include <linux/dma-mapping.h>
47 #include <linux/if_ether.h>
48
49 #include <rdma/ib_verbs.h>
50 #include <rdma/ib_user_verbs.h>
51 #include <rdma/ib_cache.h>
52
53 #include "ocrdma.h"
54 #include "ocrdma_hw.h"
55 #include "ocrdma_verbs.h"
56 #include "ocrdma_ah.h"
57
58 enum mbx_status {
59 OCRDMA_MBX_STATUS_FAILED = 1,
60 OCRDMA_MBX_STATUS_ILLEGAL_FIELD = 3,
61 OCRDMA_MBX_STATUS_OOR = 100,
62 OCRDMA_MBX_STATUS_INVALID_PD = 101,
63 OCRDMA_MBX_STATUS_PD_INUSE = 102,
64 OCRDMA_MBX_STATUS_INVALID_CQ = 103,
65 OCRDMA_MBX_STATUS_INVALID_QP = 104,
66 OCRDMA_MBX_STATUS_INVALID_LKEY = 105,
67 OCRDMA_MBX_STATUS_ORD_EXCEEDS = 106,
68 OCRDMA_MBX_STATUS_IRD_EXCEEDS = 107,
69 OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS = 108,
70 OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS = 109,
71 OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS = 110,
72 OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS = 111,
73 OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS = 112,
74 OCRDMA_MBX_STATUS_INVALID_STATE_CHANGE = 113,
75 OCRDMA_MBX_STATUS_MW_BOUND = 114,
76 OCRDMA_MBX_STATUS_INVALID_VA = 115,
77 OCRDMA_MBX_STATUS_INVALID_LENGTH = 116,
78 OCRDMA_MBX_STATUS_INVALID_FBO = 117,
79 OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS = 118,
80 OCRDMA_MBX_STATUS_INVALID_PBE_SIZE = 119,
81 OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY = 120,
82 OCRDMA_MBX_STATUS_INVALID_PBL_SHIFT = 121,
83 OCRDMA_MBX_STATUS_INVALID_SRQ_ID = 129,
84 OCRDMA_MBX_STATUS_SRQ_ERROR = 133,
85 OCRDMA_MBX_STATUS_RQE_EXCEEDS = 134,
86 OCRDMA_MBX_STATUS_MTU_EXCEEDS = 135,
87 OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS = 136,
88 OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS = 137,
89 OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS = 138,
90 OCRDMA_MBX_STATUS_QP_BOUND = 130,
91 OCRDMA_MBX_STATUS_INVALID_CHANGE = 139,
92 OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP = 140,
93 OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER = 141,
94 OCRDMA_MBX_STATUS_MW_STILL_BOUND = 142,
95 OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID = 143,
96 OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS = 144
97 };
98
99 enum additional_status {
100 OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES = 22
101 };
102
103 enum cqe_status {
104 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES = 1,
105 OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER = 2,
106 OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES = 3,
107 OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING = 4,
108 OCRDMA_MBX_CQE_STATUS_DMA_FAILED = 5
109 };
110
ocrdma_get_eqe(struct ocrdma_eq * eq)111 static inline void *ocrdma_get_eqe(struct ocrdma_eq *eq)
112 {
113 return eq->q.va + (eq->q.tail * sizeof(struct ocrdma_eqe));
114 }
115
ocrdma_eq_inc_tail(struct ocrdma_eq * eq)116 static inline void ocrdma_eq_inc_tail(struct ocrdma_eq *eq)
117 {
118 eq->q.tail = (eq->q.tail + 1) & (OCRDMA_EQ_LEN - 1);
119 }
120
ocrdma_get_mcqe(struct ocrdma_dev * dev)121 static inline void *ocrdma_get_mcqe(struct ocrdma_dev *dev)
122 {
123 struct ocrdma_mcqe *cqe = (struct ocrdma_mcqe *)
124 (dev->mq.cq.va + (dev->mq.cq.tail * sizeof(struct ocrdma_mcqe)));
125
126 if (!(le32_to_cpu(cqe->valid_ae_cmpl_cons) & OCRDMA_MCQE_VALID_MASK))
127 return NULL;
128 return cqe;
129 }
130
ocrdma_mcq_inc_tail(struct ocrdma_dev * dev)131 static inline void ocrdma_mcq_inc_tail(struct ocrdma_dev *dev)
132 {
133 dev->mq.cq.tail = (dev->mq.cq.tail + 1) & (OCRDMA_MQ_CQ_LEN - 1);
134 }
135
ocrdma_get_mqe(struct ocrdma_dev * dev)136 static inline struct ocrdma_mqe *ocrdma_get_mqe(struct ocrdma_dev *dev)
137 {
138 return dev->mq.sq.va + (dev->mq.sq.head * sizeof(struct ocrdma_mqe));
139 }
140
ocrdma_mq_inc_head(struct ocrdma_dev * dev)141 static inline void ocrdma_mq_inc_head(struct ocrdma_dev *dev)
142 {
143 dev->mq.sq.head = (dev->mq.sq.head + 1) & (OCRDMA_MQ_LEN - 1);
144 }
145
ocrdma_get_mqe_rsp(struct ocrdma_dev * dev)146 static inline void *ocrdma_get_mqe_rsp(struct ocrdma_dev *dev)
147 {
148 return dev->mq.sq.va + (dev->mqe_ctx.tag * sizeof(struct ocrdma_mqe));
149 }
150
get_ibqp_state(enum ocrdma_qp_state qps)151 enum ib_qp_state get_ibqp_state(enum ocrdma_qp_state qps)
152 {
153 switch (qps) {
154 case OCRDMA_QPS_RST:
155 return IB_QPS_RESET;
156 case OCRDMA_QPS_INIT:
157 return IB_QPS_INIT;
158 case OCRDMA_QPS_RTR:
159 return IB_QPS_RTR;
160 case OCRDMA_QPS_RTS:
161 return IB_QPS_RTS;
162 case OCRDMA_QPS_SQD:
163 case OCRDMA_QPS_SQ_DRAINING:
164 return IB_QPS_SQD;
165 case OCRDMA_QPS_SQE:
166 return IB_QPS_SQE;
167 case OCRDMA_QPS_ERR:
168 return IB_QPS_ERR;
169 }
170 return IB_QPS_ERR;
171 }
172
get_ocrdma_qp_state(enum ib_qp_state qps)173 static enum ocrdma_qp_state get_ocrdma_qp_state(enum ib_qp_state qps)
174 {
175 switch (qps) {
176 case IB_QPS_RESET:
177 return OCRDMA_QPS_RST;
178 case IB_QPS_INIT:
179 return OCRDMA_QPS_INIT;
180 case IB_QPS_RTR:
181 return OCRDMA_QPS_RTR;
182 case IB_QPS_RTS:
183 return OCRDMA_QPS_RTS;
184 case IB_QPS_SQD:
185 return OCRDMA_QPS_SQD;
186 case IB_QPS_SQE:
187 return OCRDMA_QPS_SQE;
188 case IB_QPS_ERR:
189 return OCRDMA_QPS_ERR;
190 }
191 return OCRDMA_QPS_ERR;
192 }
193
ocrdma_get_mbx_errno(u32 status)194 static int ocrdma_get_mbx_errno(u32 status)
195 {
196 int err_num;
197 u8 mbox_status = (status & OCRDMA_MBX_RSP_STATUS_MASK) >>
198 OCRDMA_MBX_RSP_STATUS_SHIFT;
199 u8 add_status = (status & OCRDMA_MBX_RSP_ASTATUS_MASK) >>
200 OCRDMA_MBX_RSP_ASTATUS_SHIFT;
201
202 switch (mbox_status) {
203 case OCRDMA_MBX_STATUS_OOR:
204 case OCRDMA_MBX_STATUS_MAX_QP_EXCEEDS:
205 err_num = -EAGAIN;
206 break;
207
208 case OCRDMA_MBX_STATUS_INVALID_PD:
209 case OCRDMA_MBX_STATUS_INVALID_CQ:
210 case OCRDMA_MBX_STATUS_INVALID_SRQ_ID:
211 case OCRDMA_MBX_STATUS_INVALID_QP:
212 case OCRDMA_MBX_STATUS_INVALID_CHANGE:
213 case OCRDMA_MBX_STATUS_MTU_EXCEEDS:
214 case OCRDMA_MBX_STATUS_INVALID_RNR_NAK_TIMER:
215 case OCRDMA_MBX_STATUS_PKEY_INDEX_INVALID:
216 case OCRDMA_MBX_STATUS_PKEY_INDEX_EXCEEDS:
217 case OCRDMA_MBX_STATUS_ILLEGAL_FIELD:
218 case OCRDMA_MBX_STATUS_INVALID_PBL_ENTRY:
219 case OCRDMA_MBX_STATUS_INVALID_LKEY:
220 case OCRDMA_MBX_STATUS_INVALID_VA:
221 case OCRDMA_MBX_STATUS_INVALID_LENGTH:
222 case OCRDMA_MBX_STATUS_INVALID_FBO:
223 case OCRDMA_MBX_STATUS_INVALID_ACC_RIGHTS:
224 case OCRDMA_MBX_STATUS_INVALID_PBE_SIZE:
225 case OCRDMA_MBX_STATUS_ATOMIC_OPS_UNSUP:
226 case OCRDMA_MBX_STATUS_SRQ_ERROR:
227 case OCRDMA_MBX_STATUS_SRQ_SIZE_UNDERUNS:
228 err_num = -EINVAL;
229 break;
230
231 case OCRDMA_MBX_STATUS_PD_INUSE:
232 case OCRDMA_MBX_STATUS_QP_BOUND:
233 case OCRDMA_MBX_STATUS_MW_STILL_BOUND:
234 case OCRDMA_MBX_STATUS_MW_BOUND:
235 err_num = -EBUSY;
236 break;
237
238 case OCRDMA_MBX_STATUS_RECVQ_RQE_EXCEEDS:
239 case OCRDMA_MBX_STATUS_SGE_RECV_EXCEEDS:
240 case OCRDMA_MBX_STATUS_RQE_EXCEEDS:
241 case OCRDMA_MBX_STATUS_SRQ_LIMIT_EXCEEDS:
242 case OCRDMA_MBX_STATUS_ORD_EXCEEDS:
243 case OCRDMA_MBX_STATUS_IRD_EXCEEDS:
244 case OCRDMA_MBX_STATUS_SENDQ_WQE_EXCEEDS:
245 case OCRDMA_MBX_STATUS_SGE_SEND_EXCEEDS:
246 case OCRDMA_MBX_STATUS_SGE_WRITE_EXCEEDS:
247 err_num = -ENOBUFS;
248 break;
249
250 case OCRDMA_MBX_STATUS_FAILED:
251 switch (add_status) {
252 case OCRDMA_MBX_ADDI_STATUS_INSUFFICIENT_RESOURCES:
253 err_num = -EAGAIN;
254 break;
255 default:
256 err_num = -EFAULT;
257 }
258 break;
259 default:
260 err_num = -EFAULT;
261 }
262 return err_num;
263 }
264
port_speed_string(struct ocrdma_dev * dev)265 char *port_speed_string(struct ocrdma_dev *dev)
266 {
267 char *str = "";
268 u16 speeds_supported;
269
270 speeds_supported = dev->phy.fixed_speeds_supported |
271 dev->phy.auto_speeds_supported;
272 if (speeds_supported & OCRDMA_PHY_SPEED_40GBPS)
273 str = "40Gbps ";
274 else if (speeds_supported & OCRDMA_PHY_SPEED_10GBPS)
275 str = "10Gbps ";
276 else if (speeds_supported & OCRDMA_PHY_SPEED_1GBPS)
277 str = "1Gbps ";
278
279 return str;
280 }
281
ocrdma_get_mbx_cqe_errno(u16 cqe_status)282 static int ocrdma_get_mbx_cqe_errno(u16 cqe_status)
283 {
284 int err_num = -EINVAL;
285
286 switch (cqe_status) {
287 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_PRIVILEDGES:
288 err_num = -EPERM;
289 break;
290 case OCRDMA_MBX_CQE_STATUS_INVALID_PARAMETER:
291 err_num = -EINVAL;
292 break;
293 case OCRDMA_MBX_CQE_STATUS_INSUFFICIENT_RESOURCES:
294 case OCRDMA_MBX_CQE_STATUS_QUEUE_FLUSHING:
295 err_num = -EINVAL;
296 break;
297 case OCRDMA_MBX_CQE_STATUS_DMA_FAILED:
298 default:
299 err_num = -EINVAL;
300 break;
301 }
302 return err_num;
303 }
304
ocrdma_ring_cq_db(struct ocrdma_dev * dev,u16 cq_id,bool armed,bool solicited,u16 cqe_popped)305 void ocrdma_ring_cq_db(struct ocrdma_dev *dev, u16 cq_id, bool armed,
306 bool solicited, u16 cqe_popped)
307 {
308 u32 val = cq_id & OCRDMA_DB_CQ_RING_ID_MASK;
309
310 val |= ((cq_id & OCRDMA_DB_CQ_RING_ID_EXT_MASK) <<
311 OCRDMA_DB_CQ_RING_ID_EXT_MASK_SHIFT);
312
313 if (armed)
314 val |= (1 << OCRDMA_DB_CQ_REARM_SHIFT);
315 if (solicited)
316 val |= (1 << OCRDMA_DB_CQ_SOLICIT_SHIFT);
317 val |= (cqe_popped << OCRDMA_DB_CQ_NUM_POPPED_SHIFT);
318 iowrite32(val, dev->nic_info.db + OCRDMA_DB_CQ_OFFSET);
319 }
320
ocrdma_ring_mq_db(struct ocrdma_dev * dev)321 static void ocrdma_ring_mq_db(struct ocrdma_dev *dev)
322 {
323 u32 val = 0;
324
325 val |= dev->mq.sq.id & OCRDMA_MQ_ID_MASK;
326 val |= 1 << OCRDMA_MQ_NUM_MQE_SHIFT;
327 iowrite32(val, dev->nic_info.db + OCRDMA_DB_MQ_OFFSET);
328 }
329
ocrdma_ring_eq_db(struct ocrdma_dev * dev,u16 eq_id,bool arm,bool clear_int,u16 num_eqe)330 static void ocrdma_ring_eq_db(struct ocrdma_dev *dev, u16 eq_id,
331 bool arm, bool clear_int, u16 num_eqe)
332 {
333 u32 val = 0;
334
335 val |= eq_id & OCRDMA_EQ_ID_MASK;
336 val |= ((eq_id & OCRDMA_EQ_ID_EXT_MASK) << OCRDMA_EQ_ID_EXT_MASK_SHIFT);
337 if (arm)
338 val |= (1 << OCRDMA_REARM_SHIFT);
339 if (clear_int)
340 val |= (1 << OCRDMA_EQ_CLR_SHIFT);
341 val |= (1 << OCRDMA_EQ_TYPE_SHIFT);
342 val |= (num_eqe << OCRDMA_NUM_EQE_SHIFT);
343 iowrite32(val, dev->nic_info.db + OCRDMA_DB_EQ_OFFSET);
344 }
345
ocrdma_init_mch(struct ocrdma_mbx_hdr * cmd_hdr,u8 opcode,u8 subsys,u32 cmd_len)346 static void ocrdma_init_mch(struct ocrdma_mbx_hdr *cmd_hdr,
347 u8 opcode, u8 subsys, u32 cmd_len)
348 {
349 cmd_hdr->subsys_op = (opcode | (subsys << OCRDMA_MCH_SUBSYS_SHIFT));
350 cmd_hdr->timeout = 20; /* seconds */
351 cmd_hdr->cmd_len = cmd_len - sizeof(struct ocrdma_mbx_hdr);
352 }
353
ocrdma_init_emb_mqe(u8 opcode,u32 cmd_len)354 static void *ocrdma_init_emb_mqe(u8 opcode, u32 cmd_len)
355 {
356 struct ocrdma_mqe *mqe;
357
358 mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
359 if (!mqe)
360 return NULL;
361 mqe->hdr.spcl_sge_cnt_emb |=
362 (OCRDMA_MQE_EMBEDDED << OCRDMA_MQE_HDR_EMB_SHIFT) &
363 OCRDMA_MQE_HDR_EMB_MASK;
364 mqe->hdr.pyld_len = cmd_len - sizeof(struct ocrdma_mqe_hdr);
365
366 ocrdma_init_mch(&mqe->u.emb_req.mch, opcode, OCRDMA_SUBSYS_ROCE,
367 mqe->hdr.pyld_len);
368 return mqe;
369 }
370
ocrdma_free_q(struct ocrdma_dev * dev,struct ocrdma_queue_info * q)371 static void ocrdma_free_q(struct ocrdma_dev *dev, struct ocrdma_queue_info *q)
372 {
373 dma_free_coherent(&dev->nic_info.pdev->dev, q->size, q->va, q->dma);
374 }
375
ocrdma_alloc_q(struct ocrdma_dev * dev,struct ocrdma_queue_info * q,u16 len,u16 entry_size)376 static int ocrdma_alloc_q(struct ocrdma_dev *dev,
377 struct ocrdma_queue_info *q, u16 len, u16 entry_size)
378 {
379 memset(q, 0, sizeof(*q));
380 q->len = len;
381 q->entry_size = entry_size;
382 q->size = len * entry_size;
383 q->va = dma_zalloc_coherent(&dev->nic_info.pdev->dev, q->size,
384 &q->dma, GFP_KERNEL);
385 if (!q->va)
386 return -ENOMEM;
387 return 0;
388 }
389
ocrdma_build_q_pages(struct ocrdma_pa * q_pa,int cnt,dma_addr_t host_pa,int hw_page_size)390 static void ocrdma_build_q_pages(struct ocrdma_pa *q_pa, int cnt,
391 dma_addr_t host_pa, int hw_page_size)
392 {
393 int i;
394
395 for (i = 0; i < cnt; i++) {
396 q_pa[i].lo = (u32) (host_pa & 0xffffffff);
397 q_pa[i].hi = (u32) upper_32_bits(host_pa);
398 host_pa += hw_page_size;
399 }
400 }
401
ocrdma_mbx_delete_q(struct ocrdma_dev * dev,struct ocrdma_queue_info * q,int queue_type)402 static int ocrdma_mbx_delete_q(struct ocrdma_dev *dev,
403 struct ocrdma_queue_info *q, int queue_type)
404 {
405 u8 opcode = 0;
406 int status;
407 struct ocrdma_delete_q_req *cmd = dev->mbx_cmd;
408
409 switch (queue_type) {
410 case QTYPE_MCCQ:
411 opcode = OCRDMA_CMD_DELETE_MQ;
412 break;
413 case QTYPE_CQ:
414 opcode = OCRDMA_CMD_DELETE_CQ;
415 break;
416 case QTYPE_EQ:
417 opcode = OCRDMA_CMD_DELETE_EQ;
418 break;
419 default:
420 BUG();
421 }
422 memset(cmd, 0, sizeof(*cmd));
423 ocrdma_init_mch(&cmd->req, opcode, OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
424 cmd->id = q->id;
425
426 status = be_roce_mcc_cmd(dev->nic_info.netdev,
427 cmd, sizeof(*cmd), NULL, NULL);
428 if (!status)
429 q->created = false;
430 return status;
431 }
432
ocrdma_mbx_create_eq(struct ocrdma_dev * dev,struct ocrdma_eq * eq)433 static int ocrdma_mbx_create_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
434 {
435 int status;
436 struct ocrdma_create_eq_req *cmd = dev->mbx_cmd;
437 struct ocrdma_create_eq_rsp *rsp = dev->mbx_cmd;
438
439 memset(cmd, 0, sizeof(*cmd));
440 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_EQ, OCRDMA_SUBSYS_COMMON,
441 sizeof(*cmd));
442
443 cmd->req.rsvd_version = 2;
444 cmd->num_pages = 4;
445 cmd->valid = OCRDMA_CREATE_EQ_VALID;
446 cmd->cnt = 4 << OCRDMA_CREATE_EQ_CNT_SHIFT;
447
448 ocrdma_build_q_pages(&cmd->pa[0], cmd->num_pages, eq->q.dma,
449 PAGE_SIZE_4K);
450 status = be_roce_mcc_cmd(dev->nic_info.netdev, cmd, sizeof(*cmd), NULL,
451 NULL);
452 if (!status) {
453 eq->q.id = rsp->vector_eqid & 0xffff;
454 eq->vector = (rsp->vector_eqid >> 16) & 0xffff;
455 eq->q.created = true;
456 }
457 return status;
458 }
459
ocrdma_create_eq(struct ocrdma_dev * dev,struct ocrdma_eq * eq,u16 q_len)460 static int ocrdma_create_eq(struct ocrdma_dev *dev,
461 struct ocrdma_eq *eq, u16 q_len)
462 {
463 int status;
464
465 status = ocrdma_alloc_q(dev, &eq->q, OCRDMA_EQ_LEN,
466 sizeof(struct ocrdma_eqe));
467 if (status)
468 return status;
469
470 status = ocrdma_mbx_create_eq(dev, eq);
471 if (status)
472 goto mbx_err;
473 eq->dev = dev;
474 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
475
476 return 0;
477 mbx_err:
478 ocrdma_free_q(dev, &eq->q);
479 return status;
480 }
481
ocrdma_get_irq(struct ocrdma_dev * dev,struct ocrdma_eq * eq)482 int ocrdma_get_irq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
483 {
484 int irq;
485
486 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX)
487 irq = dev->nic_info.pdev->irq;
488 else
489 irq = dev->nic_info.msix.vector_list[eq->vector];
490 return irq;
491 }
492
_ocrdma_destroy_eq(struct ocrdma_dev * dev,struct ocrdma_eq * eq)493 static void _ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
494 {
495 if (eq->q.created) {
496 ocrdma_mbx_delete_q(dev, &eq->q, QTYPE_EQ);
497 ocrdma_free_q(dev, &eq->q);
498 }
499 }
500
ocrdma_destroy_eq(struct ocrdma_dev * dev,struct ocrdma_eq * eq)501 static void ocrdma_destroy_eq(struct ocrdma_dev *dev, struct ocrdma_eq *eq)
502 {
503 int irq;
504
505 /* disarm EQ so that interrupts are not generated
506 * during freeing and EQ delete is in progress.
507 */
508 ocrdma_ring_eq_db(dev, eq->q.id, false, false, 0);
509
510 irq = ocrdma_get_irq(dev, eq);
511 free_irq(irq, eq);
512 _ocrdma_destroy_eq(dev, eq);
513 }
514
ocrdma_destroy_eqs(struct ocrdma_dev * dev)515 static void ocrdma_destroy_eqs(struct ocrdma_dev *dev)
516 {
517 int i;
518
519 for (i = 0; i < dev->eq_cnt; i++)
520 ocrdma_destroy_eq(dev, &dev->eq_tbl[i]);
521 }
522
ocrdma_mbx_mq_cq_create(struct ocrdma_dev * dev,struct ocrdma_queue_info * cq,struct ocrdma_queue_info * eq)523 static int ocrdma_mbx_mq_cq_create(struct ocrdma_dev *dev,
524 struct ocrdma_queue_info *cq,
525 struct ocrdma_queue_info *eq)
526 {
527 struct ocrdma_create_cq_cmd *cmd = dev->mbx_cmd;
528 struct ocrdma_create_cq_cmd_rsp *rsp = dev->mbx_cmd;
529 int status;
530
531 memset(cmd, 0, sizeof(*cmd));
532 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_CQ,
533 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
534
535 cmd->req.rsvd_version = OCRDMA_CREATE_CQ_VER2;
536 cmd->pgsz_pgcnt = (cq->size / OCRDMA_MIN_Q_PAGE_SIZE) <<
537 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
538 cmd->pgsz_pgcnt |= PAGES_4K_SPANNED(cq->va, cq->size);
539
540 cmd->ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
541 cmd->eqn = eq->id;
542 cmd->pdid_cqecnt = cq->size / sizeof(struct ocrdma_mcqe);
543
544 ocrdma_build_q_pages(&cmd->pa[0], cq->size / OCRDMA_MIN_Q_PAGE_SIZE,
545 cq->dma, PAGE_SIZE_4K);
546 status = be_roce_mcc_cmd(dev->nic_info.netdev,
547 cmd, sizeof(*cmd), NULL, NULL);
548 if (!status) {
549 cq->id = (u16) (rsp->cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
550 cq->created = true;
551 }
552 return status;
553 }
554
ocrdma_encoded_q_len(int q_len)555 static u32 ocrdma_encoded_q_len(int q_len)
556 {
557 u32 len_encoded = fls(q_len); /* log2(len) + 1 */
558
559 if (len_encoded == 16)
560 len_encoded = 0;
561 return len_encoded;
562 }
563
ocrdma_mbx_create_mq(struct ocrdma_dev * dev,struct ocrdma_queue_info * mq,struct ocrdma_queue_info * cq)564 static int ocrdma_mbx_create_mq(struct ocrdma_dev *dev,
565 struct ocrdma_queue_info *mq,
566 struct ocrdma_queue_info *cq)
567 {
568 int num_pages, status;
569 struct ocrdma_create_mq_req *cmd = dev->mbx_cmd;
570 struct ocrdma_create_mq_rsp *rsp = dev->mbx_cmd;
571 struct ocrdma_pa *pa;
572
573 memset(cmd, 0, sizeof(*cmd));
574 num_pages = PAGES_4K_SPANNED(mq->va, mq->size);
575
576 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_CREATE_MQ_EXT,
577 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
578 cmd->req.rsvd_version = 1;
579 cmd->cqid_pages = num_pages;
580 cmd->cqid_pages |= (cq->id << OCRDMA_CREATE_MQ_CQ_ID_SHIFT);
581 cmd->async_cqid_valid = OCRDMA_CREATE_MQ_ASYNC_CQ_VALID;
582
583 cmd->async_event_bitmap = BIT(OCRDMA_ASYNC_GRP5_EVE_CODE);
584 cmd->async_event_bitmap |= BIT(OCRDMA_ASYNC_RDMA_EVE_CODE);
585 /* Request link events on this MQ. */
586 cmd->async_event_bitmap |= BIT(OCRDMA_ASYNC_LINK_EVE_CODE);
587
588 cmd->async_cqid_ringsize = cq->id;
589 cmd->async_cqid_ringsize |= (ocrdma_encoded_q_len(mq->len) <<
590 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT);
591 cmd->valid = OCRDMA_CREATE_MQ_VALID;
592 pa = &cmd->pa[0];
593
594 ocrdma_build_q_pages(pa, num_pages, mq->dma, PAGE_SIZE_4K);
595 status = be_roce_mcc_cmd(dev->nic_info.netdev,
596 cmd, sizeof(*cmd), NULL, NULL);
597 if (!status) {
598 mq->id = rsp->id;
599 mq->created = true;
600 }
601 return status;
602 }
603
ocrdma_create_mq(struct ocrdma_dev * dev)604 static int ocrdma_create_mq(struct ocrdma_dev *dev)
605 {
606 int status;
607
608 /* Alloc completion queue for Mailbox queue */
609 status = ocrdma_alloc_q(dev, &dev->mq.cq, OCRDMA_MQ_CQ_LEN,
610 sizeof(struct ocrdma_mcqe));
611 if (status)
612 goto alloc_err;
613
614 dev->eq_tbl[0].cq_cnt++;
615 status = ocrdma_mbx_mq_cq_create(dev, &dev->mq.cq, &dev->eq_tbl[0].q);
616 if (status)
617 goto mbx_cq_free;
618
619 memset(&dev->mqe_ctx, 0, sizeof(dev->mqe_ctx));
620 init_waitqueue_head(&dev->mqe_ctx.cmd_wait);
621 mutex_init(&dev->mqe_ctx.lock);
622
623 /* Alloc Mailbox queue */
624 status = ocrdma_alloc_q(dev, &dev->mq.sq, OCRDMA_MQ_LEN,
625 sizeof(struct ocrdma_mqe));
626 if (status)
627 goto mbx_cq_destroy;
628 status = ocrdma_mbx_create_mq(dev, &dev->mq.sq, &dev->mq.cq);
629 if (status)
630 goto mbx_q_free;
631 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, 0);
632 return 0;
633
634 mbx_q_free:
635 ocrdma_free_q(dev, &dev->mq.sq);
636 mbx_cq_destroy:
637 ocrdma_mbx_delete_q(dev, &dev->mq.cq, QTYPE_CQ);
638 mbx_cq_free:
639 ocrdma_free_q(dev, &dev->mq.cq);
640 alloc_err:
641 return status;
642 }
643
ocrdma_destroy_mq(struct ocrdma_dev * dev)644 static void ocrdma_destroy_mq(struct ocrdma_dev *dev)
645 {
646 struct ocrdma_queue_info *mbxq, *cq;
647
648 /* mqe_ctx lock synchronizes with any other pending cmds. */
649 mutex_lock(&dev->mqe_ctx.lock);
650 mbxq = &dev->mq.sq;
651 if (mbxq->created) {
652 ocrdma_mbx_delete_q(dev, mbxq, QTYPE_MCCQ);
653 ocrdma_free_q(dev, mbxq);
654 }
655 mutex_unlock(&dev->mqe_ctx.lock);
656
657 cq = &dev->mq.cq;
658 if (cq->created) {
659 ocrdma_mbx_delete_q(dev, cq, QTYPE_CQ);
660 ocrdma_free_q(dev, cq);
661 }
662 }
663
ocrdma_process_qpcat_error(struct ocrdma_dev * dev,struct ocrdma_qp * qp)664 static void ocrdma_process_qpcat_error(struct ocrdma_dev *dev,
665 struct ocrdma_qp *qp)
666 {
667 enum ib_qp_state new_ib_qps = IB_QPS_ERR;
668 enum ib_qp_state old_ib_qps;
669
670 if (qp == NULL)
671 BUG();
672 ocrdma_qp_state_change(qp, new_ib_qps, &old_ib_qps);
673 }
674
ocrdma_dispatch_ibevent(struct ocrdma_dev * dev,struct ocrdma_ae_mcqe * cqe)675 static void ocrdma_dispatch_ibevent(struct ocrdma_dev *dev,
676 struct ocrdma_ae_mcqe *cqe)
677 {
678 struct ocrdma_qp *qp = NULL;
679 struct ocrdma_cq *cq = NULL;
680 struct ib_event ib_evt;
681 int cq_event = 0;
682 int qp_event = 1;
683 int srq_event = 0;
684 int dev_event = 0;
685 int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
686 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
687 u16 qpid = cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPID_MASK;
688 u16 cqid = cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQID_MASK;
689
690 /*
691 * Some FW version returns wrong qp or cq ids in CQEs.
692 * Checking whether the IDs are valid
693 */
694
695 if (cqe->qpvalid_qpid & OCRDMA_AE_MCQE_QPVALID) {
696 if (qpid < dev->attr.max_qp)
697 qp = dev->qp_tbl[qpid];
698 if (qp == NULL) {
699 pr_err("ocrdma%d:Async event - qpid %u is not valid\n",
700 dev->id, qpid);
701 return;
702 }
703 }
704
705 if (cqe->cqvalid_cqid & OCRDMA_AE_MCQE_CQVALID) {
706 if (cqid < dev->attr.max_cq)
707 cq = dev->cq_tbl[cqid];
708 if (cq == NULL) {
709 pr_err("ocrdma%d:Async event - cqid %u is not valid\n",
710 dev->id, cqid);
711 return;
712 }
713 }
714
715 memset(&ib_evt, 0, sizeof(ib_evt));
716
717 ib_evt.device = &dev->ibdev;
718
719 switch (type) {
720 case OCRDMA_CQ_ERROR:
721 ib_evt.element.cq = &cq->ibcq;
722 ib_evt.event = IB_EVENT_CQ_ERR;
723 cq_event = 1;
724 qp_event = 0;
725 break;
726 case OCRDMA_CQ_OVERRUN_ERROR:
727 ib_evt.element.cq = &cq->ibcq;
728 ib_evt.event = IB_EVENT_CQ_ERR;
729 cq_event = 1;
730 qp_event = 0;
731 break;
732 case OCRDMA_CQ_QPCAT_ERROR:
733 ib_evt.element.qp = &qp->ibqp;
734 ib_evt.event = IB_EVENT_QP_FATAL;
735 ocrdma_process_qpcat_error(dev, qp);
736 break;
737 case OCRDMA_QP_ACCESS_ERROR:
738 ib_evt.element.qp = &qp->ibqp;
739 ib_evt.event = IB_EVENT_QP_ACCESS_ERR;
740 break;
741 case OCRDMA_QP_COMM_EST_EVENT:
742 ib_evt.element.qp = &qp->ibqp;
743 ib_evt.event = IB_EVENT_COMM_EST;
744 break;
745 case OCRDMA_SQ_DRAINED_EVENT:
746 ib_evt.element.qp = &qp->ibqp;
747 ib_evt.event = IB_EVENT_SQ_DRAINED;
748 break;
749 case OCRDMA_DEVICE_FATAL_EVENT:
750 ib_evt.element.port_num = 1;
751 ib_evt.event = IB_EVENT_DEVICE_FATAL;
752 qp_event = 0;
753 dev_event = 1;
754 break;
755 case OCRDMA_SRQCAT_ERROR:
756 ib_evt.element.srq = &qp->srq->ibsrq;
757 ib_evt.event = IB_EVENT_SRQ_ERR;
758 srq_event = 1;
759 qp_event = 0;
760 break;
761 case OCRDMA_SRQ_LIMIT_EVENT:
762 ib_evt.element.srq = &qp->srq->ibsrq;
763 ib_evt.event = IB_EVENT_SRQ_LIMIT_REACHED;
764 srq_event = 1;
765 qp_event = 0;
766 break;
767 case OCRDMA_QP_LAST_WQE_EVENT:
768 ib_evt.element.qp = &qp->ibqp;
769 ib_evt.event = IB_EVENT_QP_LAST_WQE_REACHED;
770 break;
771 default:
772 cq_event = 0;
773 qp_event = 0;
774 srq_event = 0;
775 dev_event = 0;
776 pr_err("%s() unknown type=0x%x\n", __func__, type);
777 break;
778 }
779
780 if (type < OCRDMA_MAX_ASYNC_ERRORS)
781 atomic_inc(&dev->async_err_stats[type]);
782
783 if (qp_event) {
784 if (qp->ibqp.event_handler)
785 qp->ibqp.event_handler(&ib_evt, qp->ibqp.qp_context);
786 } else if (cq_event) {
787 if (cq->ibcq.event_handler)
788 cq->ibcq.event_handler(&ib_evt, cq->ibcq.cq_context);
789 } else if (srq_event) {
790 if (qp->srq->ibsrq.event_handler)
791 qp->srq->ibsrq.event_handler(&ib_evt,
792 qp->srq->ibsrq.
793 srq_context);
794 } else if (dev_event) {
795 pr_err("%s: Fatal event received\n", dev->ibdev.name);
796 ib_dispatch_event(&ib_evt);
797 }
798
799 }
800
ocrdma_process_grp5_aync(struct ocrdma_dev * dev,struct ocrdma_ae_mcqe * cqe)801 static void ocrdma_process_grp5_aync(struct ocrdma_dev *dev,
802 struct ocrdma_ae_mcqe *cqe)
803 {
804 struct ocrdma_ae_pvid_mcqe *evt;
805 int type = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_TYPE_MASK) >>
806 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT;
807
808 switch (type) {
809 case OCRDMA_ASYNC_EVENT_PVID_STATE:
810 evt = (struct ocrdma_ae_pvid_mcqe *)cqe;
811 if ((evt->tag_enabled & OCRDMA_AE_PVID_MCQE_ENABLED_MASK) >>
812 OCRDMA_AE_PVID_MCQE_ENABLED_SHIFT)
813 dev->pvid = ((evt->tag_enabled &
814 OCRDMA_AE_PVID_MCQE_TAG_MASK) >>
815 OCRDMA_AE_PVID_MCQE_TAG_SHIFT);
816 break;
817
818 case OCRDMA_ASYNC_EVENT_COS_VALUE:
819 atomic_set(&dev->update_sl, 1);
820 break;
821 default:
822 /* Not interested evts. */
823 break;
824 }
825 }
826
ocrdma_process_link_state(struct ocrdma_dev * dev,struct ocrdma_ae_mcqe * cqe)827 static void ocrdma_process_link_state(struct ocrdma_dev *dev,
828 struct ocrdma_ae_mcqe *cqe)
829 {
830 struct ocrdma_ae_lnkst_mcqe *evt;
831 u8 lstate;
832
833 evt = (struct ocrdma_ae_lnkst_mcqe *)cqe;
834 lstate = ocrdma_get_ae_link_state(evt->speed_state_ptn);
835
836 if (!(lstate & OCRDMA_AE_LSC_LLINK_MASK))
837 return;
838
839 if (dev->flags & OCRDMA_FLAGS_LINK_STATUS_INIT)
840 ocrdma_update_link_state(dev, (lstate & OCRDMA_LINK_ST_MASK));
841 }
842
ocrdma_process_acqe(struct ocrdma_dev * dev,void * ae_cqe)843 static void ocrdma_process_acqe(struct ocrdma_dev *dev, void *ae_cqe)
844 {
845 /* async CQE processing */
846 struct ocrdma_ae_mcqe *cqe = ae_cqe;
847 u32 evt_code = (cqe->valid_ae_event & OCRDMA_AE_MCQE_EVENT_CODE_MASK) >>
848 OCRDMA_AE_MCQE_EVENT_CODE_SHIFT;
849 switch (evt_code) {
850 case OCRDMA_ASYNC_LINK_EVE_CODE:
851 ocrdma_process_link_state(dev, cqe);
852 break;
853 case OCRDMA_ASYNC_RDMA_EVE_CODE:
854 ocrdma_dispatch_ibevent(dev, cqe);
855 break;
856 case OCRDMA_ASYNC_GRP5_EVE_CODE:
857 ocrdma_process_grp5_aync(dev, cqe);
858 break;
859 default:
860 pr_err("%s(%d) invalid evt code=0x%x\n", __func__,
861 dev->id, evt_code);
862 }
863 }
864
ocrdma_process_mcqe(struct ocrdma_dev * dev,struct ocrdma_mcqe * cqe)865 static void ocrdma_process_mcqe(struct ocrdma_dev *dev, struct ocrdma_mcqe *cqe)
866 {
867 if (dev->mqe_ctx.tag == cqe->tag_lo && dev->mqe_ctx.cmd_done == false) {
868 dev->mqe_ctx.cqe_status = (cqe->status &
869 OCRDMA_MCQE_STATUS_MASK) >> OCRDMA_MCQE_STATUS_SHIFT;
870 dev->mqe_ctx.ext_status =
871 (cqe->status & OCRDMA_MCQE_ESTATUS_MASK)
872 >> OCRDMA_MCQE_ESTATUS_SHIFT;
873 dev->mqe_ctx.cmd_done = true;
874 wake_up(&dev->mqe_ctx.cmd_wait);
875 } else
876 pr_err("%s() cqe for invalid tag0x%x.expected=0x%x\n",
877 __func__, cqe->tag_lo, dev->mqe_ctx.tag);
878 }
879
ocrdma_mq_cq_handler(struct ocrdma_dev * dev,u16 cq_id)880 static int ocrdma_mq_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
881 {
882 u16 cqe_popped = 0;
883 struct ocrdma_mcqe *cqe;
884
885 while (1) {
886 cqe = ocrdma_get_mcqe(dev);
887 if (cqe == NULL)
888 break;
889 ocrdma_le32_to_cpu(cqe, sizeof(*cqe));
890 cqe_popped += 1;
891 if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_AE_MASK)
892 ocrdma_process_acqe(dev, cqe);
893 else if (cqe->valid_ae_cmpl_cons & OCRDMA_MCQE_CMPL_MASK)
894 ocrdma_process_mcqe(dev, cqe);
895 memset(cqe, 0, sizeof(struct ocrdma_mcqe));
896 ocrdma_mcq_inc_tail(dev);
897 }
898 ocrdma_ring_cq_db(dev, dev->mq.cq.id, true, false, cqe_popped);
899 return 0;
900 }
901
_ocrdma_qp_buddy_cq_handler(struct ocrdma_dev * dev,struct ocrdma_cq * cq,bool sq)902 static struct ocrdma_cq *_ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
903 struct ocrdma_cq *cq, bool sq)
904 {
905 struct ocrdma_qp *qp;
906 struct list_head *cur;
907 struct ocrdma_cq *bcq = NULL;
908 struct list_head *head = sq?(&cq->sq_head):(&cq->rq_head);
909
910 list_for_each(cur, head) {
911 if (sq)
912 qp = list_entry(cur, struct ocrdma_qp, sq_entry);
913 else
914 qp = list_entry(cur, struct ocrdma_qp, rq_entry);
915
916 if (qp->srq)
917 continue;
918 /* if wq and rq share the same cq, than comp_handler
919 * is already invoked.
920 */
921 if (qp->sq_cq == qp->rq_cq)
922 continue;
923 /* if completion came on sq, rq's cq is buddy cq.
924 * if completion came on rq, sq's cq is buddy cq.
925 */
926 if (qp->sq_cq == cq)
927 bcq = qp->rq_cq;
928 else
929 bcq = qp->sq_cq;
930 return bcq;
931 }
932 return NULL;
933 }
934
ocrdma_qp_buddy_cq_handler(struct ocrdma_dev * dev,struct ocrdma_cq * cq)935 static void ocrdma_qp_buddy_cq_handler(struct ocrdma_dev *dev,
936 struct ocrdma_cq *cq)
937 {
938 unsigned long flags;
939 struct ocrdma_cq *bcq = NULL;
940
941 /* Go through list of QPs in error state which are using this CQ
942 * and invoke its callback handler to trigger CQE processing for
943 * error/flushed CQE. It is rare to find more than few entries in
944 * this list as most consumers stops after getting error CQE.
945 * List is traversed only once when a matching buddy cq found for a QP.
946 */
947 spin_lock_irqsave(&dev->flush_q_lock, flags);
948 /* Check if buddy CQ is present.
949 * true - Check for SQ CQ
950 * false - Check for RQ CQ
951 */
952 bcq = _ocrdma_qp_buddy_cq_handler(dev, cq, true);
953 if (bcq == NULL)
954 bcq = _ocrdma_qp_buddy_cq_handler(dev, cq, false);
955 spin_unlock_irqrestore(&dev->flush_q_lock, flags);
956
957 /* if there is valid buddy cq, look for its completion handler */
958 if (bcq && bcq->ibcq.comp_handler) {
959 spin_lock_irqsave(&bcq->comp_handler_lock, flags);
960 (*bcq->ibcq.comp_handler) (&bcq->ibcq, bcq->ibcq.cq_context);
961 spin_unlock_irqrestore(&bcq->comp_handler_lock, flags);
962 }
963 }
964
ocrdma_qp_cq_handler(struct ocrdma_dev * dev,u16 cq_idx)965 static void ocrdma_qp_cq_handler(struct ocrdma_dev *dev, u16 cq_idx)
966 {
967 unsigned long flags;
968 struct ocrdma_cq *cq;
969
970 if (cq_idx >= OCRDMA_MAX_CQ)
971 BUG();
972
973 cq = dev->cq_tbl[cq_idx];
974 if (cq == NULL)
975 return;
976
977 if (cq->ibcq.comp_handler) {
978 spin_lock_irqsave(&cq->comp_handler_lock, flags);
979 (*cq->ibcq.comp_handler) (&cq->ibcq, cq->ibcq.cq_context);
980 spin_unlock_irqrestore(&cq->comp_handler_lock, flags);
981 }
982 ocrdma_qp_buddy_cq_handler(dev, cq);
983 }
984
ocrdma_cq_handler(struct ocrdma_dev * dev,u16 cq_id)985 static void ocrdma_cq_handler(struct ocrdma_dev *dev, u16 cq_id)
986 {
987 /* process the MQ-CQE. */
988 if (cq_id == dev->mq.cq.id)
989 ocrdma_mq_cq_handler(dev, cq_id);
990 else
991 ocrdma_qp_cq_handler(dev, cq_id);
992 }
993
ocrdma_irq_handler(int irq,void * handle)994 static irqreturn_t ocrdma_irq_handler(int irq, void *handle)
995 {
996 struct ocrdma_eq *eq = handle;
997 struct ocrdma_dev *dev = eq->dev;
998 struct ocrdma_eqe eqe;
999 struct ocrdma_eqe *ptr;
1000 u16 cq_id;
1001 u8 mcode;
1002 int budget = eq->cq_cnt;
1003
1004 do {
1005 ptr = ocrdma_get_eqe(eq);
1006 eqe = *ptr;
1007 ocrdma_le32_to_cpu(&eqe, sizeof(eqe));
1008 mcode = (eqe.id_valid & OCRDMA_EQE_MAJOR_CODE_MASK)
1009 >> OCRDMA_EQE_MAJOR_CODE_SHIFT;
1010 if (mcode == OCRDMA_MAJOR_CODE_SENTINAL)
1011 pr_err("EQ full on eqid = 0x%x, eqe = 0x%x\n",
1012 eq->q.id, eqe.id_valid);
1013 if ((eqe.id_valid & OCRDMA_EQE_VALID_MASK) == 0)
1014 break;
1015
1016 ptr->id_valid = 0;
1017 /* ring eq doorbell as soon as its consumed. */
1018 ocrdma_ring_eq_db(dev, eq->q.id, false, true, 1);
1019 /* check whether its CQE or not. */
1020 if ((eqe.id_valid & OCRDMA_EQE_FOR_CQE_MASK) == 0) {
1021 cq_id = eqe.id_valid >> OCRDMA_EQE_RESOURCE_ID_SHIFT;
1022 ocrdma_cq_handler(dev, cq_id);
1023 }
1024 ocrdma_eq_inc_tail(eq);
1025
1026 /* There can be a stale EQE after the last bound CQ is
1027 * destroyed. EQE valid and budget == 0 implies this.
1028 */
1029 if (budget)
1030 budget--;
1031
1032 } while (budget);
1033
1034 eq->aic_obj.eq_intr_cnt++;
1035 ocrdma_ring_eq_db(dev, eq->q.id, true, true, 0);
1036 return IRQ_HANDLED;
1037 }
1038
ocrdma_post_mqe(struct ocrdma_dev * dev,struct ocrdma_mqe * cmd)1039 static void ocrdma_post_mqe(struct ocrdma_dev *dev, struct ocrdma_mqe *cmd)
1040 {
1041 struct ocrdma_mqe *mqe;
1042
1043 dev->mqe_ctx.tag = dev->mq.sq.head;
1044 dev->mqe_ctx.cmd_done = false;
1045 mqe = ocrdma_get_mqe(dev);
1046 cmd->hdr.tag_lo = dev->mq.sq.head;
1047 ocrdma_copy_cpu_to_le32(mqe, cmd, sizeof(*mqe));
1048 /* make sure descriptor is written before ringing doorbell */
1049 wmb();
1050 ocrdma_mq_inc_head(dev);
1051 ocrdma_ring_mq_db(dev);
1052 }
1053
ocrdma_wait_mqe_cmpl(struct ocrdma_dev * dev)1054 static int ocrdma_wait_mqe_cmpl(struct ocrdma_dev *dev)
1055 {
1056 long status;
1057 /* 30 sec timeout */
1058 status = wait_event_timeout(dev->mqe_ctx.cmd_wait,
1059 (dev->mqe_ctx.cmd_done != false),
1060 msecs_to_jiffies(30000));
1061 if (status)
1062 return 0;
1063 else {
1064 dev->mqe_ctx.fw_error_state = true;
1065 pr_err("%s(%d) mailbox timeout: fw not responding\n",
1066 __func__, dev->id);
1067 return -1;
1068 }
1069 }
1070
1071 /* issue a mailbox command on the MQ */
ocrdma_mbx_cmd(struct ocrdma_dev * dev,struct ocrdma_mqe * mqe)1072 static int ocrdma_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe)
1073 {
1074 int status = 0;
1075 u16 cqe_status, ext_status;
1076 struct ocrdma_mqe *rsp_mqe;
1077 struct ocrdma_mbx_rsp *rsp = NULL;
1078
1079 mutex_lock(&dev->mqe_ctx.lock);
1080 if (dev->mqe_ctx.fw_error_state)
1081 goto mbx_err;
1082 ocrdma_post_mqe(dev, mqe);
1083 status = ocrdma_wait_mqe_cmpl(dev);
1084 if (status)
1085 goto mbx_err;
1086 cqe_status = dev->mqe_ctx.cqe_status;
1087 ext_status = dev->mqe_ctx.ext_status;
1088 rsp_mqe = ocrdma_get_mqe_rsp(dev);
1089 ocrdma_copy_le32_to_cpu(mqe, rsp_mqe, (sizeof(*mqe)));
1090 if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >>
1091 OCRDMA_MQE_HDR_EMB_SHIFT)
1092 rsp = &mqe->u.rsp;
1093
1094 if (cqe_status || ext_status) {
1095 pr_err("%s() cqe_status=0x%x, ext_status=0x%x,\n",
1096 __func__, cqe_status, ext_status);
1097 if (rsp) {
1098 /* This is for embedded cmds. */
1099 pr_err("opcode=0x%x, subsystem=0x%x\n",
1100 (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
1101 OCRDMA_MBX_RSP_OPCODE_SHIFT,
1102 (rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >>
1103 OCRDMA_MBX_RSP_SUBSYS_SHIFT);
1104 }
1105 status = ocrdma_get_mbx_cqe_errno(cqe_status);
1106 goto mbx_err;
1107 }
1108 /* For non embedded, rsp errors are handled in ocrdma_nonemb_mbx_cmd */
1109 if (rsp && (mqe->u.rsp.status & OCRDMA_MBX_RSP_STATUS_MASK))
1110 status = ocrdma_get_mbx_errno(mqe->u.rsp.status);
1111 mbx_err:
1112 mutex_unlock(&dev->mqe_ctx.lock);
1113 return status;
1114 }
1115
ocrdma_nonemb_mbx_cmd(struct ocrdma_dev * dev,struct ocrdma_mqe * mqe,void * payload_va)1116 static int ocrdma_nonemb_mbx_cmd(struct ocrdma_dev *dev, struct ocrdma_mqe *mqe,
1117 void *payload_va)
1118 {
1119 int status;
1120 struct ocrdma_mbx_rsp *rsp = payload_va;
1121
1122 if ((mqe->hdr.spcl_sge_cnt_emb & OCRDMA_MQE_HDR_EMB_MASK) >>
1123 OCRDMA_MQE_HDR_EMB_SHIFT)
1124 BUG();
1125
1126 status = ocrdma_mbx_cmd(dev, mqe);
1127 if (!status)
1128 /* For non embedded, only CQE failures are handled in
1129 * ocrdma_mbx_cmd. We need to check for RSP errors.
1130 */
1131 if (rsp->status & OCRDMA_MBX_RSP_STATUS_MASK)
1132 status = ocrdma_get_mbx_errno(rsp->status);
1133
1134 if (status)
1135 pr_err("opcode=0x%x, subsystem=0x%x\n",
1136 (rsp->subsys_op & OCRDMA_MBX_RSP_OPCODE_MASK) >>
1137 OCRDMA_MBX_RSP_OPCODE_SHIFT,
1138 (rsp->subsys_op & OCRDMA_MBX_RSP_SUBSYS_MASK) >>
1139 OCRDMA_MBX_RSP_SUBSYS_SHIFT);
1140 return status;
1141 }
1142
ocrdma_get_attr(struct ocrdma_dev * dev,struct ocrdma_dev_attr * attr,struct ocrdma_mbx_query_config * rsp)1143 static void ocrdma_get_attr(struct ocrdma_dev *dev,
1144 struct ocrdma_dev_attr *attr,
1145 struct ocrdma_mbx_query_config *rsp)
1146 {
1147 attr->max_pd =
1148 (rsp->max_pd_ca_ack_delay & OCRDMA_MBX_QUERY_CFG_MAX_PD_MASK) >>
1149 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT;
1150 attr->udp_encap = (rsp->max_pd_ca_ack_delay &
1151 OCRDMA_MBX_QUERY_CFG_L3_TYPE_MASK) >>
1152 OCRDMA_MBX_QUERY_CFG_L3_TYPE_SHIFT;
1153 attr->max_dpp_pds =
1154 (rsp->max_dpp_pds_credits & OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_MASK) >>
1155 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET;
1156 attr->max_qp =
1157 (rsp->qp_srq_cq_ird_ord & OCRDMA_MBX_QUERY_CFG_MAX_QP_MASK) >>
1158 OCRDMA_MBX_QUERY_CFG_MAX_QP_SHIFT;
1159 attr->max_srq =
1160 (rsp->max_srq_rpir_qps & OCRDMA_MBX_QUERY_CFG_MAX_SRQ_MASK) >>
1161 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET;
1162 attr->max_send_sge = ((rsp->max_recv_send_sge &
1163 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_MASK) >>
1164 OCRDMA_MBX_QUERY_CFG_MAX_SEND_SGE_SHIFT);
1165 attr->max_recv_sge = (rsp->max_recv_send_sge &
1166 OCRDMA_MBX_QUERY_CFG_MAX_RECV_SGE_MASK) >>
1167 OCRDMA_MBX_QUERY_CFG_MAX_RECV_SGE_SHIFT;
1168 attr->max_srq_sge = (rsp->max_srq_rqe_sge &
1169 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_MASK) >>
1170 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_SGE_OFFSET;
1171 attr->max_rdma_sge = (rsp->max_wr_rd_sge &
1172 OCRDMA_MBX_QUERY_CFG_MAX_RD_SGE_MASK) >>
1173 OCRDMA_MBX_QUERY_CFG_MAX_RD_SGE_SHIFT;
1174 attr->max_ord_per_qp = (rsp->max_ird_ord_per_qp &
1175 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_MASK) >>
1176 OCRDMA_MBX_QUERY_CFG_MAX_ORD_PER_QP_SHIFT;
1177 attr->max_ird_per_qp = (rsp->max_ird_ord_per_qp &
1178 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_MASK) >>
1179 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT;
1180 attr->cq_overflow_detect = (rsp->qp_srq_cq_ird_ord &
1181 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK) >>
1182 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_SHIFT;
1183 attr->srq_supported = (rsp->qp_srq_cq_ird_ord &
1184 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK) >>
1185 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_SHIFT;
1186 attr->local_ca_ack_delay = (rsp->max_pd_ca_ack_delay &
1187 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_MASK) >>
1188 OCRDMA_MBX_QUERY_CFG_CA_ACK_DELAY_SHIFT;
1189 attr->max_mw = rsp->max_mw;
1190 attr->max_mr = rsp->max_mr;
1191 attr->max_mr_size = ((u64)rsp->max_mr_size_hi << 32) |
1192 rsp->max_mr_size_lo;
1193 attr->max_fmr = 0;
1194 attr->max_pages_per_frmr = rsp->max_pages_per_frmr;
1195 attr->max_num_mr_pbl = rsp->max_num_mr_pbl;
1196 attr->max_cqe = rsp->max_cq_cqes_per_cq &
1197 OCRDMA_MBX_QUERY_CFG_MAX_CQES_PER_CQ_MASK;
1198 attr->max_cq = (rsp->max_cq_cqes_per_cq &
1199 OCRDMA_MBX_QUERY_CFG_MAX_CQ_MASK) >>
1200 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET;
1201 attr->wqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1202 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_MASK) >>
1203 OCRDMA_MBX_QUERY_CFG_MAX_WQE_SIZE_OFFSET) *
1204 OCRDMA_WQE_STRIDE;
1205 attr->rqe_size = ((rsp->wqe_rqe_stride_max_dpp_cqs &
1206 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_MASK) >>
1207 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET) *
1208 OCRDMA_WQE_STRIDE;
1209 attr->max_inline_data =
1210 attr->wqe_size - (sizeof(struct ocrdma_hdr_wqe) +
1211 sizeof(struct ocrdma_sge));
1212 if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
1213 attr->ird = 1;
1214 attr->ird_page_size = OCRDMA_MIN_Q_PAGE_SIZE;
1215 attr->num_ird_pages = MAX_OCRDMA_IRD_PAGES;
1216 }
1217 dev->attr.max_wqe = rsp->max_wqes_rqes_per_q >>
1218 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET;
1219 dev->attr.max_rqe = rsp->max_wqes_rqes_per_q &
1220 OCRDMA_MBX_QUERY_CFG_MAX_RQES_PER_RQ_MASK;
1221 }
1222
ocrdma_check_fw_config(struct ocrdma_dev * dev,struct ocrdma_fw_conf_rsp * conf)1223 static int ocrdma_check_fw_config(struct ocrdma_dev *dev,
1224 struct ocrdma_fw_conf_rsp *conf)
1225 {
1226 u32 fn_mode;
1227
1228 fn_mode = conf->fn_mode & OCRDMA_FN_MODE_RDMA;
1229 if (fn_mode != OCRDMA_FN_MODE_RDMA)
1230 return -EINVAL;
1231 dev->base_eqid = conf->base_eqid;
1232 dev->max_eq = conf->max_eq;
1233 return 0;
1234 }
1235
1236 /* can be issued only during init time. */
ocrdma_mbx_query_fw_ver(struct ocrdma_dev * dev)1237 static int ocrdma_mbx_query_fw_ver(struct ocrdma_dev *dev)
1238 {
1239 int status = -ENOMEM;
1240 struct ocrdma_mqe *cmd;
1241 struct ocrdma_fw_ver_rsp *rsp;
1242
1243 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_VER, sizeof(*cmd));
1244 if (!cmd)
1245 return -ENOMEM;
1246 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1247 OCRDMA_CMD_GET_FW_VER,
1248 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1249
1250 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1251 if (status)
1252 goto mbx_err;
1253 rsp = (struct ocrdma_fw_ver_rsp *)cmd;
1254 memset(&dev->attr.fw_ver[0], 0, sizeof(dev->attr.fw_ver));
1255 memcpy(&dev->attr.fw_ver[0], &rsp->running_ver[0],
1256 sizeof(rsp->running_ver));
1257 ocrdma_le32_to_cpu(dev->attr.fw_ver, sizeof(rsp->running_ver));
1258 mbx_err:
1259 kfree(cmd);
1260 return status;
1261 }
1262
1263 /* can be issued only during init time. */
ocrdma_mbx_query_fw_config(struct ocrdma_dev * dev)1264 static int ocrdma_mbx_query_fw_config(struct ocrdma_dev *dev)
1265 {
1266 int status = -ENOMEM;
1267 struct ocrdma_mqe *cmd;
1268 struct ocrdma_fw_conf_rsp *rsp;
1269
1270 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_GET_FW_CONFIG, sizeof(*cmd));
1271 if (!cmd)
1272 return -ENOMEM;
1273 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1274 OCRDMA_CMD_GET_FW_CONFIG,
1275 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1276 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1277 if (status)
1278 goto mbx_err;
1279 rsp = (struct ocrdma_fw_conf_rsp *)cmd;
1280 status = ocrdma_check_fw_config(dev, rsp);
1281 mbx_err:
1282 kfree(cmd);
1283 return status;
1284 }
1285
ocrdma_mbx_rdma_stats(struct ocrdma_dev * dev,bool reset)1286 int ocrdma_mbx_rdma_stats(struct ocrdma_dev *dev, bool reset)
1287 {
1288 struct ocrdma_rdma_stats_req *req = dev->stats_mem.va;
1289 struct ocrdma_mqe *mqe = &dev->stats_mem.mqe;
1290 struct ocrdma_rdma_stats_resp *old_stats;
1291 int status;
1292
1293 old_stats = kmalloc(sizeof(*old_stats), GFP_KERNEL);
1294 if (old_stats == NULL)
1295 return -ENOMEM;
1296
1297 memset(mqe, 0, sizeof(*mqe));
1298 mqe->hdr.pyld_len = dev->stats_mem.size;
1299 mqe->hdr.spcl_sge_cnt_emb |=
1300 (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
1301 OCRDMA_MQE_HDR_SGE_CNT_MASK;
1302 mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dev->stats_mem.pa & 0xffffffff);
1303 mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dev->stats_mem.pa);
1304 mqe->u.nonemb_req.sge[0].len = dev->stats_mem.size;
1305
1306 /* Cache the old stats */
1307 memcpy(old_stats, req, sizeof(struct ocrdma_rdma_stats_resp));
1308 memset(req, 0, dev->stats_mem.size);
1309
1310 ocrdma_init_mch((struct ocrdma_mbx_hdr *)req,
1311 OCRDMA_CMD_GET_RDMA_STATS,
1312 OCRDMA_SUBSYS_ROCE,
1313 dev->stats_mem.size);
1314 if (reset)
1315 req->reset_stats = reset;
1316
1317 status = ocrdma_nonemb_mbx_cmd(dev, mqe, dev->stats_mem.va);
1318 if (status)
1319 /* Copy from cache, if mbox fails */
1320 memcpy(req, old_stats, sizeof(struct ocrdma_rdma_stats_resp));
1321 else
1322 ocrdma_le32_to_cpu(req, dev->stats_mem.size);
1323
1324 kfree(old_stats);
1325 return status;
1326 }
1327
ocrdma_mbx_get_ctrl_attribs(struct ocrdma_dev * dev)1328 static int ocrdma_mbx_get_ctrl_attribs(struct ocrdma_dev *dev)
1329 {
1330 int status = -ENOMEM;
1331 struct ocrdma_dma_mem dma;
1332 struct ocrdma_mqe *mqe;
1333 struct ocrdma_get_ctrl_attribs_rsp *ctrl_attr_rsp;
1334 struct mgmt_hba_attribs *hba_attribs;
1335
1336 mqe = kzalloc(sizeof(struct ocrdma_mqe), GFP_KERNEL);
1337 if (!mqe)
1338 return status;
1339
1340 dma.size = sizeof(struct ocrdma_get_ctrl_attribs_rsp);
1341 dma.va = dma_alloc_coherent(&dev->nic_info.pdev->dev,
1342 dma.size, &dma.pa, GFP_KERNEL);
1343 if (!dma.va)
1344 goto free_mqe;
1345
1346 mqe->hdr.pyld_len = dma.size;
1347 mqe->hdr.spcl_sge_cnt_emb |=
1348 (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
1349 OCRDMA_MQE_HDR_SGE_CNT_MASK;
1350 mqe->u.nonemb_req.sge[0].pa_lo = (u32) (dma.pa & 0xffffffff);
1351 mqe->u.nonemb_req.sge[0].pa_hi = (u32) upper_32_bits(dma.pa);
1352 mqe->u.nonemb_req.sge[0].len = dma.size;
1353
1354 memset(dma.va, 0, dma.size);
1355 ocrdma_init_mch((struct ocrdma_mbx_hdr *)dma.va,
1356 OCRDMA_CMD_GET_CTRL_ATTRIBUTES,
1357 OCRDMA_SUBSYS_COMMON,
1358 dma.size);
1359
1360 status = ocrdma_nonemb_mbx_cmd(dev, mqe, dma.va);
1361 if (!status) {
1362 ctrl_attr_rsp = (struct ocrdma_get_ctrl_attribs_rsp *)dma.va;
1363 hba_attribs = &ctrl_attr_rsp->ctrl_attribs.hba_attribs;
1364
1365 dev->hba_port_num = (hba_attribs->ptpnum_maxdoms_hbast_cv &
1366 OCRDMA_HBA_ATTRB_PTNUM_MASK)
1367 >> OCRDMA_HBA_ATTRB_PTNUM_SHIFT;
1368 strlcpy(dev->model_number,
1369 hba_attribs->controller_model_number,
1370 sizeof(dev->model_number));
1371 }
1372 dma_free_coherent(&dev->nic_info.pdev->dev, dma.size, dma.va, dma.pa);
1373 free_mqe:
1374 kfree(mqe);
1375 return status;
1376 }
1377
ocrdma_mbx_query_dev(struct ocrdma_dev * dev)1378 static int ocrdma_mbx_query_dev(struct ocrdma_dev *dev)
1379 {
1380 int status = -ENOMEM;
1381 struct ocrdma_mbx_query_config *rsp;
1382 struct ocrdma_mqe *cmd;
1383
1384 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_CONFIG, sizeof(*cmd));
1385 if (!cmd)
1386 return status;
1387 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1388 if (status)
1389 goto mbx_err;
1390 rsp = (struct ocrdma_mbx_query_config *)cmd;
1391 ocrdma_get_attr(dev, &dev->attr, rsp);
1392 mbx_err:
1393 kfree(cmd);
1394 return status;
1395 }
1396
ocrdma_mbx_get_link_speed(struct ocrdma_dev * dev,u8 * lnk_speed,u8 * lnk_state)1397 int ocrdma_mbx_get_link_speed(struct ocrdma_dev *dev, u8 *lnk_speed,
1398 u8 *lnk_state)
1399 {
1400 int status = -ENOMEM;
1401 struct ocrdma_get_link_speed_rsp *rsp;
1402 struct ocrdma_mqe *cmd;
1403
1404 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1405 sizeof(*cmd));
1406 if (!cmd)
1407 return status;
1408 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1409 OCRDMA_CMD_QUERY_NTWK_LINK_CONFIG_V1,
1410 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1411
1412 ((struct ocrdma_mbx_hdr *)cmd->u.cmd)->rsvd_version = 0x1;
1413
1414 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1415 if (status)
1416 goto mbx_err;
1417
1418 rsp = (struct ocrdma_get_link_speed_rsp *)cmd;
1419 if (lnk_speed)
1420 *lnk_speed = (rsp->pflt_pps_ld_pnum & OCRDMA_PHY_PS_MASK)
1421 >> OCRDMA_PHY_PS_SHIFT;
1422 if (lnk_state)
1423 *lnk_state = (rsp->res_lnk_st & OCRDMA_LINK_ST_MASK);
1424
1425 mbx_err:
1426 kfree(cmd);
1427 return status;
1428 }
1429
ocrdma_mbx_get_phy_info(struct ocrdma_dev * dev)1430 static int ocrdma_mbx_get_phy_info(struct ocrdma_dev *dev)
1431 {
1432 int status = -ENOMEM;
1433 struct ocrdma_mqe *cmd;
1434 struct ocrdma_get_phy_info_rsp *rsp;
1435
1436 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_PHY_DETAILS, sizeof(*cmd));
1437 if (!cmd)
1438 return status;
1439
1440 ocrdma_init_mch((struct ocrdma_mbx_hdr *)&cmd->u.cmd[0],
1441 OCRDMA_CMD_PHY_DETAILS, OCRDMA_SUBSYS_COMMON,
1442 sizeof(*cmd));
1443
1444 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1445 if (status)
1446 goto mbx_err;
1447
1448 rsp = (struct ocrdma_get_phy_info_rsp *)cmd;
1449 dev->phy.phy_type =
1450 (rsp->ityp_ptyp & OCRDMA_PHY_TYPE_MASK);
1451 dev->phy.interface_type =
1452 (rsp->ityp_ptyp & OCRDMA_IF_TYPE_MASK)
1453 >> OCRDMA_IF_TYPE_SHIFT;
1454 dev->phy.auto_speeds_supported =
1455 (rsp->fspeed_aspeed & OCRDMA_ASPEED_SUPP_MASK);
1456 dev->phy.fixed_speeds_supported =
1457 (rsp->fspeed_aspeed & OCRDMA_FSPEED_SUPP_MASK)
1458 >> OCRDMA_FSPEED_SUPP_SHIFT;
1459 mbx_err:
1460 kfree(cmd);
1461 return status;
1462 }
1463
ocrdma_mbx_alloc_pd(struct ocrdma_dev * dev,struct ocrdma_pd * pd)1464 int ocrdma_mbx_alloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1465 {
1466 int status = -ENOMEM;
1467 struct ocrdma_alloc_pd *cmd;
1468 struct ocrdma_alloc_pd_rsp *rsp;
1469
1470 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD, sizeof(*cmd));
1471 if (!cmd)
1472 return status;
1473 if (pd->dpp_enabled)
1474 cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1475 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1476 if (status)
1477 goto mbx_err;
1478 rsp = (struct ocrdma_alloc_pd_rsp *)cmd;
1479 pd->id = rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_PDID_MASK;
1480 if (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) {
1481 pd->dpp_enabled = true;
1482 pd->dpp_page = rsp->dpp_page_pdid >>
1483 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1484 } else {
1485 pd->dpp_enabled = false;
1486 pd->num_dpp_qp = 0;
1487 }
1488 mbx_err:
1489 kfree(cmd);
1490 return status;
1491 }
1492
ocrdma_mbx_dealloc_pd(struct ocrdma_dev * dev,struct ocrdma_pd * pd)1493 int ocrdma_mbx_dealloc_pd(struct ocrdma_dev *dev, struct ocrdma_pd *pd)
1494 {
1495 int status = -ENOMEM;
1496 struct ocrdma_dealloc_pd *cmd;
1497
1498 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD, sizeof(*cmd));
1499 if (!cmd)
1500 return status;
1501 cmd->id = pd->id;
1502 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1503 kfree(cmd);
1504 return status;
1505 }
1506
1507
ocrdma_mbx_alloc_pd_range(struct ocrdma_dev * dev)1508 static int ocrdma_mbx_alloc_pd_range(struct ocrdma_dev *dev)
1509 {
1510 int status = -ENOMEM;
1511 size_t pd_bitmap_size;
1512 struct ocrdma_alloc_pd_range *cmd;
1513 struct ocrdma_alloc_pd_range_rsp *rsp;
1514
1515 /* Pre allocate the DPP PDs */
1516 if (dev->attr.max_dpp_pds) {
1517 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD_RANGE,
1518 sizeof(*cmd));
1519 if (!cmd)
1520 return -ENOMEM;
1521 cmd->pd_count = dev->attr.max_dpp_pds;
1522 cmd->enable_dpp_rsvd |= OCRDMA_ALLOC_PD_ENABLE_DPP;
1523 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1524 rsp = (struct ocrdma_alloc_pd_range_rsp *)cmd;
1525
1526 if (!status && (rsp->dpp_page_pdid & OCRDMA_ALLOC_PD_RSP_DPP) &&
1527 rsp->pd_count) {
1528 dev->pd_mgr->dpp_page_index = rsp->dpp_page_pdid >>
1529 OCRDMA_ALLOC_PD_RSP_DPP_PAGE_SHIFT;
1530 dev->pd_mgr->pd_dpp_start = rsp->dpp_page_pdid &
1531 OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK;
1532 dev->pd_mgr->max_dpp_pd = rsp->pd_count;
1533 pd_bitmap_size =
1534 BITS_TO_LONGS(rsp->pd_count) * sizeof(long);
1535 dev->pd_mgr->pd_dpp_bitmap = kzalloc(pd_bitmap_size,
1536 GFP_KERNEL);
1537 }
1538 kfree(cmd);
1539 }
1540
1541 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_PD_RANGE, sizeof(*cmd));
1542 if (!cmd)
1543 return -ENOMEM;
1544
1545 cmd->pd_count = dev->attr.max_pd - dev->attr.max_dpp_pds;
1546 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1547 rsp = (struct ocrdma_alloc_pd_range_rsp *)cmd;
1548 if (!status && rsp->pd_count) {
1549 dev->pd_mgr->pd_norm_start = rsp->dpp_page_pdid &
1550 OCRDMA_ALLOC_PD_RNG_RSP_START_PDID_MASK;
1551 dev->pd_mgr->max_normal_pd = rsp->pd_count;
1552 pd_bitmap_size = BITS_TO_LONGS(rsp->pd_count) * sizeof(long);
1553 dev->pd_mgr->pd_norm_bitmap = kzalloc(pd_bitmap_size,
1554 GFP_KERNEL);
1555 }
1556 kfree(cmd);
1557
1558 if (dev->pd_mgr->pd_norm_bitmap || dev->pd_mgr->pd_dpp_bitmap) {
1559 /* Enable PD resource manager */
1560 dev->pd_mgr->pd_prealloc_valid = true;
1561 return 0;
1562 }
1563 return status;
1564 }
1565
ocrdma_mbx_dealloc_pd_range(struct ocrdma_dev * dev)1566 static void ocrdma_mbx_dealloc_pd_range(struct ocrdma_dev *dev)
1567 {
1568 struct ocrdma_dealloc_pd_range *cmd;
1569
1570 /* return normal PDs to firmware */
1571 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD_RANGE, sizeof(*cmd));
1572 if (!cmd)
1573 goto mbx_err;
1574
1575 if (dev->pd_mgr->max_normal_pd) {
1576 cmd->start_pd_id = dev->pd_mgr->pd_norm_start;
1577 cmd->pd_count = dev->pd_mgr->max_normal_pd;
1578 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1579 }
1580
1581 if (dev->pd_mgr->max_dpp_pd) {
1582 kfree(cmd);
1583 /* return DPP PDs to firmware */
1584 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_PD_RANGE,
1585 sizeof(*cmd));
1586 if (!cmd)
1587 goto mbx_err;
1588
1589 cmd->start_pd_id = dev->pd_mgr->pd_dpp_start;
1590 cmd->pd_count = dev->pd_mgr->max_dpp_pd;
1591 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1592 }
1593 mbx_err:
1594 kfree(cmd);
1595 }
1596
ocrdma_alloc_pd_pool(struct ocrdma_dev * dev)1597 void ocrdma_alloc_pd_pool(struct ocrdma_dev *dev)
1598 {
1599 int status;
1600
1601 dev->pd_mgr = kzalloc(sizeof(struct ocrdma_pd_resource_mgr),
1602 GFP_KERNEL);
1603 if (!dev->pd_mgr)
1604 return;
1605
1606 status = ocrdma_mbx_alloc_pd_range(dev);
1607 if (status) {
1608 pr_err("%s(%d) Unable to initialize PD pool, using default.\n",
1609 __func__, dev->id);
1610 }
1611 }
1612
ocrdma_free_pd_pool(struct ocrdma_dev * dev)1613 static void ocrdma_free_pd_pool(struct ocrdma_dev *dev)
1614 {
1615 ocrdma_mbx_dealloc_pd_range(dev);
1616 kfree(dev->pd_mgr->pd_norm_bitmap);
1617 kfree(dev->pd_mgr->pd_dpp_bitmap);
1618 kfree(dev->pd_mgr);
1619 }
1620
ocrdma_build_q_conf(u32 * num_entries,int entry_size,int * num_pages,int * page_size)1621 static int ocrdma_build_q_conf(u32 *num_entries, int entry_size,
1622 int *num_pages, int *page_size)
1623 {
1624 int i;
1625 int mem_size;
1626
1627 *num_entries = roundup_pow_of_two(*num_entries);
1628 mem_size = *num_entries * entry_size;
1629 /* find the possible lowest possible multiplier */
1630 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1631 if (mem_size <= (OCRDMA_Q_PAGE_BASE_SIZE << i))
1632 break;
1633 }
1634 if (i >= OCRDMA_MAX_Q_PAGE_SIZE_CNT)
1635 return -EINVAL;
1636 mem_size = roundup(mem_size,
1637 ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES));
1638 *num_pages =
1639 mem_size / ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1640 *page_size = ((OCRDMA_Q_PAGE_BASE_SIZE << i) / OCRDMA_MAX_Q_PAGES);
1641 *num_entries = mem_size / entry_size;
1642 return 0;
1643 }
1644
ocrdma_mbx_create_ah_tbl(struct ocrdma_dev * dev)1645 static int ocrdma_mbx_create_ah_tbl(struct ocrdma_dev *dev)
1646 {
1647 int i;
1648 int status = -ENOMEM;
1649 int max_ah;
1650 struct ocrdma_create_ah_tbl *cmd;
1651 struct ocrdma_create_ah_tbl_rsp *rsp;
1652 struct pci_dev *pdev = dev->nic_info.pdev;
1653 dma_addr_t pa;
1654 struct ocrdma_pbe *pbes;
1655
1656 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_AH_TBL, sizeof(*cmd));
1657 if (!cmd)
1658 return status;
1659
1660 max_ah = OCRDMA_MAX_AH;
1661 dev->av_tbl.size = sizeof(struct ocrdma_av) * max_ah;
1662
1663 /* number of PBEs in PBL */
1664 cmd->ah_conf = (OCRDMA_AH_TBL_PAGES <<
1665 OCRDMA_CREATE_AH_NUM_PAGES_SHIFT) &
1666 OCRDMA_CREATE_AH_NUM_PAGES_MASK;
1667
1668 /* page size */
1669 for (i = 0; i < OCRDMA_MAX_Q_PAGE_SIZE_CNT; i++) {
1670 if (PAGE_SIZE == (OCRDMA_MIN_Q_PAGE_SIZE << i))
1671 break;
1672 }
1673 cmd->ah_conf |= (i << OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT) &
1674 OCRDMA_CREATE_AH_PAGE_SIZE_MASK;
1675
1676 /* ah_entry size */
1677 cmd->ah_conf |= (sizeof(struct ocrdma_av) <<
1678 OCRDMA_CREATE_AH_ENTRY_SIZE_SHIFT) &
1679 OCRDMA_CREATE_AH_ENTRY_SIZE_MASK;
1680
1681 dev->av_tbl.pbl.va = dma_alloc_coherent(&pdev->dev, PAGE_SIZE,
1682 &dev->av_tbl.pbl.pa,
1683 GFP_KERNEL);
1684 if (dev->av_tbl.pbl.va == NULL)
1685 goto mem_err;
1686
1687 dev->av_tbl.va = dma_alloc_coherent(&pdev->dev, dev->av_tbl.size,
1688 &pa, GFP_KERNEL);
1689 if (dev->av_tbl.va == NULL)
1690 goto mem_err_ah;
1691 dev->av_tbl.pa = pa;
1692 dev->av_tbl.num_ah = max_ah;
1693 memset(dev->av_tbl.va, 0, dev->av_tbl.size);
1694
1695 pbes = (struct ocrdma_pbe *)dev->av_tbl.pbl.va;
1696 for (i = 0; i < dev->av_tbl.size / OCRDMA_MIN_Q_PAGE_SIZE; i++) {
1697 pbes[i].pa_lo = (u32)cpu_to_le32(pa & 0xffffffff);
1698 pbes[i].pa_hi = (u32)cpu_to_le32(upper_32_bits(pa));
1699 pa += PAGE_SIZE;
1700 }
1701 cmd->tbl_addr[0].lo = (u32)(dev->av_tbl.pbl.pa & 0xFFFFFFFF);
1702 cmd->tbl_addr[0].hi = (u32)upper_32_bits(dev->av_tbl.pbl.pa);
1703 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1704 if (status)
1705 goto mbx_err;
1706 rsp = (struct ocrdma_create_ah_tbl_rsp *)cmd;
1707 dev->av_tbl.ahid = rsp->ahid & 0xFFFF;
1708 kfree(cmd);
1709 return 0;
1710
1711 mbx_err:
1712 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1713 dev->av_tbl.pa);
1714 dev->av_tbl.va = NULL;
1715 mem_err_ah:
1716 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1717 dev->av_tbl.pbl.pa);
1718 dev->av_tbl.pbl.va = NULL;
1719 dev->av_tbl.size = 0;
1720 mem_err:
1721 kfree(cmd);
1722 return status;
1723 }
1724
ocrdma_mbx_delete_ah_tbl(struct ocrdma_dev * dev)1725 static void ocrdma_mbx_delete_ah_tbl(struct ocrdma_dev *dev)
1726 {
1727 struct ocrdma_delete_ah_tbl *cmd;
1728 struct pci_dev *pdev = dev->nic_info.pdev;
1729
1730 if (dev->av_tbl.va == NULL)
1731 return;
1732
1733 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_AH_TBL, sizeof(*cmd));
1734 if (!cmd)
1735 return;
1736 cmd->ahid = dev->av_tbl.ahid;
1737
1738 ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1739 dma_free_coherent(&pdev->dev, dev->av_tbl.size, dev->av_tbl.va,
1740 dev->av_tbl.pa);
1741 dev->av_tbl.va = NULL;
1742 dma_free_coherent(&pdev->dev, PAGE_SIZE, dev->av_tbl.pbl.va,
1743 dev->av_tbl.pbl.pa);
1744 kfree(cmd);
1745 }
1746
1747 /* Multiple CQs uses the EQ. This routine returns least used
1748 * EQ to associate with CQ. This will distributes the interrupt
1749 * processing and CPU load to associated EQ, vector and so to that CPU.
1750 */
ocrdma_bind_eq(struct ocrdma_dev * dev)1751 static u16 ocrdma_bind_eq(struct ocrdma_dev *dev)
1752 {
1753 int i, selected_eq = 0, cq_cnt = 0;
1754 u16 eq_id;
1755
1756 mutex_lock(&dev->dev_lock);
1757 cq_cnt = dev->eq_tbl[0].cq_cnt;
1758 eq_id = dev->eq_tbl[0].q.id;
1759 /* find the EQ which is has the least number of
1760 * CQs associated with it.
1761 */
1762 for (i = 0; i < dev->eq_cnt; i++) {
1763 if (dev->eq_tbl[i].cq_cnt < cq_cnt) {
1764 cq_cnt = dev->eq_tbl[i].cq_cnt;
1765 eq_id = dev->eq_tbl[i].q.id;
1766 selected_eq = i;
1767 }
1768 }
1769 dev->eq_tbl[selected_eq].cq_cnt += 1;
1770 mutex_unlock(&dev->dev_lock);
1771 return eq_id;
1772 }
1773
ocrdma_unbind_eq(struct ocrdma_dev * dev,u16 eq_id)1774 static void ocrdma_unbind_eq(struct ocrdma_dev *dev, u16 eq_id)
1775 {
1776 int i;
1777
1778 mutex_lock(&dev->dev_lock);
1779 i = ocrdma_get_eq_table_index(dev, eq_id);
1780 if (i == -EINVAL)
1781 BUG();
1782 dev->eq_tbl[i].cq_cnt -= 1;
1783 mutex_unlock(&dev->dev_lock);
1784 }
1785
ocrdma_mbx_create_cq(struct ocrdma_dev * dev,struct ocrdma_cq * cq,int entries,int dpp_cq,u16 pd_id)1786 int ocrdma_mbx_create_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq,
1787 int entries, int dpp_cq, u16 pd_id)
1788 {
1789 int status = -ENOMEM; int max_hw_cqe;
1790 struct pci_dev *pdev = dev->nic_info.pdev;
1791 struct ocrdma_create_cq *cmd;
1792 struct ocrdma_create_cq_rsp *rsp;
1793 u32 hw_pages, cqe_size, page_size, cqe_count;
1794
1795 if (entries > dev->attr.max_cqe) {
1796 pr_err("%s(%d) max_cqe=0x%x, requester_cqe=0x%x\n",
1797 __func__, dev->id, dev->attr.max_cqe, entries);
1798 return -EINVAL;
1799 }
1800 if (dpp_cq && (ocrdma_get_asic_type(dev) != OCRDMA_ASIC_GEN_SKH_R))
1801 return -EINVAL;
1802
1803 if (dpp_cq) {
1804 cq->max_hw_cqe = 1;
1805 max_hw_cqe = 1;
1806 cqe_size = OCRDMA_DPP_CQE_SIZE;
1807 hw_pages = 1;
1808 } else {
1809 cq->max_hw_cqe = dev->attr.max_cqe;
1810 max_hw_cqe = dev->attr.max_cqe;
1811 cqe_size = sizeof(struct ocrdma_cqe);
1812 hw_pages = OCRDMA_CREATE_CQ_MAX_PAGES;
1813 }
1814
1815 cq->len = roundup(max_hw_cqe * cqe_size, OCRDMA_MIN_Q_PAGE_SIZE);
1816
1817 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_CQ, sizeof(*cmd));
1818 if (!cmd)
1819 return -ENOMEM;
1820 ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_CREATE_CQ,
1821 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1822 cq->va = dma_zalloc_coherent(&pdev->dev, cq->len, &cq->pa, GFP_KERNEL);
1823 if (!cq->va) {
1824 status = -ENOMEM;
1825 goto mem_err;
1826 }
1827 page_size = cq->len / hw_pages;
1828 cmd->cmd.pgsz_pgcnt = (page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
1829 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT;
1830 cmd->cmd.pgsz_pgcnt |= hw_pages;
1831 cmd->cmd.ev_cnt_flags = OCRDMA_CREATE_CQ_DEF_FLAGS;
1832
1833 cq->eqn = ocrdma_bind_eq(dev);
1834 cmd->cmd.req.rsvd_version = OCRDMA_CREATE_CQ_VER3;
1835 cqe_count = cq->len / cqe_size;
1836 cq->cqe_cnt = cqe_count;
1837 if (cqe_count > 1024) {
1838 /* Set cnt to 3 to indicate more than 1024 cq entries */
1839 cmd->cmd.ev_cnt_flags |= (0x3 << OCRDMA_CREATE_CQ_CNT_SHIFT);
1840 } else {
1841 u8 count = 0;
1842 switch (cqe_count) {
1843 case 256:
1844 count = 0;
1845 break;
1846 case 512:
1847 count = 1;
1848 break;
1849 case 1024:
1850 count = 2;
1851 break;
1852 default:
1853 goto mbx_err;
1854 }
1855 cmd->cmd.ev_cnt_flags |= (count << OCRDMA_CREATE_CQ_CNT_SHIFT);
1856 }
1857 /* shared eq between all the consumer cqs. */
1858 cmd->cmd.eqn = cq->eqn;
1859 if (ocrdma_get_asic_type(dev) == OCRDMA_ASIC_GEN_SKH_R) {
1860 if (dpp_cq)
1861 cmd->cmd.pgsz_pgcnt |= OCRDMA_CREATE_CQ_DPP <<
1862 OCRDMA_CREATE_CQ_TYPE_SHIFT;
1863 cq->phase_change = false;
1864 cmd->cmd.pdid_cqecnt = (cq->len / cqe_size);
1865 } else {
1866 cmd->cmd.pdid_cqecnt = (cq->len / cqe_size) - 1;
1867 cmd->cmd.ev_cnt_flags |= OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID;
1868 cq->phase_change = true;
1869 }
1870
1871 /* pd_id valid only for v3 */
1872 cmd->cmd.pdid_cqecnt |= (pd_id <<
1873 OCRDMA_CREATE_CQ_CMD_PDID_SHIFT);
1874 ocrdma_build_q_pages(&cmd->cmd.pa[0], hw_pages, cq->pa, page_size);
1875 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1876 if (status)
1877 goto mbx_err;
1878
1879 rsp = (struct ocrdma_create_cq_rsp *)cmd;
1880 cq->id = (u16) (rsp->rsp.cq_id & OCRDMA_CREATE_CQ_RSP_CQ_ID_MASK);
1881 kfree(cmd);
1882 return 0;
1883 mbx_err:
1884 ocrdma_unbind_eq(dev, cq->eqn);
1885 dma_free_coherent(&pdev->dev, cq->len, cq->va, cq->pa);
1886 mem_err:
1887 kfree(cmd);
1888 return status;
1889 }
1890
ocrdma_mbx_destroy_cq(struct ocrdma_dev * dev,struct ocrdma_cq * cq)1891 int ocrdma_mbx_destroy_cq(struct ocrdma_dev *dev, struct ocrdma_cq *cq)
1892 {
1893 int status = -ENOMEM;
1894 struct ocrdma_destroy_cq *cmd;
1895
1896 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_CQ, sizeof(*cmd));
1897 if (!cmd)
1898 return status;
1899 ocrdma_init_mch(&cmd->req, OCRDMA_CMD_DELETE_CQ,
1900 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
1901
1902 cmd->bypass_flush_qid |=
1903 (cq->id << OCRDMA_DESTROY_CQ_QID_SHIFT) &
1904 OCRDMA_DESTROY_CQ_QID_MASK;
1905
1906 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1907 ocrdma_unbind_eq(dev, cq->eqn);
1908 dma_free_coherent(&dev->nic_info.pdev->dev, cq->len, cq->va, cq->pa);
1909 kfree(cmd);
1910 return status;
1911 }
1912
ocrdma_mbx_alloc_lkey(struct ocrdma_dev * dev,struct ocrdma_hw_mr * hwmr,u32 pdid,int addr_check)1913 int ocrdma_mbx_alloc_lkey(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1914 u32 pdid, int addr_check)
1915 {
1916 int status = -ENOMEM;
1917 struct ocrdma_alloc_lkey *cmd;
1918 struct ocrdma_alloc_lkey_rsp *rsp;
1919
1920 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_ALLOC_LKEY, sizeof(*cmd));
1921 if (!cmd)
1922 return status;
1923 cmd->pdid = pdid;
1924 cmd->pbl_sz_flags |= addr_check;
1925 cmd->pbl_sz_flags |= (hwmr->fr_mr << OCRDMA_ALLOC_LKEY_FMR_SHIFT);
1926 cmd->pbl_sz_flags |=
1927 (hwmr->remote_wr << OCRDMA_ALLOC_LKEY_REMOTE_WR_SHIFT);
1928 cmd->pbl_sz_flags |=
1929 (hwmr->remote_rd << OCRDMA_ALLOC_LKEY_REMOTE_RD_SHIFT);
1930 cmd->pbl_sz_flags |=
1931 (hwmr->local_wr << OCRDMA_ALLOC_LKEY_LOCAL_WR_SHIFT);
1932 cmd->pbl_sz_flags |=
1933 (hwmr->remote_atomic << OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_SHIFT);
1934 cmd->pbl_sz_flags |=
1935 (hwmr->num_pbls << OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT);
1936
1937 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1938 if (status)
1939 goto mbx_err;
1940 rsp = (struct ocrdma_alloc_lkey_rsp *)cmd;
1941 hwmr->lkey = rsp->lrkey;
1942 mbx_err:
1943 kfree(cmd);
1944 return status;
1945 }
1946
ocrdma_mbx_dealloc_lkey(struct ocrdma_dev * dev,int fr_mr,u32 lkey)1947 int ocrdma_mbx_dealloc_lkey(struct ocrdma_dev *dev, int fr_mr, u32 lkey)
1948 {
1949 int status;
1950 struct ocrdma_dealloc_lkey *cmd;
1951
1952 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DEALLOC_LKEY, sizeof(*cmd));
1953 if (!cmd)
1954 return -ENOMEM;
1955 cmd->lkey = lkey;
1956 cmd->rsvd_frmr = fr_mr ? 1 : 0;
1957 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
1958
1959 kfree(cmd);
1960 return status;
1961 }
1962
ocrdma_mbx_reg_mr(struct ocrdma_dev * dev,struct ocrdma_hw_mr * hwmr,u32 pdid,u32 pbl_cnt,u32 pbe_size,u32 last)1963 static int ocrdma_mbx_reg_mr(struct ocrdma_dev *dev, struct ocrdma_hw_mr *hwmr,
1964 u32 pdid, u32 pbl_cnt, u32 pbe_size, u32 last)
1965 {
1966 int status = -ENOMEM;
1967 int i;
1968 struct ocrdma_reg_nsmr *cmd;
1969 struct ocrdma_reg_nsmr_rsp *rsp;
1970
1971 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR, sizeof(*cmd));
1972 if (!cmd)
1973 return -ENOMEM;
1974 cmd->num_pbl_pdid =
1975 pdid | (hwmr->num_pbls << OCRDMA_REG_NSMR_NUM_PBL_SHIFT);
1976 cmd->fr_mr = hwmr->fr_mr;
1977
1978 cmd->flags_hpage_pbe_sz |= (hwmr->remote_wr <<
1979 OCRDMA_REG_NSMR_REMOTE_WR_SHIFT);
1980 cmd->flags_hpage_pbe_sz |= (hwmr->remote_rd <<
1981 OCRDMA_REG_NSMR_REMOTE_RD_SHIFT);
1982 cmd->flags_hpage_pbe_sz |= (hwmr->local_wr <<
1983 OCRDMA_REG_NSMR_LOCAL_WR_SHIFT);
1984 cmd->flags_hpage_pbe_sz |= (hwmr->remote_atomic <<
1985 OCRDMA_REG_NSMR_REMOTE_ATOMIC_SHIFT);
1986 cmd->flags_hpage_pbe_sz |= (hwmr->mw_bind <<
1987 OCRDMA_REG_NSMR_BIND_MEMWIN_SHIFT);
1988 cmd->flags_hpage_pbe_sz |= (last << OCRDMA_REG_NSMR_LAST_SHIFT);
1989
1990 cmd->flags_hpage_pbe_sz |= (hwmr->pbe_size / OCRDMA_MIN_HPAGE_SIZE);
1991 cmd->flags_hpage_pbe_sz |= (hwmr->pbl_size / OCRDMA_MIN_HPAGE_SIZE) <<
1992 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT;
1993 cmd->totlen_low = hwmr->len;
1994 cmd->totlen_high = upper_32_bits(hwmr->len);
1995 cmd->fbo_low = (u32) (hwmr->fbo & 0xffffffff);
1996 cmd->fbo_high = (u32) upper_32_bits(hwmr->fbo);
1997 cmd->va_loaddr = (u32) hwmr->va;
1998 cmd->va_hiaddr = (u32) upper_32_bits(hwmr->va);
1999
2000 for (i = 0; i < pbl_cnt; i++) {
2001 cmd->pbl[i].lo = (u32) (hwmr->pbl_table[i].pa & 0xffffffff);
2002 cmd->pbl[i].hi = upper_32_bits(hwmr->pbl_table[i].pa);
2003 }
2004 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2005 if (status)
2006 goto mbx_err;
2007 rsp = (struct ocrdma_reg_nsmr_rsp *)cmd;
2008 hwmr->lkey = rsp->lrkey;
2009 mbx_err:
2010 kfree(cmd);
2011 return status;
2012 }
2013
ocrdma_mbx_reg_mr_cont(struct ocrdma_dev * dev,struct ocrdma_hw_mr * hwmr,u32 pbl_cnt,u32 pbl_offset,u32 last)2014 static int ocrdma_mbx_reg_mr_cont(struct ocrdma_dev *dev,
2015 struct ocrdma_hw_mr *hwmr, u32 pbl_cnt,
2016 u32 pbl_offset, u32 last)
2017 {
2018 int status;
2019 int i;
2020 struct ocrdma_reg_nsmr_cont *cmd;
2021
2022 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_REGISTER_NSMR_CONT, sizeof(*cmd));
2023 if (!cmd)
2024 return -ENOMEM;
2025 cmd->lrkey = hwmr->lkey;
2026 cmd->num_pbl_offset = (pbl_cnt << OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT) |
2027 (pbl_offset & OCRDMA_REG_NSMR_CONT_PBL_SHIFT_MASK);
2028 cmd->last = last << OCRDMA_REG_NSMR_CONT_LAST_SHIFT;
2029
2030 for (i = 0; i < pbl_cnt; i++) {
2031 cmd->pbl[i].lo =
2032 (u32) (hwmr->pbl_table[i + pbl_offset].pa & 0xffffffff);
2033 cmd->pbl[i].hi =
2034 upper_32_bits(hwmr->pbl_table[i + pbl_offset].pa);
2035 }
2036 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2037
2038 kfree(cmd);
2039 return status;
2040 }
2041
ocrdma_reg_mr(struct ocrdma_dev * dev,struct ocrdma_hw_mr * hwmr,u32 pdid,int acc)2042 int ocrdma_reg_mr(struct ocrdma_dev *dev,
2043 struct ocrdma_hw_mr *hwmr, u32 pdid, int acc)
2044 {
2045 int status;
2046 u32 last = 0;
2047 u32 cur_pbl_cnt, pbl_offset;
2048 u32 pending_pbl_cnt = hwmr->num_pbls;
2049
2050 pbl_offset = 0;
2051 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
2052 if (cur_pbl_cnt == pending_pbl_cnt)
2053 last = 1;
2054
2055 status = ocrdma_mbx_reg_mr(dev, hwmr, pdid,
2056 cur_pbl_cnt, hwmr->pbe_size, last);
2057 if (status) {
2058 pr_err("%s() status=%d\n", __func__, status);
2059 return status;
2060 }
2061 /* if there is no more pbls to register then exit. */
2062 if (last)
2063 return 0;
2064
2065 while (!last) {
2066 pbl_offset += cur_pbl_cnt;
2067 pending_pbl_cnt -= cur_pbl_cnt;
2068 cur_pbl_cnt = min(pending_pbl_cnt, MAX_OCRDMA_NSMR_PBL);
2069 /* if we reach the end of the pbls, then need to set the last
2070 * bit, indicating no more pbls to register for this memory key.
2071 */
2072 if (cur_pbl_cnt == pending_pbl_cnt)
2073 last = 1;
2074
2075 status = ocrdma_mbx_reg_mr_cont(dev, hwmr, cur_pbl_cnt,
2076 pbl_offset, last);
2077 if (status)
2078 break;
2079 }
2080 if (status)
2081 pr_err("%s() err. status=%d\n", __func__, status);
2082
2083 return status;
2084 }
2085
ocrdma_is_qp_in_sq_flushlist(struct ocrdma_cq * cq,struct ocrdma_qp * qp)2086 bool ocrdma_is_qp_in_sq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
2087 {
2088 struct ocrdma_qp *tmp;
2089 bool found = false;
2090 list_for_each_entry(tmp, &cq->sq_head, sq_entry) {
2091 if (qp == tmp) {
2092 found = true;
2093 break;
2094 }
2095 }
2096 return found;
2097 }
2098
ocrdma_is_qp_in_rq_flushlist(struct ocrdma_cq * cq,struct ocrdma_qp * qp)2099 bool ocrdma_is_qp_in_rq_flushlist(struct ocrdma_cq *cq, struct ocrdma_qp *qp)
2100 {
2101 struct ocrdma_qp *tmp;
2102 bool found = false;
2103 list_for_each_entry(tmp, &cq->rq_head, rq_entry) {
2104 if (qp == tmp) {
2105 found = true;
2106 break;
2107 }
2108 }
2109 return found;
2110 }
2111
ocrdma_flush_qp(struct ocrdma_qp * qp)2112 void ocrdma_flush_qp(struct ocrdma_qp *qp)
2113 {
2114 bool found;
2115 unsigned long flags;
2116 struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
2117
2118 spin_lock_irqsave(&dev->flush_q_lock, flags);
2119 found = ocrdma_is_qp_in_sq_flushlist(qp->sq_cq, qp);
2120 if (!found)
2121 list_add_tail(&qp->sq_entry, &qp->sq_cq->sq_head);
2122 if (!qp->srq) {
2123 found = ocrdma_is_qp_in_rq_flushlist(qp->rq_cq, qp);
2124 if (!found)
2125 list_add_tail(&qp->rq_entry, &qp->rq_cq->rq_head);
2126 }
2127 spin_unlock_irqrestore(&dev->flush_q_lock, flags);
2128 }
2129
ocrdma_init_hwq_ptr(struct ocrdma_qp * qp)2130 static void ocrdma_init_hwq_ptr(struct ocrdma_qp *qp)
2131 {
2132 qp->sq.head = 0;
2133 qp->sq.tail = 0;
2134 qp->rq.head = 0;
2135 qp->rq.tail = 0;
2136 }
2137
ocrdma_qp_state_change(struct ocrdma_qp * qp,enum ib_qp_state new_ib_state,enum ib_qp_state * old_ib_state)2138 int ocrdma_qp_state_change(struct ocrdma_qp *qp, enum ib_qp_state new_ib_state,
2139 enum ib_qp_state *old_ib_state)
2140 {
2141 unsigned long flags;
2142 enum ocrdma_qp_state new_state;
2143 new_state = get_ocrdma_qp_state(new_ib_state);
2144
2145 /* sync with wqe and rqe posting */
2146 spin_lock_irqsave(&qp->q_lock, flags);
2147
2148 if (old_ib_state)
2149 *old_ib_state = get_ibqp_state(qp->state);
2150 if (new_state == qp->state) {
2151 spin_unlock_irqrestore(&qp->q_lock, flags);
2152 return 1;
2153 }
2154
2155
2156 if (new_state == OCRDMA_QPS_INIT) {
2157 ocrdma_init_hwq_ptr(qp);
2158 ocrdma_del_flush_qp(qp);
2159 } else if (new_state == OCRDMA_QPS_ERR) {
2160 ocrdma_flush_qp(qp);
2161 }
2162
2163 qp->state = new_state;
2164
2165 spin_unlock_irqrestore(&qp->q_lock, flags);
2166 return 0;
2167 }
2168
ocrdma_set_create_qp_mbx_access_flags(struct ocrdma_qp * qp)2169 static u32 ocrdma_set_create_qp_mbx_access_flags(struct ocrdma_qp *qp)
2170 {
2171 u32 flags = 0;
2172 if (qp->cap_flags & OCRDMA_QP_INB_RD)
2173 flags |= OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK;
2174 if (qp->cap_flags & OCRDMA_QP_INB_WR)
2175 flags |= OCRDMA_CREATE_QP_REQ_INB_WREN_MASK;
2176 if (qp->cap_flags & OCRDMA_QP_MW_BIND)
2177 flags |= OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK;
2178 if (qp->cap_flags & OCRDMA_QP_LKEY0)
2179 flags |= OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK;
2180 if (qp->cap_flags & OCRDMA_QP_FAST_REG)
2181 flags |= OCRDMA_CREATE_QP_REQ_FMR_EN_MASK;
2182 return flags;
2183 }
2184
ocrdma_set_create_qp_sq_cmd(struct ocrdma_create_qp_req * cmd,struct ib_qp_init_attr * attrs,struct ocrdma_qp * qp)2185 static int ocrdma_set_create_qp_sq_cmd(struct ocrdma_create_qp_req *cmd,
2186 struct ib_qp_init_attr *attrs,
2187 struct ocrdma_qp *qp)
2188 {
2189 int status;
2190 u32 len, hw_pages, hw_page_size;
2191 dma_addr_t pa;
2192 struct ocrdma_pd *pd = qp->pd;
2193 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2194 struct pci_dev *pdev = dev->nic_info.pdev;
2195 u32 max_wqe_allocated;
2196 u32 max_sges = attrs->cap.max_send_sge;
2197
2198 /* QP1 may exceed 127 */
2199 max_wqe_allocated = min_t(u32, attrs->cap.max_send_wr + 1,
2200 dev->attr.max_wqe);
2201
2202 status = ocrdma_build_q_conf(&max_wqe_allocated,
2203 dev->attr.wqe_size, &hw_pages, &hw_page_size);
2204 if (status) {
2205 pr_err("%s() req. max_send_wr=0x%x\n", __func__,
2206 max_wqe_allocated);
2207 return -EINVAL;
2208 }
2209 qp->sq.max_cnt = max_wqe_allocated;
2210 len = (hw_pages * hw_page_size);
2211
2212 qp->sq.va = dma_zalloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2213 if (!qp->sq.va)
2214 return -EINVAL;
2215 qp->sq.len = len;
2216 qp->sq.pa = pa;
2217 qp->sq.entry_size = dev->attr.wqe_size;
2218 ocrdma_build_q_pages(&cmd->wq_addr[0], hw_pages, pa, hw_page_size);
2219
2220 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2221 << OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT);
2222 cmd->num_wq_rq_pages |= (hw_pages <<
2223 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT) &
2224 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_MASK;
2225 cmd->max_sge_send_write |= (max_sges <<
2226 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT) &
2227 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_MASK;
2228 cmd->max_sge_send_write |= (max_sges <<
2229 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_SHIFT) &
2230 OCRDMA_CREATE_QP_REQ_MAX_SGE_WRITE_MASK;
2231 cmd->max_wqe_rqe |= (ilog2(qp->sq.max_cnt) <<
2232 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT) &
2233 OCRDMA_CREATE_QP_REQ_MAX_WQE_MASK;
2234 cmd->wqe_rqe_size |= (dev->attr.wqe_size <<
2235 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT) &
2236 OCRDMA_CREATE_QP_REQ_WQE_SIZE_MASK;
2237 return 0;
2238 }
2239
ocrdma_set_create_qp_rq_cmd(struct ocrdma_create_qp_req * cmd,struct ib_qp_init_attr * attrs,struct ocrdma_qp * qp)2240 static int ocrdma_set_create_qp_rq_cmd(struct ocrdma_create_qp_req *cmd,
2241 struct ib_qp_init_attr *attrs,
2242 struct ocrdma_qp *qp)
2243 {
2244 int status;
2245 u32 len, hw_pages, hw_page_size;
2246 dma_addr_t pa = 0;
2247 struct ocrdma_pd *pd = qp->pd;
2248 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2249 struct pci_dev *pdev = dev->nic_info.pdev;
2250 u32 max_rqe_allocated = attrs->cap.max_recv_wr + 1;
2251
2252 status = ocrdma_build_q_conf(&max_rqe_allocated, dev->attr.rqe_size,
2253 &hw_pages, &hw_page_size);
2254 if (status) {
2255 pr_err("%s() req. max_recv_wr=0x%x\n", __func__,
2256 attrs->cap.max_recv_wr + 1);
2257 return status;
2258 }
2259 qp->rq.max_cnt = max_rqe_allocated;
2260 len = (hw_pages * hw_page_size);
2261
2262 qp->rq.va = dma_zalloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2263 if (!qp->rq.va)
2264 return -ENOMEM;
2265 qp->rq.pa = pa;
2266 qp->rq.len = len;
2267 qp->rq.entry_size = dev->attr.rqe_size;
2268
2269 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2270 cmd->type_pgsz_pdn |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE) <<
2271 OCRDMA_CREATE_QP_REQ_RQ_PAGE_SIZE_SHIFT);
2272 cmd->num_wq_rq_pages |=
2273 (hw_pages << OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_SHIFT) &
2274 OCRDMA_CREATE_QP_REQ_NUM_RQ_PAGES_MASK;
2275 cmd->max_sge_recv_flags |= (attrs->cap.max_recv_sge <<
2276 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT) &
2277 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_MASK;
2278 cmd->max_wqe_rqe |= (ilog2(qp->rq.max_cnt) <<
2279 OCRDMA_CREATE_QP_REQ_MAX_RQE_SHIFT) &
2280 OCRDMA_CREATE_QP_REQ_MAX_RQE_MASK;
2281 cmd->wqe_rqe_size |= (dev->attr.rqe_size <<
2282 OCRDMA_CREATE_QP_REQ_RQE_SIZE_SHIFT) &
2283 OCRDMA_CREATE_QP_REQ_RQE_SIZE_MASK;
2284 return 0;
2285 }
2286
ocrdma_set_create_qp_dpp_cmd(struct ocrdma_create_qp_req * cmd,struct ocrdma_pd * pd,struct ocrdma_qp * qp,u8 enable_dpp_cq,u16 dpp_cq_id)2287 static void ocrdma_set_create_qp_dpp_cmd(struct ocrdma_create_qp_req *cmd,
2288 struct ocrdma_pd *pd,
2289 struct ocrdma_qp *qp,
2290 u8 enable_dpp_cq, u16 dpp_cq_id)
2291 {
2292 pd->num_dpp_qp--;
2293 qp->dpp_enabled = true;
2294 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
2295 if (!enable_dpp_cq)
2296 return;
2297 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK;
2298 cmd->dpp_credits_cqid = dpp_cq_id;
2299 cmd->dpp_credits_cqid |= OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT <<
2300 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT;
2301 }
2302
ocrdma_set_create_qp_ird_cmd(struct ocrdma_create_qp_req * cmd,struct ocrdma_qp * qp)2303 static int ocrdma_set_create_qp_ird_cmd(struct ocrdma_create_qp_req *cmd,
2304 struct ocrdma_qp *qp)
2305 {
2306 struct ocrdma_pd *pd = qp->pd;
2307 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2308 struct pci_dev *pdev = dev->nic_info.pdev;
2309 dma_addr_t pa = 0;
2310 int ird_page_size = dev->attr.ird_page_size;
2311 int ird_q_len = dev->attr.num_ird_pages * ird_page_size;
2312 struct ocrdma_hdr_wqe *rqe;
2313 int i = 0;
2314
2315 if (dev->attr.ird == 0)
2316 return 0;
2317
2318 qp->ird_q_va = dma_zalloc_coherent(&pdev->dev, ird_q_len, &pa,
2319 GFP_KERNEL);
2320 if (!qp->ird_q_va)
2321 return -ENOMEM;
2322 ocrdma_build_q_pages(&cmd->ird_addr[0], dev->attr.num_ird_pages,
2323 pa, ird_page_size);
2324 for (; i < ird_q_len / dev->attr.rqe_size; i++) {
2325 rqe = (struct ocrdma_hdr_wqe *)(qp->ird_q_va +
2326 (i * dev->attr.rqe_size));
2327 rqe->cw = 0;
2328 rqe->cw |= 2;
2329 rqe->cw |= (OCRDMA_TYPE_LKEY << OCRDMA_WQE_TYPE_SHIFT);
2330 rqe->cw |= (8 << OCRDMA_WQE_SIZE_SHIFT);
2331 rqe->cw |= (8 << OCRDMA_WQE_NXT_WQE_SIZE_SHIFT);
2332 }
2333 return 0;
2334 }
2335
ocrdma_get_create_qp_rsp(struct ocrdma_create_qp_rsp * rsp,struct ocrdma_qp * qp,struct ib_qp_init_attr * attrs,u16 * dpp_offset,u16 * dpp_credit_lmt)2336 static void ocrdma_get_create_qp_rsp(struct ocrdma_create_qp_rsp *rsp,
2337 struct ocrdma_qp *qp,
2338 struct ib_qp_init_attr *attrs,
2339 u16 *dpp_offset, u16 *dpp_credit_lmt)
2340 {
2341 u32 max_wqe_allocated, max_rqe_allocated;
2342 qp->id = rsp->qp_id & OCRDMA_CREATE_QP_RSP_QP_ID_MASK;
2343 qp->rq.dbid = rsp->sq_rq_id & OCRDMA_CREATE_QP_RSP_RQ_ID_MASK;
2344 qp->sq.dbid = rsp->sq_rq_id >> OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT;
2345 qp->max_ird = rsp->max_ord_ird & OCRDMA_CREATE_QP_RSP_MAX_IRD_MASK;
2346 qp->max_ord = (rsp->max_ord_ird >> OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT);
2347 qp->dpp_enabled = false;
2348 if (rsp->dpp_response & OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK) {
2349 qp->dpp_enabled = true;
2350 *dpp_credit_lmt = (rsp->dpp_response &
2351 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_MASK) >>
2352 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT;
2353 *dpp_offset = (rsp->dpp_response &
2354 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_MASK) >>
2355 OCRDMA_CREATE_QP_RSP_DPP_PAGE_OFFSET_SHIFT;
2356 }
2357 max_wqe_allocated =
2358 rsp->max_wqe_rqe >> OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT;
2359 max_wqe_allocated = 1 << max_wqe_allocated;
2360 max_rqe_allocated = 1 << ((u16)rsp->max_wqe_rqe);
2361
2362 qp->sq.max_cnt = max_wqe_allocated;
2363 qp->sq.max_wqe_idx = max_wqe_allocated - 1;
2364
2365 if (!attrs->srq) {
2366 qp->rq.max_cnt = max_rqe_allocated;
2367 qp->rq.max_wqe_idx = max_rqe_allocated - 1;
2368 }
2369 }
2370
ocrdma_mbx_create_qp(struct ocrdma_qp * qp,struct ib_qp_init_attr * attrs,u8 enable_dpp_cq,u16 dpp_cq_id,u16 * dpp_offset,u16 * dpp_credit_lmt)2371 int ocrdma_mbx_create_qp(struct ocrdma_qp *qp, struct ib_qp_init_attr *attrs,
2372 u8 enable_dpp_cq, u16 dpp_cq_id, u16 *dpp_offset,
2373 u16 *dpp_credit_lmt)
2374 {
2375 int status = -ENOMEM;
2376 u32 flags = 0;
2377 struct ocrdma_pd *pd = qp->pd;
2378 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2379 struct pci_dev *pdev = dev->nic_info.pdev;
2380 struct ocrdma_cq *cq;
2381 struct ocrdma_create_qp_req *cmd;
2382 struct ocrdma_create_qp_rsp *rsp;
2383 int qptype;
2384
2385 switch (attrs->qp_type) {
2386 case IB_QPT_GSI:
2387 qptype = OCRDMA_QPT_GSI;
2388 break;
2389 case IB_QPT_RC:
2390 qptype = OCRDMA_QPT_RC;
2391 break;
2392 case IB_QPT_UD:
2393 qptype = OCRDMA_QPT_UD;
2394 break;
2395 default:
2396 return -EINVAL;
2397 }
2398
2399 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_QP, sizeof(*cmd));
2400 if (!cmd)
2401 return status;
2402 cmd->type_pgsz_pdn |= (qptype << OCRDMA_CREATE_QP_REQ_QPT_SHIFT) &
2403 OCRDMA_CREATE_QP_REQ_QPT_MASK;
2404 status = ocrdma_set_create_qp_sq_cmd(cmd, attrs, qp);
2405 if (status)
2406 goto sq_err;
2407
2408 if (attrs->srq) {
2409 struct ocrdma_srq *srq = get_ocrdma_srq(attrs->srq);
2410 cmd->max_sge_recv_flags |= OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK;
2411 cmd->rq_addr[0].lo = srq->id;
2412 qp->srq = srq;
2413 } else {
2414 status = ocrdma_set_create_qp_rq_cmd(cmd, attrs, qp);
2415 if (status)
2416 goto rq_err;
2417 }
2418
2419 status = ocrdma_set_create_qp_ird_cmd(cmd, qp);
2420 if (status)
2421 goto mbx_err;
2422
2423 cmd->type_pgsz_pdn |= (pd->id << OCRDMA_CREATE_QP_REQ_PD_ID_SHIFT) &
2424 OCRDMA_CREATE_QP_REQ_PD_ID_MASK;
2425
2426 flags = ocrdma_set_create_qp_mbx_access_flags(qp);
2427
2428 cmd->max_sge_recv_flags |= flags;
2429 cmd->max_ord_ird |= (dev->attr.max_ord_per_qp <<
2430 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT) &
2431 OCRDMA_CREATE_QP_REQ_MAX_ORD_MASK;
2432 cmd->max_ord_ird |= (dev->attr.max_ird_per_qp <<
2433 OCRDMA_CREATE_QP_REQ_MAX_IRD_SHIFT) &
2434 OCRDMA_CREATE_QP_REQ_MAX_IRD_MASK;
2435 cq = get_ocrdma_cq(attrs->send_cq);
2436 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT) &
2437 OCRDMA_CREATE_QP_REQ_WQ_CQID_MASK;
2438 qp->sq_cq = cq;
2439 cq = get_ocrdma_cq(attrs->recv_cq);
2440 cmd->wq_rq_cqid |= (cq->id << OCRDMA_CREATE_QP_REQ_RQ_CQID_SHIFT) &
2441 OCRDMA_CREATE_QP_REQ_RQ_CQID_MASK;
2442 qp->rq_cq = cq;
2443
2444 if (pd->dpp_enabled && attrs->cap.max_inline_data && pd->num_dpp_qp &&
2445 (attrs->cap.max_inline_data <= dev->attr.max_inline_data)) {
2446 ocrdma_set_create_qp_dpp_cmd(cmd, pd, qp, enable_dpp_cq,
2447 dpp_cq_id);
2448 }
2449
2450 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2451 if (status)
2452 goto mbx_err;
2453 rsp = (struct ocrdma_create_qp_rsp *)cmd;
2454 ocrdma_get_create_qp_rsp(rsp, qp, attrs, dpp_offset, dpp_credit_lmt);
2455 qp->state = OCRDMA_QPS_RST;
2456 kfree(cmd);
2457 return 0;
2458 mbx_err:
2459 if (qp->rq.va)
2460 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2461 rq_err:
2462 pr_err("%s(%d) rq_err\n", __func__, dev->id);
2463 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2464 sq_err:
2465 pr_err("%s(%d) sq_err\n", __func__, dev->id);
2466 kfree(cmd);
2467 return status;
2468 }
2469
ocrdma_mbx_query_qp(struct ocrdma_dev * dev,struct ocrdma_qp * qp,struct ocrdma_qp_params * param)2470 int ocrdma_mbx_query_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2471 struct ocrdma_qp_params *param)
2472 {
2473 int status = -ENOMEM;
2474 struct ocrdma_query_qp *cmd;
2475 struct ocrdma_query_qp_rsp *rsp;
2476
2477 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_QP, sizeof(*rsp));
2478 if (!cmd)
2479 return status;
2480 cmd->qp_id = qp->id;
2481 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2482 if (status)
2483 goto mbx_err;
2484 rsp = (struct ocrdma_query_qp_rsp *)cmd;
2485 memcpy(param, &rsp->params, sizeof(struct ocrdma_qp_params));
2486 mbx_err:
2487 kfree(cmd);
2488 return status;
2489 }
2490
ocrdma_set_av_params(struct ocrdma_qp * qp,struct ocrdma_modify_qp * cmd,struct ib_qp_attr * attrs,int attr_mask)2491 static int ocrdma_set_av_params(struct ocrdma_qp *qp,
2492 struct ocrdma_modify_qp *cmd,
2493 struct ib_qp_attr *attrs,
2494 int attr_mask)
2495 {
2496 int status;
2497 struct rdma_ah_attr *ah_attr = &attrs->ah_attr;
2498 const struct ib_gid_attr *sgid_attr;
2499 u32 vlan_id = 0xFFFF;
2500 u8 mac_addr[6], hdr_type;
2501 union {
2502 struct sockaddr _sockaddr;
2503 struct sockaddr_in _sockaddr_in;
2504 struct sockaddr_in6 _sockaddr_in6;
2505 } sgid_addr, dgid_addr;
2506 struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
2507 const struct ib_global_route *grh;
2508
2509 if ((rdma_ah_get_ah_flags(ah_attr) & IB_AH_GRH) == 0)
2510 return -EINVAL;
2511 grh = rdma_ah_read_grh(ah_attr);
2512 if (atomic_cmpxchg(&dev->update_sl, 1, 0))
2513 ocrdma_init_service_level(dev);
2514 cmd->params.tclass_sq_psn |=
2515 (grh->traffic_class << OCRDMA_QP_PARAMS_TCLASS_SHIFT);
2516 cmd->params.rnt_rc_sl_fl |=
2517 (grh->flow_label & OCRDMA_QP_PARAMS_FLOW_LABEL_MASK);
2518 cmd->params.rnt_rc_sl_fl |= (rdma_ah_get_sl(ah_attr) <<
2519 OCRDMA_QP_PARAMS_SL_SHIFT);
2520 cmd->params.hop_lmt_rq_psn |=
2521 (grh->hop_limit << OCRDMA_QP_PARAMS_HOP_LMT_SHIFT);
2522 cmd->flags |= OCRDMA_QP_PARA_FLOW_LBL_VALID;
2523
2524 /* GIDs */
2525 memcpy(&cmd->params.dgid[0], &grh->dgid.raw[0],
2526 sizeof(cmd->params.dgid));
2527
2528 sgid_attr = ah_attr->grh.sgid_attr;
2529 vlan_id = rdma_vlan_dev_vlan_id(sgid_attr->ndev);
2530 memcpy(mac_addr, sgid_attr->ndev->dev_addr, ETH_ALEN);
2531
2532 qp->sgid_idx = grh->sgid_index;
2533 memcpy(&cmd->params.sgid[0], &sgid_attr->gid.raw[0],
2534 sizeof(cmd->params.sgid));
2535 status = ocrdma_resolve_dmac(dev, ah_attr, &mac_addr[0]);
2536 if (status)
2537 return status;
2538
2539 cmd->params.dmac_b0_to_b3 = mac_addr[0] | (mac_addr[1] << 8) |
2540 (mac_addr[2] << 16) | (mac_addr[3] << 24);
2541
2542 hdr_type = rdma_gid_attr_network_type(sgid_attr);
2543 if (hdr_type == RDMA_NETWORK_IPV4) {
2544 rdma_gid2ip(&sgid_addr._sockaddr, &sgid_attr->gid);
2545 rdma_gid2ip(&dgid_addr._sockaddr, &grh->dgid);
2546 memcpy(&cmd->params.dgid[0],
2547 &dgid_addr._sockaddr_in.sin_addr.s_addr, 4);
2548 memcpy(&cmd->params.sgid[0],
2549 &sgid_addr._sockaddr_in.sin_addr.s_addr, 4);
2550 }
2551 /* convert them to LE format. */
2552 ocrdma_cpu_to_le32(&cmd->params.dgid[0], sizeof(cmd->params.dgid));
2553 ocrdma_cpu_to_le32(&cmd->params.sgid[0], sizeof(cmd->params.sgid));
2554 cmd->params.vlan_dmac_b4_to_b5 = mac_addr[4] | (mac_addr[5] << 8);
2555
2556 if (vlan_id == 0xFFFF)
2557 vlan_id = 0;
2558 if (vlan_id || dev->pfc_state) {
2559 if (!vlan_id) {
2560 pr_err("ocrdma%d:Using VLAN with PFC is recommended\n",
2561 dev->id);
2562 pr_err("ocrdma%d:Using VLAN 0 for this connection\n",
2563 dev->id);
2564 }
2565 cmd->params.vlan_dmac_b4_to_b5 |=
2566 vlan_id << OCRDMA_QP_PARAMS_VLAN_SHIFT;
2567 cmd->flags |= OCRDMA_QP_PARA_VLAN_EN_VALID;
2568 cmd->params.rnt_rc_sl_fl |=
2569 (dev->sl & 0x07) << OCRDMA_QP_PARAMS_SL_SHIFT;
2570 }
2571 cmd->params.max_sge_recv_flags |= ((hdr_type <<
2572 OCRDMA_QP_PARAMS_FLAGS_L3_TYPE_SHIFT) &
2573 OCRDMA_QP_PARAMS_FLAGS_L3_TYPE_MASK);
2574 return 0;
2575 }
2576
ocrdma_set_qp_params(struct ocrdma_qp * qp,struct ocrdma_modify_qp * cmd,struct ib_qp_attr * attrs,int attr_mask)2577 static int ocrdma_set_qp_params(struct ocrdma_qp *qp,
2578 struct ocrdma_modify_qp *cmd,
2579 struct ib_qp_attr *attrs, int attr_mask)
2580 {
2581 int status = 0;
2582 struct ocrdma_dev *dev = get_ocrdma_dev(qp->ibqp.device);
2583
2584 if (attr_mask & IB_QP_PKEY_INDEX) {
2585 cmd->params.path_mtu_pkey_indx |= (attrs->pkey_index &
2586 OCRDMA_QP_PARAMS_PKEY_INDEX_MASK);
2587 cmd->flags |= OCRDMA_QP_PARA_PKEY_VALID;
2588 }
2589 if (attr_mask & IB_QP_QKEY) {
2590 qp->qkey = attrs->qkey;
2591 cmd->params.qkey = attrs->qkey;
2592 cmd->flags |= OCRDMA_QP_PARA_QKEY_VALID;
2593 }
2594 if (attr_mask & IB_QP_AV) {
2595 status = ocrdma_set_av_params(qp, cmd, attrs, attr_mask);
2596 if (status)
2597 return status;
2598 } else if (qp->qp_type == IB_QPT_GSI || qp->qp_type == IB_QPT_UD) {
2599 /* set the default mac address for UD, GSI QPs */
2600 cmd->params.dmac_b0_to_b3 = dev->nic_info.mac_addr[0] |
2601 (dev->nic_info.mac_addr[1] << 8) |
2602 (dev->nic_info.mac_addr[2] << 16) |
2603 (dev->nic_info.mac_addr[3] << 24);
2604 cmd->params.vlan_dmac_b4_to_b5 = dev->nic_info.mac_addr[4] |
2605 (dev->nic_info.mac_addr[5] << 8);
2606 }
2607 if ((attr_mask & IB_QP_EN_SQD_ASYNC_NOTIFY) &&
2608 attrs->en_sqd_async_notify) {
2609 cmd->params.max_sge_recv_flags |=
2610 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC;
2611 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2612 }
2613 if (attr_mask & IB_QP_DEST_QPN) {
2614 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->dest_qp_num &
2615 OCRDMA_QP_PARAMS_DEST_QPN_MASK);
2616 cmd->flags |= OCRDMA_QP_PARA_DST_QPN_VALID;
2617 }
2618 if (attr_mask & IB_QP_PATH_MTU) {
2619 if (attrs->path_mtu < IB_MTU_512 ||
2620 attrs->path_mtu > IB_MTU_4096) {
2621 pr_err("ocrdma%d: IB MTU %d is not supported\n",
2622 dev->id, ib_mtu_enum_to_int(attrs->path_mtu));
2623 status = -EINVAL;
2624 goto pmtu_err;
2625 }
2626 cmd->params.path_mtu_pkey_indx |=
2627 (ib_mtu_enum_to_int(attrs->path_mtu) <<
2628 OCRDMA_QP_PARAMS_PATH_MTU_SHIFT) &
2629 OCRDMA_QP_PARAMS_PATH_MTU_MASK;
2630 cmd->flags |= OCRDMA_QP_PARA_PMTU_VALID;
2631 }
2632 if (attr_mask & IB_QP_TIMEOUT) {
2633 cmd->params.ack_to_rnr_rtc_dest_qpn |= attrs->timeout <<
2634 OCRDMA_QP_PARAMS_ACK_TIMEOUT_SHIFT;
2635 cmd->flags |= OCRDMA_QP_PARA_ACK_TO_VALID;
2636 }
2637 if (attr_mask & IB_QP_RETRY_CNT) {
2638 cmd->params.rnt_rc_sl_fl |= (attrs->retry_cnt <<
2639 OCRDMA_QP_PARAMS_RETRY_CNT_SHIFT) &
2640 OCRDMA_QP_PARAMS_RETRY_CNT_MASK;
2641 cmd->flags |= OCRDMA_QP_PARA_RETRY_CNT_VALID;
2642 }
2643 if (attr_mask & IB_QP_MIN_RNR_TIMER) {
2644 cmd->params.rnt_rc_sl_fl |= (attrs->min_rnr_timer <<
2645 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_SHIFT) &
2646 OCRDMA_QP_PARAMS_RNR_NAK_TIMER_MASK;
2647 cmd->flags |= OCRDMA_QP_PARA_RNT_VALID;
2648 }
2649 if (attr_mask & IB_QP_RNR_RETRY) {
2650 cmd->params.ack_to_rnr_rtc_dest_qpn |= (attrs->rnr_retry <<
2651 OCRDMA_QP_PARAMS_RNR_RETRY_CNT_SHIFT)
2652 & OCRDMA_QP_PARAMS_RNR_RETRY_CNT_MASK;
2653 cmd->flags |= OCRDMA_QP_PARA_RRC_VALID;
2654 }
2655 if (attr_mask & IB_QP_SQ_PSN) {
2656 cmd->params.tclass_sq_psn |= (attrs->sq_psn & 0x00ffffff);
2657 cmd->flags |= OCRDMA_QP_PARA_SQPSN_VALID;
2658 }
2659 if (attr_mask & IB_QP_RQ_PSN) {
2660 cmd->params.hop_lmt_rq_psn |= (attrs->rq_psn & 0x00ffffff);
2661 cmd->flags |= OCRDMA_QP_PARA_RQPSN_VALID;
2662 }
2663 if (attr_mask & IB_QP_MAX_QP_RD_ATOMIC) {
2664 if (attrs->max_rd_atomic > dev->attr.max_ord_per_qp) {
2665 status = -EINVAL;
2666 goto pmtu_err;
2667 }
2668 qp->max_ord = attrs->max_rd_atomic;
2669 cmd->flags |= OCRDMA_QP_PARA_MAX_ORD_VALID;
2670 }
2671 if (attr_mask & IB_QP_MAX_DEST_RD_ATOMIC) {
2672 if (attrs->max_dest_rd_atomic > dev->attr.max_ird_per_qp) {
2673 status = -EINVAL;
2674 goto pmtu_err;
2675 }
2676 qp->max_ird = attrs->max_dest_rd_atomic;
2677 cmd->flags |= OCRDMA_QP_PARA_MAX_IRD_VALID;
2678 }
2679 cmd->params.max_ord_ird = (qp->max_ord <<
2680 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT) |
2681 (qp->max_ird & OCRDMA_QP_PARAMS_MAX_IRD_MASK);
2682 pmtu_err:
2683 return status;
2684 }
2685
ocrdma_mbx_modify_qp(struct ocrdma_dev * dev,struct ocrdma_qp * qp,struct ib_qp_attr * attrs,int attr_mask)2686 int ocrdma_mbx_modify_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp,
2687 struct ib_qp_attr *attrs, int attr_mask)
2688 {
2689 int status = -ENOMEM;
2690 struct ocrdma_modify_qp *cmd;
2691
2692 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_QP, sizeof(*cmd));
2693 if (!cmd)
2694 return status;
2695
2696 cmd->params.id = qp->id;
2697 cmd->flags = 0;
2698 if (attr_mask & IB_QP_STATE) {
2699 cmd->params.max_sge_recv_flags |=
2700 (get_ocrdma_qp_state(attrs->qp_state) <<
2701 OCRDMA_QP_PARAMS_STATE_SHIFT) &
2702 OCRDMA_QP_PARAMS_STATE_MASK;
2703 cmd->flags |= OCRDMA_QP_PARA_QPS_VALID;
2704 } else {
2705 cmd->params.max_sge_recv_flags |=
2706 (qp->state << OCRDMA_QP_PARAMS_STATE_SHIFT) &
2707 OCRDMA_QP_PARAMS_STATE_MASK;
2708 }
2709
2710 status = ocrdma_set_qp_params(qp, cmd, attrs, attr_mask);
2711 if (status)
2712 goto mbx_err;
2713 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2714 if (status)
2715 goto mbx_err;
2716
2717 mbx_err:
2718 kfree(cmd);
2719 return status;
2720 }
2721
ocrdma_mbx_destroy_qp(struct ocrdma_dev * dev,struct ocrdma_qp * qp)2722 int ocrdma_mbx_destroy_qp(struct ocrdma_dev *dev, struct ocrdma_qp *qp)
2723 {
2724 int status = -ENOMEM;
2725 struct ocrdma_destroy_qp *cmd;
2726 struct pci_dev *pdev = dev->nic_info.pdev;
2727
2728 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_QP, sizeof(*cmd));
2729 if (!cmd)
2730 return status;
2731 cmd->qp_id = qp->id;
2732 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2733 if (status)
2734 goto mbx_err;
2735
2736 mbx_err:
2737 kfree(cmd);
2738 if (qp->sq.va)
2739 dma_free_coherent(&pdev->dev, qp->sq.len, qp->sq.va, qp->sq.pa);
2740 if (!qp->srq && qp->rq.va)
2741 dma_free_coherent(&pdev->dev, qp->rq.len, qp->rq.va, qp->rq.pa);
2742 if (qp->dpp_enabled)
2743 qp->pd->num_dpp_qp++;
2744 return status;
2745 }
2746
ocrdma_mbx_create_srq(struct ocrdma_dev * dev,struct ocrdma_srq * srq,struct ib_srq_init_attr * srq_attr,struct ocrdma_pd * pd)2747 int ocrdma_mbx_create_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq,
2748 struct ib_srq_init_attr *srq_attr,
2749 struct ocrdma_pd *pd)
2750 {
2751 int status = -ENOMEM;
2752 int hw_pages, hw_page_size;
2753 int len;
2754 struct ocrdma_create_srq_rsp *rsp;
2755 struct ocrdma_create_srq *cmd;
2756 dma_addr_t pa;
2757 struct pci_dev *pdev = dev->nic_info.pdev;
2758 u32 max_rqe_allocated;
2759
2760 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_CREATE_SRQ, sizeof(*cmd));
2761 if (!cmd)
2762 return status;
2763
2764 cmd->pgsz_pdid = pd->id & OCRDMA_CREATE_SRQ_PD_ID_MASK;
2765 max_rqe_allocated = srq_attr->attr.max_wr + 1;
2766 status = ocrdma_build_q_conf(&max_rqe_allocated,
2767 dev->attr.rqe_size,
2768 &hw_pages, &hw_page_size);
2769 if (status) {
2770 pr_err("%s() req. max_wr=0x%x\n", __func__,
2771 srq_attr->attr.max_wr);
2772 status = -EINVAL;
2773 goto ret;
2774 }
2775 len = hw_pages * hw_page_size;
2776 srq->rq.va = dma_alloc_coherent(&pdev->dev, len, &pa, GFP_KERNEL);
2777 if (!srq->rq.va) {
2778 status = -ENOMEM;
2779 goto ret;
2780 }
2781 ocrdma_build_q_pages(&cmd->rq_addr[0], hw_pages, pa, hw_page_size);
2782
2783 srq->rq.entry_size = dev->attr.rqe_size;
2784 srq->rq.pa = pa;
2785 srq->rq.len = len;
2786 srq->rq.max_cnt = max_rqe_allocated;
2787
2788 cmd->max_sge_rqe = ilog2(max_rqe_allocated);
2789 cmd->max_sge_rqe |= srq_attr->attr.max_sge <<
2790 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT;
2791
2792 cmd->pgsz_pdid |= (ilog2(hw_page_size / OCRDMA_MIN_Q_PAGE_SIZE)
2793 << OCRDMA_CREATE_SRQ_PG_SZ_SHIFT);
2794 cmd->pages_rqe_sz |= (dev->attr.rqe_size
2795 << OCRDMA_CREATE_SRQ_RQE_SIZE_SHIFT)
2796 & OCRDMA_CREATE_SRQ_RQE_SIZE_MASK;
2797 cmd->pages_rqe_sz |= hw_pages << OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT;
2798
2799 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2800 if (status)
2801 goto mbx_err;
2802 rsp = (struct ocrdma_create_srq_rsp *)cmd;
2803 srq->id = rsp->id;
2804 srq->rq.dbid = rsp->id;
2805 max_rqe_allocated = ((rsp->max_sge_rqe_allocated &
2806 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_MASK) >>
2807 OCRDMA_CREATE_SRQ_RSP_MAX_RQE_ALLOCATED_SHIFT);
2808 max_rqe_allocated = (1 << max_rqe_allocated);
2809 srq->rq.max_cnt = max_rqe_allocated;
2810 srq->rq.max_wqe_idx = max_rqe_allocated - 1;
2811 srq->rq.max_sges = (rsp->max_sge_rqe_allocated &
2812 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_MASK) >>
2813 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT;
2814 goto ret;
2815 mbx_err:
2816 dma_free_coherent(&pdev->dev, srq->rq.len, srq->rq.va, pa);
2817 ret:
2818 kfree(cmd);
2819 return status;
2820 }
2821
ocrdma_mbx_modify_srq(struct ocrdma_srq * srq,struct ib_srq_attr * srq_attr)2822 int ocrdma_mbx_modify_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2823 {
2824 int status = -ENOMEM;
2825 struct ocrdma_modify_srq *cmd;
2826 struct ocrdma_pd *pd = srq->pd;
2827 struct ocrdma_dev *dev = get_ocrdma_dev(pd->ibpd.device);
2828
2829 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_SRQ, sizeof(*cmd));
2830 if (!cmd)
2831 return status;
2832 cmd->id = srq->id;
2833 cmd->limit_max_rqe |= srq_attr->srq_limit <<
2834 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT;
2835 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2836 kfree(cmd);
2837 return status;
2838 }
2839
ocrdma_mbx_query_srq(struct ocrdma_srq * srq,struct ib_srq_attr * srq_attr)2840 int ocrdma_mbx_query_srq(struct ocrdma_srq *srq, struct ib_srq_attr *srq_attr)
2841 {
2842 int status = -ENOMEM;
2843 struct ocrdma_query_srq *cmd;
2844 struct ocrdma_dev *dev = get_ocrdma_dev(srq->ibsrq.device);
2845
2846 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_QUERY_SRQ, sizeof(*cmd));
2847 if (!cmd)
2848 return status;
2849 cmd->id = srq->rq.dbid;
2850 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2851 if (status == 0) {
2852 struct ocrdma_query_srq_rsp *rsp =
2853 (struct ocrdma_query_srq_rsp *)cmd;
2854 srq_attr->max_sge =
2855 rsp->srq_lmt_max_sge &
2856 OCRDMA_QUERY_SRQ_RSP_MAX_SGE_RECV_MASK;
2857 srq_attr->max_wr =
2858 rsp->max_rqe_pdid >> OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT;
2859 srq_attr->srq_limit = rsp->srq_lmt_max_sge >>
2860 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT;
2861 }
2862 kfree(cmd);
2863 return status;
2864 }
2865
ocrdma_mbx_destroy_srq(struct ocrdma_dev * dev,struct ocrdma_srq * srq)2866 int ocrdma_mbx_destroy_srq(struct ocrdma_dev *dev, struct ocrdma_srq *srq)
2867 {
2868 int status = -ENOMEM;
2869 struct ocrdma_destroy_srq *cmd;
2870 struct pci_dev *pdev = dev->nic_info.pdev;
2871 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_DELETE_SRQ, sizeof(*cmd));
2872 if (!cmd)
2873 return status;
2874 cmd->id = srq->id;
2875 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
2876 if (srq->rq.va)
2877 dma_free_coherent(&pdev->dev, srq->rq.len,
2878 srq->rq.va, srq->rq.pa);
2879 kfree(cmd);
2880 return status;
2881 }
2882
ocrdma_mbx_get_dcbx_config(struct ocrdma_dev * dev,u32 ptype,struct ocrdma_dcbx_cfg * dcbxcfg)2883 static int ocrdma_mbx_get_dcbx_config(struct ocrdma_dev *dev, u32 ptype,
2884 struct ocrdma_dcbx_cfg *dcbxcfg)
2885 {
2886 int status;
2887 dma_addr_t pa;
2888 struct ocrdma_mqe cmd;
2889
2890 struct ocrdma_get_dcbx_cfg_req *req = NULL;
2891 struct ocrdma_get_dcbx_cfg_rsp *rsp = NULL;
2892 struct pci_dev *pdev = dev->nic_info.pdev;
2893 struct ocrdma_mqe_sge *mqe_sge = cmd.u.nonemb_req.sge;
2894
2895 memset(&cmd, 0, sizeof(struct ocrdma_mqe));
2896 cmd.hdr.pyld_len = max_t (u32, sizeof(struct ocrdma_get_dcbx_cfg_rsp),
2897 sizeof(struct ocrdma_get_dcbx_cfg_req));
2898 req = dma_alloc_coherent(&pdev->dev, cmd.hdr.pyld_len, &pa, GFP_KERNEL);
2899 if (!req) {
2900 status = -ENOMEM;
2901 goto mem_err;
2902 }
2903
2904 cmd.hdr.spcl_sge_cnt_emb |= (1 << OCRDMA_MQE_HDR_SGE_CNT_SHIFT) &
2905 OCRDMA_MQE_HDR_SGE_CNT_MASK;
2906 mqe_sge->pa_lo = (u32) (pa & 0xFFFFFFFFUL);
2907 mqe_sge->pa_hi = (u32) upper_32_bits(pa);
2908 mqe_sge->len = cmd.hdr.pyld_len;
2909
2910 memset(req, 0, sizeof(struct ocrdma_get_dcbx_cfg_req));
2911 ocrdma_init_mch(&req->hdr, OCRDMA_CMD_GET_DCBX_CONFIG,
2912 OCRDMA_SUBSYS_DCBX, cmd.hdr.pyld_len);
2913 req->param_type = ptype;
2914
2915 status = ocrdma_mbx_cmd(dev, &cmd);
2916 if (status)
2917 goto mbx_err;
2918
2919 rsp = (struct ocrdma_get_dcbx_cfg_rsp *)req;
2920 ocrdma_le32_to_cpu(rsp, sizeof(struct ocrdma_get_dcbx_cfg_rsp));
2921 memcpy(dcbxcfg, &rsp->cfg, sizeof(struct ocrdma_dcbx_cfg));
2922
2923 mbx_err:
2924 dma_free_coherent(&pdev->dev, cmd.hdr.pyld_len, req, pa);
2925 mem_err:
2926 return status;
2927 }
2928
2929 #define OCRDMA_MAX_SERVICE_LEVEL_INDEX 0x08
2930 #define OCRDMA_DEFAULT_SERVICE_LEVEL 0x05
2931
ocrdma_parse_dcbxcfg_rsp(struct ocrdma_dev * dev,int ptype,struct ocrdma_dcbx_cfg * dcbxcfg,u8 * srvc_lvl)2932 static int ocrdma_parse_dcbxcfg_rsp(struct ocrdma_dev *dev, int ptype,
2933 struct ocrdma_dcbx_cfg *dcbxcfg,
2934 u8 *srvc_lvl)
2935 {
2936 int status = -EINVAL, indx, slindx;
2937 int ventry_cnt;
2938 struct ocrdma_app_parameter *app_param;
2939 u8 valid, proto_sel;
2940 u8 app_prio, pfc_prio;
2941 u16 proto;
2942
2943 if (!(dcbxcfg->tcv_aev_opv_st & OCRDMA_DCBX_STATE_MASK)) {
2944 pr_info("%s ocrdma%d DCBX is disabled\n",
2945 dev_name(&dev->nic_info.pdev->dev), dev->id);
2946 goto out;
2947 }
2948
2949 if (!ocrdma_is_enabled_and_synced(dcbxcfg->pfc_state)) {
2950 pr_info("%s ocrdma%d priority flow control(%s) is %s%s\n",
2951 dev_name(&dev->nic_info.pdev->dev), dev->id,
2952 (ptype > 0 ? "operational" : "admin"),
2953 (dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_ENABLED) ?
2954 "enabled" : "disabled",
2955 (dcbxcfg->pfc_state & OCRDMA_STATE_FLAG_SYNC) ?
2956 "" : ", not sync'ed");
2957 goto out;
2958 } else {
2959 pr_info("%s ocrdma%d priority flow control is enabled and sync'ed\n",
2960 dev_name(&dev->nic_info.pdev->dev), dev->id);
2961 }
2962
2963 ventry_cnt = (dcbxcfg->tcv_aev_opv_st >>
2964 OCRDMA_DCBX_APP_ENTRY_SHIFT)
2965 & OCRDMA_DCBX_STATE_MASK;
2966
2967 for (indx = 0; indx < ventry_cnt; indx++) {
2968 app_param = &dcbxcfg->app_param[indx];
2969 valid = (app_param->valid_proto_app >>
2970 OCRDMA_APP_PARAM_VALID_SHIFT)
2971 & OCRDMA_APP_PARAM_VALID_MASK;
2972 proto_sel = (app_param->valid_proto_app
2973 >> OCRDMA_APP_PARAM_PROTO_SEL_SHIFT)
2974 & OCRDMA_APP_PARAM_PROTO_SEL_MASK;
2975 proto = app_param->valid_proto_app &
2976 OCRDMA_APP_PARAM_APP_PROTO_MASK;
2977
2978 if (
2979 valid && proto == ETH_P_IBOE &&
2980 proto_sel == OCRDMA_PROTO_SELECT_L2) {
2981 for (slindx = 0; slindx <
2982 OCRDMA_MAX_SERVICE_LEVEL_INDEX; slindx++) {
2983 app_prio = ocrdma_get_app_prio(
2984 (u8 *)app_param->app_prio,
2985 slindx);
2986 pfc_prio = ocrdma_get_pfc_prio(
2987 (u8 *)dcbxcfg->pfc_prio,
2988 slindx);
2989
2990 if (app_prio && pfc_prio) {
2991 *srvc_lvl = slindx;
2992 status = 0;
2993 goto out;
2994 }
2995 }
2996 if (slindx == OCRDMA_MAX_SERVICE_LEVEL_INDEX) {
2997 pr_info("%s ocrdma%d application priority not set for 0x%x protocol\n",
2998 dev_name(&dev->nic_info.pdev->dev),
2999 dev->id, proto);
3000 }
3001 }
3002 }
3003
3004 out:
3005 return status;
3006 }
3007
ocrdma_init_service_level(struct ocrdma_dev * dev)3008 void ocrdma_init_service_level(struct ocrdma_dev *dev)
3009 {
3010 int status = 0, indx;
3011 struct ocrdma_dcbx_cfg dcbxcfg;
3012 u8 srvc_lvl = OCRDMA_DEFAULT_SERVICE_LEVEL;
3013 int ptype = OCRDMA_PARAMETER_TYPE_OPER;
3014
3015 for (indx = 0; indx < 2; indx++) {
3016 status = ocrdma_mbx_get_dcbx_config(dev, ptype, &dcbxcfg);
3017 if (status) {
3018 pr_err("%s(): status=%d\n", __func__, status);
3019 ptype = OCRDMA_PARAMETER_TYPE_ADMIN;
3020 continue;
3021 }
3022
3023 status = ocrdma_parse_dcbxcfg_rsp(dev, ptype,
3024 &dcbxcfg, &srvc_lvl);
3025 if (status) {
3026 ptype = OCRDMA_PARAMETER_TYPE_ADMIN;
3027 continue;
3028 }
3029
3030 break;
3031 }
3032
3033 if (status)
3034 pr_info("%s ocrdma%d service level default\n",
3035 dev_name(&dev->nic_info.pdev->dev), dev->id);
3036 else
3037 pr_info("%s ocrdma%d service level %d\n",
3038 dev_name(&dev->nic_info.pdev->dev), dev->id,
3039 srvc_lvl);
3040
3041 dev->pfc_state = ocrdma_is_enabled_and_synced(dcbxcfg.pfc_state);
3042 dev->sl = srvc_lvl;
3043 }
3044
ocrdma_alloc_av(struct ocrdma_dev * dev,struct ocrdma_ah * ah)3045 int ocrdma_alloc_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
3046 {
3047 int i;
3048 int status = -EINVAL;
3049 struct ocrdma_av *av;
3050 unsigned long flags;
3051
3052 av = dev->av_tbl.va;
3053 spin_lock_irqsave(&dev->av_tbl.lock, flags);
3054 for (i = 0; i < dev->av_tbl.num_ah; i++) {
3055 if (av->valid == 0) {
3056 av->valid = OCRDMA_AV_VALID;
3057 ah->av = av;
3058 ah->id = i;
3059 status = 0;
3060 break;
3061 }
3062 av++;
3063 }
3064 if (i == dev->av_tbl.num_ah)
3065 status = -EAGAIN;
3066 spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
3067 return status;
3068 }
3069
ocrdma_free_av(struct ocrdma_dev * dev,struct ocrdma_ah * ah)3070 int ocrdma_free_av(struct ocrdma_dev *dev, struct ocrdma_ah *ah)
3071 {
3072 unsigned long flags;
3073 spin_lock_irqsave(&dev->av_tbl.lock, flags);
3074 ah->av->valid = 0;
3075 spin_unlock_irqrestore(&dev->av_tbl.lock, flags);
3076 return 0;
3077 }
3078
ocrdma_create_eqs(struct ocrdma_dev * dev)3079 static int ocrdma_create_eqs(struct ocrdma_dev *dev)
3080 {
3081 int num_eq, i, status = 0;
3082 int irq;
3083 unsigned long flags = 0;
3084
3085 num_eq = dev->nic_info.msix.num_vectors -
3086 dev->nic_info.msix.start_vector;
3087 if (dev->nic_info.intr_mode == BE_INTERRUPT_MODE_INTX) {
3088 num_eq = 1;
3089 flags = IRQF_SHARED;
3090 } else {
3091 num_eq = min_t(u32, num_eq, num_online_cpus());
3092 }
3093
3094 if (!num_eq)
3095 return -EINVAL;
3096
3097 dev->eq_tbl = kcalloc(num_eq, sizeof(struct ocrdma_eq), GFP_KERNEL);
3098 if (!dev->eq_tbl)
3099 return -ENOMEM;
3100
3101 for (i = 0; i < num_eq; i++) {
3102 status = ocrdma_create_eq(dev, &dev->eq_tbl[i],
3103 OCRDMA_EQ_LEN);
3104 if (status) {
3105 status = -EINVAL;
3106 break;
3107 }
3108 sprintf(dev->eq_tbl[i].irq_name, "ocrdma%d-%d",
3109 dev->id, i);
3110 irq = ocrdma_get_irq(dev, &dev->eq_tbl[i]);
3111 status = request_irq(irq, ocrdma_irq_handler, flags,
3112 dev->eq_tbl[i].irq_name,
3113 &dev->eq_tbl[i]);
3114 if (status)
3115 goto done;
3116 dev->eq_cnt += 1;
3117 }
3118 /* one eq is sufficient for data path to work */
3119 return 0;
3120 done:
3121 ocrdma_destroy_eqs(dev);
3122 return status;
3123 }
3124
ocrdma_mbx_modify_eqd(struct ocrdma_dev * dev,struct ocrdma_eq * eq,int num)3125 static int ocrdma_mbx_modify_eqd(struct ocrdma_dev *dev, struct ocrdma_eq *eq,
3126 int num)
3127 {
3128 int i, status;
3129 struct ocrdma_modify_eqd_req *cmd;
3130
3131 cmd = ocrdma_init_emb_mqe(OCRDMA_CMD_MODIFY_EQ_DELAY, sizeof(*cmd));
3132 if (!cmd)
3133 return -ENOMEM;
3134
3135 ocrdma_init_mch(&cmd->cmd.req, OCRDMA_CMD_MODIFY_EQ_DELAY,
3136 OCRDMA_SUBSYS_COMMON, sizeof(*cmd));
3137
3138 cmd->cmd.num_eq = num;
3139 for (i = 0; i < num; i++) {
3140 cmd->cmd.set_eqd[i].eq_id = eq[i].q.id;
3141 cmd->cmd.set_eqd[i].phase = 0;
3142 cmd->cmd.set_eqd[i].delay_multiplier =
3143 (eq[i].aic_obj.prev_eqd * 65)/100;
3144 }
3145 status = ocrdma_mbx_cmd(dev, (struct ocrdma_mqe *)cmd);
3146
3147 kfree(cmd);
3148 return status;
3149 }
3150
ocrdma_modify_eqd(struct ocrdma_dev * dev,struct ocrdma_eq * eq,int num)3151 static int ocrdma_modify_eqd(struct ocrdma_dev *dev, struct ocrdma_eq *eq,
3152 int num)
3153 {
3154 int num_eqs, i = 0;
3155 if (num > 8) {
3156 while (num) {
3157 num_eqs = min(num, 8);
3158 ocrdma_mbx_modify_eqd(dev, &eq[i], num_eqs);
3159 i += num_eqs;
3160 num -= num_eqs;
3161 }
3162 } else {
3163 ocrdma_mbx_modify_eqd(dev, eq, num);
3164 }
3165 return 0;
3166 }
3167
ocrdma_eqd_set_task(struct work_struct * work)3168 void ocrdma_eqd_set_task(struct work_struct *work)
3169 {
3170 struct ocrdma_dev *dev =
3171 container_of(work, struct ocrdma_dev, eqd_work.work);
3172 struct ocrdma_eq *eq = NULL;
3173 int i, num = 0;
3174 u64 eq_intr;
3175
3176 for (i = 0; i < dev->eq_cnt; i++) {
3177 eq = &dev->eq_tbl[i];
3178 if (eq->aic_obj.eq_intr_cnt > eq->aic_obj.prev_eq_intr_cnt) {
3179 eq_intr = eq->aic_obj.eq_intr_cnt -
3180 eq->aic_obj.prev_eq_intr_cnt;
3181 if ((eq_intr > EQ_INTR_PER_SEC_THRSH_HI) &&
3182 (eq->aic_obj.prev_eqd == EQ_AIC_MIN_EQD)) {
3183 eq->aic_obj.prev_eqd = EQ_AIC_MAX_EQD;
3184 num++;
3185 } else if ((eq_intr < EQ_INTR_PER_SEC_THRSH_LOW) &&
3186 (eq->aic_obj.prev_eqd == EQ_AIC_MAX_EQD)) {
3187 eq->aic_obj.prev_eqd = EQ_AIC_MIN_EQD;
3188 num++;
3189 }
3190 }
3191 eq->aic_obj.prev_eq_intr_cnt = eq->aic_obj.eq_intr_cnt;
3192 }
3193
3194 if (num)
3195 ocrdma_modify_eqd(dev, &dev->eq_tbl[0], num);
3196 schedule_delayed_work(&dev->eqd_work, msecs_to_jiffies(1000));
3197 }
3198
ocrdma_init_hw(struct ocrdma_dev * dev)3199 int ocrdma_init_hw(struct ocrdma_dev *dev)
3200 {
3201 int status;
3202
3203 /* create the eqs */
3204 status = ocrdma_create_eqs(dev);
3205 if (status)
3206 goto qpeq_err;
3207 status = ocrdma_create_mq(dev);
3208 if (status)
3209 goto mq_err;
3210 status = ocrdma_mbx_query_fw_config(dev);
3211 if (status)
3212 goto conf_err;
3213 status = ocrdma_mbx_query_dev(dev);
3214 if (status)
3215 goto conf_err;
3216 status = ocrdma_mbx_query_fw_ver(dev);
3217 if (status)
3218 goto conf_err;
3219 status = ocrdma_mbx_create_ah_tbl(dev);
3220 if (status)
3221 goto conf_err;
3222 status = ocrdma_mbx_get_phy_info(dev);
3223 if (status)
3224 goto info_attrb_err;
3225 status = ocrdma_mbx_get_ctrl_attribs(dev);
3226 if (status)
3227 goto info_attrb_err;
3228
3229 return 0;
3230
3231 info_attrb_err:
3232 ocrdma_mbx_delete_ah_tbl(dev);
3233 conf_err:
3234 ocrdma_destroy_mq(dev);
3235 mq_err:
3236 ocrdma_destroy_eqs(dev);
3237 qpeq_err:
3238 pr_err("%s() status=%d\n", __func__, status);
3239 return status;
3240 }
3241
ocrdma_cleanup_hw(struct ocrdma_dev * dev)3242 void ocrdma_cleanup_hw(struct ocrdma_dev *dev)
3243 {
3244 ocrdma_free_pd_pool(dev);
3245 ocrdma_mbx_delete_ah_tbl(dev);
3246
3247 /* cleanup the control path */
3248 ocrdma_destroy_mq(dev);
3249
3250 /* cleanup the eqs */
3251 ocrdma_destroy_eqs(dev);
3252 }
3253
