1 /*
2 * Copyright (c) 2016 Hisilicon Limited.
3 * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
4 *
5 * This software is available to you under a choice of one of two
6 * licenses. You may choose to be licensed under the terms of the GNU
7 * General Public License (GPL) Version 2, available from the file
8 * COPYING in the main directory of this source tree, or the
9 * OpenIB.org BSD license below:
10 *
11 * Redistribution and use in source and binary forms, with or
12 * without modification, are permitted provided that the following
13 * conditions are met:
14 *
15 * - Redistributions of source code must retain the above
16 * copyright notice, this list of conditions and the following
17 * disclaimer.
18 *
19 * - Redistributions in binary form must reproduce the above
20 * copyright notice, this list of conditions and the following
21 * disclaimer in the documentation and/or other materials
22 * provided with the distribution.
23 *
24 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
25 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
26 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
27 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
28 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
29 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
30 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
31 * SOFTWARE.
32 */
33 #include <linux/acpi.h>
34 #include <linux/of_platform.h>
35 #include <linux/module.h>
36 #include <rdma/ib_addr.h>
37 #include <rdma/ib_smi.h>
38 #include <rdma/ib_user_verbs.h>
39 #include <rdma/ib_cache.h>
40 #include "hns_roce_common.h"
41 #include "hns_roce_device.h"
42 #include <rdma/hns-abi.h>
43 #include "hns_roce_hem.h"
44
45 /**
46 * hns_get_gid_index - Get gid index.
47 * @hr_dev: pointer to structure hns_roce_dev.
48 * @port: port, value range: 0 ~ MAX
49 * @gid_index: gid_index, value range: 0 ~ MAX
50 * Description:
51 * N ports shared gids, allocation method as follow:
52 * GID[0][0], GID[1][0],.....GID[N - 1][0],
53 * GID[0][0], GID[1][0],.....GID[N - 1][0],
54 * And so on
55 */
hns_get_gid_index(struct hns_roce_dev * hr_dev,u8 port,int gid_index)56 int hns_get_gid_index(struct hns_roce_dev *hr_dev, u8 port, int gid_index)
57 {
58 return gid_index * hr_dev->caps.num_ports + port;
59 }
60 EXPORT_SYMBOL_GPL(hns_get_gid_index);
61
hns_roce_set_mac(struct hns_roce_dev * hr_dev,u8 port,u8 * addr)62 static int hns_roce_set_mac(struct hns_roce_dev *hr_dev, u8 port, u8 *addr)
63 {
64 u8 phy_port;
65 u32 i = 0;
66
67 if (!memcmp(hr_dev->dev_addr[port], addr, MAC_ADDR_OCTET_NUM))
68 return 0;
69
70 for (i = 0; i < MAC_ADDR_OCTET_NUM; i++)
71 hr_dev->dev_addr[port][i] = addr[i];
72
73 phy_port = hr_dev->iboe.phy_port[port];
74 return hr_dev->hw->set_mac(hr_dev, phy_port, addr);
75 }
76
hns_roce_add_gid(const struct ib_gid_attr * attr,void ** context)77 static int hns_roce_add_gid(const struct ib_gid_attr *attr, void **context)
78 {
79 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
80 u8 port = attr->port_num - 1;
81 unsigned long flags;
82 int ret;
83
84 if (port >= hr_dev->caps.num_ports)
85 return -EINVAL;
86
87 spin_lock_irqsave(&hr_dev->iboe.lock, flags);
88
89 ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &attr->gid, attr);
90
91 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
92
93 return ret;
94 }
95
hns_roce_del_gid(const struct ib_gid_attr * attr,void ** context)96 static int hns_roce_del_gid(const struct ib_gid_attr *attr, void **context)
97 {
98 struct hns_roce_dev *hr_dev = to_hr_dev(attr->device);
99 struct ib_gid_attr zattr = { };
100 u8 port = attr->port_num - 1;
101 unsigned long flags;
102 int ret;
103
104 if (port >= hr_dev->caps.num_ports)
105 return -EINVAL;
106
107 spin_lock_irqsave(&hr_dev->iboe.lock, flags);
108
109 ret = hr_dev->hw->set_gid(hr_dev, port, attr->index, &zgid, &zattr);
110
111 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
112
113 return ret;
114 }
115
handle_en_event(struct hns_roce_dev * hr_dev,u8 port,unsigned long event)116 static int handle_en_event(struct hns_roce_dev *hr_dev, u8 port,
117 unsigned long event)
118 {
119 struct device *dev = hr_dev->dev;
120 struct net_device *netdev;
121 int ret = 0;
122
123 netdev = hr_dev->iboe.netdevs[port];
124 if (!netdev) {
125 dev_err(dev, "port(%d) can't find netdev\n", port);
126 return -ENODEV;
127 }
128
129 switch (event) {
130 case NETDEV_UP:
131 case NETDEV_CHANGE:
132 case NETDEV_REGISTER:
133 case NETDEV_CHANGEADDR:
134 ret = hns_roce_set_mac(hr_dev, port, netdev->dev_addr);
135 break;
136 case NETDEV_DOWN:
137 /*
138 * In v1 engine, only support all ports closed together.
139 */
140 break;
141 default:
142 dev_dbg(dev, "NETDEV event = 0x%x!\n", (u32)(event));
143 break;
144 }
145
146 return ret;
147 }
148
hns_roce_netdev_event(struct notifier_block * self,unsigned long event,void * ptr)149 static int hns_roce_netdev_event(struct notifier_block *self,
150 unsigned long event, void *ptr)
151 {
152 struct net_device *dev = netdev_notifier_info_to_dev(ptr);
153 struct hns_roce_ib_iboe *iboe = NULL;
154 struct hns_roce_dev *hr_dev = NULL;
155 u8 port = 0;
156 int ret = 0;
157
158 hr_dev = container_of(self, struct hns_roce_dev, iboe.nb);
159 iboe = &hr_dev->iboe;
160
161 for (port = 0; port < hr_dev->caps.num_ports; port++) {
162 if (dev == iboe->netdevs[port]) {
163 ret = handle_en_event(hr_dev, port, event);
164 if (ret)
165 return NOTIFY_DONE;
166 break;
167 }
168 }
169
170 return NOTIFY_DONE;
171 }
172
hns_roce_setup_mtu_mac(struct hns_roce_dev * hr_dev)173 static int hns_roce_setup_mtu_mac(struct hns_roce_dev *hr_dev)
174 {
175 int ret;
176 u8 i;
177
178 for (i = 0; i < hr_dev->caps.num_ports; i++) {
179 if (hr_dev->hw->set_mtu)
180 hr_dev->hw->set_mtu(hr_dev, hr_dev->iboe.phy_port[i],
181 hr_dev->caps.max_mtu);
182 ret = hns_roce_set_mac(hr_dev, i,
183 hr_dev->iboe.netdevs[i]->dev_addr);
184 if (ret)
185 return ret;
186 }
187
188 return 0;
189 }
190
hns_roce_query_device(struct ib_device * ib_dev,struct ib_device_attr * props,struct ib_udata * uhw)191 static int hns_roce_query_device(struct ib_device *ib_dev,
192 struct ib_device_attr *props,
193 struct ib_udata *uhw)
194 {
195 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
196
197 memset(props, 0, sizeof(*props));
198
199 props->sys_image_guid = cpu_to_be64(hr_dev->sys_image_guid);
200 props->max_mr_size = (u64)(~(0ULL));
201 props->page_size_cap = hr_dev->caps.page_size_cap;
202 props->vendor_id = hr_dev->vendor_id;
203 props->vendor_part_id = hr_dev->vendor_part_id;
204 props->hw_ver = hr_dev->hw_rev;
205 props->max_qp = hr_dev->caps.num_qps;
206 props->max_qp_wr = hr_dev->caps.max_wqes;
207 props->device_cap_flags = IB_DEVICE_PORT_ACTIVE_EVENT |
208 IB_DEVICE_RC_RNR_NAK_GEN;
209 props->max_send_sge = hr_dev->caps.max_sq_sg;
210 props->max_recv_sge = hr_dev->caps.max_rq_sg;
211 props->max_sge_rd = 1;
212 props->max_cq = hr_dev->caps.num_cqs;
213 props->max_cqe = hr_dev->caps.max_cqes;
214 props->max_mr = hr_dev->caps.num_mtpts;
215 props->max_pd = hr_dev->caps.num_pds;
216 props->max_qp_rd_atom = hr_dev->caps.max_qp_dest_rdma;
217 props->max_qp_init_rd_atom = hr_dev->caps.max_qp_init_rdma;
218 props->atomic_cap = IB_ATOMIC_NONE;
219 props->max_pkeys = 1;
220 props->local_ca_ack_delay = hr_dev->caps.local_ca_ack_delay;
221
222 return 0;
223 }
224
hns_roce_get_netdev(struct ib_device * ib_dev,u8 port_num)225 static struct net_device *hns_roce_get_netdev(struct ib_device *ib_dev,
226 u8 port_num)
227 {
228 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
229 struct net_device *ndev;
230
231 if (port_num < 1 || port_num > hr_dev->caps.num_ports)
232 return NULL;
233
234 rcu_read_lock();
235
236 ndev = hr_dev->iboe.netdevs[port_num - 1];
237 if (ndev)
238 dev_hold(ndev);
239
240 rcu_read_unlock();
241 return ndev;
242 }
243
hns_roce_query_port(struct ib_device * ib_dev,u8 port_num,struct ib_port_attr * props)244 static int hns_roce_query_port(struct ib_device *ib_dev, u8 port_num,
245 struct ib_port_attr *props)
246 {
247 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
248 struct device *dev = hr_dev->dev;
249 struct net_device *net_dev;
250 unsigned long flags;
251 enum ib_mtu mtu;
252 u8 port;
253
254 assert(port_num > 0);
255 port = port_num - 1;
256
257 /* props being zeroed by the caller, avoid zeroing it here */
258
259 props->max_mtu = hr_dev->caps.max_mtu;
260 props->gid_tbl_len = hr_dev->caps.gid_table_len[port];
261 props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_REINIT_SUP |
262 IB_PORT_VENDOR_CLASS_SUP |
263 IB_PORT_BOOT_MGMT_SUP;
264 props->max_msg_sz = HNS_ROCE_MAX_MSG_LEN;
265 props->pkey_tbl_len = 1;
266 props->active_width = IB_WIDTH_4X;
267 props->active_speed = 1;
268
269 spin_lock_irqsave(&hr_dev->iboe.lock, flags);
270
271 net_dev = hr_dev->iboe.netdevs[port];
272 if (!net_dev) {
273 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
274 dev_err(dev, "find netdev %d failed!\r\n", port);
275 return -EINVAL;
276 }
277
278 mtu = iboe_get_mtu(net_dev->mtu);
279 props->active_mtu = mtu ? min(props->max_mtu, mtu) : IB_MTU_256;
280 props->state = (netif_running(net_dev) && netif_carrier_ok(net_dev)) ?
281 IB_PORT_ACTIVE : IB_PORT_DOWN;
282 props->phys_state = (props->state == IB_PORT_ACTIVE) ? 5 : 3;
283
284 spin_unlock_irqrestore(&hr_dev->iboe.lock, flags);
285
286 return 0;
287 }
288
hns_roce_get_link_layer(struct ib_device * device,u8 port_num)289 static enum rdma_link_layer hns_roce_get_link_layer(struct ib_device *device,
290 u8 port_num)
291 {
292 return IB_LINK_LAYER_ETHERNET;
293 }
294
hns_roce_query_pkey(struct ib_device * ib_dev,u8 port,u16 index,u16 * pkey)295 static int hns_roce_query_pkey(struct ib_device *ib_dev, u8 port, u16 index,
296 u16 *pkey)
297 {
298 *pkey = PKEY_ID;
299
300 return 0;
301 }
302
hns_roce_modify_device(struct ib_device * ib_dev,int mask,struct ib_device_modify * props)303 static int hns_roce_modify_device(struct ib_device *ib_dev, int mask,
304 struct ib_device_modify *props)
305 {
306 unsigned long flags;
307
308 if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
309 return -EOPNOTSUPP;
310
311 if (mask & IB_DEVICE_MODIFY_NODE_DESC) {
312 spin_lock_irqsave(&to_hr_dev(ib_dev)->sm_lock, flags);
313 memcpy(ib_dev->node_desc, props->node_desc, NODE_DESC_SIZE);
314 spin_unlock_irqrestore(&to_hr_dev(ib_dev)->sm_lock, flags);
315 }
316
317 return 0;
318 }
319
hns_roce_modify_port(struct ib_device * ib_dev,u8 port_num,int mask,struct ib_port_modify * props)320 static int hns_roce_modify_port(struct ib_device *ib_dev, u8 port_num, int mask,
321 struct ib_port_modify *props)
322 {
323 return 0;
324 }
325
hns_roce_alloc_ucontext(struct ib_device * ib_dev,struct ib_udata * udata)326 static struct ib_ucontext *hns_roce_alloc_ucontext(struct ib_device *ib_dev,
327 struct ib_udata *udata)
328 {
329 int ret = 0;
330 struct hns_roce_ucontext *context;
331 struct hns_roce_ib_alloc_ucontext_resp resp = {};
332 struct hns_roce_dev *hr_dev = to_hr_dev(ib_dev);
333
334 if (!hr_dev->active)
335 return ERR_PTR(-EAGAIN);
336
337 resp.qp_tab_size = hr_dev->caps.num_qps;
338
339 context = kmalloc(sizeof(*context), GFP_KERNEL);
340 if (!context)
341 return ERR_PTR(-ENOMEM);
342
343 ret = hns_roce_uar_alloc(hr_dev, &context->uar);
344 if (ret)
345 goto error_fail_uar_alloc;
346
347 INIT_LIST_HEAD(&context->vma_list);
348 mutex_init(&context->vma_list_mutex);
349 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) {
350 INIT_LIST_HEAD(&context->page_list);
351 mutex_init(&context->page_mutex);
352 }
353
354 ret = ib_copy_to_udata(udata, &resp, sizeof(resp));
355 if (ret)
356 goto error_fail_copy_to_udata;
357
358 return &context->ibucontext;
359
360 error_fail_copy_to_udata:
361 hns_roce_uar_free(hr_dev, &context->uar);
362
363 error_fail_uar_alloc:
364 kfree(context);
365
366 return ERR_PTR(ret);
367 }
368
hns_roce_dealloc_ucontext(struct ib_ucontext * ibcontext)369 static int hns_roce_dealloc_ucontext(struct ib_ucontext *ibcontext)
370 {
371 struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
372
373 hns_roce_uar_free(to_hr_dev(ibcontext->device), &context->uar);
374 kfree(context);
375
376 return 0;
377 }
378
hns_roce_vma_open(struct vm_area_struct * vma)379 static void hns_roce_vma_open(struct vm_area_struct *vma)
380 {
381 vma->vm_ops = NULL;
382 }
383
hns_roce_vma_close(struct vm_area_struct * vma)384 static void hns_roce_vma_close(struct vm_area_struct *vma)
385 {
386 struct hns_roce_vma_data *vma_data;
387
388 vma_data = (struct hns_roce_vma_data *)vma->vm_private_data;
389 vma_data->vma = NULL;
390 mutex_lock(vma_data->vma_list_mutex);
391 list_del(&vma_data->list);
392 mutex_unlock(vma_data->vma_list_mutex);
393 kfree(vma_data);
394 }
395
396 static const struct vm_operations_struct hns_roce_vm_ops = {
397 .open = hns_roce_vma_open,
398 .close = hns_roce_vma_close,
399 };
400
hns_roce_set_vma_data(struct vm_area_struct * vma,struct hns_roce_ucontext * context)401 static int hns_roce_set_vma_data(struct vm_area_struct *vma,
402 struct hns_roce_ucontext *context)
403 {
404 struct list_head *vma_head = &context->vma_list;
405 struct hns_roce_vma_data *vma_data;
406
407 vma_data = kzalloc(sizeof(*vma_data), GFP_KERNEL);
408 if (!vma_data)
409 return -ENOMEM;
410
411 vma_data->vma = vma;
412 vma_data->vma_list_mutex = &context->vma_list_mutex;
413 vma->vm_private_data = vma_data;
414 vma->vm_ops = &hns_roce_vm_ops;
415
416 mutex_lock(&context->vma_list_mutex);
417 list_add(&vma_data->list, vma_head);
418 mutex_unlock(&context->vma_list_mutex);
419
420 return 0;
421 }
422
hns_roce_mmap(struct ib_ucontext * context,struct vm_area_struct * vma)423 static int hns_roce_mmap(struct ib_ucontext *context,
424 struct vm_area_struct *vma)
425 {
426 struct hns_roce_dev *hr_dev = to_hr_dev(context->device);
427
428 if (((vma->vm_end - vma->vm_start) % PAGE_SIZE) != 0)
429 return -EINVAL;
430
431 if (vma->vm_pgoff == 0) {
432 vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
433 if (io_remap_pfn_range(vma, vma->vm_start,
434 to_hr_ucontext(context)->uar.pfn,
435 PAGE_SIZE, vma->vm_page_prot))
436 return -EAGAIN;
437 } else if (vma->vm_pgoff == 1 && hr_dev->tptr_dma_addr &&
438 hr_dev->tptr_size) {
439 /* vm_pgoff: 1 -- TPTR */
440 if (io_remap_pfn_range(vma, vma->vm_start,
441 hr_dev->tptr_dma_addr >> PAGE_SHIFT,
442 hr_dev->tptr_size,
443 vma->vm_page_prot))
444 return -EAGAIN;
445 } else
446 return -EINVAL;
447
448 return hns_roce_set_vma_data(vma, to_hr_ucontext(context));
449 }
450
hns_roce_port_immutable(struct ib_device * ib_dev,u8 port_num,struct ib_port_immutable * immutable)451 static int hns_roce_port_immutable(struct ib_device *ib_dev, u8 port_num,
452 struct ib_port_immutable *immutable)
453 {
454 struct ib_port_attr attr;
455 int ret;
456
457 ret = ib_query_port(ib_dev, port_num, &attr);
458 if (ret)
459 return ret;
460
461 immutable->pkey_tbl_len = attr.pkey_tbl_len;
462 immutable->gid_tbl_len = attr.gid_tbl_len;
463
464 immutable->max_mad_size = IB_MGMT_MAD_SIZE;
465 immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
466 if (to_hr_dev(ib_dev)->caps.flags & HNS_ROCE_CAP_FLAG_ROCE_V1_V2)
467 immutable->core_cap_flags |= RDMA_CORE_PORT_IBA_ROCE_UDP_ENCAP;
468
469 return 0;
470 }
471
hns_roce_disassociate_ucontext(struct ib_ucontext * ibcontext)472 static void hns_roce_disassociate_ucontext(struct ib_ucontext *ibcontext)
473 {
474 struct hns_roce_ucontext *context = to_hr_ucontext(ibcontext);
475 struct hns_roce_vma_data *vma_data, *n;
476 struct vm_area_struct *vma;
477
478 mutex_lock(&context->vma_list_mutex);
479 list_for_each_entry_safe(vma_data, n, &context->vma_list, list) {
480 vma = vma_data->vma;
481 zap_vma_ptes(vma, vma->vm_start, PAGE_SIZE);
482
483 vma->vm_flags &= ~(VM_SHARED | VM_MAYSHARE);
484 vma->vm_ops = NULL;
485 list_del(&vma_data->list);
486 kfree(vma_data);
487 }
488 mutex_unlock(&context->vma_list_mutex);
489 }
490
hns_roce_unregister_device(struct hns_roce_dev * hr_dev)491 static void hns_roce_unregister_device(struct hns_roce_dev *hr_dev)
492 {
493 struct hns_roce_ib_iboe *iboe = &hr_dev->iboe;
494
495 hr_dev->active = false;
496 unregister_netdevice_notifier(&iboe->nb);
497 ib_unregister_device(&hr_dev->ib_dev);
498 }
499
hns_roce_register_device(struct hns_roce_dev * hr_dev)500 static int hns_roce_register_device(struct hns_roce_dev *hr_dev)
501 {
502 int ret;
503 struct hns_roce_ib_iboe *iboe = NULL;
504 struct ib_device *ib_dev = NULL;
505 struct device *dev = hr_dev->dev;
506
507 iboe = &hr_dev->iboe;
508 spin_lock_init(&iboe->lock);
509
510 ib_dev = &hr_dev->ib_dev;
511 strlcpy(ib_dev->name, "hns_%d", IB_DEVICE_NAME_MAX);
512
513 ib_dev->owner = THIS_MODULE;
514 ib_dev->node_type = RDMA_NODE_IB_CA;
515 ib_dev->dev.parent = dev;
516
517 ib_dev->phys_port_cnt = hr_dev->caps.num_ports;
518 ib_dev->local_dma_lkey = hr_dev->caps.reserved_lkey;
519 ib_dev->num_comp_vectors = hr_dev->caps.num_comp_vectors;
520 ib_dev->uverbs_abi_ver = 1;
521 ib_dev->uverbs_cmd_mask =
522 (1ULL << IB_USER_VERBS_CMD_GET_CONTEXT) |
523 (1ULL << IB_USER_VERBS_CMD_QUERY_DEVICE) |
524 (1ULL << IB_USER_VERBS_CMD_QUERY_PORT) |
525 (1ULL << IB_USER_VERBS_CMD_ALLOC_PD) |
526 (1ULL << IB_USER_VERBS_CMD_DEALLOC_PD) |
527 (1ULL << IB_USER_VERBS_CMD_REG_MR) |
528 (1ULL << IB_USER_VERBS_CMD_DEREG_MR) |
529 (1ULL << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
530 (1ULL << IB_USER_VERBS_CMD_CREATE_CQ) |
531 (1ULL << IB_USER_VERBS_CMD_DESTROY_CQ) |
532 (1ULL << IB_USER_VERBS_CMD_CREATE_QP) |
533 (1ULL << IB_USER_VERBS_CMD_MODIFY_QP) |
534 (1ULL << IB_USER_VERBS_CMD_QUERY_QP) |
535 (1ULL << IB_USER_VERBS_CMD_DESTROY_QP);
536
537 ib_dev->uverbs_ex_cmd_mask |=
538 (1ULL << IB_USER_VERBS_EX_CMD_MODIFY_CQ);
539
540 /* HCA||device||port */
541 ib_dev->modify_device = hns_roce_modify_device;
542 ib_dev->query_device = hns_roce_query_device;
543 ib_dev->query_port = hns_roce_query_port;
544 ib_dev->modify_port = hns_roce_modify_port;
545 ib_dev->get_link_layer = hns_roce_get_link_layer;
546 ib_dev->get_netdev = hns_roce_get_netdev;
547 ib_dev->add_gid = hns_roce_add_gid;
548 ib_dev->del_gid = hns_roce_del_gid;
549 ib_dev->query_pkey = hns_roce_query_pkey;
550 ib_dev->alloc_ucontext = hns_roce_alloc_ucontext;
551 ib_dev->dealloc_ucontext = hns_roce_dealloc_ucontext;
552 ib_dev->mmap = hns_roce_mmap;
553
554 /* PD */
555 ib_dev->alloc_pd = hns_roce_alloc_pd;
556 ib_dev->dealloc_pd = hns_roce_dealloc_pd;
557
558 /* AH */
559 ib_dev->create_ah = hns_roce_create_ah;
560 ib_dev->query_ah = hns_roce_query_ah;
561 ib_dev->destroy_ah = hns_roce_destroy_ah;
562
563 /* QP */
564 ib_dev->create_qp = hns_roce_create_qp;
565 ib_dev->modify_qp = hns_roce_modify_qp;
566 ib_dev->query_qp = hr_dev->hw->query_qp;
567 ib_dev->destroy_qp = hr_dev->hw->destroy_qp;
568 ib_dev->post_send = hr_dev->hw->post_send;
569 ib_dev->post_recv = hr_dev->hw->post_recv;
570
571 /* CQ */
572 ib_dev->create_cq = hns_roce_ib_create_cq;
573 ib_dev->modify_cq = hr_dev->hw->modify_cq;
574 ib_dev->destroy_cq = hns_roce_ib_destroy_cq;
575 ib_dev->req_notify_cq = hr_dev->hw->req_notify_cq;
576 ib_dev->poll_cq = hr_dev->hw->poll_cq;
577
578 /* MR */
579 ib_dev->get_dma_mr = hns_roce_get_dma_mr;
580 ib_dev->reg_user_mr = hns_roce_reg_user_mr;
581 ib_dev->dereg_mr = hns_roce_dereg_mr;
582 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_REREG_MR) {
583 ib_dev->rereg_user_mr = hns_roce_rereg_user_mr;
584 ib_dev->uverbs_cmd_mask |= (1ULL << IB_USER_VERBS_CMD_REREG_MR);
585 }
586
587 /* OTHERS */
588 ib_dev->get_port_immutable = hns_roce_port_immutable;
589 ib_dev->disassociate_ucontext = hns_roce_disassociate_ucontext;
590
591 ib_dev->driver_id = RDMA_DRIVER_HNS;
592 ret = ib_register_device(ib_dev, NULL);
593 if (ret) {
594 dev_err(dev, "ib_register_device failed!\n");
595 return ret;
596 }
597
598 ret = hns_roce_setup_mtu_mac(hr_dev);
599 if (ret) {
600 dev_err(dev, "setup_mtu_mac failed!\n");
601 goto error_failed_setup_mtu_mac;
602 }
603
604 iboe->nb.notifier_call = hns_roce_netdev_event;
605 ret = register_netdevice_notifier(&iboe->nb);
606 if (ret) {
607 dev_err(dev, "register_netdevice_notifier failed!\n");
608 goto error_failed_setup_mtu_mac;
609 }
610
611 hr_dev->active = true;
612 return 0;
613
614 error_failed_setup_mtu_mac:
615 ib_unregister_device(ib_dev);
616
617 return ret;
618 }
619
hns_roce_init_hem(struct hns_roce_dev * hr_dev)620 static int hns_roce_init_hem(struct hns_roce_dev *hr_dev)
621 {
622 int ret;
623 struct device *dev = hr_dev->dev;
624
625 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtt_table,
626 HEM_TYPE_MTT, hr_dev->caps.mtt_entry_sz,
627 hr_dev->caps.num_mtt_segs, 1);
628 if (ret) {
629 dev_err(dev, "Failed to init MTT context memory, aborting.\n");
630 return ret;
631 }
632
633 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE)) {
634 ret = hns_roce_init_hem_table(hr_dev,
635 &hr_dev->mr_table.mtt_cqe_table,
636 HEM_TYPE_CQE, hr_dev->caps.mtt_entry_sz,
637 hr_dev->caps.num_cqe_segs, 1);
638 if (ret) {
639 dev_err(dev, "Failed to init MTT CQE context memory, aborting.\n");
640 goto err_unmap_cqe;
641 }
642 }
643
644 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table,
645 HEM_TYPE_MTPT, hr_dev->caps.mtpt_entry_sz,
646 hr_dev->caps.num_mtpts, 1);
647 if (ret) {
648 dev_err(dev, "Failed to init MTPT context memory, aborting.\n");
649 goto err_unmap_mtt;
650 }
651
652 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.qp_table,
653 HEM_TYPE_QPC, hr_dev->caps.qpc_entry_sz,
654 hr_dev->caps.num_qps, 1);
655 if (ret) {
656 dev_err(dev, "Failed to init QP context memory, aborting.\n");
657 goto err_unmap_dmpt;
658 }
659
660 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->qp_table.irrl_table,
661 HEM_TYPE_IRRL,
662 hr_dev->caps.irrl_entry_sz *
663 hr_dev->caps.max_qp_init_rdma,
664 hr_dev->caps.num_qps, 1);
665 if (ret) {
666 dev_err(dev, "Failed to init irrl_table memory, aborting.\n");
667 goto err_unmap_qp;
668 }
669
670 if (hr_dev->caps.trrl_entry_sz) {
671 ret = hns_roce_init_hem_table(hr_dev,
672 &hr_dev->qp_table.trrl_table,
673 HEM_TYPE_TRRL,
674 hr_dev->caps.trrl_entry_sz *
675 hr_dev->caps.max_qp_dest_rdma,
676 hr_dev->caps.num_qps, 1);
677 if (ret) {
678 dev_err(dev,
679 "Failed to init trrl_table memory, aborting.\n");
680 goto err_unmap_irrl;
681 }
682 }
683
684 ret = hns_roce_init_hem_table(hr_dev, &hr_dev->cq_table.table,
685 HEM_TYPE_CQC, hr_dev->caps.cqc_entry_sz,
686 hr_dev->caps.num_cqs, 1);
687 if (ret) {
688 dev_err(dev, "Failed to init CQ context memory, aborting.\n");
689 goto err_unmap_trrl;
690 }
691
692 return 0;
693
694 err_unmap_trrl:
695 if (hr_dev->caps.trrl_entry_sz)
696 hns_roce_cleanup_hem_table(hr_dev,
697 &hr_dev->qp_table.trrl_table);
698
699 err_unmap_irrl:
700 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.irrl_table);
701
702 err_unmap_qp:
703 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->qp_table.qp_table);
704
705 err_unmap_dmpt:
706 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtpt_table);
707
708 err_unmap_mtt:
709 if (hns_roce_check_whether_mhop(hr_dev, HEM_TYPE_CQE))
710 hns_roce_cleanup_hem_table(hr_dev,
711 &hr_dev->mr_table.mtt_cqe_table);
712
713 err_unmap_cqe:
714 hns_roce_cleanup_hem_table(hr_dev, &hr_dev->mr_table.mtt_table);
715
716 return ret;
717 }
718
719 /**
720 * hns_roce_setup_hca - setup host channel adapter
721 * @hr_dev: pointer to hns roce device
722 * Return : int
723 */
hns_roce_setup_hca(struct hns_roce_dev * hr_dev)724 static int hns_roce_setup_hca(struct hns_roce_dev *hr_dev)
725 {
726 int ret;
727 struct device *dev = hr_dev->dev;
728
729 spin_lock_init(&hr_dev->sm_lock);
730 spin_lock_init(&hr_dev->bt_cmd_lock);
731
732 if (hr_dev->caps.flags & HNS_ROCE_CAP_FLAG_RECORD_DB) {
733 INIT_LIST_HEAD(&hr_dev->pgdir_list);
734 mutex_init(&hr_dev->pgdir_mutex);
735 }
736
737 ret = hns_roce_init_uar_table(hr_dev);
738 if (ret) {
739 dev_err(dev, "Failed to initialize uar table. aborting\n");
740 return ret;
741 }
742
743 ret = hns_roce_uar_alloc(hr_dev, &hr_dev->priv_uar);
744 if (ret) {
745 dev_err(dev, "Failed to allocate priv_uar.\n");
746 goto err_uar_table_free;
747 }
748
749 ret = hns_roce_init_pd_table(hr_dev);
750 if (ret) {
751 dev_err(dev, "Failed to init protected domain table.\n");
752 goto err_uar_alloc_free;
753 }
754
755 ret = hns_roce_init_mr_table(hr_dev);
756 if (ret) {
757 dev_err(dev, "Failed to init memory region table.\n");
758 goto err_pd_table_free;
759 }
760
761 ret = hns_roce_init_cq_table(hr_dev);
762 if (ret) {
763 dev_err(dev, "Failed to init completion queue table.\n");
764 goto err_mr_table_free;
765 }
766
767 ret = hns_roce_init_qp_table(hr_dev);
768 if (ret) {
769 dev_err(dev, "Failed to init queue pair table.\n");
770 goto err_cq_table_free;
771 }
772
773 return 0;
774
775 err_cq_table_free:
776 hns_roce_cleanup_cq_table(hr_dev);
777
778 err_mr_table_free:
779 hns_roce_cleanup_mr_table(hr_dev);
780
781 err_pd_table_free:
782 hns_roce_cleanup_pd_table(hr_dev);
783
784 err_uar_alloc_free:
785 hns_roce_uar_free(hr_dev, &hr_dev->priv_uar);
786
787 err_uar_table_free:
788 hns_roce_cleanup_uar_table(hr_dev);
789 return ret;
790 }
791
hns_roce_init(struct hns_roce_dev * hr_dev)792 int hns_roce_init(struct hns_roce_dev *hr_dev)
793 {
794 int ret;
795 struct device *dev = hr_dev->dev;
796
797 if (hr_dev->hw->reset) {
798 ret = hr_dev->hw->reset(hr_dev, true);
799 if (ret) {
800 dev_err(dev, "Reset RoCE engine failed!\n");
801 return ret;
802 }
803 }
804 hr_dev->is_reset = false;
805
806 if (hr_dev->hw->cmq_init) {
807 ret = hr_dev->hw->cmq_init(hr_dev);
808 if (ret) {
809 dev_err(dev, "Init RoCE Command Queue failed!\n");
810 goto error_failed_cmq_init;
811 }
812 }
813
814 ret = hr_dev->hw->hw_profile(hr_dev);
815 if (ret) {
816 dev_err(dev, "Get RoCE engine profile failed!\n");
817 goto error_failed_cmd_init;
818 }
819
820 ret = hns_roce_cmd_init(hr_dev);
821 if (ret) {
822 dev_err(dev, "cmd init failed!\n");
823 goto error_failed_cmd_init;
824 }
825
826 ret = hr_dev->hw->init_eq(hr_dev);
827 if (ret) {
828 dev_err(dev, "eq init failed!\n");
829 goto error_failed_eq_table;
830 }
831
832 if (hr_dev->cmd_mod) {
833 ret = hns_roce_cmd_use_events(hr_dev);
834 if (ret) {
835 dev_err(dev, "Switch to event-driven cmd failed!\n");
836 goto error_failed_use_event;
837 }
838 }
839
840 ret = hns_roce_init_hem(hr_dev);
841 if (ret) {
842 dev_err(dev, "init HEM(Hardware Entry Memory) failed!\n");
843 goto error_failed_init_hem;
844 }
845
846 ret = hns_roce_setup_hca(hr_dev);
847 if (ret) {
848 dev_err(dev, "setup hca failed!\n");
849 goto error_failed_setup_hca;
850 }
851
852 if (hr_dev->hw->hw_init) {
853 ret = hr_dev->hw->hw_init(hr_dev);
854 if (ret) {
855 dev_err(dev, "hw_init failed!\n");
856 goto error_failed_engine_init;
857 }
858 }
859
860 ret = hns_roce_register_device(hr_dev);
861 if (ret)
862 goto error_failed_register_device;
863
864 return 0;
865
866 error_failed_register_device:
867 if (hr_dev->hw->hw_exit)
868 hr_dev->hw->hw_exit(hr_dev);
869
870 error_failed_engine_init:
871 hns_roce_cleanup_bitmap(hr_dev);
872
873 error_failed_setup_hca:
874 hns_roce_cleanup_hem(hr_dev);
875
876 error_failed_init_hem:
877 if (hr_dev->cmd_mod)
878 hns_roce_cmd_use_polling(hr_dev);
879
880 error_failed_use_event:
881 hr_dev->hw->cleanup_eq(hr_dev);
882
883 error_failed_eq_table:
884 hns_roce_cmd_cleanup(hr_dev);
885
886 error_failed_cmd_init:
887 if (hr_dev->hw->cmq_exit)
888 hr_dev->hw->cmq_exit(hr_dev);
889
890 error_failed_cmq_init:
891 if (hr_dev->hw->reset) {
892 if (hr_dev->hw->reset(hr_dev, false))
893 dev_err(dev, "Dereset RoCE engine failed!\n");
894 }
895
896 return ret;
897 }
898 EXPORT_SYMBOL_GPL(hns_roce_init);
899
hns_roce_exit(struct hns_roce_dev * hr_dev)900 void hns_roce_exit(struct hns_roce_dev *hr_dev)
901 {
902 hns_roce_unregister_device(hr_dev);
903
904 if (hr_dev->hw->hw_exit)
905 hr_dev->hw->hw_exit(hr_dev);
906 hns_roce_cleanup_bitmap(hr_dev);
907 hns_roce_cleanup_hem(hr_dev);
908
909 if (hr_dev->cmd_mod)
910 hns_roce_cmd_use_polling(hr_dev);
911
912 hr_dev->hw->cleanup_eq(hr_dev);
913 hns_roce_cmd_cleanup(hr_dev);
914 if (hr_dev->hw->cmq_exit)
915 hr_dev->hw->cmq_exit(hr_dev);
916 if (hr_dev->hw->reset)
917 hr_dev->hw->reset(hr_dev, false);
918 }
919 EXPORT_SYMBOL_GPL(hns_roce_exit);
920
921 MODULE_LICENSE("Dual BSD/GPL");
922 MODULE_AUTHOR("Wei Hu <xavier.huwei@huawei.com>");
923 MODULE_AUTHOR("Nenglong Zhao <zhaonenglong@hisilicon.com>");
924 MODULE_AUTHOR("Lijun Ou <oulijun@huawei.com>");
925 MODULE_DESCRIPTION("HNS RoCE Driver");
926
