1 /*
2 * drivers/i2c/busses/i2c-ibm_iic.c
3 *
4 * Support for the IIC peripheral on IBM PPC 4xx
5 *
6 * Copyright (c) 2003, 2004 Zultys Technologies.
7 * Eugene Surovegin <eugene.surovegin@zultys.com> or <ebs@ebshome.net>
8 *
9 * Copyright (c) 2008 PIKA Technologies
10 * Sean MacLennan <smaclennan@pikatech.com>
11 *
12 * Based on original work by
13 * Ian DaSilva <idasilva@mvista.com>
14 * Armin Kuster <akuster@mvista.com>
15 * Matt Porter <mporter@mvista.com>
16 *
17 * Copyright 2000-2003 MontaVista Software Inc.
18 *
19 * Original driver version was highly leveraged from i2c-elektor.c
20 *
21 * Copyright 1995-97 Simon G. Vogl
22 * 1998-99 Hans Berglund
23 *
24 * With some changes from Kyösti Mälkki <kmalkki@cc.hut.fi>
25 * and even Frodo Looijaard <frodol@dds.nl>
26 *
27 * This program is free software; you can redistribute it and/or modify it
28 * under the terms of the GNU General Public License as published by the
29 * Free Software Foundation; either version 2 of the License, or (at your
30 * option) any later version.
31 *
32 */
33
34 #include <linux/module.h>
35 #include <linux/kernel.h>
36 #include <linux/ioport.h>
37 #include <linux/delay.h>
38 #include <linux/slab.h>
39 #include <linux/interrupt.h>
40 #include <linux/sched/signal.h>
41
42 #include <asm/irq.h>
43 #include <linux/io.h>
44 #include <linux/i2c.h>
45 #include <linux/of_address.h>
46 #include <linux/of_irq.h>
47 #include <linux/of_platform.h>
48
49 #include "i2c-ibm_iic.h"
50
51 #define DRIVER_VERSION "2.2"
52
53 MODULE_DESCRIPTION("IBM IIC driver v" DRIVER_VERSION);
54 MODULE_LICENSE("GPL");
55
56 static bool iic_force_poll;
57 module_param(iic_force_poll, bool, 0);
58 MODULE_PARM_DESC(iic_force_poll, "Force polling mode");
59
60 static bool iic_force_fast;
61 module_param(iic_force_fast, bool, 0);
62 MODULE_PARM_DESC(iic_force_fast, "Force fast mode (400 kHz)");
63
64 #define DBG_LEVEL 0
65
66 #ifdef DBG
67 #undef DBG
68 #endif
69
70 #ifdef DBG2
71 #undef DBG2
72 #endif
73
74 #if DBG_LEVEL > 0
75 # define DBG(f,x...) printk(KERN_DEBUG "ibm-iic" f, ##x)
76 #else
77 # define DBG(f,x...) ((void)0)
78 #endif
79 #if DBG_LEVEL > 1
80 # define DBG2(f,x...) DBG(f, ##x)
81 #else
82 # define DBG2(f,x...) ((void)0)
83 #endif
84 #if DBG_LEVEL > 2
dump_iic_regs(const char * header,struct ibm_iic_private * dev)85 static void dump_iic_regs(const char* header, struct ibm_iic_private* dev)
86 {
87 volatile struct iic_regs __iomem *iic = dev->vaddr;
88 printk(KERN_DEBUG "ibm-iic%d: %s\n", dev->idx, header);
89 printk(KERN_DEBUG
90 " cntl = 0x%02x, mdcntl = 0x%02x\n"
91 " sts = 0x%02x, extsts = 0x%02x\n"
92 " clkdiv = 0x%02x, xfrcnt = 0x%02x\n"
93 " xtcntlss = 0x%02x, directcntl = 0x%02x\n",
94 in_8(&iic->cntl), in_8(&iic->mdcntl), in_8(&iic->sts),
95 in_8(&iic->extsts), in_8(&iic->clkdiv), in_8(&iic->xfrcnt),
96 in_8(&iic->xtcntlss), in_8(&iic->directcntl));
97 }
98 # define DUMP_REGS(h,dev) dump_iic_regs((h),(dev))
99 #else
100 # define DUMP_REGS(h,dev) ((void)0)
101 #endif
102
103 /* Bus timings (in ns) for bit-banging */
104 static struct ibm_iic_timings {
105 unsigned int hd_sta;
106 unsigned int su_sto;
107 unsigned int low;
108 unsigned int high;
109 unsigned int buf;
110 } timings [] = {
111 /* Standard mode (100 KHz) */
112 {
113 .hd_sta = 4000,
114 .su_sto = 4000,
115 .low = 4700,
116 .high = 4000,
117 .buf = 4700,
118 },
119 /* Fast mode (400 KHz) */
120 {
121 .hd_sta = 600,
122 .su_sto = 600,
123 .low = 1300,
124 .high = 600,
125 .buf = 1300,
126 }};
127
128 /* Enable/disable interrupt generation */
iic_interrupt_mode(struct ibm_iic_private * dev,int enable)129 static inline void iic_interrupt_mode(struct ibm_iic_private* dev, int enable)
130 {
131 out_8(&dev->vaddr->intmsk, enable ? INTRMSK_EIMTC : 0);
132 }
133
134 /*
135 * Initialize IIC interface.
136 */
iic_dev_init(struct ibm_iic_private * dev)137 static void iic_dev_init(struct ibm_iic_private* dev)
138 {
139 volatile struct iic_regs __iomem *iic = dev->vaddr;
140
141 DBG("%d: init\n", dev->idx);
142
143 /* Clear master address */
144 out_8(&iic->lmadr, 0);
145 out_8(&iic->hmadr, 0);
146
147 /* Clear slave address */
148 out_8(&iic->lsadr, 0);
149 out_8(&iic->hsadr, 0);
150
151 /* Clear status & extended status */
152 out_8(&iic->sts, STS_SCMP | STS_IRQA);
153 out_8(&iic->extsts, EXTSTS_IRQP | EXTSTS_IRQD | EXTSTS_LA
154 | EXTSTS_ICT | EXTSTS_XFRA);
155
156 /* Set clock divider */
157 out_8(&iic->clkdiv, dev->clckdiv);
158
159 /* Clear transfer count */
160 out_8(&iic->xfrcnt, 0);
161
162 /* Clear extended control and status */
163 out_8(&iic->xtcntlss, XTCNTLSS_SRC | XTCNTLSS_SRS | XTCNTLSS_SWC
164 | XTCNTLSS_SWS);
165
166 /* Clear control register */
167 out_8(&iic->cntl, 0);
168
169 /* Enable interrupts if possible */
170 iic_interrupt_mode(dev, dev->irq >= 0);
171
172 /* Set mode control */
173 out_8(&iic->mdcntl, MDCNTL_FMDB | MDCNTL_EINT | MDCNTL_EUBS
174 | (dev->fast_mode ? MDCNTL_FSM : 0));
175
176 DUMP_REGS("iic_init", dev);
177 }
178
179 /*
180 * Reset IIC interface
181 */
iic_dev_reset(struct ibm_iic_private * dev)182 static void iic_dev_reset(struct ibm_iic_private* dev)
183 {
184 volatile struct iic_regs __iomem *iic = dev->vaddr;
185 int i;
186 u8 dc;
187
188 DBG("%d: soft reset\n", dev->idx);
189 DUMP_REGS("reset", dev);
190
191 /* Place chip in the reset state */
192 out_8(&iic->xtcntlss, XTCNTLSS_SRST);
193
194 /* Check if bus is free */
195 dc = in_8(&iic->directcntl);
196 if (!DIRCTNL_FREE(dc)){
197 DBG("%d: trying to regain bus control\n", dev->idx);
198
199 /* Try to set bus free state */
200 out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
201
202 /* Wait until we regain bus control */
203 for (i = 0; i < 100; ++i){
204 dc = in_8(&iic->directcntl);
205 if (DIRCTNL_FREE(dc))
206 break;
207
208 /* Toggle SCL line */
209 dc ^= DIRCNTL_SCC;
210 out_8(&iic->directcntl, dc);
211 udelay(10);
212 dc ^= DIRCNTL_SCC;
213 out_8(&iic->directcntl, dc);
214
215 /* be nice */
216 cond_resched();
217 }
218 }
219
220 /* Remove reset */
221 out_8(&iic->xtcntlss, 0);
222
223 /* Reinitialize interface */
224 iic_dev_init(dev);
225 }
226
227 /*
228 * Do 0-length transaction using bit-banging through IIC_DIRECTCNTL register.
229 */
230
231 /* Wait for SCL and/or SDA to be high */
iic_dc_wait(volatile struct iic_regs __iomem * iic,u8 mask)232 static int iic_dc_wait(volatile struct iic_regs __iomem *iic, u8 mask)
233 {
234 unsigned long x = jiffies + HZ / 28 + 2;
235 while ((in_8(&iic->directcntl) & mask) != mask){
236 if (unlikely(time_after(jiffies, x)))
237 return -1;
238 cond_resched();
239 }
240 return 0;
241 }
242
iic_smbus_quick(struct ibm_iic_private * dev,const struct i2c_msg * p)243 static int iic_smbus_quick(struct ibm_iic_private* dev, const struct i2c_msg* p)
244 {
245 volatile struct iic_regs __iomem *iic = dev->vaddr;
246 const struct ibm_iic_timings *t = &timings[dev->fast_mode ? 1 : 0];
247 u8 mask, v, sda;
248 int i, res;
249
250 /* Only 7-bit addresses are supported */
251 if (unlikely(p->flags & I2C_M_TEN)){
252 DBG("%d: smbus_quick - 10 bit addresses are not supported\n",
253 dev->idx);
254 return -EINVAL;
255 }
256
257 DBG("%d: smbus_quick(0x%02x)\n", dev->idx, p->addr);
258
259 /* Reset IIC interface */
260 out_8(&iic->xtcntlss, XTCNTLSS_SRST);
261
262 /* Wait for bus to become free */
263 out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
264 if (unlikely(iic_dc_wait(iic, DIRCNTL_MSDA | DIRCNTL_MSC)))
265 goto err;
266 ndelay(t->buf);
267
268 /* START */
269 out_8(&iic->directcntl, DIRCNTL_SCC);
270 sda = 0;
271 ndelay(t->hd_sta);
272
273 /* Send address */
274 v = i2c_8bit_addr_from_msg(p);
275 for (i = 0, mask = 0x80; i < 8; ++i, mask >>= 1){
276 out_8(&iic->directcntl, sda);
277 ndelay(t->low / 2);
278 sda = (v & mask) ? DIRCNTL_SDAC : 0;
279 out_8(&iic->directcntl, sda);
280 ndelay(t->low / 2);
281
282 out_8(&iic->directcntl, DIRCNTL_SCC | sda);
283 if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
284 goto err;
285 ndelay(t->high);
286 }
287
288 /* ACK */
289 out_8(&iic->directcntl, sda);
290 ndelay(t->low / 2);
291 out_8(&iic->directcntl, DIRCNTL_SDAC);
292 ndelay(t->low / 2);
293 out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
294 if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
295 goto err;
296 res = (in_8(&iic->directcntl) & DIRCNTL_MSDA) ? -EREMOTEIO : 1;
297 ndelay(t->high);
298
299 /* STOP */
300 out_8(&iic->directcntl, 0);
301 ndelay(t->low);
302 out_8(&iic->directcntl, DIRCNTL_SCC);
303 if (unlikely(iic_dc_wait(iic, DIRCNTL_MSC)))
304 goto err;
305 ndelay(t->su_sto);
306 out_8(&iic->directcntl, DIRCNTL_SDAC | DIRCNTL_SCC);
307
308 ndelay(t->buf);
309
310 DBG("%d: smbus_quick -> %s\n", dev->idx, res ? "NACK" : "ACK");
311 out:
312 /* Remove reset */
313 out_8(&iic->xtcntlss, 0);
314
315 /* Reinitialize interface */
316 iic_dev_init(dev);
317
318 return res;
319 err:
320 DBG("%d: smbus_quick - bus is stuck\n", dev->idx);
321 res = -EREMOTEIO;
322 goto out;
323 }
324
325 /*
326 * IIC interrupt handler
327 */
iic_handler(int irq,void * dev_id)328 static irqreturn_t iic_handler(int irq, void *dev_id)
329 {
330 struct ibm_iic_private* dev = (struct ibm_iic_private*)dev_id;
331 volatile struct iic_regs __iomem *iic = dev->vaddr;
332
333 DBG2("%d: irq handler, STS = 0x%02x, EXTSTS = 0x%02x\n",
334 dev->idx, in_8(&iic->sts), in_8(&iic->extsts));
335
336 /* Acknowledge IRQ and wakeup iic_wait_for_tc */
337 out_8(&iic->sts, STS_IRQA | STS_SCMP);
338 wake_up_interruptible(&dev->wq);
339
340 return IRQ_HANDLED;
341 }
342
343 /*
344 * Get master transfer result and clear errors if any.
345 * Returns the number of actually transferred bytes or error (<0)
346 */
iic_xfer_result(struct ibm_iic_private * dev)347 static int iic_xfer_result(struct ibm_iic_private* dev)
348 {
349 volatile struct iic_regs __iomem *iic = dev->vaddr;
350
351 if (unlikely(in_8(&iic->sts) & STS_ERR)){
352 DBG("%d: xfer error, EXTSTS = 0x%02x\n", dev->idx,
353 in_8(&iic->extsts));
354
355 /* Clear errors and possible pending IRQs */
356 out_8(&iic->extsts, EXTSTS_IRQP | EXTSTS_IRQD |
357 EXTSTS_LA | EXTSTS_ICT | EXTSTS_XFRA);
358
359 /* Flush master data buffer */
360 out_8(&iic->mdcntl, in_8(&iic->mdcntl) | MDCNTL_FMDB);
361
362 /* Is bus free?
363 * If error happened during combined xfer
364 * IIC interface is usually stuck in some strange
365 * state, the only way out - soft reset.
366 */
367 if ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
368 DBG("%d: bus is stuck, resetting\n", dev->idx);
369 iic_dev_reset(dev);
370 }
371 return -EREMOTEIO;
372 }
373 else
374 return in_8(&iic->xfrcnt) & XFRCNT_MTC_MASK;
375 }
376
377 /*
378 * Try to abort active transfer.
379 */
iic_abort_xfer(struct ibm_iic_private * dev)380 static void iic_abort_xfer(struct ibm_iic_private* dev)
381 {
382 volatile struct iic_regs __iomem *iic = dev->vaddr;
383 unsigned long x;
384
385 DBG("%d: iic_abort_xfer\n", dev->idx);
386
387 out_8(&iic->cntl, CNTL_HMT);
388
389 /*
390 * Wait for the abort command to complete.
391 * It's not worth to be optimized, just poll (timeout >= 1 tick)
392 */
393 x = jiffies + 2;
394 while ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
395 if (time_after(jiffies, x)){
396 DBG("%d: abort timeout, resetting...\n", dev->idx);
397 iic_dev_reset(dev);
398 return;
399 }
400 schedule();
401 }
402
403 /* Just to clear errors */
404 iic_xfer_result(dev);
405 }
406
407 /*
408 * Wait for master transfer to complete.
409 * It puts current process to sleep until we get interrupt or timeout expires.
410 * Returns the number of transferred bytes or error (<0)
411 */
iic_wait_for_tc(struct ibm_iic_private * dev)412 static int iic_wait_for_tc(struct ibm_iic_private* dev){
413
414 volatile struct iic_regs __iomem *iic = dev->vaddr;
415 int ret = 0;
416
417 if (dev->irq >= 0){
418 /* Interrupt mode */
419 ret = wait_event_interruptible_timeout(dev->wq,
420 !(in_8(&iic->sts) & STS_PT), dev->adap.timeout);
421
422 if (unlikely(ret < 0))
423 DBG("%d: wait interrupted\n", dev->idx);
424 else if (unlikely(in_8(&iic->sts) & STS_PT)){
425 DBG("%d: wait timeout\n", dev->idx);
426 ret = -ETIMEDOUT;
427 }
428 }
429 else {
430 /* Polling mode */
431 unsigned long x = jiffies + dev->adap.timeout;
432
433 while (in_8(&iic->sts) & STS_PT){
434 if (unlikely(time_after(jiffies, x))){
435 DBG("%d: poll timeout\n", dev->idx);
436 ret = -ETIMEDOUT;
437 break;
438 }
439
440 if (unlikely(signal_pending(current))){
441 DBG("%d: poll interrupted\n", dev->idx);
442 ret = -ERESTARTSYS;
443 break;
444 }
445 schedule();
446 }
447 }
448
449 if (unlikely(ret < 0))
450 iic_abort_xfer(dev);
451 else
452 ret = iic_xfer_result(dev);
453
454 DBG2("%d: iic_wait_for_tc -> %d\n", dev->idx, ret);
455
456 return ret;
457 }
458
459 /*
460 * Low level master transfer routine
461 */
iic_xfer_bytes(struct ibm_iic_private * dev,struct i2c_msg * pm,int combined_xfer)462 static int iic_xfer_bytes(struct ibm_iic_private* dev, struct i2c_msg* pm,
463 int combined_xfer)
464 {
465 volatile struct iic_regs __iomem *iic = dev->vaddr;
466 char* buf = pm->buf;
467 int i, j, loops, ret = 0;
468 int len = pm->len;
469
470 u8 cntl = (in_8(&iic->cntl) & CNTL_AMD) | CNTL_PT;
471 if (pm->flags & I2C_M_RD)
472 cntl |= CNTL_RW;
473
474 loops = (len + 3) / 4;
475 for (i = 0; i < loops; ++i, len -= 4){
476 int count = len > 4 ? 4 : len;
477 u8 cmd = cntl | ((count - 1) << CNTL_TCT_SHIFT);
478
479 if (!(cntl & CNTL_RW))
480 for (j = 0; j < count; ++j)
481 out_8((void __iomem *)&iic->mdbuf, *buf++);
482
483 if (i < loops - 1)
484 cmd |= CNTL_CHT;
485 else if (combined_xfer)
486 cmd |= CNTL_RPST;
487
488 DBG2("%d: xfer_bytes, %d, CNTL = 0x%02x\n", dev->idx, count, cmd);
489
490 /* Start transfer */
491 out_8(&iic->cntl, cmd);
492
493 /* Wait for completion */
494 ret = iic_wait_for_tc(dev);
495
496 if (unlikely(ret < 0))
497 break;
498 else if (unlikely(ret != count)){
499 DBG("%d: xfer_bytes, requested %d, transferred %d\n",
500 dev->idx, count, ret);
501
502 /* If it's not a last part of xfer, abort it */
503 if (combined_xfer || (i < loops - 1))
504 iic_abort_xfer(dev);
505
506 ret = -EREMOTEIO;
507 break;
508 }
509
510 if (cntl & CNTL_RW)
511 for (j = 0; j < count; ++j)
512 *buf++ = in_8((void __iomem *)&iic->mdbuf);
513 }
514
515 return ret > 0 ? 0 : ret;
516 }
517
518 /*
519 * Set target slave address for master transfer
520 */
iic_address(struct ibm_iic_private * dev,struct i2c_msg * msg)521 static inline void iic_address(struct ibm_iic_private* dev, struct i2c_msg* msg)
522 {
523 volatile struct iic_regs __iomem *iic = dev->vaddr;
524 u16 addr = msg->addr;
525
526 DBG2("%d: iic_address, 0x%03x (%d-bit)\n", dev->idx,
527 addr, msg->flags & I2C_M_TEN ? 10 : 7);
528
529 if (msg->flags & I2C_M_TEN){
530 out_8(&iic->cntl, CNTL_AMD);
531 out_8(&iic->lmadr, addr);
532 out_8(&iic->hmadr, 0xf0 | ((addr >> 7) & 0x06));
533 }
534 else {
535 out_8(&iic->cntl, 0);
536 out_8(&iic->lmadr, addr << 1);
537 }
538 }
539
iic_invalid_address(const struct i2c_msg * p)540 static inline int iic_invalid_address(const struct i2c_msg* p)
541 {
542 return (p->addr > 0x3ff) || (!(p->flags & I2C_M_TEN) && (p->addr > 0x7f));
543 }
544
iic_address_neq(const struct i2c_msg * p1,const struct i2c_msg * p2)545 static inline int iic_address_neq(const struct i2c_msg* p1,
546 const struct i2c_msg* p2)
547 {
548 return (p1->addr != p2->addr)
549 || ((p1->flags & I2C_M_TEN) != (p2->flags & I2C_M_TEN));
550 }
551
552 /*
553 * Generic master transfer entrypoint.
554 * Returns the number of processed messages or error (<0)
555 */
iic_xfer(struct i2c_adapter * adap,struct i2c_msg * msgs,int num)556 static int iic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
557 {
558 struct ibm_iic_private* dev = (struct ibm_iic_private*)(i2c_get_adapdata(adap));
559 volatile struct iic_regs __iomem *iic = dev->vaddr;
560 int i, ret = 0;
561
562 DBG2("%d: iic_xfer, %d msg(s)\n", dev->idx, num);
563
564 /* Check the sanity of the passed messages.
565 * Uhh, generic i2c layer is more suitable place for such code...
566 */
567 if (unlikely(iic_invalid_address(&msgs[0]))){
568 DBG("%d: invalid address 0x%03x (%d-bit)\n", dev->idx,
569 msgs[0].addr, msgs[0].flags & I2C_M_TEN ? 10 : 7);
570 return -EINVAL;
571 }
572 for (i = 0; i < num; ++i){
573 if (unlikely(msgs[i].len <= 0)){
574 if (num == 1 && !msgs[0].len){
575 /* Special case for I2C_SMBUS_QUICK emulation.
576 * IBM IIC doesn't support 0-length transactions
577 * so we have to emulate them using bit-banging.
578 */
579 return iic_smbus_quick(dev, &msgs[0]);
580 }
581 DBG("%d: invalid len %d in msg[%d]\n", dev->idx,
582 msgs[i].len, i);
583 return -EINVAL;
584 }
585 if (unlikely(iic_address_neq(&msgs[0], &msgs[i]))){
586 DBG("%d: invalid addr in msg[%d]\n", dev->idx, i);
587 return -EINVAL;
588 }
589 }
590
591 /* Check bus state */
592 if (unlikely((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE)){
593 DBG("%d: iic_xfer, bus is not free\n", dev->idx);
594
595 /* Usually it means something serious has happened.
596 * We *cannot* have unfinished previous transfer
597 * so it doesn't make any sense to try to stop it.
598 * Probably we were not able to recover from the
599 * previous error.
600 * The only *reasonable* thing I can think of here
601 * is soft reset. --ebs
602 */
603 iic_dev_reset(dev);
604
605 if ((in_8(&iic->extsts) & EXTSTS_BCS_MASK) != EXTSTS_BCS_FREE){
606 DBG("%d: iic_xfer, bus is still not free\n", dev->idx);
607 return -EREMOTEIO;
608 }
609 }
610 else {
611 /* Flush master data buffer (just in case) */
612 out_8(&iic->mdcntl, in_8(&iic->mdcntl) | MDCNTL_FMDB);
613 }
614
615 /* Load slave address */
616 iic_address(dev, &msgs[0]);
617
618 /* Do real transfer */
619 for (i = 0; i < num && !ret; ++i)
620 ret = iic_xfer_bytes(dev, &msgs[i], i < num - 1);
621
622 return ret < 0 ? ret : num;
623 }
624
iic_func(struct i2c_adapter * adap)625 static u32 iic_func(struct i2c_adapter *adap)
626 {
627 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR;
628 }
629
630 static const struct i2c_algorithm iic_algo = {
631 .master_xfer = iic_xfer,
632 .functionality = iic_func
633 };
634
635 /*
636 * Calculates IICx_CLCKDIV value for a specific OPB clock frequency
637 */
iic_clckdiv(unsigned int opb)638 static inline u8 iic_clckdiv(unsigned int opb)
639 {
640 /* Compatibility kludge, should go away after all cards
641 * are fixed to fill correct value for opbfreq.
642 * Previous driver version used hardcoded divider value 4,
643 * it corresponds to OPB frequency from the range (40, 50] MHz
644 */
645 if (!opb){
646 printk(KERN_WARNING "ibm-iic: using compatibility value for OPB freq,"
647 " fix your board specific setup\n");
648 opb = 50000000;
649 }
650
651 /* Convert to MHz */
652 opb /= 1000000;
653
654 if (opb < 20 || opb > 150){
655 printk(KERN_WARNING "ibm-iic: invalid OPB clock frequency %u MHz\n",
656 opb);
657 opb = opb < 20 ? 20 : 150;
658 }
659 return (u8)((opb + 9) / 10 - 1);
660 }
661
iic_request_irq(struct platform_device * ofdev,struct ibm_iic_private * dev)662 static int iic_request_irq(struct platform_device *ofdev,
663 struct ibm_iic_private *dev)
664 {
665 struct device_node *np = ofdev->dev.of_node;
666 int irq;
667
668 if (iic_force_poll)
669 return 0;
670
671 irq = irq_of_parse_and_map(np, 0);
672 if (!irq) {
673 dev_err(&ofdev->dev, "irq_of_parse_and_map failed\n");
674 return 0;
675 }
676
677 /* Disable interrupts until we finish initialization, assumes
678 * level-sensitive IRQ setup...
679 */
680 iic_interrupt_mode(dev, 0);
681 if (request_irq(irq, iic_handler, 0, "IBM IIC", dev)) {
682 dev_err(&ofdev->dev, "request_irq %d failed\n", irq);
683 /* Fallback to the polling mode */
684 return 0;
685 }
686
687 return irq;
688 }
689
690 /*
691 * Register single IIC interface
692 */
iic_probe(struct platform_device * ofdev)693 static int iic_probe(struct platform_device *ofdev)
694 {
695 struct device_node *np = ofdev->dev.of_node;
696 struct ibm_iic_private *dev;
697 struct i2c_adapter *adap;
698 const u32 *freq;
699 int ret;
700
701 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
702 if (!dev) {
703 dev_err(&ofdev->dev, "failed to allocate device data\n");
704 return -ENOMEM;
705 }
706
707 platform_set_drvdata(ofdev, dev);
708
709 dev->vaddr = of_iomap(np, 0);
710 if (dev->vaddr == NULL) {
711 dev_err(&ofdev->dev, "failed to iomap device\n");
712 ret = -ENXIO;
713 goto error_cleanup;
714 }
715
716 init_waitqueue_head(&dev->wq);
717
718 dev->irq = iic_request_irq(ofdev, dev);
719 if (!dev->irq)
720 dev_warn(&ofdev->dev, "using polling mode\n");
721
722 /* Board specific settings */
723 if (iic_force_fast || of_get_property(np, "fast-mode", NULL))
724 dev->fast_mode = 1;
725
726 freq = of_get_property(np, "clock-frequency", NULL);
727 if (freq == NULL) {
728 freq = of_get_property(np->parent, "clock-frequency", NULL);
729 if (freq == NULL) {
730 dev_err(&ofdev->dev, "Unable to get bus frequency\n");
731 ret = -EINVAL;
732 goto error_cleanup;
733 }
734 }
735
736 dev->clckdiv = iic_clckdiv(*freq);
737 dev_dbg(&ofdev->dev, "clckdiv = %d\n", dev->clckdiv);
738
739 /* Initialize IIC interface */
740 iic_dev_init(dev);
741
742 /* Register it with i2c layer */
743 adap = &dev->adap;
744 adap->dev.parent = &ofdev->dev;
745 adap->dev.of_node = of_node_get(np);
746 strlcpy(adap->name, "IBM IIC", sizeof(adap->name));
747 i2c_set_adapdata(adap, dev);
748 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
749 adap->algo = &iic_algo;
750 adap->timeout = HZ;
751
752 ret = i2c_add_adapter(adap);
753 if (ret < 0)
754 goto error_cleanup;
755
756 dev_info(&ofdev->dev, "using %s mode\n",
757 dev->fast_mode ? "fast (400 kHz)" : "standard (100 kHz)");
758
759 return 0;
760
761 error_cleanup:
762 if (dev->irq) {
763 iic_interrupt_mode(dev, 0);
764 free_irq(dev->irq, dev);
765 }
766
767 if (dev->vaddr)
768 iounmap(dev->vaddr);
769
770 kfree(dev);
771 return ret;
772 }
773
774 /*
775 * Cleanup initialized IIC interface
776 */
iic_remove(struct platform_device * ofdev)777 static int iic_remove(struct platform_device *ofdev)
778 {
779 struct ibm_iic_private *dev = platform_get_drvdata(ofdev);
780
781 i2c_del_adapter(&dev->adap);
782
783 if (dev->irq) {
784 iic_interrupt_mode(dev, 0);
785 free_irq(dev->irq, dev);
786 }
787
788 iounmap(dev->vaddr);
789 kfree(dev);
790
791 return 0;
792 }
793
794 static const struct of_device_id ibm_iic_match[] = {
795 { .compatible = "ibm,iic", },
796 {}
797 };
798 MODULE_DEVICE_TABLE(of, ibm_iic_match);
799
800 static struct platform_driver ibm_iic_driver = {
801 .driver = {
802 .name = "ibm-iic",
803 .of_match_table = ibm_iic_match,
804 },
805 .probe = iic_probe,
806 .remove = iic_remove,
807 };
808
809 module_platform_driver(ibm_iic_driver);
810
