1 /* 2 * Copyright 2016 Linaro Ltd. 3 * Copyright 2016 ZTE Corporation. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 */ 10 11 #ifndef __ZX_PLANE_REGS_H__ 12 #define __ZX_PLANE_REGS_H__ 13 14 /* GL registers */ 15 #define GL_CTRL0 0x00 16 #define GL_UPDATE BIT(5) 17 #define GL_CTRL1 0x04 18 #define GL_DATA_FMT_SHIFT 0 19 #define GL_DATA_FMT_MASK (0xf << GL_DATA_FMT_SHIFT) 20 #define GL_FMT_ARGB8888 0 21 #define GL_FMT_RGB888 1 22 #define GL_FMT_RGB565 2 23 #define GL_FMT_ARGB1555 3 24 #define GL_FMT_ARGB4444 4 25 #define GL_CTRL2 0x08 26 #define GL_GLOBAL_ALPHA_SHIFT 8 27 #define GL_GLOBAL_ALPHA_MASK (0xff << GL_GLOBAL_ALPHA_SHIFT) 28 #define GL_CTRL3 0x0c 29 #define GL_SCALER_BYPASS_MODE BIT(0) 30 #define GL_STRIDE 0x18 31 #define GL_ADDR 0x1c 32 #define GL_SRC_SIZE 0x38 33 #define GL_SRC_W_SHIFT 16 34 #define GL_SRC_W_MASK (0x3fff << GL_SRC_W_SHIFT) 35 #define GL_SRC_H_SHIFT 0 36 #define GL_SRC_H_MASK (0x3fff << GL_SRC_H_SHIFT) 37 #define GL_POS_START 0x9c 38 #define GL_POS_END 0xa0 39 #define GL_POS_X_SHIFT 16 40 #define GL_POS_X_MASK (0x1fff << GL_POS_X_SHIFT) 41 #define GL_POS_Y_SHIFT 0 42 #define GL_POS_Y_MASK (0x1fff << GL_POS_Y_SHIFT) 43 44 #define GL_SRC_W(x) (((x) << GL_SRC_W_SHIFT) & GL_SRC_W_MASK) 45 #define GL_SRC_H(x) (((x) << GL_SRC_H_SHIFT) & GL_SRC_H_MASK) 46 #define GL_POS_X(x) (((x) << GL_POS_X_SHIFT) & GL_POS_X_MASK) 47 #define GL_POS_Y(x) (((x) << GL_POS_Y_SHIFT) & GL_POS_Y_MASK) 48 49 /* VL registers */ 50 #define VL_CTRL0 0x00 51 #define VL_UPDATE BIT(3) 52 #define VL_CTRL1 0x04 53 #define VL_YUV420_PLANAR BIT(5) 54 #define VL_YUV422_SHIFT 3 55 #define VL_YUV422_YUYV (0 << VL_YUV422_SHIFT) 56 #define VL_YUV422_YVYU (1 << VL_YUV422_SHIFT) 57 #define VL_YUV422_UYVY (2 << VL_YUV422_SHIFT) 58 #define VL_YUV422_VYUY (3 << VL_YUV422_SHIFT) 59 #define VL_FMT_YUV420 0 60 #define VL_FMT_YUV422 1 61 #define VL_FMT_YUV420_P010 2 62 #define VL_FMT_YUV420_HANTRO 3 63 #define VL_FMT_YUV444_8BIT 4 64 #define VL_FMT_YUV444_10BIT 5 65 #define VL_CTRL2 0x08 66 #define VL_SCALER_BYPASS_MODE BIT(0) 67 #define VL_STRIDE 0x0c 68 #define LUMA_STRIDE_SHIFT 16 69 #define LUMA_STRIDE_MASK (0xffff << LUMA_STRIDE_SHIFT) 70 #define CHROMA_STRIDE_SHIFT 0 71 #define CHROMA_STRIDE_MASK (0xffff << CHROMA_STRIDE_SHIFT) 72 #define VL_SRC_SIZE 0x10 73 #define VL_Y 0x14 74 #define VL_POS_START 0x30 75 #define VL_POS_END 0x34 76 77 #define LUMA_STRIDE(x) (((x) << LUMA_STRIDE_SHIFT) & LUMA_STRIDE_MASK) 78 #define CHROMA_STRIDE(x) (((x) << CHROMA_STRIDE_SHIFT) & CHROMA_STRIDE_MASK) 79 80 /* RSZ registers */ 81 #define RSZ_SRC_CFG 0x00 82 #define RSZ_DEST_CFG 0x04 83 #define RSZ_ENABLE_CFG 0x14 84 85 #define RSZ_VL_LUMA_HOR 0x08 86 #define RSZ_VL_LUMA_VER 0x0c 87 #define RSZ_VL_CHROMA_HOR 0x10 88 #define RSZ_VL_CHROMA_VER 0x14 89 #define RSZ_VL_CTRL_CFG 0x18 90 #define RSZ_VL_FMT_SHIFT 3 91 #define RSZ_VL_FMT_MASK (0x3 << RSZ_VL_FMT_SHIFT) 92 #define RSZ_VL_FMT_YCBCR420 (0x0 << RSZ_VL_FMT_SHIFT) 93 #define RSZ_VL_FMT_YCBCR422 (0x1 << RSZ_VL_FMT_SHIFT) 94 #define RSZ_VL_FMT_YCBCR444 (0x2 << RSZ_VL_FMT_SHIFT) 95 #define RSZ_VL_ENABLE_CFG 0x1c 96 97 #define RSZ_VER_SHIFT 16 98 #define RSZ_VER_MASK (0xffff << RSZ_VER_SHIFT) 99 #define RSZ_HOR_SHIFT 0 100 #define RSZ_HOR_MASK (0xffff << RSZ_HOR_SHIFT) 101 102 #define RSZ_VER(x) (((x) << RSZ_VER_SHIFT) & RSZ_VER_MASK) 103 #define RSZ_HOR(x) (((x) << RSZ_HOR_SHIFT) & RSZ_HOR_MASK) 104 105 #define RSZ_DATA_STEP_SHIFT 16 106 #define RSZ_DATA_STEP_MASK (0xffff << RSZ_DATA_STEP_SHIFT) 107 #define RSZ_PARA_STEP_SHIFT 0 108 #define RSZ_PARA_STEP_MASK (0xffff << RSZ_PARA_STEP_SHIFT) 109 110 #define RSZ_DATA_STEP(x) (((x) << RSZ_DATA_STEP_SHIFT) & RSZ_DATA_STEP_MASK) 111 #define RSZ_PARA_STEP(x) (((x) << RSZ_PARA_STEP_SHIFT) & RSZ_PARA_STEP_MASK) 112 113 /* HBSC registers */ 114 #define HBSC_SATURATION 0x00 115 #define HBSC_HUE 0x04 116 #define HBSC_BRIGHT 0x08 117 #define HBSC_CONTRAST 0x0c 118 #define HBSC_THRESHOLD_COL1 0x10 119 #define HBSC_THRESHOLD_COL2 0x14 120 #define HBSC_THRESHOLD_COL3 0x18 121 #define HBSC_CTRL0 0x28 122 #define HBSC_CTRL_EN BIT(2) 123 124 #endif /* __ZX_PLANE_REGS_H__ */ 125
