1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2014-2018 Broadcom */
3
4 #include <linux/circ_buf.h>
5 #include <linux/ctype.h>
6 #include <linux/debugfs.h>
7 #include <linux/pm_runtime.h>
8 #include <linux/seq_file.h>
9 #include <drm/drmP.h>
10
11 #include "v3d_drv.h"
12 #include "v3d_regs.h"
13
14 #define REGDEF(reg) { reg, #reg }
15 struct v3d_reg_def {
16 u32 reg;
17 const char *name;
18 };
19
20 static const struct v3d_reg_def v3d_hub_reg_defs[] = {
21 REGDEF(V3D_HUB_AXICFG),
22 REGDEF(V3D_HUB_UIFCFG),
23 REGDEF(V3D_HUB_IDENT0),
24 REGDEF(V3D_HUB_IDENT1),
25 REGDEF(V3D_HUB_IDENT2),
26 REGDEF(V3D_HUB_IDENT3),
27 REGDEF(V3D_HUB_INT_STS),
28 REGDEF(V3D_HUB_INT_MSK_STS),
29 };
30
31 static const struct v3d_reg_def v3d_gca_reg_defs[] = {
32 REGDEF(V3D_GCA_SAFE_SHUTDOWN),
33 REGDEF(V3D_GCA_SAFE_SHUTDOWN_ACK),
34 };
35
36 static const struct v3d_reg_def v3d_core_reg_defs[] = {
37 REGDEF(V3D_CTL_IDENT0),
38 REGDEF(V3D_CTL_IDENT1),
39 REGDEF(V3D_CTL_IDENT2),
40 REGDEF(V3D_CTL_MISCCFG),
41 REGDEF(V3D_CTL_INT_STS),
42 REGDEF(V3D_CTL_INT_MSK_STS),
43 REGDEF(V3D_CLE_CT0CS),
44 REGDEF(V3D_CLE_CT0CA),
45 REGDEF(V3D_CLE_CT0EA),
46 REGDEF(V3D_CLE_CT1CS),
47 REGDEF(V3D_CLE_CT1CA),
48 REGDEF(V3D_CLE_CT1EA),
49
50 REGDEF(V3D_PTB_BPCA),
51 REGDEF(V3D_PTB_BPCS),
52
53 REGDEF(V3D_MMU_CTL),
54 REGDEF(V3D_MMU_VIO_ADDR),
55
56 REGDEF(V3D_GMP_STATUS),
57 REGDEF(V3D_GMP_CFG),
58 REGDEF(V3D_GMP_VIO_ADDR),
59 };
60
v3d_v3d_debugfs_regs(struct seq_file * m,void * unused)61 static int v3d_v3d_debugfs_regs(struct seq_file *m, void *unused)
62 {
63 struct drm_info_node *node = (struct drm_info_node *)m->private;
64 struct drm_device *dev = node->minor->dev;
65 struct v3d_dev *v3d = to_v3d_dev(dev);
66 int i, core;
67
68 for (i = 0; i < ARRAY_SIZE(v3d_hub_reg_defs); i++) {
69 seq_printf(m, "%s (0x%04x): 0x%08x\n",
70 v3d_hub_reg_defs[i].name, v3d_hub_reg_defs[i].reg,
71 V3D_READ(v3d_hub_reg_defs[i].reg));
72 }
73
74 for (i = 0; i < ARRAY_SIZE(v3d_gca_reg_defs); i++) {
75 seq_printf(m, "%s (0x%04x): 0x%08x\n",
76 v3d_gca_reg_defs[i].name, v3d_gca_reg_defs[i].reg,
77 V3D_GCA_READ(v3d_gca_reg_defs[i].reg));
78 }
79
80 for (core = 0; core < v3d->cores; core++) {
81 for (i = 0; i < ARRAY_SIZE(v3d_core_reg_defs); i++) {
82 seq_printf(m, "core %d %s (0x%04x): 0x%08x\n",
83 core,
84 v3d_core_reg_defs[i].name,
85 v3d_core_reg_defs[i].reg,
86 V3D_CORE_READ(core,
87 v3d_core_reg_defs[i].reg));
88 }
89 }
90
91 return 0;
92 }
93
v3d_v3d_debugfs_ident(struct seq_file * m,void * unused)94 static int v3d_v3d_debugfs_ident(struct seq_file *m, void *unused)
95 {
96 struct drm_info_node *node = (struct drm_info_node *)m->private;
97 struct drm_device *dev = node->minor->dev;
98 struct v3d_dev *v3d = to_v3d_dev(dev);
99 u32 ident0, ident1, ident2, ident3, cores;
100 int ret, core;
101
102 ret = pm_runtime_get_sync(v3d->dev);
103 if (ret < 0)
104 return ret;
105
106 ident0 = V3D_READ(V3D_HUB_IDENT0);
107 ident1 = V3D_READ(V3D_HUB_IDENT1);
108 ident2 = V3D_READ(V3D_HUB_IDENT2);
109 ident3 = V3D_READ(V3D_HUB_IDENT3);
110 cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES);
111
112 seq_printf(m, "Revision: %d.%d.%d.%d\n",
113 V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER),
114 V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV),
115 V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPREV),
116 V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPIDX));
117 seq_printf(m, "MMU: %s\n",
118 (ident2 & V3D_HUB_IDENT2_WITH_MMU) ? "yes" : "no");
119 seq_printf(m, "TFU: %s\n",
120 (ident1 & V3D_HUB_IDENT1_WITH_TFU) ? "yes" : "no");
121 seq_printf(m, "TSY: %s\n",
122 (ident1 & V3D_HUB_IDENT1_WITH_TSY) ? "yes" : "no");
123 seq_printf(m, "MSO: %s\n",
124 (ident1 & V3D_HUB_IDENT1_WITH_MSO) ? "yes" : "no");
125 seq_printf(m, "L3C: %s (%dkb)\n",
126 (ident1 & V3D_HUB_IDENT1_WITH_L3C) ? "yes" : "no",
127 V3D_GET_FIELD(ident2, V3D_HUB_IDENT2_L3C_NKB));
128
129 for (core = 0; core < cores; core++) {
130 u32 misccfg;
131 u32 nslc, ntmu, qups;
132
133 ident0 = V3D_CORE_READ(core, V3D_CTL_IDENT0);
134 ident1 = V3D_CORE_READ(core, V3D_CTL_IDENT1);
135 ident2 = V3D_CORE_READ(core, V3D_CTL_IDENT2);
136 misccfg = V3D_CORE_READ(core, V3D_CTL_MISCCFG);
137
138 nslc = V3D_GET_FIELD(ident1, V3D_IDENT1_NSLC);
139 ntmu = V3D_GET_FIELD(ident1, V3D_IDENT1_NTMU);
140 qups = V3D_GET_FIELD(ident1, V3D_IDENT1_QUPS);
141
142 seq_printf(m, "Core %d:\n", core);
143 seq_printf(m, " Revision: %d.%d\n",
144 V3D_GET_FIELD(ident0, V3D_IDENT0_VER),
145 V3D_GET_FIELD(ident1, V3D_IDENT1_REV));
146 seq_printf(m, " Slices: %d\n", nslc);
147 seq_printf(m, " TMUs: %d\n", nslc * ntmu);
148 seq_printf(m, " QPUs: %d\n", nslc * qups);
149 seq_printf(m, " Semaphores: %d\n",
150 V3D_GET_FIELD(ident1, V3D_IDENT1_NSEM));
151 seq_printf(m, " BCG int: %d\n",
152 (ident2 & V3D_IDENT2_BCG_INT) != 0);
153 seq_printf(m, " Override TMU: %d\n",
154 (misccfg & V3D_MISCCFG_OVRTMUOUT) != 0);
155 }
156
157 pm_runtime_mark_last_busy(v3d->dev);
158 pm_runtime_put_autosuspend(v3d->dev);
159
160 return 0;
161 }
162
v3d_debugfs_bo_stats(struct seq_file * m,void * unused)163 static int v3d_debugfs_bo_stats(struct seq_file *m, void *unused)
164 {
165 struct drm_info_node *node = (struct drm_info_node *)m->private;
166 struct drm_device *dev = node->minor->dev;
167 struct v3d_dev *v3d = to_v3d_dev(dev);
168
169 mutex_lock(&v3d->bo_lock);
170 seq_printf(m, "allocated bos: %d\n",
171 v3d->bo_stats.num_allocated);
172 seq_printf(m, "allocated bo size (kb): %ld\n",
173 (long)v3d->bo_stats.pages_allocated << (PAGE_SHIFT - 10));
174 mutex_unlock(&v3d->bo_lock);
175
176 return 0;
177 }
178
179 static const struct drm_info_list v3d_debugfs_list[] = {
180 {"v3d_ident", v3d_v3d_debugfs_ident, 0},
181 {"v3d_regs", v3d_v3d_debugfs_regs, 0},
182 {"bo_stats", v3d_debugfs_bo_stats, 0},
183 };
184
185 int
v3d_debugfs_init(struct drm_minor * minor)186 v3d_debugfs_init(struct drm_minor *minor)
187 {
188 return drm_debugfs_create_files(v3d_debugfs_list,
189 ARRAY_SIZE(v3d_debugfs_list),
190 minor->debugfs_root, minor);
191 }
192
