1 /* savage_drv.h -- Private header for the savage driver */ 2 /* 3 * Copyright 2004 Felix Kuehling 4 * All Rights Reserved. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sub license, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice (including the 14 * next paragraph) shall be included in all copies or substantial portions 15 * of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 20 * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR 21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF 22 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION 23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 24 */ 25 26 #ifndef __SAVAGE_DRV_H__ 27 #define __SAVAGE_DRV_H__ 28 29 #include <drm/drm_legacy.h> 30 31 #define DRIVER_AUTHOR "Felix Kuehling" 32 33 #define DRIVER_NAME "savage" 34 #define DRIVER_DESC "Savage3D/MX/IX, Savage4, SuperSavage, Twister, ProSavage[DDR]" 35 #define DRIVER_DATE "20050313" 36 37 #define DRIVER_MAJOR 2 38 #define DRIVER_MINOR 4 39 #define DRIVER_PATCHLEVEL 1 40 /* Interface history: 41 * 42 * 1.x The DRM driver from the VIA/S3 code drop, basically a dummy 43 * 2.0 The first real DRM 44 * 2.1 Scissors registers managed by the DRM, 3D operations clipped by 45 * cliprects of the cmdbuf ioctl 46 * 2.2 Implemented SAVAGE_CMD_DMA_IDX and SAVAGE_CMD_VB_IDX 47 * 2.3 Event counters used by BCI_EVENT_EMIT/WAIT ioctls are now 32 bits 48 * wide and thus very long lived (unlikely to ever wrap). The size 49 * in the struct was 32 bits before, but only 16 bits were used 50 * 2.4 Implemented command DMA. Now drm_savage_init_t.cmd_dma_offset is 51 * actually used 52 */ 53 54 typedef struct drm_savage_age { 55 uint16_t event; 56 unsigned int wrap; 57 } drm_savage_age_t; 58 59 typedef struct drm_savage_buf_priv { 60 struct drm_savage_buf_priv *next; 61 struct drm_savage_buf_priv *prev; 62 drm_savage_age_t age; 63 struct drm_buf *buf; 64 } drm_savage_buf_priv_t; 65 66 typedef struct drm_savage_dma_page { 67 drm_savage_age_t age; 68 unsigned int used, flushed; 69 } drm_savage_dma_page_t; 70 #define SAVAGE_DMA_PAGE_SIZE 1024 /* in dwords */ 71 /* Fake DMA buffer size in bytes. 4 pages. Allows a maximum command 72 * size of 16kbytes or 4k entries. Minimum requirement would be 73 * 10kbytes for 255 40-byte vertices in one drawing command. */ 74 #define SAVAGE_FAKE_DMA_SIZE (SAVAGE_DMA_PAGE_SIZE*4*4) 75 76 /* interesting bits of hardware state that are saved in dev_priv */ 77 typedef union { 78 struct drm_savage_common_state { 79 uint32_t vbaddr; 80 } common; 81 struct { 82 unsigned char pad[sizeof(struct drm_savage_common_state)]; 83 uint32_t texctrl, texaddr; 84 uint32_t scstart, new_scstart; 85 uint32_t scend, new_scend; 86 } s3d; 87 struct { 88 unsigned char pad[sizeof(struct drm_savage_common_state)]; 89 uint32_t texdescr, texaddr0, texaddr1; 90 uint32_t drawctrl0, new_drawctrl0; 91 uint32_t drawctrl1, new_drawctrl1; 92 } s4; 93 } drm_savage_state_t; 94 95 /* these chip tags should match the ones in the 2D driver in savage_regs.h. */ 96 enum savage_family { 97 S3_UNKNOWN = 0, 98 S3_SAVAGE3D, 99 S3_SAVAGE_MX, 100 S3_SAVAGE4, 101 S3_PROSAVAGE, 102 S3_TWISTER, 103 S3_PROSAVAGEDDR, 104 S3_SUPERSAVAGE, 105 S3_SAVAGE2000, 106 S3_LAST 107 }; 108 109 extern const struct drm_ioctl_desc savage_ioctls[]; 110 extern int savage_max_ioctl; 111 112 #define S3_SAVAGE3D_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE_MX)) 113 114 #define S3_SAVAGE4_SERIES(chip) ((chip==S3_SAVAGE4) \ 115 || (chip==S3_PROSAVAGE) \ 116 || (chip==S3_TWISTER) \ 117 || (chip==S3_PROSAVAGEDDR)) 118 119 #define S3_SAVAGE_MOBILE_SERIES(chip) ((chip==S3_SAVAGE_MX) || (chip==S3_SUPERSAVAGE)) 120 121 #define S3_SAVAGE_SERIES(chip) ((chip>=S3_SAVAGE3D) && (chip<=S3_SAVAGE2000)) 122 123 #define S3_MOBILE_TWISTER_SERIES(chip) ((chip==S3_TWISTER) \ 124 ||(chip==S3_PROSAVAGEDDR)) 125 126 /* flags */ 127 #define SAVAGE_IS_AGP 1 128 129 typedef struct drm_savage_private { 130 drm_savage_sarea_t *sarea_priv; 131 132 drm_savage_buf_priv_t head, tail; 133 134 /* who am I? */ 135 enum savage_family chipset; 136 137 unsigned int cob_size; 138 unsigned int bci_threshold_lo, bci_threshold_hi; 139 unsigned int dma_type; 140 141 /* frame buffer layout */ 142 unsigned int fb_bpp; 143 unsigned int front_offset, front_pitch; 144 unsigned int back_offset, back_pitch; 145 unsigned int depth_bpp; 146 unsigned int depth_offset, depth_pitch; 147 148 /* bitmap descriptors for swap and clear */ 149 unsigned int front_bd, back_bd, depth_bd; 150 151 /* local textures */ 152 unsigned int texture_offset; 153 unsigned int texture_size; 154 155 /* memory regions in physical memory */ 156 drm_local_map_t *sarea; 157 drm_local_map_t *mmio; 158 drm_local_map_t *fb; 159 drm_local_map_t *aperture; 160 drm_local_map_t *status; 161 drm_local_map_t *agp_textures; 162 drm_local_map_t *cmd_dma; 163 drm_local_map_t fake_dma; 164 165 int mtrr_handles[3]; 166 167 /* BCI and status-related stuff */ 168 volatile uint32_t *status_ptr, *bci_ptr; 169 uint32_t status_used_mask; 170 uint16_t event_counter; 171 unsigned int event_wrap; 172 173 /* Savage4 command DMA */ 174 drm_savage_dma_page_t *dma_pages; 175 unsigned int nr_dma_pages, first_dma_page, current_dma_page; 176 drm_savage_age_t last_dma_age; 177 178 /* saved hw state for global/local check on S3D */ 179 uint32_t hw_draw_ctrl, hw_zbuf_ctrl; 180 /* and for scissors (global, so don't emit if not changed) */ 181 uint32_t hw_scissors_start, hw_scissors_end; 182 183 drm_savage_state_t state; 184 185 /* after emitting a wait cmd Savage3D needs 63 nops before next DMA */ 186 unsigned int waiting; 187 188 /* config/hardware-dependent function pointers */ 189 int (*wait_fifo) (struct drm_savage_private * dev_priv, unsigned int n); 190 int (*wait_evnt) (struct drm_savage_private * dev_priv, uint16_t e); 191 /* Err, there is a macro wait_event in include/linux/wait.h. 192 * Avoid unwanted macro expansion. */ 193 void (*emit_clip_rect) (struct drm_savage_private * dev_priv, 194 const struct drm_clip_rect * pbox); 195 void (*dma_flush) (struct drm_savage_private * dev_priv); 196 } drm_savage_private_t; 197 198 /* ioctls */ 199 extern int savage_bci_cmdbuf(struct drm_device *dev, void *data, struct drm_file *file_priv); 200 extern int savage_bci_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv); 201 202 /* BCI functions */ 203 extern uint16_t savage_bci_emit_event(drm_savage_private_t * dev_priv, 204 unsigned int flags); 205 extern void savage_freelist_put(struct drm_device * dev, struct drm_buf * buf); 206 extern void savage_dma_reset(drm_savage_private_t * dev_priv); 207 extern void savage_dma_wait(drm_savage_private_t * dev_priv, unsigned int page); 208 extern uint32_t *savage_dma_alloc(drm_savage_private_t * dev_priv, 209 unsigned int n); 210 extern int savage_driver_load(struct drm_device *dev, unsigned long chipset); 211 extern int savage_driver_firstopen(struct drm_device *dev); 212 extern void savage_driver_lastclose(struct drm_device *dev); 213 extern void savage_driver_unload(struct drm_device *dev); 214 extern void savage_reclaim_buffers(struct drm_device *dev, 215 struct drm_file *file_priv); 216 217 /* state functions */ 218 extern void savage_emit_clip_rect_s3d(drm_savage_private_t * dev_priv, 219 const struct drm_clip_rect * pbox); 220 extern void savage_emit_clip_rect_s4(drm_savage_private_t * dev_priv, 221 const struct drm_clip_rect * pbox); 222 223 #define SAVAGE_FB_SIZE_S3 0x01000000 /* 16MB */ 224 #define SAVAGE_FB_SIZE_S4 0x02000000 /* 32MB */ 225 #define SAVAGE_MMIO_SIZE 0x00080000 /* 512kB */ 226 #define SAVAGE_APERTURE_OFFSET 0x02000000 /* 32MB */ 227 #define SAVAGE_APERTURE_SIZE 0x05000000 /* 5 tiled surfaces, 16MB each */ 228 229 #define SAVAGE_BCI_OFFSET 0x00010000 /* offset of the BCI region 230 * inside the MMIO region */ 231 #define SAVAGE_BCI_FIFO_SIZE 32 /* number of entries in on-chip 232 * BCI FIFO */ 233 234 /* 235 * MMIO registers 236 */ 237 #define SAVAGE_STATUS_WORD0 0x48C00 238 #define SAVAGE_STATUS_WORD1 0x48C04 239 #define SAVAGE_ALT_STATUS_WORD0 0x48C60 240 241 #define SAVAGE_FIFO_USED_MASK_S3D 0x0001ffff 242 #define SAVAGE_FIFO_USED_MASK_S4 0x001fffff 243 244 /* Copied from savage_bci.h in the 2D driver with some renaming. */ 245 246 /* Bitmap descriptors */ 247 #define SAVAGE_BD_STRIDE_SHIFT 0 248 #define SAVAGE_BD_BPP_SHIFT 16 249 #define SAVAGE_BD_TILE_SHIFT 24 250 #define SAVAGE_BD_BW_DISABLE (1<<28) 251 /* common: */ 252 #define SAVAGE_BD_TILE_LINEAR 0 253 /* savage4, MX, IX, 3D */ 254 #define SAVAGE_BD_TILE_16BPP 2 255 #define SAVAGE_BD_TILE_32BPP 3 256 /* twister, prosavage, DDR, supersavage, 2000 */ 257 #define SAVAGE_BD_TILE_DEST 1 258 #define SAVAGE_BD_TILE_TEXTURE 2 259 /* GBD - BCI enable */ 260 /* savage4, MX, IX, 3D */ 261 #define SAVAGE_GBD_BCI_ENABLE 8 262 /* twister, prosavage, DDR, supersavage, 2000 */ 263 #define SAVAGE_GBD_BCI_ENABLE_TWISTER 0 264 265 #define SAVAGE_GBD_BIG_ENDIAN 4 266 #define SAVAGE_GBD_LITTLE_ENDIAN 0 267 #define SAVAGE_GBD_64 1 268 269 /* Global Bitmap Descriptor */ 270 #define SAVAGE_BCI_GLB_BD_LOW 0x8168 271 #define SAVAGE_BCI_GLB_BD_HIGH 0x816C 272 273 /* 274 * BCI registers 275 */ 276 /* Savage4/Twister/ProSavage 3D registers */ 277 #define SAVAGE_DRAWLOCALCTRL_S4 0x1e 278 #define SAVAGE_TEXPALADDR_S4 0x1f 279 #define SAVAGE_TEXCTRL0_S4 0x20 280 #define SAVAGE_TEXCTRL1_S4 0x21 281 #define SAVAGE_TEXADDR0_S4 0x22 282 #define SAVAGE_TEXADDR1_S4 0x23 283 #define SAVAGE_TEXBLEND0_S4 0x24 284 #define SAVAGE_TEXBLEND1_S4 0x25 285 #define SAVAGE_TEXXPRCLR_S4 0x26 /* never used */ 286 #define SAVAGE_TEXDESCR_S4 0x27 287 #define SAVAGE_FOGTABLE_S4 0x28 288 #define SAVAGE_FOGCTRL_S4 0x30 289 #define SAVAGE_STENCILCTRL_S4 0x31 290 #define SAVAGE_ZBUFCTRL_S4 0x32 291 #define SAVAGE_ZBUFOFF_S4 0x33 292 #define SAVAGE_DESTCTRL_S4 0x34 293 #define SAVAGE_DRAWCTRL0_S4 0x35 294 #define SAVAGE_DRAWCTRL1_S4 0x36 295 #define SAVAGE_ZWATERMARK_S4 0x37 296 #define SAVAGE_DESTTEXRWWATERMARK_S4 0x38 297 #define SAVAGE_TEXBLENDCOLOR_S4 0x39 298 /* Savage3D/MX/IX 3D registers */ 299 #define SAVAGE_TEXPALADDR_S3D 0x18 300 #define SAVAGE_TEXXPRCLR_S3D 0x19 /* never used */ 301 #define SAVAGE_TEXADDR_S3D 0x1A 302 #define SAVAGE_TEXDESCR_S3D 0x1B 303 #define SAVAGE_TEXCTRL_S3D 0x1C 304 #define SAVAGE_FOGTABLE_S3D 0x20 305 #define SAVAGE_FOGCTRL_S3D 0x30 306 #define SAVAGE_DRAWCTRL_S3D 0x31 307 #define SAVAGE_ZBUFCTRL_S3D 0x32 308 #define SAVAGE_ZBUFOFF_S3D 0x33 309 #define SAVAGE_DESTCTRL_S3D 0x34 310 #define SAVAGE_SCSTART_S3D 0x35 311 #define SAVAGE_SCEND_S3D 0x36 312 #define SAVAGE_ZWATERMARK_S3D 0x37 313 #define SAVAGE_DESTTEXRWWATERMARK_S3D 0x38 314 /* common stuff */ 315 #define SAVAGE_VERTBUFADDR 0x3e 316 #define SAVAGE_BITPLANEWTMASK 0xd7 317 #define SAVAGE_DMABUFADDR 0x51 318 319 /* texture enable bits (needed for tex addr checking) */ 320 #define SAVAGE_TEXCTRL_TEXEN_MASK 0x00010000 /* S3D */ 321 #define SAVAGE_TEXDESCR_TEX0EN_MASK 0x02000000 /* S4 */ 322 #define SAVAGE_TEXDESCR_TEX1EN_MASK 0x04000000 /* S4 */ 323 324 /* Global fields in Savage4/Twister/ProSavage 3D registers: 325 * 326 * All texture registers and DrawLocalCtrl are local. All other 327 * registers are global. */ 328 329 /* Global fields in Savage3D/MX/IX 3D registers: 330 * 331 * All texture registers are local. DrawCtrl and ZBufCtrl are 332 * partially local. All other registers are global. 333 * 334 * DrawCtrl global fields: cullMode, alphaTestCmpFunc, alphaTestEn, alphaRefVal 335 * ZBufCtrl global fields: zCmpFunc, zBufEn 336 */ 337 #define SAVAGE_DRAWCTRL_S3D_GLOBAL 0x03f3c00c 338 #define SAVAGE_ZBUFCTRL_S3D_GLOBAL 0x00000027 339 340 /* Masks for scissor bits (drawCtrl[01] on s4, scissorStart/End on s3d) 341 */ 342 #define SAVAGE_SCISSOR_MASK_S4 0x00fff7ff 343 #define SAVAGE_SCISSOR_MASK_S3D 0x07ff07ff 344 345 /* 346 * BCI commands 347 */ 348 #define BCI_CMD_NOP 0x40000000 349 #define BCI_CMD_RECT 0x48000000 350 #define BCI_CMD_RECT_XP 0x01000000 351 #define BCI_CMD_RECT_YP 0x02000000 352 #define BCI_CMD_SCANLINE 0x50000000 353 #define BCI_CMD_LINE 0x5C000000 354 #define BCI_CMD_LINE_LAST_PIXEL 0x58000000 355 #define BCI_CMD_BYTE_TEXT 0x63000000 356 #define BCI_CMD_NT_BYTE_TEXT 0x67000000 357 #define BCI_CMD_BIT_TEXT 0x6C000000 358 #define BCI_CMD_GET_ROP(cmd) (((cmd) >> 16) & 0xFF) 359 #define BCI_CMD_SET_ROP(cmd, rop) ((cmd) |= ((rop & 0xFF) << 16)) 360 #define BCI_CMD_SEND_COLOR 0x00008000 361 362 #define BCI_CMD_CLIP_NONE 0x00000000 363 #define BCI_CMD_CLIP_CURRENT 0x00002000 364 #define BCI_CMD_CLIP_LR 0x00004000 365 #define BCI_CMD_CLIP_NEW 0x00006000 366 367 #define BCI_CMD_DEST_GBD 0x00000000 368 #define BCI_CMD_DEST_PBD 0x00000800 369 #define BCI_CMD_DEST_PBD_NEW 0x00000C00 370 #define BCI_CMD_DEST_SBD 0x00001000 371 #define BCI_CMD_DEST_SBD_NEW 0x00001400 372 373 #define BCI_CMD_SRC_TRANSPARENT 0x00000200 374 #define BCI_CMD_SRC_SOLID 0x00000000 375 #define BCI_CMD_SRC_GBD 0x00000020 376 #define BCI_CMD_SRC_COLOR 0x00000040 377 #define BCI_CMD_SRC_MONO 0x00000060 378 #define BCI_CMD_SRC_PBD_COLOR 0x00000080 379 #define BCI_CMD_SRC_PBD_MONO 0x000000A0 380 #define BCI_CMD_SRC_PBD_COLOR_NEW 0x000000C0 381 #define BCI_CMD_SRC_PBD_MONO_NEW 0x000000E0 382 #define BCI_CMD_SRC_SBD_COLOR 0x00000100 383 #define BCI_CMD_SRC_SBD_MONO 0x00000120 384 #define BCI_CMD_SRC_SBD_COLOR_NEW 0x00000140 385 #define BCI_CMD_SRC_SBD_MONO_NEW 0x00000160 386 387 #define BCI_CMD_PAT_TRANSPARENT 0x00000010 388 #define BCI_CMD_PAT_NONE 0x00000000 389 #define BCI_CMD_PAT_COLOR 0x00000002 390 #define BCI_CMD_PAT_MONO 0x00000003 391 #define BCI_CMD_PAT_PBD_COLOR 0x00000004 392 #define BCI_CMD_PAT_PBD_MONO 0x00000005 393 #define BCI_CMD_PAT_PBD_COLOR_NEW 0x00000006 394 #define BCI_CMD_PAT_PBD_MONO_NEW 0x00000007 395 #define BCI_CMD_PAT_SBD_COLOR 0x00000008 396 #define BCI_CMD_PAT_SBD_MONO 0x00000009 397 #define BCI_CMD_PAT_SBD_COLOR_NEW 0x0000000A 398 #define BCI_CMD_PAT_SBD_MONO_NEW 0x0000000B 399 400 #define BCI_BD_BW_DISABLE 0x10000000 401 #define BCI_BD_TILE_MASK 0x03000000 402 #define BCI_BD_TILE_NONE 0x00000000 403 #define BCI_BD_TILE_16 0x02000000 404 #define BCI_BD_TILE_32 0x03000000 405 #define BCI_BD_GET_BPP(bd) (((bd) >> 16) & 0xFF) 406 #define BCI_BD_SET_BPP(bd, bpp) ((bd) |= (((bpp) & 0xFF) << 16)) 407 #define BCI_BD_GET_STRIDE(bd) ((bd) & 0xFFFF) 408 #define BCI_BD_SET_STRIDE(bd, st) ((bd) |= ((st) & 0xFFFF)) 409 410 #define BCI_CMD_SET_REGISTER 0x96000000 411 412 #define BCI_CMD_WAIT 0xC0000000 413 #define BCI_CMD_WAIT_3D 0x00010000 414 #define BCI_CMD_WAIT_2D 0x00020000 415 416 #define BCI_CMD_UPDATE_EVENT_TAG 0x98000000 417 418 #define BCI_CMD_DRAW_PRIM 0x80000000 419 #define BCI_CMD_DRAW_INDEXED_PRIM 0x88000000 420 #define BCI_CMD_DRAW_CONT 0x01000000 421 #define BCI_CMD_DRAW_TRILIST 0x00000000 422 #define BCI_CMD_DRAW_TRISTRIP 0x02000000 423 #define BCI_CMD_DRAW_TRIFAN 0x04000000 424 #define BCI_CMD_DRAW_SKIPFLAGS 0x000000ff 425 #define BCI_CMD_DRAW_NO_Z 0x00000001 426 #define BCI_CMD_DRAW_NO_W 0x00000002 427 #define BCI_CMD_DRAW_NO_CD 0x00000004 428 #define BCI_CMD_DRAW_NO_CS 0x00000008 429 #define BCI_CMD_DRAW_NO_U0 0x00000010 430 #define BCI_CMD_DRAW_NO_V0 0x00000020 431 #define BCI_CMD_DRAW_NO_UV0 0x00000030 432 #define BCI_CMD_DRAW_NO_U1 0x00000040 433 #define BCI_CMD_DRAW_NO_V1 0x00000080 434 #define BCI_CMD_DRAW_NO_UV1 0x000000c0 435 436 #define BCI_CMD_DMA 0xa8000000 437 438 #define BCI_W_H(w, h) ((((h) << 16) | (w)) & 0x0FFF0FFF) 439 #define BCI_X_Y(x, y) ((((y) << 16) | (x)) & 0x0FFF0FFF) 440 #define BCI_X_W(x, y) ((((w) << 16) | (x)) & 0x0FFF0FFF) 441 #define BCI_CLIP_LR(l, r) ((((r) << 16) | (l)) & 0x0FFF0FFF) 442 #define BCI_CLIP_TL(t, l) ((((t) << 16) | (l)) & 0x0FFF0FFF) 443 #define BCI_CLIP_BR(b, r) ((((b) << 16) | (r)) & 0x0FFF0FFF) 444 445 #define BCI_LINE_X_Y(x, y) (((y) << 16) | ((x) & 0xFFFF)) 446 #define BCI_LINE_STEPS(diag, axi) (((axi) << 16) | ((diag) & 0xFFFF)) 447 #define BCI_LINE_MISC(maj, ym, xp, yp, err) \ 448 (((maj) & 0x1FFF) | \ 449 ((ym) ? 1<<13 : 0) | \ 450 ((xp) ? 1<<14 : 0) | \ 451 ((yp) ? 1<<15 : 0) | \ 452 ((err) << 16)) 453 454 /* 455 * common commands 456 */ 457 #define BCI_SET_REGISTERS( first, n ) \ 458 BCI_WRITE(BCI_CMD_SET_REGISTER | \ 459 ((uint32_t)(n) & 0xff) << 16 | \ 460 ((uint32_t)(first) & 0xffff)) 461 #define DMA_SET_REGISTERS( first, n ) \ 462 DMA_WRITE(BCI_CMD_SET_REGISTER | \ 463 ((uint32_t)(n) & 0xff) << 16 | \ 464 ((uint32_t)(first) & 0xffff)) 465 466 #define BCI_DRAW_PRIMITIVE(n, type, skip) \ 467 BCI_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \ 468 ((n) << 16)) 469 #define DMA_DRAW_PRIMITIVE(n, type, skip) \ 470 DMA_WRITE(BCI_CMD_DRAW_PRIM | (type) | (skip) | \ 471 ((n) << 16)) 472 473 #define BCI_DRAW_INDICES_S3D(n, type, i0) \ 474 BCI_WRITE(BCI_CMD_DRAW_INDEXED_PRIM | (type) | \ 475 ((n) << 16) | (i0)) 476 477 #define BCI_DRAW_INDICES_S4(n, type, skip) \ 478 BCI_WRITE(BCI_CMD_DRAW_INDEXED_PRIM | (type) | \ 479 (skip) | ((n) << 16)) 480 481 #define BCI_DMA(n) \ 482 BCI_WRITE(BCI_CMD_DMA | (((n) >> 1) - 1)) 483 484 /* 485 * access to MMIO 486 */ 487 #define SAVAGE_READ(reg) DRM_READ32( dev_priv->mmio, (reg) ) 488 #define SAVAGE_WRITE(reg) DRM_WRITE32( dev_priv->mmio, (reg) ) 489 490 /* 491 * access to the burst command interface (BCI) 492 */ 493 #define SAVAGE_BCI_DEBUG 1 494 495 #define BCI_LOCALS volatile uint32_t *bci_ptr; 496 497 #define BEGIN_BCI( n ) do { \ 498 dev_priv->wait_fifo(dev_priv, (n)); \ 499 bci_ptr = dev_priv->bci_ptr; \ 500 } while(0) 501 502 #define BCI_WRITE( val ) *bci_ptr++ = (uint32_t)(val) 503 504 /* 505 * command DMA support 506 */ 507 #define SAVAGE_DMA_DEBUG 1 508 509 #define DMA_LOCALS uint32_t *dma_ptr; 510 511 #define BEGIN_DMA( n ) do { \ 512 unsigned int cur = dev_priv->current_dma_page; \ 513 unsigned int rest = SAVAGE_DMA_PAGE_SIZE - \ 514 dev_priv->dma_pages[cur].used; \ 515 if ((n) > rest) { \ 516 dma_ptr = savage_dma_alloc(dev_priv, (n)); \ 517 } else { /* fast path for small allocations */ \ 518 dma_ptr = (uint32_t *)dev_priv->cmd_dma->handle + \ 519 cur * SAVAGE_DMA_PAGE_SIZE + \ 520 dev_priv->dma_pages[cur].used; \ 521 if (dev_priv->dma_pages[cur].used == 0) \ 522 savage_dma_wait(dev_priv, cur); \ 523 dev_priv->dma_pages[cur].used += (n); \ 524 } \ 525 } while(0) 526 527 #define DMA_WRITE( val ) *dma_ptr++ = (uint32_t)(val) 528 529 #define DMA_COPY(src, n) do { \ 530 memcpy(dma_ptr, (src), (n)*4); \ 531 dma_ptr += n; \ 532 } while(0) 533 534 #if SAVAGE_DMA_DEBUG 535 #define DMA_COMMIT() do { \ 536 unsigned int cur = dev_priv->current_dma_page; \ 537 uint32_t *expected = (uint32_t *)dev_priv->cmd_dma->handle + \ 538 cur * SAVAGE_DMA_PAGE_SIZE + \ 539 dev_priv->dma_pages[cur].used; \ 540 if (dma_ptr != expected) { \ 541 DRM_ERROR("DMA allocation and use don't match: " \ 542 "%p != %p\n", expected, dma_ptr); \ 543 savage_dma_reset(dev_priv); \ 544 } \ 545 } while(0) 546 #else 547 #define DMA_COMMIT() do {/* nothing */} while(0) 548 #endif 549 550 #define DMA_FLUSH() dev_priv->dma_flush(dev_priv) 551 552 /* Buffer aging via event tag 553 */ 554 555 #define UPDATE_EVENT_COUNTER( ) do { \ 556 if (dev_priv->status_ptr) { \ 557 uint16_t count; \ 558 /* coordinate with Xserver */ \ 559 count = dev_priv->status_ptr[1023]; \ 560 if (count < dev_priv->event_counter) \ 561 dev_priv->event_wrap++; \ 562 dev_priv->event_counter = count; \ 563 } \ 564 } while(0) 565 566 #define SET_AGE( age, e, w ) do { \ 567 (age)->event = e; \ 568 (age)->wrap = w; \ 569 } while(0) 570 571 #define TEST_AGE( age, e, w ) \ 572 ( (age)->wrap < (w) || ( (age)->wrap == (w) && (age)->event <= (e) ) ) 573 574 #endif /* __SAVAGE_DRV_H__ */ 575
