1 /* savage_bci.c -- BCI support for Savage
2 *
3 * Copyright 2004 Felix Kuehling
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sub license,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the
14 * next paragraph) shall be included in all copies or substantial portions
15 * of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
18 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
19 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
20 * NON-INFRINGEMENT. IN NO EVENT SHALL FELIX KUEHLING BE LIABLE FOR
21 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF
22 * CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
23 * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
24 */
25 #include <drm/drmP.h>
26 #include <drm/savage_drm.h>
27 #include "savage_drv.h"
28
29 /* Need a long timeout for shadow status updates can take a while
30 * and so can waiting for events when the queue is full. */
31 #define SAVAGE_DEFAULT_USEC_TIMEOUT 1000000 /* 1s */
32 #define SAVAGE_EVENT_USEC_TIMEOUT 5000000 /* 5s */
33 #define SAVAGE_FREELIST_DEBUG 0
34
35 static int savage_do_cleanup_bci(struct drm_device *dev);
36
37 static int
savage_bci_wait_fifo_shadow(drm_savage_private_t * dev_priv,unsigned int n)38 savage_bci_wait_fifo_shadow(drm_savage_private_t * dev_priv, unsigned int n)
39 {
40 uint32_t mask = dev_priv->status_used_mask;
41 uint32_t threshold = dev_priv->bci_threshold_hi;
42 uint32_t status;
43 int i;
44
45 #if SAVAGE_BCI_DEBUG
46 if (n > dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - threshold)
47 DRM_ERROR("Trying to emit %d words "
48 "(more than guaranteed space in COB)\n", n);
49 #endif
50
51 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) {
52 mb();
53 status = dev_priv->status_ptr[0];
54 if ((status & mask) < threshold)
55 return 0;
56 DRM_UDELAY(1);
57 }
58
59 #if SAVAGE_BCI_DEBUG
60 DRM_ERROR("failed!\n");
61 DRM_INFO(" status=0x%08x, threshold=0x%08x\n", status, threshold);
62 #endif
63 return -EBUSY;
64 }
65
66 static int
savage_bci_wait_fifo_s3d(drm_savage_private_t * dev_priv,unsigned int n)67 savage_bci_wait_fifo_s3d(drm_savage_private_t * dev_priv, unsigned int n)
68 {
69 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n;
70 uint32_t status;
71 int i;
72
73 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) {
74 status = SAVAGE_READ(SAVAGE_STATUS_WORD0);
75 if ((status & SAVAGE_FIFO_USED_MASK_S3D) <= maxUsed)
76 return 0;
77 DRM_UDELAY(1);
78 }
79
80 #if SAVAGE_BCI_DEBUG
81 DRM_ERROR("failed!\n");
82 DRM_INFO(" status=0x%08x\n", status);
83 #endif
84 return -EBUSY;
85 }
86
87 static int
savage_bci_wait_fifo_s4(drm_savage_private_t * dev_priv,unsigned int n)88 savage_bci_wait_fifo_s4(drm_savage_private_t * dev_priv, unsigned int n)
89 {
90 uint32_t maxUsed = dev_priv->cob_size + SAVAGE_BCI_FIFO_SIZE - n;
91 uint32_t status;
92 int i;
93
94 for (i = 0; i < SAVAGE_DEFAULT_USEC_TIMEOUT; i++) {
95 status = SAVAGE_READ(SAVAGE_ALT_STATUS_WORD0);
96 if ((status & SAVAGE_FIFO_USED_MASK_S4) <= maxUsed)
97 return 0;
98 DRM_UDELAY(1);
99 }
100
101 #if SAVAGE_BCI_DEBUG
102 DRM_ERROR("failed!\n");
103 DRM_INFO(" status=0x%08x\n", status);
104 #endif
105 return -EBUSY;
106 }
107
108 /*
109 * Waiting for events.
110 *
111 * The BIOSresets the event tag to 0 on mode changes. Therefore we
112 * never emit 0 to the event tag. If we find a 0 event tag we know the
113 * BIOS stomped on it and return success assuming that the BIOS waited
114 * for engine idle.
115 *
116 * Note: if the Xserver uses the event tag it has to follow the same
117 * rule. Otherwise there may be glitches every 2^16 events.
118 */
119 static int
savage_bci_wait_event_shadow(drm_savage_private_t * dev_priv,uint16_t e)120 savage_bci_wait_event_shadow(drm_savage_private_t * dev_priv, uint16_t e)
121 {
122 uint32_t status;
123 int i;
124
125 for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) {
126 mb();
127 status = dev_priv->status_ptr[1];
128 if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff ||
129 (status & 0xffff) == 0)
130 return 0;
131 DRM_UDELAY(1);
132 }
133
134 #if SAVAGE_BCI_DEBUG
135 DRM_ERROR("failed!\n");
136 DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e);
137 #endif
138
139 return -EBUSY;
140 }
141
142 static int
savage_bci_wait_event_reg(drm_savage_private_t * dev_priv,uint16_t e)143 savage_bci_wait_event_reg(drm_savage_private_t * dev_priv, uint16_t e)
144 {
145 uint32_t status;
146 int i;
147
148 for (i = 0; i < SAVAGE_EVENT_USEC_TIMEOUT; i++) {
149 status = SAVAGE_READ(SAVAGE_STATUS_WORD1);
150 if ((((status & 0xffff) - e) & 0xffff) <= 0x7fff ||
151 (status & 0xffff) == 0)
152 return 0;
153 DRM_UDELAY(1);
154 }
155
156 #if SAVAGE_BCI_DEBUG
157 DRM_ERROR("failed!\n");
158 DRM_INFO(" status=0x%08x, e=0x%04x\n", status, e);
159 #endif
160
161 return -EBUSY;
162 }
163
savage_bci_emit_event(drm_savage_private_t * dev_priv,unsigned int flags)164 uint16_t savage_bci_emit_event(drm_savage_private_t * dev_priv,
165 unsigned int flags)
166 {
167 uint16_t count;
168 BCI_LOCALS;
169
170 if (dev_priv->status_ptr) {
171 /* coordinate with Xserver */
172 count = dev_priv->status_ptr[1023];
173 if (count < dev_priv->event_counter)
174 dev_priv->event_wrap++;
175 } else {
176 count = dev_priv->event_counter;
177 }
178 count = (count + 1) & 0xffff;
179 if (count == 0) {
180 count++; /* See the comment above savage_wait_event_*. */
181 dev_priv->event_wrap++;
182 }
183 dev_priv->event_counter = count;
184 if (dev_priv->status_ptr)
185 dev_priv->status_ptr[1023] = (uint32_t) count;
186
187 if ((flags & (SAVAGE_WAIT_2D | SAVAGE_WAIT_3D))) {
188 unsigned int wait_cmd = BCI_CMD_WAIT;
189 if ((flags & SAVAGE_WAIT_2D))
190 wait_cmd |= BCI_CMD_WAIT_2D;
191 if ((flags & SAVAGE_WAIT_3D))
192 wait_cmd |= BCI_CMD_WAIT_3D;
193 BEGIN_BCI(2);
194 BCI_WRITE(wait_cmd);
195 } else {
196 BEGIN_BCI(1);
197 }
198 BCI_WRITE(BCI_CMD_UPDATE_EVENT_TAG | (uint32_t) count);
199
200 return count;
201 }
202
203 /*
204 * Freelist management
205 */
savage_freelist_init(struct drm_device * dev)206 static int savage_freelist_init(struct drm_device * dev)
207 {
208 drm_savage_private_t *dev_priv = dev->dev_private;
209 struct drm_device_dma *dma = dev->dma;
210 struct drm_buf *buf;
211 drm_savage_buf_priv_t *entry;
212 int i;
213 DRM_DEBUG("count=%d\n", dma->buf_count);
214
215 dev_priv->head.next = &dev_priv->tail;
216 dev_priv->head.prev = NULL;
217 dev_priv->head.buf = NULL;
218
219 dev_priv->tail.next = NULL;
220 dev_priv->tail.prev = &dev_priv->head;
221 dev_priv->tail.buf = NULL;
222
223 for (i = 0; i < dma->buf_count; i++) {
224 buf = dma->buflist[i];
225 entry = buf->dev_private;
226
227 SET_AGE(&entry->age, 0, 0);
228 entry->buf = buf;
229
230 entry->next = dev_priv->head.next;
231 entry->prev = &dev_priv->head;
232 dev_priv->head.next->prev = entry;
233 dev_priv->head.next = entry;
234 }
235
236 return 0;
237 }
238
savage_freelist_get(struct drm_device * dev)239 static struct drm_buf *savage_freelist_get(struct drm_device * dev)
240 {
241 drm_savage_private_t *dev_priv = dev->dev_private;
242 drm_savage_buf_priv_t *tail = dev_priv->tail.prev;
243 uint16_t event;
244 unsigned int wrap;
245 DRM_DEBUG("\n");
246
247 UPDATE_EVENT_COUNTER();
248 if (dev_priv->status_ptr)
249 event = dev_priv->status_ptr[1] & 0xffff;
250 else
251 event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
252 wrap = dev_priv->event_wrap;
253 if (event > dev_priv->event_counter)
254 wrap--; /* hardware hasn't passed the last wrap yet */
255
256 DRM_DEBUG(" tail=0x%04x %d\n", tail->age.event, tail->age.wrap);
257 DRM_DEBUG(" head=0x%04x %d\n", event, wrap);
258
259 if (tail->buf && (TEST_AGE(&tail->age, event, wrap) || event == 0)) {
260 drm_savage_buf_priv_t *next = tail->next;
261 drm_savage_buf_priv_t *prev = tail->prev;
262 prev->next = next;
263 next->prev = prev;
264 tail->next = tail->prev = NULL;
265 return tail->buf;
266 }
267
268 DRM_DEBUG("returning NULL, tail->buf=%p!\n", tail->buf);
269 return NULL;
270 }
271
savage_freelist_put(struct drm_device * dev,struct drm_buf * buf)272 void savage_freelist_put(struct drm_device * dev, struct drm_buf * buf)
273 {
274 drm_savage_private_t *dev_priv = dev->dev_private;
275 drm_savage_buf_priv_t *entry = buf->dev_private, *prev, *next;
276
277 DRM_DEBUG("age=0x%04x wrap=%d\n", entry->age.event, entry->age.wrap);
278
279 if (entry->next != NULL || entry->prev != NULL) {
280 DRM_ERROR("entry already on freelist.\n");
281 return;
282 }
283
284 prev = &dev_priv->head;
285 next = prev->next;
286 prev->next = entry;
287 next->prev = entry;
288 entry->prev = prev;
289 entry->next = next;
290 }
291
292 /*
293 * Command DMA
294 */
savage_dma_init(drm_savage_private_t * dev_priv)295 static int savage_dma_init(drm_savage_private_t * dev_priv)
296 {
297 unsigned int i;
298
299 dev_priv->nr_dma_pages = dev_priv->cmd_dma->size /
300 (SAVAGE_DMA_PAGE_SIZE * 4);
301 dev_priv->dma_pages = kmalloc_array(dev_priv->nr_dma_pages,
302 sizeof(drm_savage_dma_page_t),
303 GFP_KERNEL);
304 if (dev_priv->dma_pages == NULL)
305 return -ENOMEM;
306
307 for (i = 0; i < dev_priv->nr_dma_pages; ++i) {
308 SET_AGE(&dev_priv->dma_pages[i].age, 0, 0);
309 dev_priv->dma_pages[i].used = 0;
310 dev_priv->dma_pages[i].flushed = 0;
311 }
312 SET_AGE(&dev_priv->last_dma_age, 0, 0);
313
314 dev_priv->first_dma_page = 0;
315 dev_priv->current_dma_page = 0;
316
317 return 0;
318 }
319
savage_dma_reset(drm_savage_private_t * dev_priv)320 void savage_dma_reset(drm_savage_private_t * dev_priv)
321 {
322 uint16_t event;
323 unsigned int wrap, i;
324 event = savage_bci_emit_event(dev_priv, 0);
325 wrap = dev_priv->event_wrap;
326 for (i = 0; i < dev_priv->nr_dma_pages; ++i) {
327 SET_AGE(&dev_priv->dma_pages[i].age, event, wrap);
328 dev_priv->dma_pages[i].used = 0;
329 dev_priv->dma_pages[i].flushed = 0;
330 }
331 SET_AGE(&dev_priv->last_dma_age, event, wrap);
332 dev_priv->first_dma_page = dev_priv->current_dma_page = 0;
333 }
334
savage_dma_wait(drm_savage_private_t * dev_priv,unsigned int page)335 void savage_dma_wait(drm_savage_private_t * dev_priv, unsigned int page)
336 {
337 uint16_t event;
338 unsigned int wrap;
339
340 /* Faked DMA buffer pages don't age. */
341 if (dev_priv->cmd_dma == &dev_priv->fake_dma)
342 return;
343
344 UPDATE_EVENT_COUNTER();
345 if (dev_priv->status_ptr)
346 event = dev_priv->status_ptr[1] & 0xffff;
347 else
348 event = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
349 wrap = dev_priv->event_wrap;
350 if (event > dev_priv->event_counter)
351 wrap--; /* hardware hasn't passed the last wrap yet */
352
353 if (dev_priv->dma_pages[page].age.wrap > wrap ||
354 (dev_priv->dma_pages[page].age.wrap == wrap &&
355 dev_priv->dma_pages[page].age.event > event)) {
356 if (dev_priv->wait_evnt(dev_priv,
357 dev_priv->dma_pages[page].age.event)
358 < 0)
359 DRM_ERROR("wait_evnt failed!\n");
360 }
361 }
362
savage_dma_alloc(drm_savage_private_t * dev_priv,unsigned int n)363 uint32_t *savage_dma_alloc(drm_savage_private_t * dev_priv, unsigned int n)
364 {
365 unsigned int cur = dev_priv->current_dma_page;
366 unsigned int rest = SAVAGE_DMA_PAGE_SIZE -
367 dev_priv->dma_pages[cur].used;
368 unsigned int nr_pages = (n - rest + SAVAGE_DMA_PAGE_SIZE - 1) /
369 SAVAGE_DMA_PAGE_SIZE;
370 uint32_t *dma_ptr;
371 unsigned int i;
372
373 DRM_DEBUG("cur=%u, cur->used=%u, n=%u, rest=%u, nr_pages=%u\n",
374 cur, dev_priv->dma_pages[cur].used, n, rest, nr_pages);
375
376 if (cur + nr_pages < dev_priv->nr_dma_pages) {
377 dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle +
378 cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used;
379 if (n < rest)
380 rest = n;
381 dev_priv->dma_pages[cur].used += rest;
382 n -= rest;
383 cur++;
384 } else {
385 dev_priv->dma_flush(dev_priv);
386 nr_pages =
387 (n + SAVAGE_DMA_PAGE_SIZE - 1) / SAVAGE_DMA_PAGE_SIZE;
388 for (i = cur; i < dev_priv->nr_dma_pages; ++i) {
389 dev_priv->dma_pages[i].age = dev_priv->last_dma_age;
390 dev_priv->dma_pages[i].used = 0;
391 dev_priv->dma_pages[i].flushed = 0;
392 }
393 dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle;
394 dev_priv->first_dma_page = cur = 0;
395 }
396 for (i = cur; nr_pages > 0; ++i, --nr_pages) {
397 #if SAVAGE_DMA_DEBUG
398 if (dev_priv->dma_pages[i].used) {
399 DRM_ERROR("unflushed page %u: used=%u\n",
400 i, dev_priv->dma_pages[i].used);
401 }
402 #endif
403 if (n > SAVAGE_DMA_PAGE_SIZE)
404 dev_priv->dma_pages[i].used = SAVAGE_DMA_PAGE_SIZE;
405 else
406 dev_priv->dma_pages[i].used = n;
407 n -= SAVAGE_DMA_PAGE_SIZE;
408 }
409 dev_priv->current_dma_page = --i;
410
411 DRM_DEBUG("cur=%u, cur->used=%u, n=%u\n",
412 i, dev_priv->dma_pages[i].used, n);
413
414 savage_dma_wait(dev_priv, dev_priv->current_dma_page);
415
416 return dma_ptr;
417 }
418
savage_dma_flush(drm_savage_private_t * dev_priv)419 static void savage_dma_flush(drm_savage_private_t * dev_priv)
420 {
421 unsigned int first = dev_priv->first_dma_page;
422 unsigned int cur = dev_priv->current_dma_page;
423 uint16_t event;
424 unsigned int wrap, pad, align, len, i;
425 unsigned long phys_addr;
426 BCI_LOCALS;
427
428 if (first == cur &&
429 dev_priv->dma_pages[cur].used == dev_priv->dma_pages[cur].flushed)
430 return;
431
432 /* pad length to multiples of 2 entries
433 * align start of next DMA block to multiles of 8 entries */
434 pad = -dev_priv->dma_pages[cur].used & 1;
435 align = -(dev_priv->dma_pages[cur].used + pad) & 7;
436
437 DRM_DEBUG("first=%u, cur=%u, first->flushed=%u, cur->used=%u, "
438 "pad=%u, align=%u\n",
439 first, cur, dev_priv->dma_pages[first].flushed,
440 dev_priv->dma_pages[cur].used, pad, align);
441
442 /* pad with noops */
443 if (pad) {
444 uint32_t *dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle +
445 cur * SAVAGE_DMA_PAGE_SIZE + dev_priv->dma_pages[cur].used;
446 dev_priv->dma_pages[cur].used += pad;
447 while (pad != 0) {
448 *dma_ptr++ = BCI_CMD_WAIT;
449 pad--;
450 }
451 }
452
453 mb();
454
455 /* do flush ... */
456 phys_addr = dev_priv->cmd_dma->offset +
457 (first * SAVAGE_DMA_PAGE_SIZE +
458 dev_priv->dma_pages[first].flushed) * 4;
459 len = (cur - first) * SAVAGE_DMA_PAGE_SIZE +
460 dev_priv->dma_pages[cur].used - dev_priv->dma_pages[first].flushed;
461
462 DRM_DEBUG("phys_addr=%lx, len=%u\n",
463 phys_addr | dev_priv->dma_type, len);
464
465 BEGIN_BCI(3);
466 BCI_SET_REGISTERS(SAVAGE_DMABUFADDR, 1);
467 BCI_WRITE(phys_addr | dev_priv->dma_type);
468 BCI_DMA(len);
469
470 /* fix alignment of the start of the next block */
471 dev_priv->dma_pages[cur].used += align;
472
473 /* age DMA pages */
474 event = savage_bci_emit_event(dev_priv, 0);
475 wrap = dev_priv->event_wrap;
476 for (i = first; i < cur; ++i) {
477 SET_AGE(&dev_priv->dma_pages[i].age, event, wrap);
478 dev_priv->dma_pages[i].used = 0;
479 dev_priv->dma_pages[i].flushed = 0;
480 }
481 /* age the current page only when it's full */
482 if (dev_priv->dma_pages[cur].used == SAVAGE_DMA_PAGE_SIZE) {
483 SET_AGE(&dev_priv->dma_pages[cur].age, event, wrap);
484 dev_priv->dma_pages[cur].used = 0;
485 dev_priv->dma_pages[cur].flushed = 0;
486 /* advance to next page */
487 cur++;
488 if (cur == dev_priv->nr_dma_pages)
489 cur = 0;
490 dev_priv->first_dma_page = dev_priv->current_dma_page = cur;
491 } else {
492 dev_priv->first_dma_page = cur;
493 dev_priv->dma_pages[cur].flushed = dev_priv->dma_pages[i].used;
494 }
495 SET_AGE(&dev_priv->last_dma_age, event, wrap);
496
497 DRM_DEBUG("first=cur=%u, cur->used=%u, cur->flushed=%u\n", cur,
498 dev_priv->dma_pages[cur].used,
499 dev_priv->dma_pages[cur].flushed);
500 }
501
savage_fake_dma_flush(drm_savage_private_t * dev_priv)502 static void savage_fake_dma_flush(drm_savage_private_t * dev_priv)
503 {
504 unsigned int i, j;
505 BCI_LOCALS;
506
507 if (dev_priv->first_dma_page == dev_priv->current_dma_page &&
508 dev_priv->dma_pages[dev_priv->current_dma_page].used == 0)
509 return;
510
511 DRM_DEBUG("first=%u, cur=%u, cur->used=%u\n",
512 dev_priv->first_dma_page, dev_priv->current_dma_page,
513 dev_priv->dma_pages[dev_priv->current_dma_page].used);
514
515 for (i = dev_priv->first_dma_page;
516 i <= dev_priv->current_dma_page && dev_priv->dma_pages[i].used;
517 ++i) {
518 uint32_t *dma_ptr = (uint32_t *) dev_priv->cmd_dma->handle +
519 i * SAVAGE_DMA_PAGE_SIZE;
520 #if SAVAGE_DMA_DEBUG
521 /* Sanity check: all pages except the last one must be full. */
522 if (i < dev_priv->current_dma_page &&
523 dev_priv->dma_pages[i].used != SAVAGE_DMA_PAGE_SIZE) {
524 DRM_ERROR("partial DMA page %u: used=%u",
525 i, dev_priv->dma_pages[i].used);
526 }
527 #endif
528 BEGIN_BCI(dev_priv->dma_pages[i].used);
529 for (j = 0; j < dev_priv->dma_pages[i].used; ++j) {
530 BCI_WRITE(dma_ptr[j]);
531 }
532 dev_priv->dma_pages[i].used = 0;
533 }
534
535 /* reset to first page */
536 dev_priv->first_dma_page = dev_priv->current_dma_page = 0;
537 }
538
savage_driver_load(struct drm_device * dev,unsigned long chipset)539 int savage_driver_load(struct drm_device *dev, unsigned long chipset)
540 {
541 drm_savage_private_t *dev_priv;
542
543 dev_priv = kzalloc(sizeof(drm_savage_private_t), GFP_KERNEL);
544 if (dev_priv == NULL)
545 return -ENOMEM;
546
547 dev->dev_private = (void *)dev_priv;
548
549 dev_priv->chipset = (enum savage_family)chipset;
550
551 pci_set_master(dev->pdev);
552
553 return 0;
554 }
555
556
557 /*
558 * Initialize mappings. On Savage4 and SavageIX the alignment
559 * and size of the aperture is not suitable for automatic MTRR setup
560 * in drm_legacy_addmap. Therefore we add them manually before the maps are
561 * initialized, and tear them down on last close.
562 */
savage_driver_firstopen(struct drm_device * dev)563 int savage_driver_firstopen(struct drm_device *dev)
564 {
565 drm_savage_private_t *dev_priv = dev->dev_private;
566 unsigned long mmio_base, fb_base, fb_size, aperture_base;
567 /* fb_rsrc and aper_rsrc aren't really used currently, but still exist
568 * in case we decide we need information on the BAR for BSD in the
569 * future.
570 */
571 unsigned int fb_rsrc, aper_rsrc;
572 int ret = 0;
573
574 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
575 fb_rsrc = 0;
576 fb_base = pci_resource_start(dev->pdev, 0);
577 fb_size = SAVAGE_FB_SIZE_S3;
578 mmio_base = fb_base + SAVAGE_FB_SIZE_S3;
579 aper_rsrc = 0;
580 aperture_base = fb_base + SAVAGE_APERTURE_OFFSET;
581 /* this should always be true */
582 if (pci_resource_len(dev->pdev, 0) == 0x08000000) {
583 /* Don't make MMIO write-cobining! We need 3
584 * MTRRs. */
585 dev_priv->mtrr_handles[0] =
586 arch_phys_wc_add(fb_base, 0x01000000);
587 dev_priv->mtrr_handles[1] =
588 arch_phys_wc_add(fb_base + 0x02000000,
589 0x02000000);
590 dev_priv->mtrr_handles[2] =
591 arch_phys_wc_add(fb_base + 0x04000000,
592 0x04000000);
593 } else {
594 DRM_ERROR("strange pci_resource_len %08llx\n",
595 (unsigned long long)
596 pci_resource_len(dev->pdev, 0));
597 }
598 } else if (dev_priv->chipset != S3_SUPERSAVAGE &&
599 dev_priv->chipset != S3_SAVAGE2000) {
600 mmio_base = pci_resource_start(dev->pdev, 0);
601 fb_rsrc = 1;
602 fb_base = pci_resource_start(dev->pdev, 1);
603 fb_size = SAVAGE_FB_SIZE_S4;
604 aper_rsrc = 1;
605 aperture_base = fb_base + SAVAGE_APERTURE_OFFSET;
606 /* this should always be true */
607 if (pci_resource_len(dev->pdev, 1) == 0x08000000) {
608 /* Can use one MTRR to cover both fb and
609 * aperture. */
610 dev_priv->mtrr_handles[0] =
611 arch_phys_wc_add(fb_base,
612 0x08000000);
613 } else {
614 DRM_ERROR("strange pci_resource_len %08llx\n",
615 (unsigned long long)
616 pci_resource_len(dev->pdev, 1));
617 }
618 } else {
619 mmio_base = pci_resource_start(dev->pdev, 0);
620 fb_rsrc = 1;
621 fb_base = pci_resource_start(dev->pdev, 1);
622 fb_size = pci_resource_len(dev->pdev, 1);
623 aper_rsrc = 2;
624 aperture_base = pci_resource_start(dev->pdev, 2);
625 /* Automatic MTRR setup will do the right thing. */
626 }
627
628 ret = drm_legacy_addmap(dev, mmio_base, SAVAGE_MMIO_SIZE,
629 _DRM_REGISTERS, _DRM_READ_ONLY,
630 &dev_priv->mmio);
631 if (ret)
632 return ret;
633
634 ret = drm_legacy_addmap(dev, fb_base, fb_size, _DRM_FRAME_BUFFER,
635 _DRM_WRITE_COMBINING, &dev_priv->fb);
636 if (ret)
637 return ret;
638
639 ret = drm_legacy_addmap(dev, aperture_base, SAVAGE_APERTURE_SIZE,
640 _DRM_FRAME_BUFFER, _DRM_WRITE_COMBINING,
641 &dev_priv->aperture);
642 return ret;
643 }
644
645 /*
646 * Delete MTRRs and free device-private data.
647 */
savage_driver_lastclose(struct drm_device * dev)648 void savage_driver_lastclose(struct drm_device *dev)
649 {
650 drm_savage_private_t *dev_priv = dev->dev_private;
651 int i;
652
653 for (i = 0; i < 3; ++i) {
654 arch_phys_wc_del(dev_priv->mtrr_handles[i]);
655 dev_priv->mtrr_handles[i] = 0;
656 }
657 }
658
savage_driver_unload(struct drm_device * dev)659 void savage_driver_unload(struct drm_device *dev)
660 {
661 drm_savage_private_t *dev_priv = dev->dev_private;
662
663 kfree(dev_priv);
664 }
665
savage_do_init_bci(struct drm_device * dev,drm_savage_init_t * init)666 static int savage_do_init_bci(struct drm_device * dev, drm_savage_init_t * init)
667 {
668 drm_savage_private_t *dev_priv = dev->dev_private;
669
670 if (init->fb_bpp != 16 && init->fb_bpp != 32) {
671 DRM_ERROR("invalid frame buffer bpp %d!\n", init->fb_bpp);
672 return -EINVAL;
673 }
674 if (init->depth_bpp != 16 && init->depth_bpp != 32) {
675 DRM_ERROR("invalid depth buffer bpp %d!\n", init->fb_bpp);
676 return -EINVAL;
677 }
678 if (init->dma_type != SAVAGE_DMA_AGP &&
679 init->dma_type != SAVAGE_DMA_PCI) {
680 DRM_ERROR("invalid dma memory type %d!\n", init->dma_type);
681 return -EINVAL;
682 }
683
684 dev_priv->cob_size = init->cob_size;
685 dev_priv->bci_threshold_lo = init->bci_threshold_lo;
686 dev_priv->bci_threshold_hi = init->bci_threshold_hi;
687 dev_priv->dma_type = init->dma_type;
688
689 dev_priv->fb_bpp = init->fb_bpp;
690 dev_priv->front_offset = init->front_offset;
691 dev_priv->front_pitch = init->front_pitch;
692 dev_priv->back_offset = init->back_offset;
693 dev_priv->back_pitch = init->back_pitch;
694 dev_priv->depth_bpp = init->depth_bpp;
695 dev_priv->depth_offset = init->depth_offset;
696 dev_priv->depth_pitch = init->depth_pitch;
697
698 dev_priv->texture_offset = init->texture_offset;
699 dev_priv->texture_size = init->texture_size;
700
701 dev_priv->sarea = drm_legacy_getsarea(dev);
702 if (!dev_priv->sarea) {
703 DRM_ERROR("could not find sarea!\n");
704 savage_do_cleanup_bci(dev);
705 return -EINVAL;
706 }
707 if (init->status_offset != 0) {
708 dev_priv->status = drm_legacy_findmap(dev, init->status_offset);
709 if (!dev_priv->status) {
710 DRM_ERROR("could not find shadow status region!\n");
711 savage_do_cleanup_bci(dev);
712 return -EINVAL;
713 }
714 } else {
715 dev_priv->status = NULL;
716 }
717 if (dev_priv->dma_type == SAVAGE_DMA_AGP && init->buffers_offset) {
718 dev->agp_buffer_token = init->buffers_offset;
719 dev->agp_buffer_map = drm_legacy_findmap(dev,
720 init->buffers_offset);
721 if (!dev->agp_buffer_map) {
722 DRM_ERROR("could not find DMA buffer region!\n");
723 savage_do_cleanup_bci(dev);
724 return -EINVAL;
725 }
726 drm_legacy_ioremap(dev->agp_buffer_map, dev);
727 if (!dev->agp_buffer_map->handle) {
728 DRM_ERROR("failed to ioremap DMA buffer region!\n");
729 savage_do_cleanup_bci(dev);
730 return -ENOMEM;
731 }
732 }
733 if (init->agp_textures_offset) {
734 dev_priv->agp_textures =
735 drm_legacy_findmap(dev, init->agp_textures_offset);
736 if (!dev_priv->agp_textures) {
737 DRM_ERROR("could not find agp texture region!\n");
738 savage_do_cleanup_bci(dev);
739 return -EINVAL;
740 }
741 } else {
742 dev_priv->agp_textures = NULL;
743 }
744
745 if (init->cmd_dma_offset) {
746 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
747 DRM_ERROR("command DMA not supported on "
748 "Savage3D/MX/IX.\n");
749 savage_do_cleanup_bci(dev);
750 return -EINVAL;
751 }
752 if (dev->dma && dev->dma->buflist) {
753 DRM_ERROR("command and vertex DMA not supported "
754 "at the same time.\n");
755 savage_do_cleanup_bci(dev);
756 return -EINVAL;
757 }
758 dev_priv->cmd_dma = drm_legacy_findmap(dev, init->cmd_dma_offset);
759 if (!dev_priv->cmd_dma) {
760 DRM_ERROR("could not find command DMA region!\n");
761 savage_do_cleanup_bci(dev);
762 return -EINVAL;
763 }
764 if (dev_priv->dma_type == SAVAGE_DMA_AGP) {
765 if (dev_priv->cmd_dma->type != _DRM_AGP) {
766 DRM_ERROR("AGP command DMA region is not a "
767 "_DRM_AGP map!\n");
768 savage_do_cleanup_bci(dev);
769 return -EINVAL;
770 }
771 drm_legacy_ioremap(dev_priv->cmd_dma, dev);
772 if (!dev_priv->cmd_dma->handle) {
773 DRM_ERROR("failed to ioremap command "
774 "DMA region!\n");
775 savage_do_cleanup_bci(dev);
776 return -ENOMEM;
777 }
778 } else if (dev_priv->cmd_dma->type != _DRM_CONSISTENT) {
779 DRM_ERROR("PCI command DMA region is not a "
780 "_DRM_CONSISTENT map!\n");
781 savage_do_cleanup_bci(dev);
782 return -EINVAL;
783 }
784 } else {
785 dev_priv->cmd_dma = NULL;
786 }
787
788 dev_priv->dma_flush = savage_dma_flush;
789 if (!dev_priv->cmd_dma) {
790 DRM_DEBUG("falling back to faked command DMA.\n");
791 dev_priv->fake_dma.offset = 0;
792 dev_priv->fake_dma.size = SAVAGE_FAKE_DMA_SIZE;
793 dev_priv->fake_dma.type = _DRM_SHM;
794 dev_priv->fake_dma.handle = kmalloc(SAVAGE_FAKE_DMA_SIZE,
795 GFP_KERNEL);
796 if (!dev_priv->fake_dma.handle) {
797 DRM_ERROR("could not allocate faked DMA buffer!\n");
798 savage_do_cleanup_bci(dev);
799 return -ENOMEM;
800 }
801 dev_priv->cmd_dma = &dev_priv->fake_dma;
802 dev_priv->dma_flush = savage_fake_dma_flush;
803 }
804
805 dev_priv->sarea_priv =
806 (drm_savage_sarea_t *) ((uint8_t *) dev_priv->sarea->handle +
807 init->sarea_priv_offset);
808
809 /* setup bitmap descriptors */
810 {
811 unsigned int color_tile_format;
812 unsigned int depth_tile_format;
813 unsigned int front_stride, back_stride, depth_stride;
814 if (dev_priv->chipset <= S3_SAVAGE4) {
815 color_tile_format = dev_priv->fb_bpp == 16 ?
816 SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP;
817 depth_tile_format = dev_priv->depth_bpp == 16 ?
818 SAVAGE_BD_TILE_16BPP : SAVAGE_BD_TILE_32BPP;
819 } else {
820 color_tile_format = SAVAGE_BD_TILE_DEST;
821 depth_tile_format = SAVAGE_BD_TILE_DEST;
822 }
823 front_stride = dev_priv->front_pitch / (dev_priv->fb_bpp / 8);
824 back_stride = dev_priv->back_pitch / (dev_priv->fb_bpp / 8);
825 depth_stride =
826 dev_priv->depth_pitch / (dev_priv->depth_bpp / 8);
827
828 dev_priv->front_bd = front_stride | SAVAGE_BD_BW_DISABLE |
829 (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) |
830 (color_tile_format << SAVAGE_BD_TILE_SHIFT);
831
832 dev_priv->back_bd = back_stride | SAVAGE_BD_BW_DISABLE |
833 (dev_priv->fb_bpp << SAVAGE_BD_BPP_SHIFT) |
834 (color_tile_format << SAVAGE_BD_TILE_SHIFT);
835
836 dev_priv->depth_bd = depth_stride | SAVAGE_BD_BW_DISABLE |
837 (dev_priv->depth_bpp << SAVAGE_BD_BPP_SHIFT) |
838 (depth_tile_format << SAVAGE_BD_TILE_SHIFT);
839 }
840
841 /* setup status and bci ptr */
842 dev_priv->event_counter = 0;
843 dev_priv->event_wrap = 0;
844 dev_priv->bci_ptr = (volatile uint32_t *)
845 ((uint8_t *) dev_priv->mmio->handle + SAVAGE_BCI_OFFSET);
846 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
847 dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S3D;
848 } else {
849 dev_priv->status_used_mask = SAVAGE_FIFO_USED_MASK_S4;
850 }
851 if (dev_priv->status != NULL) {
852 dev_priv->status_ptr =
853 (volatile uint32_t *)dev_priv->status->handle;
854 dev_priv->wait_fifo = savage_bci_wait_fifo_shadow;
855 dev_priv->wait_evnt = savage_bci_wait_event_shadow;
856 dev_priv->status_ptr[1023] = dev_priv->event_counter;
857 } else {
858 dev_priv->status_ptr = NULL;
859 if (S3_SAVAGE3D_SERIES(dev_priv->chipset)) {
860 dev_priv->wait_fifo = savage_bci_wait_fifo_s3d;
861 } else {
862 dev_priv->wait_fifo = savage_bci_wait_fifo_s4;
863 }
864 dev_priv->wait_evnt = savage_bci_wait_event_reg;
865 }
866
867 /* cliprect functions */
868 if (S3_SAVAGE3D_SERIES(dev_priv->chipset))
869 dev_priv->emit_clip_rect = savage_emit_clip_rect_s3d;
870 else
871 dev_priv->emit_clip_rect = savage_emit_clip_rect_s4;
872
873 if (savage_freelist_init(dev) < 0) {
874 DRM_ERROR("could not initialize freelist\n");
875 savage_do_cleanup_bci(dev);
876 return -ENOMEM;
877 }
878
879 if (savage_dma_init(dev_priv) < 0) {
880 DRM_ERROR("could not initialize command DMA\n");
881 savage_do_cleanup_bci(dev);
882 return -ENOMEM;
883 }
884
885 return 0;
886 }
887
savage_do_cleanup_bci(struct drm_device * dev)888 static int savage_do_cleanup_bci(struct drm_device * dev)
889 {
890 drm_savage_private_t *dev_priv = dev->dev_private;
891
892 if (dev_priv->cmd_dma == &dev_priv->fake_dma) {
893 kfree(dev_priv->fake_dma.handle);
894 } else if (dev_priv->cmd_dma && dev_priv->cmd_dma->handle &&
895 dev_priv->cmd_dma->type == _DRM_AGP &&
896 dev_priv->dma_type == SAVAGE_DMA_AGP)
897 drm_legacy_ioremapfree(dev_priv->cmd_dma, dev);
898
899 if (dev_priv->dma_type == SAVAGE_DMA_AGP &&
900 dev->agp_buffer_map && dev->agp_buffer_map->handle) {
901 drm_legacy_ioremapfree(dev->agp_buffer_map, dev);
902 /* make sure the next instance (which may be running
903 * in PCI mode) doesn't try to use an old
904 * agp_buffer_map. */
905 dev->agp_buffer_map = NULL;
906 }
907
908 kfree(dev_priv->dma_pages);
909
910 return 0;
911 }
912
savage_bci_init(struct drm_device * dev,void * data,struct drm_file * file_priv)913 static int savage_bci_init(struct drm_device *dev, void *data, struct drm_file *file_priv)
914 {
915 drm_savage_init_t *init = data;
916
917 LOCK_TEST_WITH_RETURN(dev, file_priv);
918
919 switch (init->func) {
920 case SAVAGE_INIT_BCI:
921 return savage_do_init_bci(dev, init);
922 case SAVAGE_CLEANUP_BCI:
923 return savage_do_cleanup_bci(dev);
924 }
925
926 return -EINVAL;
927 }
928
savage_bci_event_emit(struct drm_device * dev,void * data,struct drm_file * file_priv)929 static int savage_bci_event_emit(struct drm_device *dev, void *data, struct drm_file *file_priv)
930 {
931 drm_savage_private_t *dev_priv = dev->dev_private;
932 drm_savage_event_emit_t *event = data;
933
934 DRM_DEBUG("\n");
935
936 LOCK_TEST_WITH_RETURN(dev, file_priv);
937
938 event->count = savage_bci_emit_event(dev_priv, event->flags);
939 event->count |= dev_priv->event_wrap << 16;
940
941 return 0;
942 }
943
savage_bci_event_wait(struct drm_device * dev,void * data,struct drm_file * file_priv)944 static int savage_bci_event_wait(struct drm_device *dev, void *data, struct drm_file *file_priv)
945 {
946 drm_savage_private_t *dev_priv = dev->dev_private;
947 drm_savage_event_wait_t *event = data;
948 unsigned int event_e, hw_e;
949 unsigned int event_w, hw_w;
950
951 DRM_DEBUG("\n");
952
953 UPDATE_EVENT_COUNTER();
954 if (dev_priv->status_ptr)
955 hw_e = dev_priv->status_ptr[1] & 0xffff;
956 else
957 hw_e = SAVAGE_READ(SAVAGE_STATUS_WORD1) & 0xffff;
958 hw_w = dev_priv->event_wrap;
959 if (hw_e > dev_priv->event_counter)
960 hw_w--; /* hardware hasn't passed the last wrap yet */
961
962 event_e = event->count & 0xffff;
963 event_w = event->count >> 16;
964
965 /* Don't need to wait if
966 * - event counter wrapped since the event was emitted or
967 * - the hardware has advanced up to or over the event to wait for.
968 */
969 if (event_w < hw_w || (event_w == hw_w && event_e <= hw_e))
970 return 0;
971 else
972 return dev_priv->wait_evnt(dev_priv, event_e);
973 }
974
975 /*
976 * DMA buffer management
977 */
978
savage_bci_get_buffers(struct drm_device * dev,struct drm_file * file_priv,struct drm_dma * d)979 static int savage_bci_get_buffers(struct drm_device *dev,
980 struct drm_file *file_priv,
981 struct drm_dma *d)
982 {
983 struct drm_buf *buf;
984 int i;
985
986 for (i = d->granted_count; i < d->request_count; i++) {
987 buf = savage_freelist_get(dev);
988 if (!buf)
989 return -EAGAIN;
990
991 buf->file_priv = file_priv;
992
993 if (copy_to_user(&d->request_indices[i],
994 &buf->idx, sizeof(buf->idx)))
995 return -EFAULT;
996 if (copy_to_user(&d->request_sizes[i],
997 &buf->total, sizeof(buf->total)))
998 return -EFAULT;
999
1000 d->granted_count++;
1001 }
1002 return 0;
1003 }
1004
savage_bci_buffers(struct drm_device * dev,void * data,struct drm_file * file_priv)1005 int savage_bci_buffers(struct drm_device *dev, void *data, struct drm_file *file_priv)
1006 {
1007 struct drm_device_dma *dma = dev->dma;
1008 struct drm_dma *d = data;
1009 int ret = 0;
1010
1011 LOCK_TEST_WITH_RETURN(dev, file_priv);
1012
1013 /* Please don't send us buffers.
1014 */
1015 if (d->send_count != 0) {
1016 DRM_ERROR("Process %d trying to send %d buffers via drmDMA\n",
1017 DRM_CURRENTPID, d->send_count);
1018 return -EINVAL;
1019 }
1020
1021 /* We'll send you buffers.
1022 */
1023 if (d->request_count < 0 || d->request_count > dma->buf_count) {
1024 DRM_ERROR("Process %d trying to get %d buffers (of %d max)\n",
1025 DRM_CURRENTPID, d->request_count, dma->buf_count);
1026 return -EINVAL;
1027 }
1028
1029 d->granted_count = 0;
1030
1031 if (d->request_count) {
1032 ret = savage_bci_get_buffers(dev, file_priv, d);
1033 }
1034
1035 return ret;
1036 }
1037
savage_reclaim_buffers(struct drm_device * dev,struct drm_file * file_priv)1038 void savage_reclaim_buffers(struct drm_device *dev, struct drm_file *file_priv)
1039 {
1040 struct drm_device_dma *dma = dev->dma;
1041 drm_savage_private_t *dev_priv = dev->dev_private;
1042 int release_idlelock = 0;
1043 int i;
1044
1045 if (!dma)
1046 return;
1047 if (!dev_priv)
1048 return;
1049 if (!dma->buflist)
1050 return;
1051
1052 if (file_priv->master && file_priv->master->lock.hw_lock) {
1053 drm_legacy_idlelock_take(&file_priv->master->lock);
1054 release_idlelock = 1;
1055 }
1056
1057 for (i = 0; i < dma->buf_count; i++) {
1058 struct drm_buf *buf = dma->buflist[i];
1059 drm_savage_buf_priv_t *buf_priv = buf->dev_private;
1060
1061 if (buf->file_priv == file_priv && buf_priv &&
1062 buf_priv->next == NULL && buf_priv->prev == NULL) {
1063 uint16_t event;
1064 DRM_DEBUG("reclaimed from client\n");
1065 event = savage_bci_emit_event(dev_priv, SAVAGE_WAIT_3D);
1066 SET_AGE(&buf_priv->age, event, dev_priv->event_wrap);
1067 savage_freelist_put(dev, buf);
1068 }
1069 }
1070
1071 if (release_idlelock)
1072 drm_legacy_idlelock_release(&file_priv->master->lock);
1073 }
1074
1075 const struct drm_ioctl_desc savage_ioctls[] = {
1076 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_INIT, savage_bci_init, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
1077 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_CMDBUF, savage_bci_cmdbuf, DRM_AUTH),
1078 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_EVENT_EMIT, savage_bci_event_emit, DRM_AUTH),
1079 DRM_IOCTL_DEF_DRV(SAVAGE_BCI_EVENT_WAIT, savage_bci_event_wait, DRM_AUTH),
1080 };
1081
1082 int savage_max_ioctl = ARRAY_SIZE(savage_ioctls);
1083
