1 /* 2 * rcar_du_regs.h -- R-Car Display Unit Registers Definitions 3 * 4 * Copyright (C) 2013-2015 Renesas Electronics Corporation 5 * 6 * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com) 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2 10 * as published by the Free Software Foundation. 11 */ 12 13 #ifndef __RCAR_DU_REGS_H__ 14 #define __RCAR_DU_REGS_H__ 15 16 #define DU0_REG_OFFSET 0x00000 17 #define DU1_REG_OFFSET 0x30000 18 #define DU2_REG_OFFSET 0x40000 19 #define DU3_REG_OFFSET 0x70000 20 21 /* ----------------------------------------------------------------------------- 22 * Display Control Registers 23 */ 24 25 #define DSYSR 0x00000 /* display 1 */ 26 #define DSYSR_ILTS (1 << 29) 27 #define DSYSR_DSEC (1 << 20) 28 #define DSYSR_IUPD (1 << 16) 29 #define DSYSR_DRES (1 << 9) 30 #define DSYSR_DEN (1 << 8) 31 #define DSYSR_TVM_MASTER (0 << 6) 32 #define DSYSR_TVM_SWITCH (1 << 6) 33 #define DSYSR_TVM_TVSYNC (2 << 6) 34 #define DSYSR_TVM_MASK (3 << 6) 35 #define DSYSR_SCM_INT_NONE (0 << 4) 36 #define DSYSR_SCM_INT_SYNC (2 << 4) 37 #define DSYSR_SCM_INT_VIDEO (3 << 4) 38 #define DSYSR_SCM_MASK (3 << 4) 39 40 #define DSMR 0x00004 41 #define DSMR_VSPM (1 << 28) 42 #define DSMR_ODPM (1 << 27) 43 #define DSMR_DIPM_DISP (0 << 25) 44 #define DSMR_DIPM_CSYNC (1 << 25) 45 #define DSMR_DIPM_DE (3 << 25) 46 #define DSMR_DIPM_MASK (3 << 25) 47 #define DSMR_CSPM (1 << 24) 48 #define DSMR_DIL (1 << 19) 49 #define DSMR_VSL (1 << 18) 50 #define DSMR_HSL (1 << 17) 51 #define DSMR_DDIS (1 << 16) 52 #define DSMR_CDEL (1 << 15) 53 #define DSMR_CDEM_CDE (0 << 13) 54 #define DSMR_CDEM_LOW (2 << 13) 55 #define DSMR_CDEM_HIGH (3 << 13) 56 #define DSMR_CDEM_MASK (3 << 13) 57 #define DSMR_CDED (1 << 12) 58 #define DSMR_ODEV (1 << 8) 59 #define DSMR_CSY_VH_OR (0 << 6) 60 #define DSMR_CSY_333 (2 << 6) 61 #define DSMR_CSY_222 (3 << 6) 62 #define DSMR_CSY_MASK (3 << 6) 63 64 #define DSSR 0x00008 65 #define DSSR_VC1FB_DSA0 (0 << 30) 66 #define DSSR_VC1FB_DSA1 (1 << 30) 67 #define DSSR_VC1FB_DSA2 (2 << 30) 68 #define DSSR_VC1FB_INIT (3 << 30) 69 #define DSSR_VC1FB_MASK (3 << 30) 70 #define DSSR_VC0FB_DSA0 (0 << 28) 71 #define DSSR_VC0FB_DSA1 (1 << 28) 72 #define DSSR_VC0FB_DSA2 (2 << 28) 73 #define DSSR_VC0FB_INIT (3 << 28) 74 #define DSSR_VC0FB_MASK (3 << 28) 75 #define DSSR_DFB(n) (1 << ((n)+15)) 76 #define DSSR_TVR (1 << 15) 77 #define DSSR_FRM (1 << 14) 78 #define DSSR_VBK (1 << 11) 79 #define DSSR_RINT (1 << 9) 80 #define DSSR_HBK (1 << 8) 81 #define DSSR_ADC(n) (1 << ((n)-1)) 82 83 #define DSRCR 0x0000c 84 #define DSRCR_TVCL (1 << 15) 85 #define DSRCR_FRCL (1 << 14) 86 #define DSRCR_VBCL (1 << 11) 87 #define DSRCR_RICL (1 << 9) 88 #define DSRCR_HBCL (1 << 8) 89 #define DSRCR_ADCL(n) (1 << ((n)-1)) 90 #define DSRCR_MASK 0x0000cbff 91 92 #define DIER 0x00010 93 #define DIER_TVE (1 << 15) 94 #define DIER_FRE (1 << 14) 95 #define DIER_VBE (1 << 11) 96 #define DIER_RIE (1 << 9) 97 #define DIER_HBE (1 << 8) 98 #define DIER_ADCE(n) (1 << ((n)-1)) 99 100 #define CPCR 0x00014 101 #define CPCR_CP4CE (1 << 19) 102 #define CPCR_CP3CE (1 << 18) 103 #define CPCR_CP2CE (1 << 17) 104 #define CPCR_CP1CE (1 << 16) 105 106 #define DPPR 0x00018 107 #define DPPR_DPE(n) (1 << ((n)*4-1)) 108 #define DPPR_DPS(n, p) (((p)-1) << DPPR_DPS_SHIFT(n)) 109 #define DPPR_DPS_SHIFT(n) (((n)-1)*4) 110 #define DPPR_BPP16 (DPPR_DPE(8) | DPPR_DPS(8, 1)) /* plane1 */ 111 #define DPPR_BPP32_P1 (DPPR_DPE(7) | DPPR_DPS(7, 1)) 112 #define DPPR_BPP32_P2 (DPPR_DPE(8) | DPPR_DPS(8, 2)) 113 #define DPPR_BPP32 (DPPR_BPP32_P1 | DPPR_BPP32_P2) /* plane1 & 2 */ 114 115 #define DEFR 0x00020 116 #define DEFR_CODE (0x7773 << 16) 117 #define DEFR_EXSL (1 << 12) 118 #define DEFR_EXVL (1 << 11) 119 #define DEFR_EXUP (1 << 5) 120 #define DEFR_VCUP (1 << 4) 121 #define DEFR_DEFE (1 << 0) 122 123 #define DAPCR 0x00024 124 #define DAPCR_CODE (0x7773 << 16) 125 #define DAPCR_AP2E (1 << 4) 126 #define DAPCR_AP1E (1 << 0) 127 128 #define DCPCR 0x00028 129 #define DCPCR_CODE (0x7773 << 16) 130 #define DCPCR_CA2B (1 << 13) 131 #define DCPCR_CD2F (1 << 12) 132 #define DCPCR_DC2E (1 << 8) 133 #define DCPCR_CAB (1 << 5) 134 #define DCPCR_CDF (1 << 4) 135 #define DCPCR_DCE (1 << 0) 136 137 #define DEFR2 0x00034 138 #define DEFR2_CODE (0x7775 << 16) 139 #define DEFR2_DEFE2G (1 << 0) 140 141 #define DEFR3 0x00038 142 #define DEFR3_CODE (0x7776 << 16) 143 #define DEFR3_EVDA (1 << 14) 144 #define DEFR3_EVDM_1 (1 << 12) 145 #define DEFR3_EVDM_2 (2 << 12) 146 #define DEFR3_EVDM_3 (3 << 12) 147 #define DEFR3_VMSM2_EMA (1 << 6) 148 #define DEFR3_VMSM1_ENA (1 << 4) 149 #define DEFR3_DEFE3 (1 << 0) 150 151 #define DEFR4 0x0003c 152 #define DEFR4_CODE (0x7777 << 16) 153 #define DEFR4_LRUO (1 << 5) 154 #define DEFR4_SPCE (1 << 4) 155 156 #define DVCSR 0x000d0 157 #define DVCSR_VCnFB2_DSA0(n) (0 << ((n)*2+16)) 158 #define DVCSR_VCnFB2_DSA1(n) (1 << ((n)*2+16)) 159 #define DVCSR_VCnFB2_DSA2(n) (2 << ((n)*2+16)) 160 #define DVCSR_VCnFB2_INIT(n) (3 << ((n)*2+16)) 161 #define DVCSR_VCnFB2_MASK(n) (3 << ((n)*2+16)) 162 #define DVCSR_VCnFB_DSA0(n) (0 << ((n)*2)) 163 #define DVCSR_VCnFB_DSA1(n) (1 << ((n)*2)) 164 #define DVCSR_VCnFB_DSA2(n) (2 << ((n)*2)) 165 #define DVCSR_VCnFB_INIT(n) (3 << ((n)*2)) 166 #define DVCSR_VCnFB_MASK(n) (3 << ((n)*2)) 167 168 #define DEFR5 0x000e0 169 #define DEFR5_CODE (0x66 << 24) 170 #define DEFR5_YCRGB2_DIS (0 << 14) 171 #define DEFR5_YCRGB2_PRI1 (1 << 14) 172 #define DEFR5_YCRGB2_PRI2 (2 << 14) 173 #define DEFR5_YCRGB2_PRI3 (3 << 14) 174 #define DEFR5_YCRGB2_MASK (3 << 14) 175 #define DEFR5_YCRGB1_DIS (0 << 12) 176 #define DEFR5_YCRGB1_PRI1 (1 << 12) 177 #define DEFR5_YCRGB1_PRI2 (2 << 12) 178 #define DEFR5_YCRGB1_PRI3 (3 << 12) 179 #define DEFR5_YCRGB1_MASK (3 << 12) 180 #define DEFR5_DEFE5 (1 << 0) 181 182 #define DDLTR 0x000e4 183 #define DDLTR_CODE (0x7766 << 16) 184 #define DDLTR_DLAR2 (1 << 6) 185 #define DDLTR_DLAY2 (1 << 5) 186 #define DDLTR_DLAY1 (1 << 1) 187 188 #define DEFR6 0x000e8 189 #define DEFR6_CODE (0x7778 << 16) 190 #define DEFR6_ODPM12_DSMR (0 << 10) 191 #define DEFR6_ODPM12_DISP (2 << 10) 192 #define DEFR6_ODPM12_CDE (3 << 10) 193 #define DEFR6_ODPM12_MASK (3 << 10) 194 #define DEFR6_ODPM02_DSMR (0 << 8) 195 #define DEFR6_ODPM02_DISP (2 << 8) 196 #define DEFR6_ODPM02_CDE (3 << 8) 197 #define DEFR6_ODPM02_MASK (3 << 8) 198 #define DEFR6_TCNE1 (1 << 6) 199 #define DEFR6_TCNE0 (1 << 4) 200 #define DEFR6_MLOS1 (1 << 2) 201 #define DEFR6_DEFAULT (DEFR6_CODE | DEFR6_TCNE1) 202 203 /* ----------------------------------------------------------------------------- 204 * R8A7790-only Control Registers 205 */ 206 207 #define DD1SSR 0x20008 208 #define DD1SSR_TVR (1 << 15) 209 #define DD1SSR_FRM (1 << 14) 210 #define DD1SSR_BUF (1 << 12) 211 #define DD1SSR_VBK (1 << 11) 212 #define DD1SSR_RINT (1 << 9) 213 #define DD1SSR_HBK (1 << 8) 214 #define DD1SSR_ADC(n) (1 << ((n)-1)) 215 216 #define DD1SRCR 0x2000c 217 #define DD1SRCR_TVR (1 << 15) 218 #define DD1SRCR_FRM (1 << 14) 219 #define DD1SRCR_BUF (1 << 12) 220 #define DD1SRCR_VBK (1 << 11) 221 #define DD1SRCR_RINT (1 << 9) 222 #define DD1SRCR_HBK (1 << 8) 223 #define DD1SRCR_ADC(n) (1 << ((n)-1)) 224 225 #define DD1IER 0x20010 226 #define DD1IER_TVR (1 << 15) 227 #define DD1IER_FRM (1 << 14) 228 #define DD1IER_BUF (1 << 12) 229 #define DD1IER_VBK (1 << 11) 230 #define DD1IER_RINT (1 << 9) 231 #define DD1IER_HBK (1 << 8) 232 #define DD1IER_ADC(n) (1 << ((n)-1)) 233 234 #define DEFR8 0x20020 235 #define DEFR8_CODE (0x7790 << 16) 236 #define DEFR8_VSCS (1 << 6) 237 #define DEFR8_DRGBS_DU(n) ((n) << 4) 238 #define DEFR8_DRGBS_MASK (3 << 4) 239 #define DEFR8_DEFE8 (1 << 0) 240 241 #define DOFLR 0x20024 242 #define DOFLR_CODE (0x7790 << 16) 243 #define DOFLR_HSYCFL1 (1 << 13) 244 #define DOFLR_VSYCFL1 (1 << 12) 245 #define DOFLR_ODDFL1 (1 << 11) 246 #define DOFLR_DISPFL1 (1 << 10) 247 #define DOFLR_CDEFL1 (1 << 9) 248 #define DOFLR_RGBFL1 (1 << 8) 249 #define DOFLR_HSYCFL0 (1 << 5) 250 #define DOFLR_VSYCFL0 (1 << 4) 251 #define DOFLR_ODDFL0 (1 << 3) 252 #define DOFLR_DISPFL0 (1 << 2) 253 #define DOFLR_CDEFL0 (1 << 1) 254 #define DOFLR_RGBFL0 (1 << 0) 255 256 #define DIDSR 0x20028 257 #define DIDSR_CODE (0x7790 << 16) 258 #define DIDSR_LCDS_DCLKIN(n) (0 << (8 + (n) * 2)) 259 #define DIDSR_LCDS_LVDS0(n) (2 << (8 + (n) * 2)) 260 #define DIDSR_LCDS_LVDS1(n) (3 << (8 + (n) * 2)) 261 #define DIDSR_LCDS_MASK(n) (3 << (8 + (n) * 2)) 262 #define DIDSR_PDCS_CLK(n, clk) (clk << ((n) * 2)) 263 #define DIDSR_PDCS_MASK(n) (3 << ((n) * 2)) 264 265 #define DEFR10 0x20038 266 #define DEFR10_CODE (0x7795 << 16) 267 #define DEFR10_VSPF1_RGB (0 << 14) 268 #define DEFR10_VSPF1_YC (1 << 14) 269 #define DEFR10_DOCF1_RGB (0 << 12) 270 #define DEFR10_DOCF1_YC (1 << 12) 271 #define DEFR10_YCDF0_YCBCR444 (0 << 11) 272 #define DEFR10_YCDF0_YCBCR422 (1 << 11) 273 #define DEFR10_VSPF0_RGB (0 << 10) 274 #define DEFR10_VSPF0_YC (1 << 10) 275 #define DEFR10_DOCF0_RGB (0 << 8) 276 #define DEFR10_DOCF0_YC (1 << 8) 277 #define DEFR10_TSEL_H3_TCON1 (0 << 1) /* DEFR102 register only (DU2/DU3) */ 278 #define DEFR10_DEFE10 (1 << 0) 279 280 #define DPLLCR 0x20044 281 #define DPLLCR_CODE (0x95 << 24) 282 #define DPLLCR_PLCS1 (1 << 23) 283 /* 284 * PLCS0 is bit 21, but H3 ES1.x requires bit 20 to be set as well. As bit 20 285 * isn't implemented by other SoC in the Gen3 family it can safely be set 286 * unconditionally. 287 */ 288 #define DPLLCR_PLCS0 (3 << 20) 289 #define DPLLCR_CLKE (1 << 18) 290 #define DPLLCR_FDPLL(n) ((n) << 12) 291 #define DPLLCR_N(n) ((n) << 5) 292 #define DPLLCR_M(n) ((n) << 3) 293 #define DPLLCR_STBY (1 << 2) 294 #define DPLLCR_INCS_DOTCLKIN0 (0 << 0) 295 #define DPLLCR_INCS_DOTCLKIN1 (1 << 1) 296 297 #define DPLLC2R 0x20048 298 #define DPLLC2R_CODE (0x95 << 24) 299 #define DPLLC2R_SELC (1 << 12) 300 #define DPLLC2R_M(n) ((n) << 8) 301 #define DPLLC2R_FDPLL(n) ((n) << 0) 302 303 /* ----------------------------------------------------------------------------- 304 * Display Timing Generation Registers 305 */ 306 307 #define HDSR 0x00040 308 #define HDER 0x00044 309 #define VDSR 0x00048 310 #define VDER 0x0004c 311 #define HCR 0x00050 312 #define HSWR 0x00054 313 #define VCR 0x00058 314 #define VSPR 0x0005c 315 #define EQWR 0x00060 316 #define SPWR 0x00064 317 #define CLAMPSR 0x00070 318 #define CLAMPWR 0x00074 319 #define DESR 0x00078 320 #define DEWR 0x0007c 321 322 /* ----------------------------------------------------------------------------- 323 * Display Attribute Registers 324 */ 325 326 #define CP1TR 0x00080 327 #define CP2TR 0x00084 328 #define CP3TR 0x00088 329 #define CP4TR 0x0008c 330 331 #define DOOR 0x00090 332 #define DOOR_RGB(r, g, b) (((r) << 18) | ((g) << 10) | ((b) << 2)) 333 #define CDER 0x00094 334 #define CDER_RGB(r, g, b) (((r) << 18) | ((g) << 10) | ((b) << 2)) 335 #define BPOR 0x00098 336 #define BPOR_RGB(r, g, b) (((r) << 18) | ((g) << 10) | ((b) << 2)) 337 338 #define RINTOFSR 0x0009c 339 340 #define DSHPR 0x000c8 341 #define DSHPR_CODE (0x7776 << 16) 342 #define DSHPR_PRIH (0xa << 4) 343 #define DSHPR_PRIL_BPP16 (0x8 << 0) 344 #define DSHPR_PRIL_BPP32 (0x9 << 0) 345 346 /* ----------------------------------------------------------------------------- 347 * Display Plane Registers 348 */ 349 350 #define PLANE_OFF 0x00100 351 352 #define PnMR 0x00100 /* plane 1 */ 353 #define PnMR_VISL_VIN0 (0 << 26) /* use Video Input 0 */ 354 #define PnMR_VISL_VIN1 (1 << 26) /* use Video Input 1 */ 355 #define PnMR_VISL_VIN2 (2 << 26) /* use Video Input 2 */ 356 #define PnMR_VISL_VIN3 (3 << 26) /* use Video Input 3 */ 357 #define PnMR_YCDF_YUYV (1 << 20) /* YUYV format */ 358 #define PnMR_TC_R (0 << 17) /* Tranparent color is PnTC1R */ 359 #define PnMR_TC_CP (1 << 17) /* Tranparent color is color palette */ 360 #define PnMR_WAE (1 << 16) /* Wrap around Enable */ 361 #define PnMR_SPIM_TP (0 << 12) /* Transparent Color */ 362 #define PnMR_SPIM_ALP (1 << 12) /* Alpha Blending */ 363 #define PnMR_SPIM_EOR (2 << 12) /* EOR */ 364 #define PnMR_SPIM_TP_OFF (1 << 14) /* No Transparent Color */ 365 #define PnMR_CPSL_CP1 (0 << 8) /* Color Palette selected 1 */ 366 #define PnMR_CPSL_CP2 (1 << 8) /* Color Palette selected 2 */ 367 #define PnMR_CPSL_CP3 (2 << 8) /* Color Palette selected 3 */ 368 #define PnMR_CPSL_CP4 (3 << 8) /* Color Palette selected 4 */ 369 #define PnMR_DC (1 << 7) /* Display Area Change */ 370 #define PnMR_BM_MD (0 << 4) /* Manual Display Change Mode */ 371 #define PnMR_BM_AR (1 << 4) /* Auto Rendering Mode */ 372 #define PnMR_BM_AD (2 << 4) /* Auto Display Change Mode */ 373 #define PnMR_BM_VC (3 << 4) /* Video Capture Mode */ 374 #define PnMR_DDDF_8BPP (0 << 0) /* 8bit */ 375 #define PnMR_DDDF_16BPP (1 << 0) /* 16bit or 32bit */ 376 #define PnMR_DDDF_ARGB (2 << 0) /* ARGB */ 377 #define PnMR_DDDF_YC (3 << 0) /* YC */ 378 #define PnMR_DDDF_MASK (3 << 0) 379 380 #define PnMWR 0x00104 381 382 #define PnALPHAR 0x00108 383 #define PnALPHAR_ABIT_1 (0 << 12) 384 #define PnALPHAR_ABIT_0 (1 << 12) 385 #define PnALPHAR_ABIT_X (2 << 12) 386 387 #define PnDSXR 0x00110 388 #define PnDSYR 0x00114 389 #define PnDPXR 0x00118 390 #define PnDPYR 0x0011c 391 392 #define PnDSA0R 0x00120 393 #define PnDSA1R 0x00124 394 #define PnDSA2R 0x00128 395 #define PnDSA_MASK 0xfffffff0 396 397 #define PnSPXR 0x00130 398 #define PnSPYR 0x00134 399 #define PnWASPR 0x00138 400 #define PnWAMWR 0x0013c 401 402 #define PnBTR 0x00140 403 404 #define PnTC1R 0x00144 405 #define PnTC2R 0x00148 406 #define PnTC3R 0x0014c 407 #define PnTC3R_CODE (0x66 << 24) 408 409 #define PnMLR 0x00150 410 411 #define PnSWAPR 0x00180 412 #define PnSWAPR_DIGN (1 << 4) 413 #define PnSWAPR_SPQW (1 << 3) 414 #define PnSWAPR_SPLW (1 << 2) 415 #define PnSWAPR_SPWD (1 << 1) 416 #define PnSWAPR_SPBY (1 << 0) 417 418 #define PnDDCR 0x00184 419 #define PnDDCR_CODE (0x7775 << 16) 420 #define PnDDCR_LRGB1 (1 << 11) 421 #define PnDDCR_LRGB0 (1 << 10) 422 423 #define PnDDCR2 0x00188 424 #define PnDDCR2_CODE (0x7776 << 16) 425 #define PnDDCR2_NV21 (1 << 5) 426 #define PnDDCR2_Y420 (1 << 4) 427 #define PnDDCR2_DIVU (1 << 1) 428 #define PnDDCR2_DIVY (1 << 0) 429 430 #define PnDDCR4 0x00190 431 #define PnDDCR4_CODE (0x7766 << 16) 432 #define PnDDCR4_VSPS (1 << 13) 433 #define PnDDCR4_SDFS_RGB (0 << 4) 434 #define PnDDCR4_SDFS_YC (5 << 4) 435 #define PnDDCR4_SDFS_MASK (7 << 4) 436 #define PnDDCR4_EDF_NONE (0 << 0) 437 #define PnDDCR4_EDF_ARGB8888 (1 << 0) 438 #define PnDDCR4_EDF_RGB888 (2 << 0) 439 #define PnDDCR4_EDF_RGB666 (3 << 0) 440 #define PnDDCR4_EDF_MASK (7 << 0) 441 442 #define APnMR 0x0a100 443 #define APnMR_WAE (1 << 16) /* Wrap around Enable */ 444 #define APnMR_DC (1 << 7) /* Display Area Change */ 445 #define APnMR_BM_MD (0 << 4) /* Manual Display Change Mode */ 446 #define APnMR_BM_AD (2 << 4) /* Auto Display Change Mode */ 447 448 #define APnMWR 0x0a104 449 450 #define APnDSXR 0x0a110 451 #define APnDSYR 0x0a114 452 #define APnDPXR 0x0a118 453 #define APnDPYR 0x0a11c 454 455 #define APnDSA0R 0x0a120 456 #define APnDSA1R 0x0a124 457 #define APnDSA2R 0x0a128 458 459 #define APnSPXR 0x0a130 460 #define APnSPYR 0x0a134 461 #define APnWASPR 0x0a138 462 #define APnWAMWR 0x0a13c 463 464 #define APnBTR 0x0a140 465 466 #define APnMLR 0x0a150 467 #define APnSWAPR 0x0a180 468 469 /* ----------------------------------------------------------------------------- 470 * Display Capture Registers 471 */ 472 473 #define DCMR 0x0c100 474 #define DCMWR 0x0c104 475 #define DCSAR 0x0c120 476 #define DCMLR 0x0c150 477 478 /* ----------------------------------------------------------------------------- 479 * Color Palette Registers 480 */ 481 482 #define CP1_000R 0x01000 483 #define CP1_255R 0x013fc 484 #define CP2_000R 0x02000 485 #define CP2_255R 0x023fc 486 #define CP3_000R 0x03000 487 #define CP3_255R 0x033fc 488 #define CP4_000R 0x04000 489 #define CP4_255R 0x043fc 490 491 /* ----------------------------------------------------------------------------- 492 * External Synchronization Control Registers 493 */ 494 495 #define ESCR 0x10000 496 #define ESCR2 0x31000 497 #define ESCR_DCLKOINV (1 << 25) 498 #define ESCR_DCLKSEL_DCLKIN (0 << 20) 499 #define ESCR_DCLKSEL_CLKS (1 << 20) 500 #define ESCR_DCLKSEL_MASK (1 << 20) 501 #define ESCR_DCLKDIS (1 << 16) 502 #define ESCR_SYNCSEL_OFF (0 << 8) 503 #define ESCR_SYNCSEL_EXVSYNC (2 << 8) 504 #define ESCR_SYNCSEL_EXHSYNC (3 << 8) 505 #define ESCR_FRQSEL_MASK (0x3f << 0) 506 507 #define OTAR 0x10004 508 #define OTAR2 0x31004 509 510 /* ----------------------------------------------------------------------------- 511 * Dual Display Output Control Registers 512 */ 513 514 #define DORCR 0x11000 515 #define DORCR_PG2T (1 << 30) 516 #define DORCR_DK2S (1 << 28) 517 #define DORCR_PG2D_DS1 (0 << 24) 518 #define DORCR_PG2D_DS2 (1 << 24) 519 #define DORCR_PG2D_FIX0 (2 << 24) 520 #define DORCR_PG2D_DOOR (3 << 24) 521 #define DORCR_PG2D_MASK (3 << 24) 522 #define DORCR_DR1D (1 << 21) 523 #define DORCR_PG1D_DS1 (0 << 16) 524 #define DORCR_PG1D_DS2 (1 << 16) 525 #define DORCR_PG1D_FIX0 (2 << 16) 526 #define DORCR_PG1D_DOOR (3 << 16) 527 #define DORCR_PG1D_MASK (3 << 16) 528 #define DORCR_RGPV (1 << 4) 529 #define DORCR_DPRS (1 << 0) 530 531 #define DPTSR 0x11004 532 #define DPTSR_PnDK(n) (1 << ((n) + 16)) 533 #define DPTSR_PnTS(n) (1 << (n)) 534 535 #define DAPTSR 0x11008 536 #define DAPTSR_APnDK(n) (1 << ((n) + 16)) 537 #define DAPTSR_APnTS(n) (1 << (n)) 538 539 #define DS1PR 0x11020 540 #define DS2PR 0x11024 541 542 /* ----------------------------------------------------------------------------- 543 * YC-RGB Conversion Coefficient Registers 544 */ 545 546 #define YNCR 0x11080 547 #define YNOR 0x11084 548 #define CRNOR 0x11088 549 #define CBNOR 0x1108c 550 #define RCRCR 0x11090 551 #define GCRCR 0x11094 552 #define GCBCR 0x11098 553 #define BCBCR 0x1109c 554 555 #endif /* __RCAR_DU_REGS_H__ */ 556
