1 /*
2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
23 *
24 * Authors: Dave Airlie
25 * Alex Deucher
26 * Jerome Glisse
27 */
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
30 #include <drm/drmP.h>
31 #include "rv515d.h"
32 #include "radeon.h"
33 #include "radeon_asic.h"
34 #include "atom.h"
35 #include "rv515_reg_safe.h"
36
37 /* This files gather functions specifics to: rv515 */
38 static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev);
39 static int rv515_debugfs_ga_info_init(struct radeon_device *rdev);
40 static void rv515_gpu_init(struct radeon_device *rdev);
41 int rv515_mc_wait_for_idle(struct radeon_device *rdev);
42
43 static const u32 crtc_offsets[2] =
44 {
45 0,
46 AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL
47 };
48
rv515_debugfs(struct radeon_device * rdev)49 void rv515_debugfs(struct radeon_device *rdev)
50 {
51 if (r100_debugfs_rbbm_init(rdev)) {
52 DRM_ERROR("Failed to register debugfs file for RBBM !\n");
53 }
54 if (rv515_debugfs_pipes_info_init(rdev)) {
55 DRM_ERROR("Failed to register debugfs file for pipes !\n");
56 }
57 if (rv515_debugfs_ga_info_init(rdev)) {
58 DRM_ERROR("Failed to register debugfs file for pipes !\n");
59 }
60 }
61
rv515_ring_start(struct radeon_device * rdev,struct radeon_ring * ring)62 void rv515_ring_start(struct radeon_device *rdev, struct radeon_ring *ring)
63 {
64 int r;
65
66 r = radeon_ring_lock(rdev, ring, 64);
67 if (r) {
68 return;
69 }
70 radeon_ring_write(ring, PACKET0(ISYNC_CNTL, 0));
71 radeon_ring_write(ring,
72 ISYNC_ANY2D_IDLE3D |
73 ISYNC_ANY3D_IDLE2D |
74 ISYNC_WAIT_IDLEGUI |
75 ISYNC_CPSCRATCH_IDLEGUI);
76 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
77 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
78 radeon_ring_write(ring, PACKET0(R300_DST_PIPE_CONFIG, 0));
79 radeon_ring_write(ring, R300_PIPE_AUTO_CONFIG);
80 radeon_ring_write(ring, PACKET0(GB_SELECT, 0));
81 radeon_ring_write(ring, 0);
82 radeon_ring_write(ring, PACKET0(GB_ENABLE, 0));
83 radeon_ring_write(ring, 0);
84 radeon_ring_write(ring, PACKET0(R500_SU_REG_DEST, 0));
85 radeon_ring_write(ring, (1 << rdev->num_gb_pipes) - 1);
86 radeon_ring_write(ring, PACKET0(VAP_INDEX_OFFSET, 0));
87 radeon_ring_write(ring, 0);
88 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
89 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
90 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
91 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
92 radeon_ring_write(ring, PACKET0(WAIT_UNTIL, 0));
93 radeon_ring_write(ring, WAIT_2D_IDLECLEAN | WAIT_3D_IDLECLEAN);
94 radeon_ring_write(ring, PACKET0(GB_AA_CONFIG, 0));
95 radeon_ring_write(ring, 0);
96 radeon_ring_write(ring, PACKET0(RB3D_DSTCACHE_CTLSTAT, 0));
97 radeon_ring_write(ring, RB3D_DC_FLUSH | RB3D_DC_FREE);
98 radeon_ring_write(ring, PACKET0(ZB_ZCACHE_CTLSTAT, 0));
99 radeon_ring_write(ring, ZC_FLUSH | ZC_FREE);
100 radeon_ring_write(ring, PACKET0(GB_MSPOS0, 0));
101 radeon_ring_write(ring,
102 ((6 << MS_X0_SHIFT) |
103 (6 << MS_Y0_SHIFT) |
104 (6 << MS_X1_SHIFT) |
105 (6 << MS_Y1_SHIFT) |
106 (6 << MS_X2_SHIFT) |
107 (6 << MS_Y2_SHIFT) |
108 (6 << MSBD0_Y_SHIFT) |
109 (6 << MSBD0_X_SHIFT)));
110 radeon_ring_write(ring, PACKET0(GB_MSPOS1, 0));
111 radeon_ring_write(ring,
112 ((6 << MS_X3_SHIFT) |
113 (6 << MS_Y3_SHIFT) |
114 (6 << MS_X4_SHIFT) |
115 (6 << MS_Y4_SHIFT) |
116 (6 << MS_X5_SHIFT) |
117 (6 << MS_Y5_SHIFT) |
118 (6 << MSBD1_SHIFT)));
119 radeon_ring_write(ring, PACKET0(GA_ENHANCE, 0));
120 radeon_ring_write(ring, GA_DEADLOCK_CNTL | GA_FASTSYNC_CNTL);
121 radeon_ring_write(ring, PACKET0(GA_POLY_MODE, 0));
122 radeon_ring_write(ring, FRONT_PTYPE_TRIANGE | BACK_PTYPE_TRIANGE);
123 radeon_ring_write(ring, PACKET0(GA_ROUND_MODE, 0));
124 radeon_ring_write(ring, GEOMETRY_ROUND_NEAREST | COLOR_ROUND_NEAREST);
125 radeon_ring_write(ring, PACKET0(0x20C8, 0));
126 radeon_ring_write(ring, 0);
127 radeon_ring_unlock_commit(rdev, ring, false);
128 }
129
rv515_mc_wait_for_idle(struct radeon_device * rdev)130 int rv515_mc_wait_for_idle(struct radeon_device *rdev)
131 {
132 unsigned i;
133 uint32_t tmp;
134
135 for (i = 0; i < rdev->usec_timeout; i++) {
136 /* read MC_STATUS */
137 tmp = RREG32_MC(MC_STATUS);
138 if (tmp & MC_STATUS_IDLE) {
139 return 0;
140 }
141 DRM_UDELAY(1);
142 }
143 return -1;
144 }
145
rv515_vga_render_disable(struct radeon_device * rdev)146 void rv515_vga_render_disable(struct radeon_device *rdev)
147 {
148 WREG32(R_000300_VGA_RENDER_CONTROL,
149 RREG32(R_000300_VGA_RENDER_CONTROL) & C_000300_VGA_VSTATUS_CNTL);
150 }
151
rv515_gpu_init(struct radeon_device * rdev)152 static void rv515_gpu_init(struct radeon_device *rdev)
153 {
154 unsigned pipe_select_current, gb_pipe_select, tmp;
155
156 if (r100_gui_wait_for_idle(rdev)) {
157 pr_warn("Failed to wait GUI idle while resetting GPU. Bad things might happen.\n");
158 }
159 rv515_vga_render_disable(rdev);
160 r420_pipes_init(rdev);
161 gb_pipe_select = RREG32(R400_GB_PIPE_SELECT);
162 tmp = RREG32(R300_DST_PIPE_CONFIG);
163 pipe_select_current = (tmp >> 2) & 3;
164 tmp = (1 << pipe_select_current) |
165 (((gb_pipe_select >> 8) & 0xF) << 4);
166 WREG32_PLL(0x000D, tmp);
167 if (r100_gui_wait_for_idle(rdev)) {
168 pr_warn("Failed to wait GUI idle while resetting GPU. Bad things might happen.\n");
169 }
170 if (rv515_mc_wait_for_idle(rdev)) {
171 pr_warn("Failed to wait MC idle while programming pipes. Bad things might happen.\n");
172 }
173 }
174
rv515_vram_get_type(struct radeon_device * rdev)175 static void rv515_vram_get_type(struct radeon_device *rdev)
176 {
177 uint32_t tmp;
178
179 rdev->mc.vram_width = 128;
180 rdev->mc.vram_is_ddr = true;
181 tmp = RREG32_MC(RV515_MC_CNTL) & MEM_NUM_CHANNELS_MASK;
182 switch (tmp) {
183 case 0:
184 rdev->mc.vram_width = 64;
185 break;
186 case 1:
187 rdev->mc.vram_width = 128;
188 break;
189 default:
190 rdev->mc.vram_width = 128;
191 break;
192 }
193 }
194
rv515_mc_init(struct radeon_device * rdev)195 static void rv515_mc_init(struct radeon_device *rdev)
196 {
197
198 rv515_vram_get_type(rdev);
199 r100_vram_init_sizes(rdev);
200 radeon_vram_location(rdev, &rdev->mc, 0);
201 rdev->mc.gtt_base_align = 0;
202 if (!(rdev->flags & RADEON_IS_AGP))
203 radeon_gtt_location(rdev, &rdev->mc);
204 radeon_update_bandwidth_info(rdev);
205 }
206
rv515_mc_rreg(struct radeon_device * rdev,uint32_t reg)207 uint32_t rv515_mc_rreg(struct radeon_device *rdev, uint32_t reg)
208 {
209 unsigned long flags;
210 uint32_t r;
211
212 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
213 WREG32(MC_IND_INDEX, 0x7f0000 | (reg & 0xffff));
214 r = RREG32(MC_IND_DATA);
215 WREG32(MC_IND_INDEX, 0);
216 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
217
218 return r;
219 }
220
rv515_mc_wreg(struct radeon_device * rdev,uint32_t reg,uint32_t v)221 void rv515_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
222 {
223 unsigned long flags;
224
225 spin_lock_irqsave(&rdev->mc_idx_lock, flags);
226 WREG32(MC_IND_INDEX, 0xff0000 | ((reg) & 0xffff));
227 WREG32(MC_IND_DATA, (v));
228 WREG32(MC_IND_INDEX, 0);
229 spin_unlock_irqrestore(&rdev->mc_idx_lock, flags);
230 }
231
232 #if defined(CONFIG_DEBUG_FS)
rv515_debugfs_pipes_info(struct seq_file * m,void * data)233 static int rv515_debugfs_pipes_info(struct seq_file *m, void *data)
234 {
235 struct drm_info_node *node = (struct drm_info_node *) m->private;
236 struct drm_device *dev = node->minor->dev;
237 struct radeon_device *rdev = dev->dev_private;
238 uint32_t tmp;
239
240 tmp = RREG32(GB_PIPE_SELECT);
241 seq_printf(m, "GB_PIPE_SELECT 0x%08x\n", tmp);
242 tmp = RREG32(SU_REG_DEST);
243 seq_printf(m, "SU_REG_DEST 0x%08x\n", tmp);
244 tmp = RREG32(GB_TILE_CONFIG);
245 seq_printf(m, "GB_TILE_CONFIG 0x%08x\n", tmp);
246 tmp = RREG32(DST_PIPE_CONFIG);
247 seq_printf(m, "DST_PIPE_CONFIG 0x%08x\n", tmp);
248 return 0;
249 }
250
rv515_debugfs_ga_info(struct seq_file * m,void * data)251 static int rv515_debugfs_ga_info(struct seq_file *m, void *data)
252 {
253 struct drm_info_node *node = (struct drm_info_node *) m->private;
254 struct drm_device *dev = node->minor->dev;
255 struct radeon_device *rdev = dev->dev_private;
256 uint32_t tmp;
257
258 tmp = RREG32(0x2140);
259 seq_printf(m, "VAP_CNTL_STATUS 0x%08x\n", tmp);
260 radeon_asic_reset(rdev);
261 tmp = RREG32(0x425C);
262 seq_printf(m, "GA_IDLE 0x%08x\n", tmp);
263 return 0;
264 }
265
266 static struct drm_info_list rv515_pipes_info_list[] = {
267 {"rv515_pipes_info", rv515_debugfs_pipes_info, 0, NULL},
268 };
269
270 static struct drm_info_list rv515_ga_info_list[] = {
271 {"rv515_ga_info", rv515_debugfs_ga_info, 0, NULL},
272 };
273 #endif
274
rv515_debugfs_pipes_info_init(struct radeon_device * rdev)275 static int rv515_debugfs_pipes_info_init(struct radeon_device *rdev)
276 {
277 #if defined(CONFIG_DEBUG_FS)
278 return radeon_debugfs_add_files(rdev, rv515_pipes_info_list, 1);
279 #else
280 return 0;
281 #endif
282 }
283
rv515_debugfs_ga_info_init(struct radeon_device * rdev)284 static int rv515_debugfs_ga_info_init(struct radeon_device *rdev)
285 {
286 #if defined(CONFIG_DEBUG_FS)
287 return radeon_debugfs_add_files(rdev, rv515_ga_info_list, 1);
288 #else
289 return 0;
290 #endif
291 }
292
rv515_mc_stop(struct radeon_device * rdev,struct rv515_mc_save * save)293 void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save)
294 {
295 u32 crtc_enabled, tmp, frame_count, blackout;
296 int i, j;
297
298 save->vga_render_control = RREG32(R_000300_VGA_RENDER_CONTROL);
299 save->vga_hdp_control = RREG32(R_000328_VGA_HDP_CONTROL);
300
301 /* disable VGA render */
302 WREG32(R_000300_VGA_RENDER_CONTROL, 0);
303 /* blank the display controllers */
304 for (i = 0; i < rdev->num_crtc; i++) {
305 crtc_enabled = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]) & AVIVO_CRTC_EN;
306 if (crtc_enabled) {
307 save->crtc_enabled[i] = true;
308 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
309 if (!(tmp & AVIVO_CRTC_DISP_READ_REQUEST_DISABLE)) {
310 radeon_wait_for_vblank(rdev, i);
311 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
312 tmp |= AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
313 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
314 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
315 }
316 /* wait for the next frame */
317 frame_count = radeon_get_vblank_counter(rdev, i);
318 for (j = 0; j < rdev->usec_timeout; j++) {
319 if (radeon_get_vblank_counter(rdev, i) != frame_count)
320 break;
321 udelay(1);
322 }
323
324 /* XXX this is a hack to avoid strange behavior with EFI on certain systems */
325 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 1);
326 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
327 tmp &= ~AVIVO_CRTC_EN;
328 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
329 WREG32(AVIVO_D1CRTC_UPDATE_LOCK + crtc_offsets[i], 0);
330 save->crtc_enabled[i] = false;
331 /* ***** */
332 } else {
333 save->crtc_enabled[i] = false;
334 }
335 }
336
337 radeon_mc_wait_for_idle(rdev);
338
339 if (rdev->family >= CHIP_R600) {
340 if (rdev->family >= CHIP_RV770)
341 blackout = RREG32(R700_MC_CITF_CNTL);
342 else
343 blackout = RREG32(R600_CITF_CNTL);
344 if ((blackout & R600_BLACKOUT_MASK) != R600_BLACKOUT_MASK) {
345 /* Block CPU access */
346 WREG32(R600_BIF_FB_EN, 0);
347 /* blackout the MC */
348 blackout |= R600_BLACKOUT_MASK;
349 if (rdev->family >= CHIP_RV770)
350 WREG32(R700_MC_CITF_CNTL, blackout);
351 else
352 WREG32(R600_CITF_CNTL, blackout);
353 }
354 }
355 /* wait for the MC to settle */
356 udelay(100);
357
358 /* lock double buffered regs */
359 for (i = 0; i < rdev->num_crtc; i++) {
360 if (save->crtc_enabled[i]) {
361 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
362 if (!(tmp & AVIVO_D1GRPH_UPDATE_LOCK)) {
363 tmp |= AVIVO_D1GRPH_UPDATE_LOCK;
364 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
365 }
366 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
367 if (!(tmp & 1)) {
368 tmp |= 1;
369 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
370 }
371 }
372 }
373 }
374
rv515_mc_resume(struct radeon_device * rdev,struct rv515_mc_save * save)375 void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save)
376 {
377 u32 tmp, frame_count;
378 int i, j;
379
380 /* update crtc base addresses */
381 for (i = 0; i < rdev->num_crtc; i++) {
382 if (rdev->family >= CHIP_RV770) {
383 if (i == 0) {
384 WREG32(R700_D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
385 upper_32_bits(rdev->mc.vram_start));
386 WREG32(R700_D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
387 upper_32_bits(rdev->mc.vram_start));
388 } else {
389 WREG32(R700_D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH,
390 upper_32_bits(rdev->mc.vram_start));
391 WREG32(R700_D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH,
392 upper_32_bits(rdev->mc.vram_start));
393 }
394 }
395 WREG32(R_006110_D1GRPH_PRIMARY_SURFACE_ADDRESS + crtc_offsets[i],
396 (u32)rdev->mc.vram_start);
397 WREG32(R_006118_D1GRPH_SECONDARY_SURFACE_ADDRESS + crtc_offsets[i],
398 (u32)rdev->mc.vram_start);
399 }
400 WREG32(R_000310_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
401
402 /* unlock regs and wait for update */
403 for (i = 0; i < rdev->num_crtc; i++) {
404 if (save->crtc_enabled[i]) {
405 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i]);
406 if ((tmp & 0x7) != 3) {
407 tmp &= ~0x7;
408 tmp |= 0x3;
409 WREG32(AVIVO_D1MODE_MASTER_UPDATE_MODE + crtc_offsets[i], tmp);
410 }
411 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
412 if (tmp & AVIVO_D1GRPH_UPDATE_LOCK) {
413 tmp &= ~AVIVO_D1GRPH_UPDATE_LOCK;
414 WREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i], tmp);
415 }
416 tmp = RREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i]);
417 if (tmp & 1) {
418 tmp &= ~1;
419 WREG32(AVIVO_D1MODE_MASTER_UPDATE_LOCK + crtc_offsets[i], tmp);
420 }
421 for (j = 0; j < rdev->usec_timeout; j++) {
422 tmp = RREG32(AVIVO_D1GRPH_UPDATE + crtc_offsets[i]);
423 if ((tmp & AVIVO_D1GRPH_SURFACE_UPDATE_PENDING) == 0)
424 break;
425 udelay(1);
426 }
427 }
428 }
429
430 if (rdev->family >= CHIP_R600) {
431 /* unblackout the MC */
432 if (rdev->family >= CHIP_RV770)
433 tmp = RREG32(R700_MC_CITF_CNTL);
434 else
435 tmp = RREG32(R600_CITF_CNTL);
436 tmp &= ~R600_BLACKOUT_MASK;
437 if (rdev->family >= CHIP_RV770)
438 WREG32(R700_MC_CITF_CNTL, tmp);
439 else
440 WREG32(R600_CITF_CNTL, tmp);
441 /* allow CPU access */
442 WREG32(R600_BIF_FB_EN, R600_FB_READ_EN | R600_FB_WRITE_EN);
443 }
444
445 for (i = 0; i < rdev->num_crtc; i++) {
446 if (save->crtc_enabled[i]) {
447 tmp = RREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i]);
448 tmp &= ~AVIVO_CRTC_DISP_READ_REQUEST_DISABLE;
449 WREG32(AVIVO_D1CRTC_CONTROL + crtc_offsets[i], tmp);
450 /* wait for the next frame */
451 frame_count = radeon_get_vblank_counter(rdev, i);
452 for (j = 0; j < rdev->usec_timeout; j++) {
453 if (radeon_get_vblank_counter(rdev, i) != frame_count)
454 break;
455 udelay(1);
456 }
457 }
458 }
459 /* Unlock vga access */
460 WREG32(R_000328_VGA_HDP_CONTROL, save->vga_hdp_control);
461 mdelay(1);
462 WREG32(R_000300_VGA_RENDER_CONTROL, save->vga_render_control);
463 }
464
rv515_mc_program(struct radeon_device * rdev)465 static void rv515_mc_program(struct radeon_device *rdev)
466 {
467 struct rv515_mc_save save;
468
469 /* Stops all mc clients */
470 rv515_mc_stop(rdev, &save);
471
472 /* Wait for mc idle */
473 if (rv515_mc_wait_for_idle(rdev))
474 dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n");
475 /* Write VRAM size in case we are limiting it */
476 WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
477 /* Program MC, should be a 32bits limited address space */
478 WREG32_MC(R_000001_MC_FB_LOCATION,
479 S_000001_MC_FB_START(rdev->mc.vram_start >> 16) |
480 S_000001_MC_FB_TOP(rdev->mc.vram_end >> 16));
481 WREG32(R_000134_HDP_FB_LOCATION,
482 S_000134_HDP_FB_START(rdev->mc.vram_start >> 16));
483 if (rdev->flags & RADEON_IS_AGP) {
484 WREG32_MC(R_000002_MC_AGP_LOCATION,
485 S_000002_MC_AGP_START(rdev->mc.gtt_start >> 16) |
486 S_000002_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
487 WREG32_MC(R_000003_MC_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
488 WREG32_MC(R_000004_MC_AGP_BASE_2,
489 S_000004_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base)));
490 } else {
491 WREG32_MC(R_000002_MC_AGP_LOCATION, 0xFFFFFFFF);
492 WREG32_MC(R_000003_MC_AGP_BASE, 0);
493 WREG32_MC(R_000004_MC_AGP_BASE_2, 0);
494 }
495
496 rv515_mc_resume(rdev, &save);
497 }
498
rv515_clock_startup(struct radeon_device * rdev)499 void rv515_clock_startup(struct radeon_device *rdev)
500 {
501 if (radeon_dynclks != -1 && radeon_dynclks)
502 radeon_atom_set_clock_gating(rdev, 1);
503 /* We need to force on some of the block */
504 WREG32_PLL(R_00000F_CP_DYN_CNTL,
505 RREG32_PLL(R_00000F_CP_DYN_CNTL) | S_00000F_CP_FORCEON(1));
506 WREG32_PLL(R_000011_E2_DYN_CNTL,
507 RREG32_PLL(R_000011_E2_DYN_CNTL) | S_000011_E2_FORCEON(1));
508 WREG32_PLL(R_000013_IDCT_DYN_CNTL,
509 RREG32_PLL(R_000013_IDCT_DYN_CNTL) | S_000013_IDCT_FORCEON(1));
510 }
511
rv515_startup(struct radeon_device * rdev)512 static int rv515_startup(struct radeon_device *rdev)
513 {
514 int r;
515
516 rv515_mc_program(rdev);
517 /* Resume clock */
518 rv515_clock_startup(rdev);
519 /* Initialize GPU configuration (# pipes, ...) */
520 rv515_gpu_init(rdev);
521 /* Initialize GART (initialize after TTM so we can allocate
522 * memory through TTM but finalize after TTM) */
523 if (rdev->flags & RADEON_IS_PCIE) {
524 r = rv370_pcie_gart_enable(rdev);
525 if (r)
526 return r;
527 }
528
529 /* allocate wb buffer */
530 r = radeon_wb_init(rdev);
531 if (r)
532 return r;
533
534 r = radeon_fence_driver_start_ring(rdev, RADEON_RING_TYPE_GFX_INDEX);
535 if (r) {
536 dev_err(rdev->dev, "failed initializing CP fences (%d).\n", r);
537 return r;
538 }
539
540 /* Enable IRQ */
541 if (!rdev->irq.installed) {
542 r = radeon_irq_kms_init(rdev);
543 if (r)
544 return r;
545 }
546
547 rs600_irq_set(rdev);
548 rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
549 /* 1M ring buffer */
550 r = r100_cp_init(rdev, 1024 * 1024);
551 if (r) {
552 dev_err(rdev->dev, "failed initializing CP (%d).\n", r);
553 return r;
554 }
555
556 r = radeon_ib_pool_init(rdev);
557 if (r) {
558 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
559 return r;
560 }
561
562 return 0;
563 }
564
rv515_resume(struct radeon_device * rdev)565 int rv515_resume(struct radeon_device *rdev)
566 {
567 int r;
568
569 /* Make sur GART are not working */
570 if (rdev->flags & RADEON_IS_PCIE)
571 rv370_pcie_gart_disable(rdev);
572 /* Resume clock before doing reset */
573 rv515_clock_startup(rdev);
574 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
575 if (radeon_asic_reset(rdev)) {
576 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
577 RREG32(R_000E40_RBBM_STATUS),
578 RREG32(R_0007C0_CP_STAT));
579 }
580 /* post */
581 atom_asic_init(rdev->mode_info.atom_context);
582 /* Resume clock after posting */
583 rv515_clock_startup(rdev);
584 /* Initialize surface registers */
585 radeon_surface_init(rdev);
586
587 rdev->accel_working = true;
588 r = rv515_startup(rdev);
589 if (r) {
590 rdev->accel_working = false;
591 }
592 return r;
593 }
594
rv515_suspend(struct radeon_device * rdev)595 int rv515_suspend(struct radeon_device *rdev)
596 {
597 radeon_pm_suspend(rdev);
598 r100_cp_disable(rdev);
599 radeon_wb_disable(rdev);
600 rs600_irq_disable(rdev);
601 if (rdev->flags & RADEON_IS_PCIE)
602 rv370_pcie_gart_disable(rdev);
603 return 0;
604 }
605
rv515_set_safe_registers(struct radeon_device * rdev)606 void rv515_set_safe_registers(struct radeon_device *rdev)
607 {
608 rdev->config.r300.reg_safe_bm = rv515_reg_safe_bm;
609 rdev->config.r300.reg_safe_bm_size = ARRAY_SIZE(rv515_reg_safe_bm);
610 }
611
rv515_fini(struct radeon_device * rdev)612 void rv515_fini(struct radeon_device *rdev)
613 {
614 radeon_pm_fini(rdev);
615 r100_cp_fini(rdev);
616 radeon_wb_fini(rdev);
617 radeon_ib_pool_fini(rdev);
618 radeon_gem_fini(rdev);
619 rv370_pcie_gart_fini(rdev);
620 radeon_agp_fini(rdev);
621 radeon_irq_kms_fini(rdev);
622 radeon_fence_driver_fini(rdev);
623 radeon_bo_fini(rdev);
624 radeon_atombios_fini(rdev);
625 kfree(rdev->bios);
626 rdev->bios = NULL;
627 }
628
rv515_init(struct radeon_device * rdev)629 int rv515_init(struct radeon_device *rdev)
630 {
631 int r;
632
633 /* Initialize scratch registers */
634 radeon_scratch_init(rdev);
635 /* Initialize surface registers */
636 radeon_surface_init(rdev);
637 /* TODO: disable VGA need to use VGA request */
638 /* restore some register to sane defaults */
639 r100_restore_sanity(rdev);
640 /* BIOS*/
641 if (!radeon_get_bios(rdev)) {
642 if (ASIC_IS_AVIVO(rdev))
643 return -EINVAL;
644 }
645 if (rdev->is_atom_bios) {
646 r = radeon_atombios_init(rdev);
647 if (r)
648 return r;
649 } else {
650 dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n");
651 return -EINVAL;
652 }
653 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
654 if (radeon_asic_reset(rdev)) {
655 dev_warn(rdev->dev,
656 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
657 RREG32(R_000E40_RBBM_STATUS),
658 RREG32(R_0007C0_CP_STAT));
659 }
660 /* check if cards are posted or not */
661 if (radeon_boot_test_post_card(rdev) == false)
662 return -EINVAL;
663 /* Initialize clocks */
664 radeon_get_clock_info(rdev->ddev);
665 /* initialize AGP */
666 if (rdev->flags & RADEON_IS_AGP) {
667 r = radeon_agp_init(rdev);
668 if (r) {
669 radeon_agp_disable(rdev);
670 }
671 }
672 /* initialize memory controller */
673 rv515_mc_init(rdev);
674 rv515_debugfs(rdev);
675 /* Fence driver */
676 r = radeon_fence_driver_init(rdev);
677 if (r)
678 return r;
679 /* Memory manager */
680 r = radeon_bo_init(rdev);
681 if (r)
682 return r;
683 r = rv370_pcie_gart_init(rdev);
684 if (r)
685 return r;
686 rv515_set_safe_registers(rdev);
687
688 /* Initialize power management */
689 radeon_pm_init(rdev);
690
691 rdev->accel_working = true;
692 r = rv515_startup(rdev);
693 if (r) {
694 /* Somethings want wront with the accel init stop accel */
695 dev_err(rdev->dev, "Disabling GPU acceleration\n");
696 r100_cp_fini(rdev);
697 radeon_wb_fini(rdev);
698 radeon_ib_pool_fini(rdev);
699 radeon_irq_kms_fini(rdev);
700 rv370_pcie_gart_fini(rdev);
701 radeon_agp_fini(rdev);
702 rdev->accel_working = false;
703 }
704 return 0;
705 }
706
atom_rv515_force_tv_scaler(struct radeon_device * rdev,struct radeon_crtc * crtc)707 void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *crtc)
708 {
709 int index_reg = 0x6578 + crtc->crtc_offset;
710 int data_reg = 0x657c + crtc->crtc_offset;
711
712 WREG32(0x659C + crtc->crtc_offset, 0x0);
713 WREG32(0x6594 + crtc->crtc_offset, 0x705);
714 WREG32(0x65A4 + crtc->crtc_offset, 0x10001);
715 WREG32(0x65D8 + crtc->crtc_offset, 0x0);
716 WREG32(0x65B0 + crtc->crtc_offset, 0x0);
717 WREG32(0x65C0 + crtc->crtc_offset, 0x0);
718 WREG32(0x65D4 + crtc->crtc_offset, 0x0);
719 WREG32(index_reg, 0x0);
720 WREG32(data_reg, 0x841880A8);
721 WREG32(index_reg, 0x1);
722 WREG32(data_reg, 0x84208680);
723 WREG32(index_reg, 0x2);
724 WREG32(data_reg, 0xBFF880B0);
725 WREG32(index_reg, 0x100);
726 WREG32(data_reg, 0x83D88088);
727 WREG32(index_reg, 0x101);
728 WREG32(data_reg, 0x84608680);
729 WREG32(index_reg, 0x102);
730 WREG32(data_reg, 0xBFF080D0);
731 WREG32(index_reg, 0x200);
732 WREG32(data_reg, 0x83988068);
733 WREG32(index_reg, 0x201);
734 WREG32(data_reg, 0x84A08680);
735 WREG32(index_reg, 0x202);
736 WREG32(data_reg, 0xBFF080F8);
737 WREG32(index_reg, 0x300);
738 WREG32(data_reg, 0x83588058);
739 WREG32(index_reg, 0x301);
740 WREG32(data_reg, 0x84E08660);
741 WREG32(index_reg, 0x302);
742 WREG32(data_reg, 0xBFF88120);
743 WREG32(index_reg, 0x400);
744 WREG32(data_reg, 0x83188040);
745 WREG32(index_reg, 0x401);
746 WREG32(data_reg, 0x85008660);
747 WREG32(index_reg, 0x402);
748 WREG32(data_reg, 0xBFF88150);
749 WREG32(index_reg, 0x500);
750 WREG32(data_reg, 0x82D88030);
751 WREG32(index_reg, 0x501);
752 WREG32(data_reg, 0x85408640);
753 WREG32(index_reg, 0x502);
754 WREG32(data_reg, 0xBFF88180);
755 WREG32(index_reg, 0x600);
756 WREG32(data_reg, 0x82A08018);
757 WREG32(index_reg, 0x601);
758 WREG32(data_reg, 0x85808620);
759 WREG32(index_reg, 0x602);
760 WREG32(data_reg, 0xBFF081B8);
761 WREG32(index_reg, 0x700);
762 WREG32(data_reg, 0x82608010);
763 WREG32(index_reg, 0x701);
764 WREG32(data_reg, 0x85A08600);
765 WREG32(index_reg, 0x702);
766 WREG32(data_reg, 0x800081F0);
767 WREG32(index_reg, 0x800);
768 WREG32(data_reg, 0x8228BFF8);
769 WREG32(index_reg, 0x801);
770 WREG32(data_reg, 0x85E085E0);
771 WREG32(index_reg, 0x802);
772 WREG32(data_reg, 0xBFF88228);
773 WREG32(index_reg, 0x10000);
774 WREG32(data_reg, 0x82A8BF00);
775 WREG32(index_reg, 0x10001);
776 WREG32(data_reg, 0x82A08CC0);
777 WREG32(index_reg, 0x10002);
778 WREG32(data_reg, 0x8008BEF8);
779 WREG32(index_reg, 0x10100);
780 WREG32(data_reg, 0x81F0BF28);
781 WREG32(index_reg, 0x10101);
782 WREG32(data_reg, 0x83608CA0);
783 WREG32(index_reg, 0x10102);
784 WREG32(data_reg, 0x8018BED0);
785 WREG32(index_reg, 0x10200);
786 WREG32(data_reg, 0x8148BF38);
787 WREG32(index_reg, 0x10201);
788 WREG32(data_reg, 0x84408C80);
789 WREG32(index_reg, 0x10202);
790 WREG32(data_reg, 0x8008BEB8);
791 WREG32(index_reg, 0x10300);
792 WREG32(data_reg, 0x80B0BF78);
793 WREG32(index_reg, 0x10301);
794 WREG32(data_reg, 0x85008C20);
795 WREG32(index_reg, 0x10302);
796 WREG32(data_reg, 0x8020BEA0);
797 WREG32(index_reg, 0x10400);
798 WREG32(data_reg, 0x8028BF90);
799 WREG32(index_reg, 0x10401);
800 WREG32(data_reg, 0x85E08BC0);
801 WREG32(index_reg, 0x10402);
802 WREG32(data_reg, 0x8018BE90);
803 WREG32(index_reg, 0x10500);
804 WREG32(data_reg, 0xBFB8BFB0);
805 WREG32(index_reg, 0x10501);
806 WREG32(data_reg, 0x86C08B40);
807 WREG32(index_reg, 0x10502);
808 WREG32(data_reg, 0x8010BE90);
809 WREG32(index_reg, 0x10600);
810 WREG32(data_reg, 0xBF58BFC8);
811 WREG32(index_reg, 0x10601);
812 WREG32(data_reg, 0x87A08AA0);
813 WREG32(index_reg, 0x10602);
814 WREG32(data_reg, 0x8010BE98);
815 WREG32(index_reg, 0x10700);
816 WREG32(data_reg, 0xBF10BFF0);
817 WREG32(index_reg, 0x10701);
818 WREG32(data_reg, 0x886089E0);
819 WREG32(index_reg, 0x10702);
820 WREG32(data_reg, 0x8018BEB0);
821 WREG32(index_reg, 0x10800);
822 WREG32(data_reg, 0xBED8BFE8);
823 WREG32(index_reg, 0x10801);
824 WREG32(data_reg, 0x89408940);
825 WREG32(index_reg, 0x10802);
826 WREG32(data_reg, 0xBFE8BED8);
827 WREG32(index_reg, 0x20000);
828 WREG32(data_reg, 0x80008000);
829 WREG32(index_reg, 0x20001);
830 WREG32(data_reg, 0x90008000);
831 WREG32(index_reg, 0x20002);
832 WREG32(data_reg, 0x80008000);
833 WREG32(index_reg, 0x20003);
834 WREG32(data_reg, 0x80008000);
835 WREG32(index_reg, 0x20100);
836 WREG32(data_reg, 0x80108000);
837 WREG32(index_reg, 0x20101);
838 WREG32(data_reg, 0x8FE0BF70);
839 WREG32(index_reg, 0x20102);
840 WREG32(data_reg, 0xBFE880C0);
841 WREG32(index_reg, 0x20103);
842 WREG32(data_reg, 0x80008000);
843 WREG32(index_reg, 0x20200);
844 WREG32(data_reg, 0x8018BFF8);
845 WREG32(index_reg, 0x20201);
846 WREG32(data_reg, 0x8F80BF08);
847 WREG32(index_reg, 0x20202);
848 WREG32(data_reg, 0xBFD081A0);
849 WREG32(index_reg, 0x20203);
850 WREG32(data_reg, 0xBFF88000);
851 WREG32(index_reg, 0x20300);
852 WREG32(data_reg, 0x80188000);
853 WREG32(index_reg, 0x20301);
854 WREG32(data_reg, 0x8EE0BEC0);
855 WREG32(index_reg, 0x20302);
856 WREG32(data_reg, 0xBFB082A0);
857 WREG32(index_reg, 0x20303);
858 WREG32(data_reg, 0x80008000);
859 WREG32(index_reg, 0x20400);
860 WREG32(data_reg, 0x80188000);
861 WREG32(index_reg, 0x20401);
862 WREG32(data_reg, 0x8E00BEA0);
863 WREG32(index_reg, 0x20402);
864 WREG32(data_reg, 0xBF8883C0);
865 WREG32(index_reg, 0x20403);
866 WREG32(data_reg, 0x80008000);
867 WREG32(index_reg, 0x20500);
868 WREG32(data_reg, 0x80188000);
869 WREG32(index_reg, 0x20501);
870 WREG32(data_reg, 0x8D00BE90);
871 WREG32(index_reg, 0x20502);
872 WREG32(data_reg, 0xBF588500);
873 WREG32(index_reg, 0x20503);
874 WREG32(data_reg, 0x80008008);
875 WREG32(index_reg, 0x20600);
876 WREG32(data_reg, 0x80188000);
877 WREG32(index_reg, 0x20601);
878 WREG32(data_reg, 0x8BC0BE98);
879 WREG32(index_reg, 0x20602);
880 WREG32(data_reg, 0xBF308660);
881 WREG32(index_reg, 0x20603);
882 WREG32(data_reg, 0x80008008);
883 WREG32(index_reg, 0x20700);
884 WREG32(data_reg, 0x80108000);
885 WREG32(index_reg, 0x20701);
886 WREG32(data_reg, 0x8A80BEB0);
887 WREG32(index_reg, 0x20702);
888 WREG32(data_reg, 0xBF0087C0);
889 WREG32(index_reg, 0x20703);
890 WREG32(data_reg, 0x80008008);
891 WREG32(index_reg, 0x20800);
892 WREG32(data_reg, 0x80108000);
893 WREG32(index_reg, 0x20801);
894 WREG32(data_reg, 0x8920BED0);
895 WREG32(index_reg, 0x20802);
896 WREG32(data_reg, 0xBED08920);
897 WREG32(index_reg, 0x20803);
898 WREG32(data_reg, 0x80008010);
899 WREG32(index_reg, 0x30000);
900 WREG32(data_reg, 0x90008000);
901 WREG32(index_reg, 0x30001);
902 WREG32(data_reg, 0x80008000);
903 WREG32(index_reg, 0x30100);
904 WREG32(data_reg, 0x8FE0BF90);
905 WREG32(index_reg, 0x30101);
906 WREG32(data_reg, 0xBFF880A0);
907 WREG32(index_reg, 0x30200);
908 WREG32(data_reg, 0x8F60BF40);
909 WREG32(index_reg, 0x30201);
910 WREG32(data_reg, 0xBFE88180);
911 WREG32(index_reg, 0x30300);
912 WREG32(data_reg, 0x8EC0BF00);
913 WREG32(index_reg, 0x30301);
914 WREG32(data_reg, 0xBFC88280);
915 WREG32(index_reg, 0x30400);
916 WREG32(data_reg, 0x8DE0BEE0);
917 WREG32(index_reg, 0x30401);
918 WREG32(data_reg, 0xBFA083A0);
919 WREG32(index_reg, 0x30500);
920 WREG32(data_reg, 0x8CE0BED0);
921 WREG32(index_reg, 0x30501);
922 WREG32(data_reg, 0xBF7884E0);
923 WREG32(index_reg, 0x30600);
924 WREG32(data_reg, 0x8BA0BED8);
925 WREG32(index_reg, 0x30601);
926 WREG32(data_reg, 0xBF508640);
927 WREG32(index_reg, 0x30700);
928 WREG32(data_reg, 0x8A60BEE8);
929 WREG32(index_reg, 0x30701);
930 WREG32(data_reg, 0xBF2087A0);
931 WREG32(index_reg, 0x30800);
932 WREG32(data_reg, 0x8900BF00);
933 WREG32(index_reg, 0x30801);
934 WREG32(data_reg, 0xBF008900);
935 }
936
937 struct rv515_watermark {
938 u32 lb_request_fifo_depth;
939 fixed20_12 num_line_pair;
940 fixed20_12 estimated_width;
941 fixed20_12 worst_case_latency;
942 fixed20_12 consumption_rate;
943 fixed20_12 active_time;
944 fixed20_12 dbpp;
945 fixed20_12 priority_mark_max;
946 fixed20_12 priority_mark;
947 fixed20_12 sclk;
948 };
949
rv515_crtc_bandwidth_compute(struct radeon_device * rdev,struct radeon_crtc * crtc,struct rv515_watermark * wm,bool low)950 static void rv515_crtc_bandwidth_compute(struct radeon_device *rdev,
951 struct radeon_crtc *crtc,
952 struct rv515_watermark *wm,
953 bool low)
954 {
955 struct drm_display_mode *mode = &crtc->base.mode;
956 fixed20_12 a, b, c;
957 fixed20_12 pclk, request_fifo_depth, tolerable_latency, estimated_width;
958 fixed20_12 consumption_time, line_time, chunk_time, read_delay_latency;
959 fixed20_12 sclk;
960 u32 selected_sclk;
961
962 if (!crtc->base.enabled) {
963 /* FIXME: wouldn't it better to set priority mark to maximum */
964 wm->lb_request_fifo_depth = 4;
965 return;
966 }
967
968 /* rv6xx, rv7xx */
969 if ((rdev->family >= CHIP_RV610) &&
970 (rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
971 selected_sclk = radeon_dpm_get_sclk(rdev, low);
972 else
973 selected_sclk = rdev->pm.current_sclk;
974
975 /* sclk in Mhz */
976 a.full = dfixed_const(100);
977 sclk.full = dfixed_const(selected_sclk);
978 sclk.full = dfixed_div(sclk, a);
979
980 if (crtc->vsc.full > dfixed_const(2))
981 wm->num_line_pair.full = dfixed_const(2);
982 else
983 wm->num_line_pair.full = dfixed_const(1);
984
985 b.full = dfixed_const(mode->crtc_hdisplay);
986 c.full = dfixed_const(256);
987 a.full = dfixed_div(b, c);
988 request_fifo_depth.full = dfixed_mul(a, wm->num_line_pair);
989 request_fifo_depth.full = dfixed_ceil(request_fifo_depth);
990 if (a.full < dfixed_const(4)) {
991 wm->lb_request_fifo_depth = 4;
992 } else {
993 wm->lb_request_fifo_depth = dfixed_trunc(request_fifo_depth);
994 }
995
996 /* Determine consumption rate
997 * pclk = pixel clock period(ns) = 1000 / (mode.clock / 1000)
998 * vtaps = number of vertical taps,
999 * vsc = vertical scaling ratio, defined as source/destination
1000 * hsc = horizontal scaling ration, defined as source/destination
1001 */
1002 a.full = dfixed_const(mode->clock);
1003 b.full = dfixed_const(1000);
1004 a.full = dfixed_div(a, b);
1005 pclk.full = dfixed_div(b, a);
1006 if (crtc->rmx_type != RMX_OFF) {
1007 b.full = dfixed_const(2);
1008 if (crtc->vsc.full > b.full)
1009 b.full = crtc->vsc.full;
1010 b.full = dfixed_mul(b, crtc->hsc);
1011 c.full = dfixed_const(2);
1012 b.full = dfixed_div(b, c);
1013 consumption_time.full = dfixed_div(pclk, b);
1014 } else {
1015 consumption_time.full = pclk.full;
1016 }
1017 a.full = dfixed_const(1);
1018 wm->consumption_rate.full = dfixed_div(a, consumption_time);
1019
1020
1021 /* Determine line time
1022 * LineTime = total time for one line of displayhtotal
1023 * LineTime = total number of horizontal pixels
1024 * pclk = pixel clock period(ns)
1025 */
1026 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
1027 line_time.full = dfixed_mul(a, pclk);
1028
1029 /* Determine active time
1030 * ActiveTime = time of active region of display within one line,
1031 * hactive = total number of horizontal active pixels
1032 * htotal = total number of horizontal pixels
1033 */
1034 a.full = dfixed_const(crtc->base.mode.crtc_htotal);
1035 b.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
1036 wm->active_time.full = dfixed_mul(line_time, b);
1037 wm->active_time.full = dfixed_div(wm->active_time, a);
1038
1039 /* Determine chunk time
1040 * ChunkTime = the time it takes the DCP to send one chunk of data
1041 * to the LB which consists of pipeline delay and inter chunk gap
1042 * sclk = system clock(Mhz)
1043 */
1044 a.full = dfixed_const(600 * 1000);
1045 chunk_time.full = dfixed_div(a, sclk);
1046 read_delay_latency.full = dfixed_const(1000);
1047
1048 /* Determine the worst case latency
1049 * NumLinePair = Number of line pairs to request(1=2 lines, 2=4 lines)
1050 * WorstCaseLatency = worst case time from urgent to when the MC starts
1051 * to return data
1052 * READ_DELAY_IDLE_MAX = constant of 1us
1053 * ChunkTime = time it takes the DCP to send one chunk of data to the LB
1054 * which consists of pipeline delay and inter chunk gap
1055 */
1056 if (dfixed_trunc(wm->num_line_pair) > 1) {
1057 a.full = dfixed_const(3);
1058 wm->worst_case_latency.full = dfixed_mul(a, chunk_time);
1059 wm->worst_case_latency.full += read_delay_latency.full;
1060 } else {
1061 wm->worst_case_latency.full = chunk_time.full + read_delay_latency.full;
1062 }
1063
1064 /* Determine the tolerable latency
1065 * TolerableLatency = Any given request has only 1 line time
1066 * for the data to be returned
1067 * LBRequestFifoDepth = Number of chunk requests the LB can
1068 * put into the request FIFO for a display
1069 * LineTime = total time for one line of display
1070 * ChunkTime = the time it takes the DCP to send one chunk
1071 * of data to the LB which consists of
1072 * pipeline delay and inter chunk gap
1073 */
1074 if ((2+wm->lb_request_fifo_depth) >= dfixed_trunc(request_fifo_depth)) {
1075 tolerable_latency.full = line_time.full;
1076 } else {
1077 tolerable_latency.full = dfixed_const(wm->lb_request_fifo_depth - 2);
1078 tolerable_latency.full = request_fifo_depth.full - tolerable_latency.full;
1079 tolerable_latency.full = dfixed_mul(tolerable_latency, chunk_time);
1080 tolerable_latency.full = line_time.full - tolerable_latency.full;
1081 }
1082 /* We assume worst case 32bits (4 bytes) */
1083 wm->dbpp.full = dfixed_const(2 * 16);
1084
1085 /* Determine the maximum priority mark
1086 * width = viewport width in pixels
1087 */
1088 a.full = dfixed_const(16);
1089 wm->priority_mark_max.full = dfixed_const(crtc->base.mode.crtc_hdisplay);
1090 wm->priority_mark_max.full = dfixed_div(wm->priority_mark_max, a);
1091 wm->priority_mark_max.full = dfixed_ceil(wm->priority_mark_max);
1092
1093 /* Determine estimated width */
1094 estimated_width.full = tolerable_latency.full - wm->worst_case_latency.full;
1095 estimated_width.full = dfixed_div(estimated_width, consumption_time);
1096 if (dfixed_trunc(estimated_width) > crtc->base.mode.crtc_hdisplay) {
1097 wm->priority_mark.full = wm->priority_mark_max.full;
1098 } else {
1099 a.full = dfixed_const(16);
1100 wm->priority_mark.full = dfixed_div(estimated_width, a);
1101 wm->priority_mark.full = dfixed_ceil(wm->priority_mark);
1102 wm->priority_mark.full = wm->priority_mark_max.full - wm->priority_mark.full;
1103 }
1104 }
1105
rv515_compute_mode_priority(struct radeon_device * rdev,struct rv515_watermark * wm0,struct rv515_watermark * wm1,struct drm_display_mode * mode0,struct drm_display_mode * mode1,u32 * d1mode_priority_a_cnt,u32 * d2mode_priority_a_cnt)1106 static void rv515_compute_mode_priority(struct radeon_device *rdev,
1107 struct rv515_watermark *wm0,
1108 struct rv515_watermark *wm1,
1109 struct drm_display_mode *mode0,
1110 struct drm_display_mode *mode1,
1111 u32 *d1mode_priority_a_cnt,
1112 u32 *d2mode_priority_a_cnt)
1113 {
1114 fixed20_12 priority_mark02, priority_mark12, fill_rate;
1115 fixed20_12 a, b;
1116
1117 *d1mode_priority_a_cnt = MODE_PRIORITY_OFF;
1118 *d2mode_priority_a_cnt = MODE_PRIORITY_OFF;
1119
1120 if (mode0 && mode1) {
1121 if (dfixed_trunc(wm0->dbpp) > 64)
1122 a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair);
1123 else
1124 a.full = wm0->num_line_pair.full;
1125 if (dfixed_trunc(wm1->dbpp) > 64)
1126 b.full = dfixed_div(wm1->dbpp, wm1->num_line_pair);
1127 else
1128 b.full = wm1->num_line_pair.full;
1129 a.full += b.full;
1130 fill_rate.full = dfixed_div(wm0->sclk, a);
1131 if (wm0->consumption_rate.full > fill_rate.full) {
1132 b.full = wm0->consumption_rate.full - fill_rate.full;
1133 b.full = dfixed_mul(b, wm0->active_time);
1134 a.full = dfixed_const(16);
1135 b.full = dfixed_div(b, a);
1136 a.full = dfixed_mul(wm0->worst_case_latency,
1137 wm0->consumption_rate);
1138 priority_mark02.full = a.full + b.full;
1139 } else {
1140 a.full = dfixed_mul(wm0->worst_case_latency,
1141 wm0->consumption_rate);
1142 b.full = dfixed_const(16 * 1000);
1143 priority_mark02.full = dfixed_div(a, b);
1144 }
1145 if (wm1->consumption_rate.full > fill_rate.full) {
1146 b.full = wm1->consumption_rate.full - fill_rate.full;
1147 b.full = dfixed_mul(b, wm1->active_time);
1148 a.full = dfixed_const(16);
1149 b.full = dfixed_div(b, a);
1150 a.full = dfixed_mul(wm1->worst_case_latency,
1151 wm1->consumption_rate);
1152 priority_mark12.full = a.full + b.full;
1153 } else {
1154 a.full = dfixed_mul(wm1->worst_case_latency,
1155 wm1->consumption_rate);
1156 b.full = dfixed_const(16 * 1000);
1157 priority_mark12.full = dfixed_div(a, b);
1158 }
1159 if (wm0->priority_mark.full > priority_mark02.full)
1160 priority_mark02.full = wm0->priority_mark.full;
1161 if (wm0->priority_mark_max.full > priority_mark02.full)
1162 priority_mark02.full = wm0->priority_mark_max.full;
1163 if (wm1->priority_mark.full > priority_mark12.full)
1164 priority_mark12.full = wm1->priority_mark.full;
1165 if (wm1->priority_mark_max.full > priority_mark12.full)
1166 priority_mark12.full = wm1->priority_mark_max.full;
1167 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1168 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1169 if (rdev->disp_priority == 2) {
1170 *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1171 *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1172 }
1173 } else if (mode0) {
1174 if (dfixed_trunc(wm0->dbpp) > 64)
1175 a.full = dfixed_div(wm0->dbpp, wm0->num_line_pair);
1176 else
1177 a.full = wm0->num_line_pair.full;
1178 fill_rate.full = dfixed_div(wm0->sclk, a);
1179 if (wm0->consumption_rate.full > fill_rate.full) {
1180 b.full = wm0->consumption_rate.full - fill_rate.full;
1181 b.full = dfixed_mul(b, wm0->active_time);
1182 a.full = dfixed_const(16);
1183 b.full = dfixed_div(b, a);
1184 a.full = dfixed_mul(wm0->worst_case_latency,
1185 wm0->consumption_rate);
1186 priority_mark02.full = a.full + b.full;
1187 } else {
1188 a.full = dfixed_mul(wm0->worst_case_latency,
1189 wm0->consumption_rate);
1190 b.full = dfixed_const(16);
1191 priority_mark02.full = dfixed_div(a, b);
1192 }
1193 if (wm0->priority_mark.full > priority_mark02.full)
1194 priority_mark02.full = wm0->priority_mark.full;
1195 if (wm0->priority_mark_max.full > priority_mark02.full)
1196 priority_mark02.full = wm0->priority_mark_max.full;
1197 *d1mode_priority_a_cnt = dfixed_trunc(priority_mark02);
1198 if (rdev->disp_priority == 2)
1199 *d1mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1200 } else if (mode1) {
1201 if (dfixed_trunc(wm1->dbpp) > 64)
1202 a.full = dfixed_div(wm1->dbpp, wm1->num_line_pair);
1203 else
1204 a.full = wm1->num_line_pair.full;
1205 fill_rate.full = dfixed_div(wm1->sclk, a);
1206 if (wm1->consumption_rate.full > fill_rate.full) {
1207 b.full = wm1->consumption_rate.full - fill_rate.full;
1208 b.full = dfixed_mul(b, wm1->active_time);
1209 a.full = dfixed_const(16);
1210 b.full = dfixed_div(b, a);
1211 a.full = dfixed_mul(wm1->worst_case_latency,
1212 wm1->consumption_rate);
1213 priority_mark12.full = a.full + b.full;
1214 } else {
1215 a.full = dfixed_mul(wm1->worst_case_latency,
1216 wm1->consumption_rate);
1217 b.full = dfixed_const(16 * 1000);
1218 priority_mark12.full = dfixed_div(a, b);
1219 }
1220 if (wm1->priority_mark.full > priority_mark12.full)
1221 priority_mark12.full = wm1->priority_mark.full;
1222 if (wm1->priority_mark_max.full > priority_mark12.full)
1223 priority_mark12.full = wm1->priority_mark_max.full;
1224 *d2mode_priority_a_cnt = dfixed_trunc(priority_mark12);
1225 if (rdev->disp_priority == 2)
1226 *d2mode_priority_a_cnt |= MODE_PRIORITY_ALWAYS_ON;
1227 }
1228 }
1229
rv515_bandwidth_avivo_update(struct radeon_device * rdev)1230 void rv515_bandwidth_avivo_update(struct radeon_device *rdev)
1231 {
1232 struct drm_display_mode *mode0 = NULL;
1233 struct drm_display_mode *mode1 = NULL;
1234 struct rv515_watermark wm0_high, wm0_low;
1235 struct rv515_watermark wm1_high, wm1_low;
1236 u32 tmp;
1237 u32 d1mode_priority_a_cnt, d1mode_priority_b_cnt;
1238 u32 d2mode_priority_a_cnt, d2mode_priority_b_cnt;
1239
1240 if (rdev->mode_info.crtcs[0]->base.enabled)
1241 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1242 if (rdev->mode_info.crtcs[1]->base.enabled)
1243 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1244 rs690_line_buffer_adjust(rdev, mode0, mode1);
1245
1246 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_high, false);
1247 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_high, false);
1248
1249 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[0], &wm0_low, false);
1250 rv515_crtc_bandwidth_compute(rdev, rdev->mode_info.crtcs[1], &wm1_low, false);
1251
1252 tmp = wm0_high.lb_request_fifo_depth;
1253 tmp |= wm1_high.lb_request_fifo_depth << 16;
1254 WREG32(LB_MAX_REQ_OUTSTANDING, tmp);
1255
1256 rv515_compute_mode_priority(rdev,
1257 &wm0_high, &wm1_high,
1258 mode0, mode1,
1259 &d1mode_priority_a_cnt, &d2mode_priority_a_cnt);
1260 rv515_compute_mode_priority(rdev,
1261 &wm0_low, &wm1_low,
1262 mode0, mode1,
1263 &d1mode_priority_b_cnt, &d2mode_priority_b_cnt);
1264
1265 WREG32(D1MODE_PRIORITY_A_CNT, d1mode_priority_a_cnt);
1266 WREG32(D1MODE_PRIORITY_B_CNT, d1mode_priority_b_cnt);
1267 WREG32(D2MODE_PRIORITY_A_CNT, d2mode_priority_a_cnt);
1268 WREG32(D2MODE_PRIORITY_B_CNT, d2mode_priority_b_cnt);
1269 }
1270
rv515_bandwidth_update(struct radeon_device * rdev)1271 void rv515_bandwidth_update(struct radeon_device *rdev)
1272 {
1273 uint32_t tmp;
1274 struct drm_display_mode *mode0 = NULL;
1275 struct drm_display_mode *mode1 = NULL;
1276
1277 if (!rdev->mode_info.mode_config_initialized)
1278 return;
1279
1280 radeon_update_display_priority(rdev);
1281
1282 if (rdev->mode_info.crtcs[0]->base.enabled)
1283 mode0 = &rdev->mode_info.crtcs[0]->base.mode;
1284 if (rdev->mode_info.crtcs[1]->base.enabled)
1285 mode1 = &rdev->mode_info.crtcs[1]->base.mode;
1286 /*
1287 * Set display0/1 priority up in the memory controller for
1288 * modes if the user specifies HIGH for displaypriority
1289 * option.
1290 */
1291 if ((rdev->disp_priority == 2) &&
1292 (rdev->family == CHIP_RV515)) {
1293 tmp = RREG32_MC(MC_MISC_LAT_TIMER);
1294 tmp &= ~MC_DISP1R_INIT_LAT_MASK;
1295 tmp &= ~MC_DISP0R_INIT_LAT_MASK;
1296 if (mode1)
1297 tmp |= (1 << MC_DISP1R_INIT_LAT_SHIFT);
1298 if (mode0)
1299 tmp |= (1 << MC_DISP0R_INIT_LAT_SHIFT);
1300 WREG32_MC(MC_MISC_LAT_TIMER, tmp);
1301 }
1302 rv515_bandwidth_avivo_update(rdev);
1303 }
1304
