1 /* 2 * HDMI header definition for OMAP4 HDMI core IP 3 * 4 * Copyright (C) 2010-2011 Texas Instruments Incorporated - http://www.ti.com/ 5 * 6 * This program is free software; you can redistribute it and/or modify it 7 * under the terms of the GNU General Public License version 2 as published by 8 * the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, but WITHOUT 11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 13 * more details. 14 * 15 * You should have received a copy of the GNU General Public License along with 16 * this program. If not, see <http://www.gnu.org/licenses/>. 17 */ 18 19 #ifndef _HDMI4_CORE_H_ 20 #define _HDMI4_CORE_H_ 21 22 #include "hdmi.h" 23 24 /* OMAP4 HDMI IP Core System */ 25 26 #define HDMI_CORE_SYS_VND_IDL 0x0 27 #define HDMI_CORE_SYS_DEV_IDL 0x8 28 #define HDMI_CORE_SYS_DEV_IDH 0xC 29 #define HDMI_CORE_SYS_DEV_REV 0x10 30 #define HDMI_CORE_SYS_SRST 0x14 31 #define HDMI_CORE_SYS_SYS_CTRL1 0x20 32 #define HDMI_CORE_SYS_SYS_STAT 0x24 33 #define HDMI_CORE_SYS_SYS_CTRL3 0x28 34 #define HDMI_CORE_SYS_DCTL 0x34 35 #define HDMI_CORE_SYS_DE_DLY 0xC8 36 #define HDMI_CORE_SYS_DE_CTRL 0xCC 37 #define HDMI_CORE_SYS_DE_TOP 0xD0 38 #define HDMI_CORE_SYS_DE_CNTL 0xD8 39 #define HDMI_CORE_SYS_DE_CNTH 0xDC 40 #define HDMI_CORE_SYS_DE_LINL 0xE0 41 #define HDMI_CORE_SYS_DE_LINH_1 0xE4 42 #define HDMI_CORE_SYS_HRES_L 0xE8 43 #define HDMI_CORE_SYS_HRES_H 0xEC 44 #define HDMI_CORE_SYS_VRES_L 0xF0 45 #define HDMI_CORE_SYS_VRES_H 0xF4 46 #define HDMI_CORE_SYS_IADJUST 0xF8 47 #define HDMI_CORE_SYS_POLDETECT 0xFC 48 #define HDMI_CORE_SYS_HWIDTH1 0x110 49 #define HDMI_CORE_SYS_HWIDTH2 0x114 50 #define HDMI_CORE_SYS_VWIDTH 0x11C 51 #define HDMI_CORE_SYS_VID_CTRL 0x120 52 #define HDMI_CORE_SYS_VID_ACEN 0x124 53 #define HDMI_CORE_SYS_VID_MODE 0x128 54 #define HDMI_CORE_SYS_VID_BLANK1 0x12C 55 #define HDMI_CORE_SYS_VID_BLANK2 0x130 56 #define HDMI_CORE_SYS_VID_BLANK3 0x134 57 #define HDMI_CORE_SYS_DC_HEADER 0x138 58 #define HDMI_CORE_SYS_VID_DITHER 0x13C 59 #define HDMI_CORE_SYS_RGB2XVYCC_CT 0x140 60 #define HDMI_CORE_SYS_R2Y_COEFF_LOW 0x144 61 #define HDMI_CORE_SYS_R2Y_COEFF_UP 0x148 62 #define HDMI_CORE_SYS_G2Y_COEFF_LOW 0x14C 63 #define HDMI_CORE_SYS_G2Y_COEFF_UP 0x150 64 #define HDMI_CORE_SYS_B2Y_COEFF_LOW 0x154 65 #define HDMI_CORE_SYS_B2Y_COEFF_UP 0x158 66 #define HDMI_CORE_SYS_R2CB_COEFF_LOW 0x15C 67 #define HDMI_CORE_SYS_R2CB_COEFF_UP 0x160 68 #define HDMI_CORE_SYS_G2CB_COEFF_LOW 0x164 69 #define HDMI_CORE_SYS_G2CB_COEFF_UP 0x168 70 #define HDMI_CORE_SYS_B2CB_COEFF_LOW 0x16C 71 #define HDMI_CORE_SYS_B2CB_COEFF_UP 0x170 72 #define HDMI_CORE_SYS_R2CR_COEFF_LOW 0x174 73 #define HDMI_CORE_SYS_R2CR_COEFF_UP 0x178 74 #define HDMI_CORE_SYS_G2CR_COEFF_LOW 0x17C 75 #define HDMI_CORE_SYS_G2CR_COEFF_UP 0x180 76 #define HDMI_CORE_SYS_B2CR_COEFF_LOW 0x184 77 #define HDMI_CORE_SYS_B2CR_COEFF_UP 0x188 78 #define HDMI_CORE_SYS_RGB_OFFSET_LOW 0x18C 79 #define HDMI_CORE_SYS_RGB_OFFSET_UP 0x190 80 #define HDMI_CORE_SYS_Y_OFFSET_LOW 0x194 81 #define HDMI_CORE_SYS_Y_OFFSET_UP 0x198 82 #define HDMI_CORE_SYS_CBCR_OFFSET_LOW 0x19C 83 #define HDMI_CORE_SYS_CBCR_OFFSET_UP 0x1A0 84 #define HDMI_CORE_SYS_INTR_STATE 0x1C0 85 #define HDMI_CORE_SYS_INTR1 0x1C4 86 #define HDMI_CORE_SYS_INTR2 0x1C8 87 #define HDMI_CORE_SYS_INTR3 0x1CC 88 #define HDMI_CORE_SYS_INTR4 0x1D0 89 #define HDMI_CORE_SYS_INTR_UNMASK1 0x1D4 90 #define HDMI_CORE_SYS_INTR_UNMASK2 0x1D8 91 #define HDMI_CORE_SYS_INTR_UNMASK3 0x1DC 92 #define HDMI_CORE_SYS_INTR_UNMASK4 0x1E0 93 #define HDMI_CORE_SYS_INTR_CTRL 0x1E4 94 #define HDMI_CORE_SYS_TMDS_CTRL 0x208 95 96 /* value definitions for HDMI_CORE_SYS_SYS_CTRL1 fields */ 97 #define HDMI_CORE_SYS_SYS_CTRL1_VEN_FOLLOWVSYNC 0x1 98 #define HDMI_CORE_SYS_SYS_CTRL1_HEN_FOLLOWHSYNC 0x1 99 #define HDMI_CORE_SYS_SYS_CTRL1_BSEL_24BITBUS 0x1 100 #define HDMI_CORE_SYS_SYS_CTRL1_EDGE_RISINGEDGE 0x1 101 102 /* HDMI DDC E-DID */ 103 #define HDMI_CORE_DDC_ADDR 0x3B4 104 #define HDMI_CORE_DDC_SEGM 0x3B8 105 #define HDMI_CORE_DDC_OFFSET 0x3BC 106 #define HDMI_CORE_DDC_COUNT1 0x3C0 107 #define HDMI_CORE_DDC_COUNT2 0x3C4 108 #define HDMI_CORE_DDC_STATUS 0x3C8 109 #define HDMI_CORE_DDC_CMD 0x3CC 110 #define HDMI_CORE_DDC_DATA 0x3D0 111 112 /* HDMI IP Core Audio Video */ 113 114 #define HDMI_CORE_AV_ACR_CTRL 0x4 115 #define HDMI_CORE_AV_FREQ_SVAL 0x8 116 #define HDMI_CORE_AV_N_SVAL1 0xC 117 #define HDMI_CORE_AV_N_SVAL2 0x10 118 #define HDMI_CORE_AV_N_SVAL3 0x14 119 #define HDMI_CORE_AV_CTS_SVAL1 0x18 120 #define HDMI_CORE_AV_CTS_SVAL2 0x1C 121 #define HDMI_CORE_AV_CTS_SVAL3 0x20 122 #define HDMI_CORE_AV_CTS_HVAL1 0x24 123 #define HDMI_CORE_AV_CTS_HVAL2 0x28 124 #define HDMI_CORE_AV_CTS_HVAL3 0x2C 125 #define HDMI_CORE_AV_AUD_MODE 0x50 126 #define HDMI_CORE_AV_SPDIF_CTRL 0x54 127 #define HDMI_CORE_AV_HW_SPDIF_FS 0x60 128 #define HDMI_CORE_AV_SWAP_I2S 0x64 129 #define HDMI_CORE_AV_SPDIF_ERTH 0x6C 130 #define HDMI_CORE_AV_I2S_IN_MAP 0x70 131 #define HDMI_CORE_AV_I2S_IN_CTRL 0x74 132 #define HDMI_CORE_AV_I2S_CHST0 0x78 133 #define HDMI_CORE_AV_I2S_CHST1 0x7C 134 #define HDMI_CORE_AV_I2S_CHST2 0x80 135 #define HDMI_CORE_AV_I2S_CHST4 0x84 136 #define HDMI_CORE_AV_I2S_CHST5 0x88 137 #define HDMI_CORE_AV_ASRC 0x8C 138 #define HDMI_CORE_AV_I2S_IN_LEN 0x90 139 #define HDMI_CORE_AV_HDMI_CTRL 0xBC 140 #define HDMI_CORE_AV_AUDO_TXSTAT 0xC0 141 #define HDMI_CORE_AV_AUD_PAR_BUSCLK_1 0xCC 142 #define HDMI_CORE_AV_AUD_PAR_BUSCLK_2 0xD0 143 #define HDMI_CORE_AV_AUD_PAR_BUSCLK_3 0xD4 144 #define HDMI_CORE_AV_TEST_TXCTRL 0xF0 145 #define HDMI_CORE_AV_DPD 0xF4 146 #define HDMI_CORE_AV_PB_CTRL1 0xF8 147 #define HDMI_CORE_AV_PB_CTRL2 0xFC 148 #define HDMI_CORE_AV_AVI_BASE 0x100 149 #define HDMI_CORE_AV_AVI_TYPE 0x100 150 #define HDMI_CORE_AV_AVI_VERS 0x104 151 #define HDMI_CORE_AV_AVI_LEN 0x108 152 #define HDMI_CORE_AV_AVI_CHSUM 0x10C 153 #define HDMI_CORE_AV_AVI_DBYTE(n) (n * 4 + 0x110) 154 #define HDMI_CORE_AV_SPD_TYPE 0x180 155 #define HDMI_CORE_AV_SPD_VERS 0x184 156 #define HDMI_CORE_AV_SPD_LEN 0x188 157 #define HDMI_CORE_AV_SPD_CHSUM 0x18C 158 #define HDMI_CORE_AV_SPD_DBYTE(n) (n * 4 + 0x190) 159 #define HDMI_CORE_AV_AUDIO_TYPE 0x200 160 #define HDMI_CORE_AV_AUDIO_VERS 0x204 161 #define HDMI_CORE_AV_AUDIO_LEN 0x208 162 #define HDMI_CORE_AV_AUDIO_CHSUM 0x20C 163 #define HDMI_CORE_AV_AUD_DBYTE(n) (n * 4 + 0x210) 164 #define HDMI_CORE_AV_MPEG_TYPE 0x280 165 #define HDMI_CORE_AV_MPEG_VERS 0x284 166 #define HDMI_CORE_AV_MPEG_LEN 0x288 167 #define HDMI_CORE_AV_MPEG_CHSUM 0x28C 168 #define HDMI_CORE_AV_MPEG_DBYTE(n) (n * 4 + 0x290) 169 #define HDMI_CORE_AV_GEN_DBYTE(n) (n * 4 + 0x300) 170 #define HDMI_CORE_AV_CP_BYTE1 0x37C 171 #define HDMI_CORE_AV_GEN2_DBYTE(n) (n * 4 + 0x380) 172 #define HDMI_CORE_AV_CEC_ADDR_ID 0x3FC 173 174 #define HDMI_CORE_AV_SPD_DBYTE_ELSIZE 0x4 175 #define HDMI_CORE_AV_GEN2_DBYTE_ELSIZE 0x4 176 #define HDMI_CORE_AV_MPEG_DBYTE_ELSIZE 0x4 177 #define HDMI_CORE_AV_GEN_DBYTE_ELSIZE 0x4 178 179 #define HDMI_CORE_AV_AVI_DBYTE_NELEMS 15 180 #define HDMI_CORE_AV_SPD_DBYTE_NELEMS 27 181 #define HDMI_CORE_AV_AUD_DBYTE_NELEMS 10 182 #define HDMI_CORE_AV_MPEG_DBYTE_NELEMS 27 183 #define HDMI_CORE_AV_GEN_DBYTE_NELEMS 31 184 #define HDMI_CORE_AV_GEN2_DBYTE_NELEMS 31 185 186 enum hdmi_core_inputbus_width { 187 HDMI_INPUT_8BIT = 0, 188 HDMI_INPUT_10BIT = 1, 189 HDMI_INPUT_12BIT = 2 190 }; 191 192 enum hdmi_core_dither_trunc { 193 HDMI_OUTPUTTRUNCATION_8BIT = 0, 194 HDMI_OUTPUTTRUNCATION_10BIT = 1, 195 HDMI_OUTPUTTRUNCATION_12BIT = 2, 196 HDMI_OUTPUTDITHER_8BIT = 3, 197 HDMI_OUTPUTDITHER_10BIT = 4, 198 HDMI_OUTPUTDITHER_12BIT = 5 199 }; 200 201 enum hdmi_core_deepcolor_ed { 202 HDMI_DEEPCOLORPACKECTDISABLE = 0, 203 HDMI_DEEPCOLORPACKECTENABLE = 1 204 }; 205 206 enum hdmi_core_packet_mode { 207 HDMI_PACKETMODERESERVEDVALUE = 0, 208 HDMI_PACKETMODE24BITPERPIXEL = 4, 209 HDMI_PACKETMODE30BITPERPIXEL = 5, 210 HDMI_PACKETMODE36BITPERPIXEL = 6, 211 HDMI_PACKETMODE48BITPERPIXEL = 7 212 }; 213 214 enum hdmi_core_tclkselclkmult { 215 HDMI_FPLL05IDCK = 0, 216 HDMI_FPLL10IDCK = 1, 217 HDMI_FPLL20IDCK = 2, 218 HDMI_FPLL40IDCK = 3 219 }; 220 221 enum hdmi_core_packet_ctrl { 222 HDMI_PACKETENABLE = 1, 223 HDMI_PACKETDISABLE = 0, 224 HDMI_PACKETREPEATON = 1, 225 HDMI_PACKETREPEATOFF = 0 226 }; 227 228 enum hdmi_audio_i2s_config { 229 HDMI_AUDIO_I2S_MSB_SHIFTED_FIRST = 0, 230 HDMI_AUDIO_I2S_LSB_SHIFTED_FIRST = 1, 231 HDMI_AUDIO_I2S_SCK_EDGE_FALLING = 0, 232 HDMI_AUDIO_I2S_SCK_EDGE_RISING = 1, 233 HDMI_AUDIO_I2S_VBIT_FOR_PCM = 0, 234 HDMI_AUDIO_I2S_VBIT_FOR_COMPRESSED = 1, 235 HDMI_AUDIO_I2S_FIRST_BIT_SHIFT = 0, 236 HDMI_AUDIO_I2S_FIRST_BIT_NO_SHIFT = 1, 237 HDMI_AUDIO_I2S_SD0_EN = 1, 238 HDMI_AUDIO_I2S_SD1_EN = 1 << 1, 239 HDMI_AUDIO_I2S_SD2_EN = 1 << 2, 240 HDMI_AUDIO_I2S_SD3_EN = 1 << 3, 241 }; 242 243 struct hdmi_core_video_config { 244 enum hdmi_core_inputbus_width ip_bus_width; 245 enum hdmi_core_dither_trunc op_dither_truc; 246 enum hdmi_core_deepcolor_ed deep_color_pkt; 247 enum hdmi_core_packet_mode pkt_mode; 248 enum hdmi_core_hdmi_dvi hdmi_dvi; 249 enum hdmi_core_tclkselclkmult tclk_sel_clkmult; 250 }; 251 252 struct hdmi_core_packet_enable_repeat { 253 u32 audio_pkt; 254 u32 audio_pkt_repeat; 255 u32 avi_infoframe; 256 u32 avi_infoframe_repeat; 257 u32 gen_cntrl_pkt; 258 u32 gen_cntrl_pkt_repeat; 259 u32 generic_pkt; 260 u32 generic_pkt_repeat; 261 }; 262 263 int hdmi4_read_edid(struct hdmi_core_data *core, u8 *edid, int len); 264 void hdmi4_configure(struct hdmi_core_data *core, struct hdmi_wp_data *wp, 265 struct hdmi_config *cfg); 266 void hdmi4_core_dump(struct hdmi_core_data *core, struct seq_file *s); 267 int hdmi4_core_init(struct platform_device *pdev, struct hdmi_core_data *core); 268 269 int hdmi4_core_enable(struct hdmi_core_data *core); 270 void hdmi4_core_disable(struct hdmi_core_data *core); 271 void hdmi4_core_powerdown_disable(struct hdmi_core_data *core); 272 273 int hdmi4_audio_start(struct hdmi_core_data *core, struct hdmi_wp_data *wp); 274 void hdmi4_audio_stop(struct hdmi_core_data *core, struct hdmi_wp_data *wp); 275 int hdmi4_audio_config(struct hdmi_core_data *core, struct hdmi_wp_data *wp, 276 struct omap_dss_audio *audio, u32 pclk); 277 #endif 278
