1 /*
2 * Toppoly TD028TTEC1 panel support
3 *
4 * Copyright (C) 2008 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
6 *
7 * Neo 1973 code (jbt6k74.c):
8 * Copyright (C) 2006-2007 by OpenMoko, Inc.
9 * Author: Harald Welte <laforge@openmoko.org>
10 *
11 * Ported and adapted from Neo 1973 U-Boot by:
12 * H. Nikolaus Schaller <hns@goldelico.com>
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of the GNU General Public License version 2 as published by
16 * the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * more details.
22 *
23 * You should have received a copy of the GNU General Public License along with
24 * this program. If not, see <http://www.gnu.org/licenses/>.
25 */
26
27 #include <linux/module.h>
28 #include <linux/delay.h>
29 #include <linux/spi/spi.h>
30 #include <linux/gpio.h>
31
32 #include "../dss/omapdss.h"
33
34 struct panel_drv_data {
35 struct omap_dss_device dssdev;
36 struct omap_dss_device *in;
37
38 struct videomode vm;
39
40 struct spi_device *spi_dev;
41 };
42
43 static const struct videomode td028ttec1_panel_vm = {
44 .hactive = 480,
45 .vactive = 640,
46 .pixelclock = 22153000,
47 .hfront_porch = 24,
48 .hsync_len = 8,
49 .hback_porch = 8,
50 .vfront_porch = 4,
51 .vsync_len = 2,
52 .vback_porch = 2,
53
54 .flags = DISPLAY_FLAGS_HSYNC_LOW | DISPLAY_FLAGS_VSYNC_LOW |
55 DISPLAY_FLAGS_DE_HIGH | DISPLAY_FLAGS_SYNC_POSEDGE |
56 DISPLAY_FLAGS_PIXDATA_NEGEDGE,
57 /*
58 * Note: According to the panel documentation:
59 * SYNC needs to be driven on the FALLING edge
60 */
61 };
62
63 #define JBT_COMMAND 0x000
64 #define JBT_DATA 0x100
65
jbt_ret_write_0(struct panel_drv_data * ddata,u8 reg)66 static int jbt_ret_write_0(struct panel_drv_data *ddata, u8 reg)
67 {
68 int rc;
69 u16 tx_buf = JBT_COMMAND | reg;
70
71 rc = spi_write(ddata->spi_dev, (u8 *)&tx_buf,
72 1*sizeof(u16));
73 if (rc != 0)
74 dev_err(&ddata->spi_dev->dev,
75 "jbt_ret_write_0 spi_write ret %d\n", rc);
76
77 return rc;
78 }
79
jbt_reg_write_1(struct panel_drv_data * ddata,u8 reg,u8 data)80 static int jbt_reg_write_1(struct panel_drv_data *ddata, u8 reg, u8 data)
81 {
82 int rc;
83 u16 tx_buf[2];
84
85 tx_buf[0] = JBT_COMMAND | reg;
86 tx_buf[1] = JBT_DATA | data;
87 rc = spi_write(ddata->spi_dev, (u8 *)tx_buf,
88 2*sizeof(u16));
89 if (rc != 0)
90 dev_err(&ddata->spi_dev->dev,
91 "jbt_reg_write_1 spi_write ret %d\n", rc);
92
93 return rc;
94 }
95
jbt_reg_write_2(struct panel_drv_data * ddata,u8 reg,u16 data)96 static int jbt_reg_write_2(struct panel_drv_data *ddata, u8 reg, u16 data)
97 {
98 int rc;
99 u16 tx_buf[3];
100
101 tx_buf[0] = JBT_COMMAND | reg;
102 tx_buf[1] = JBT_DATA | (data >> 8);
103 tx_buf[2] = JBT_DATA | (data & 0xff);
104
105 rc = spi_write(ddata->spi_dev, (u8 *)tx_buf,
106 3*sizeof(u16));
107
108 if (rc != 0)
109 dev_err(&ddata->spi_dev->dev,
110 "jbt_reg_write_2 spi_write ret %d\n", rc);
111
112 return rc;
113 }
114
115 enum jbt_register {
116 JBT_REG_SLEEP_IN = 0x10,
117 JBT_REG_SLEEP_OUT = 0x11,
118
119 JBT_REG_DISPLAY_OFF = 0x28,
120 JBT_REG_DISPLAY_ON = 0x29,
121
122 JBT_REG_RGB_FORMAT = 0x3a,
123 JBT_REG_QUAD_RATE = 0x3b,
124
125 JBT_REG_POWER_ON_OFF = 0xb0,
126 JBT_REG_BOOSTER_OP = 0xb1,
127 JBT_REG_BOOSTER_MODE = 0xb2,
128 JBT_REG_BOOSTER_FREQ = 0xb3,
129 JBT_REG_OPAMP_SYSCLK = 0xb4,
130 JBT_REG_VSC_VOLTAGE = 0xb5,
131 JBT_REG_VCOM_VOLTAGE = 0xb6,
132 JBT_REG_EXT_DISPL = 0xb7,
133 JBT_REG_OUTPUT_CONTROL = 0xb8,
134 JBT_REG_DCCLK_DCEV = 0xb9,
135 JBT_REG_DISPLAY_MODE1 = 0xba,
136 JBT_REG_DISPLAY_MODE2 = 0xbb,
137 JBT_REG_DISPLAY_MODE = 0xbc,
138 JBT_REG_ASW_SLEW = 0xbd,
139 JBT_REG_DUMMY_DISPLAY = 0xbe,
140 JBT_REG_DRIVE_SYSTEM = 0xbf,
141
142 JBT_REG_SLEEP_OUT_FR_A = 0xc0,
143 JBT_REG_SLEEP_OUT_FR_B = 0xc1,
144 JBT_REG_SLEEP_OUT_FR_C = 0xc2,
145 JBT_REG_SLEEP_IN_LCCNT_D = 0xc3,
146 JBT_REG_SLEEP_IN_LCCNT_E = 0xc4,
147 JBT_REG_SLEEP_IN_LCCNT_F = 0xc5,
148 JBT_REG_SLEEP_IN_LCCNT_G = 0xc6,
149
150 JBT_REG_GAMMA1_FINE_1 = 0xc7,
151 JBT_REG_GAMMA1_FINE_2 = 0xc8,
152 JBT_REG_GAMMA1_INCLINATION = 0xc9,
153 JBT_REG_GAMMA1_BLUE_OFFSET = 0xca,
154
155 JBT_REG_BLANK_CONTROL = 0xcf,
156 JBT_REG_BLANK_TH_TV = 0xd0,
157 JBT_REG_CKV_ON_OFF = 0xd1,
158 JBT_REG_CKV_1_2 = 0xd2,
159 JBT_REG_OEV_TIMING = 0xd3,
160 JBT_REG_ASW_TIMING_1 = 0xd4,
161 JBT_REG_ASW_TIMING_2 = 0xd5,
162
163 JBT_REG_HCLOCK_VGA = 0xec,
164 JBT_REG_HCLOCK_QVGA = 0xed,
165 };
166
167 #define to_panel_data(p) container_of(p, struct panel_drv_data, dssdev)
168
td028ttec1_panel_connect(struct omap_dss_device * dssdev)169 static int td028ttec1_panel_connect(struct omap_dss_device *dssdev)
170 {
171 struct panel_drv_data *ddata = to_panel_data(dssdev);
172 struct omap_dss_device *in;
173 int r;
174
175 if (omapdss_device_is_connected(dssdev))
176 return 0;
177
178 in = omapdss_of_find_source_for_first_ep(dssdev->dev->of_node);
179 if (IS_ERR(in)) {
180 dev_err(dssdev->dev, "failed to find video source\n");
181 return PTR_ERR(in);
182 }
183
184 r = in->ops.dpi->connect(in, dssdev);
185 if (r) {
186 omap_dss_put_device(in);
187 return r;
188 }
189
190 ddata->in = in;
191 return 0;
192 }
193
td028ttec1_panel_disconnect(struct omap_dss_device * dssdev)194 static void td028ttec1_panel_disconnect(struct omap_dss_device *dssdev)
195 {
196 struct panel_drv_data *ddata = to_panel_data(dssdev);
197 struct omap_dss_device *in = ddata->in;
198
199 if (!omapdss_device_is_connected(dssdev))
200 return;
201
202 in->ops.dpi->disconnect(in, dssdev);
203
204 omap_dss_put_device(in);
205 ddata->in = NULL;
206 }
207
td028ttec1_panel_enable(struct omap_dss_device * dssdev)208 static int td028ttec1_panel_enable(struct omap_dss_device *dssdev)
209 {
210 struct panel_drv_data *ddata = to_panel_data(dssdev);
211 struct omap_dss_device *in = ddata->in;
212 int r;
213
214 if (!omapdss_device_is_connected(dssdev))
215 return -ENODEV;
216
217 if (omapdss_device_is_enabled(dssdev))
218 return 0;
219
220 in->ops.dpi->set_timings(in, &ddata->vm);
221
222 r = in->ops.dpi->enable(in);
223 if (r)
224 return r;
225
226 dev_dbg(dssdev->dev, "td028ttec1_panel_enable() - state %d\n",
227 dssdev->state);
228
229 /* three times command zero */
230 r |= jbt_ret_write_0(ddata, 0x00);
231 usleep_range(1000, 2000);
232 r |= jbt_ret_write_0(ddata, 0x00);
233 usleep_range(1000, 2000);
234 r |= jbt_ret_write_0(ddata, 0x00);
235 usleep_range(1000, 2000);
236
237 if (r) {
238 dev_warn(dssdev->dev, "transfer error\n");
239 goto transfer_err;
240 }
241
242 /* deep standby out */
243 r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x17);
244
245 /* RGB I/F on, RAM write off, QVGA through, SIGCON enable */
246 r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE, 0x80);
247
248 /* Quad mode off */
249 r |= jbt_reg_write_1(ddata, JBT_REG_QUAD_RATE, 0x00);
250
251 /* AVDD on, XVDD on */
252 r |= jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x16);
253
254 /* Output control */
255 r |= jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0xfff9);
256
257 /* Sleep mode off */
258 r |= jbt_ret_write_0(ddata, JBT_REG_SLEEP_OUT);
259
260 /* at this point we have like 50% grey */
261
262 /* initialize register set */
263 r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE1, 0x01);
264 r |= jbt_reg_write_1(ddata, JBT_REG_DISPLAY_MODE2, 0x00);
265 r |= jbt_reg_write_1(ddata, JBT_REG_RGB_FORMAT, 0x60);
266 r |= jbt_reg_write_1(ddata, JBT_REG_DRIVE_SYSTEM, 0x10);
267 r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_OP, 0x56);
268 r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_MODE, 0x33);
269 r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11);
270 r |= jbt_reg_write_1(ddata, JBT_REG_BOOSTER_FREQ, 0x11);
271 r |= jbt_reg_write_1(ddata, JBT_REG_OPAMP_SYSCLK, 0x02);
272 r |= jbt_reg_write_1(ddata, JBT_REG_VSC_VOLTAGE, 0x2b);
273 r |= jbt_reg_write_1(ddata, JBT_REG_VCOM_VOLTAGE, 0x40);
274 r |= jbt_reg_write_1(ddata, JBT_REG_EXT_DISPL, 0x03);
275 r |= jbt_reg_write_1(ddata, JBT_REG_DCCLK_DCEV, 0x04);
276 /*
277 * default of 0x02 in JBT_REG_ASW_SLEW responsible for 72Hz requirement
278 * to avoid red / blue flicker
279 */
280 r |= jbt_reg_write_1(ddata, JBT_REG_ASW_SLEW, 0x04);
281 r |= jbt_reg_write_1(ddata, JBT_REG_DUMMY_DISPLAY, 0x00);
282
283 r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_A, 0x11);
284 r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_B, 0x11);
285 r |= jbt_reg_write_1(ddata, JBT_REG_SLEEP_OUT_FR_C, 0x11);
286 r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_D, 0x2040);
287 r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_E, 0x60c0);
288 r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_F, 0x1020);
289 r |= jbt_reg_write_2(ddata, JBT_REG_SLEEP_IN_LCCNT_G, 0x60c0);
290
291 r |= jbt_reg_write_2(ddata, JBT_REG_GAMMA1_FINE_1, 0x5533);
292 r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_FINE_2, 0x00);
293 r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_INCLINATION, 0x00);
294 r |= jbt_reg_write_1(ddata, JBT_REG_GAMMA1_BLUE_OFFSET, 0x00);
295
296 r |= jbt_reg_write_2(ddata, JBT_REG_HCLOCK_VGA, 0x1f0);
297 r |= jbt_reg_write_1(ddata, JBT_REG_BLANK_CONTROL, 0x02);
298 r |= jbt_reg_write_2(ddata, JBT_REG_BLANK_TH_TV, 0x0804);
299
300 r |= jbt_reg_write_1(ddata, JBT_REG_CKV_ON_OFF, 0x01);
301 r |= jbt_reg_write_2(ddata, JBT_REG_CKV_1_2, 0x0000);
302
303 r |= jbt_reg_write_2(ddata, JBT_REG_OEV_TIMING, 0x0d0e);
304 r |= jbt_reg_write_2(ddata, JBT_REG_ASW_TIMING_1, 0x11a4);
305 r |= jbt_reg_write_1(ddata, JBT_REG_ASW_TIMING_2, 0x0e);
306
307 r |= jbt_ret_write_0(ddata, JBT_REG_DISPLAY_ON);
308
309 dssdev->state = OMAP_DSS_DISPLAY_ACTIVE;
310
311 transfer_err:
312
313 return r ? -EIO : 0;
314 }
315
td028ttec1_panel_disable(struct omap_dss_device * dssdev)316 static void td028ttec1_panel_disable(struct omap_dss_device *dssdev)
317 {
318 struct panel_drv_data *ddata = to_panel_data(dssdev);
319 struct omap_dss_device *in = ddata->in;
320
321 if (!omapdss_device_is_enabled(dssdev))
322 return;
323
324 dev_dbg(dssdev->dev, "td028ttec1_panel_disable()\n");
325
326 jbt_ret_write_0(ddata, JBT_REG_DISPLAY_OFF);
327 jbt_reg_write_2(ddata, JBT_REG_OUTPUT_CONTROL, 0x8002);
328 jbt_ret_write_0(ddata, JBT_REG_SLEEP_IN);
329 jbt_reg_write_1(ddata, JBT_REG_POWER_ON_OFF, 0x00);
330
331 in->ops.dpi->disable(in);
332
333 dssdev->state = OMAP_DSS_DISPLAY_DISABLED;
334 }
335
td028ttec1_panel_set_timings(struct omap_dss_device * dssdev,struct videomode * vm)336 static void td028ttec1_panel_set_timings(struct omap_dss_device *dssdev,
337 struct videomode *vm)
338 {
339 struct panel_drv_data *ddata = to_panel_data(dssdev);
340 struct omap_dss_device *in = ddata->in;
341
342 ddata->vm = *vm;
343 dssdev->panel.vm = *vm;
344
345 in->ops.dpi->set_timings(in, vm);
346 }
347
td028ttec1_panel_get_timings(struct omap_dss_device * dssdev,struct videomode * vm)348 static void td028ttec1_panel_get_timings(struct omap_dss_device *dssdev,
349 struct videomode *vm)
350 {
351 struct panel_drv_data *ddata = to_panel_data(dssdev);
352
353 *vm = ddata->vm;
354 }
355
td028ttec1_panel_check_timings(struct omap_dss_device * dssdev,struct videomode * vm)356 static int td028ttec1_panel_check_timings(struct omap_dss_device *dssdev,
357 struct videomode *vm)
358 {
359 struct panel_drv_data *ddata = to_panel_data(dssdev);
360 struct omap_dss_device *in = ddata->in;
361
362 return in->ops.dpi->check_timings(in, vm);
363 }
364
365 static struct omap_dss_driver td028ttec1_ops = {
366 .connect = td028ttec1_panel_connect,
367 .disconnect = td028ttec1_panel_disconnect,
368
369 .enable = td028ttec1_panel_enable,
370 .disable = td028ttec1_panel_disable,
371
372 .set_timings = td028ttec1_panel_set_timings,
373 .get_timings = td028ttec1_panel_get_timings,
374 .check_timings = td028ttec1_panel_check_timings,
375 };
376
td028ttec1_panel_probe(struct spi_device * spi)377 static int td028ttec1_panel_probe(struct spi_device *spi)
378 {
379 struct panel_drv_data *ddata;
380 struct omap_dss_device *dssdev;
381 int r;
382
383 dev_dbg(&spi->dev, "%s\n", __func__);
384
385 spi->bits_per_word = 9;
386 spi->mode = SPI_MODE_3;
387
388 r = spi_setup(spi);
389 if (r < 0) {
390 dev_err(&spi->dev, "spi_setup failed: %d\n", r);
391 return r;
392 }
393
394 ddata = devm_kzalloc(&spi->dev, sizeof(*ddata), GFP_KERNEL);
395 if (ddata == NULL)
396 return -ENOMEM;
397
398 dev_set_drvdata(&spi->dev, ddata);
399
400 ddata->spi_dev = spi;
401
402 ddata->vm = td028ttec1_panel_vm;
403
404 dssdev = &ddata->dssdev;
405 dssdev->dev = &spi->dev;
406 dssdev->driver = &td028ttec1_ops;
407 dssdev->type = OMAP_DISPLAY_TYPE_DPI;
408 dssdev->owner = THIS_MODULE;
409 dssdev->panel.vm = ddata->vm;
410
411 r = omapdss_register_display(dssdev);
412 if (r) {
413 dev_err(&spi->dev, "Failed to register panel\n");
414 return r;
415 }
416
417 return 0;
418 }
419
td028ttec1_panel_remove(struct spi_device * spi)420 static int td028ttec1_panel_remove(struct spi_device *spi)
421 {
422 struct panel_drv_data *ddata = dev_get_drvdata(&spi->dev);
423 struct omap_dss_device *dssdev = &ddata->dssdev;
424
425 dev_dbg(&ddata->spi_dev->dev, "%s\n", __func__);
426
427 omapdss_unregister_display(dssdev);
428
429 td028ttec1_panel_disable(dssdev);
430 td028ttec1_panel_disconnect(dssdev);
431
432 return 0;
433 }
434
435 static const struct of_device_id td028ttec1_of_match[] = {
436 { .compatible = "omapdss,tpo,td028ttec1", },
437 /* keep to not break older DTB */
438 { .compatible = "omapdss,toppoly,td028ttec1", },
439 {},
440 };
441
442 MODULE_DEVICE_TABLE(of, td028ttec1_of_match);
443
444 static const struct spi_device_id td028ttec1_ids[] = {
445 { "toppoly,td028ttec1", 0 },
446 { "tpo,td028ttec1", 0},
447 { /* sentinel */ }
448 };
449
450 MODULE_DEVICE_TABLE(spi, td028ttec1_ids);
451
452
453 static struct spi_driver td028ttec1_spi_driver = {
454 .probe = td028ttec1_panel_probe,
455 .remove = td028ttec1_panel_remove,
456 .id_table = td028ttec1_ids,
457
458 .driver = {
459 .name = "panel-tpo-td028ttec1",
460 .of_match_table = td028ttec1_of_match,
461 .suppress_bind_attrs = true,
462 },
463 };
464
465 module_spi_driver(td028ttec1_spi_driver);
466
467 MODULE_AUTHOR("H. Nikolaus Schaller <hns@goldelico.com>");
468 MODULE_DESCRIPTION("Toppoly TD028TTEC1 panel driver");
469 MODULE_LICENSE("GPL");
470
