1 /*
2 * Copyright 2015 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs <bskeggs@redhat.com>
23 */
24 #include "priv.h"
25
26 #include <core/pci.h>
27
28 static int
g84_pcie_version_supported(struct nvkm_pci * pci)29 g84_pcie_version_supported(struct nvkm_pci *pci)
30 {
31 /* g84 and g86 report wrong information about what they support */
32 return 1;
33 }
34
35 int
g84_pcie_version(struct nvkm_pci * pci)36 g84_pcie_version(struct nvkm_pci *pci)
37 {
38 struct nvkm_device *device = pci->subdev.device;
39 return (nvkm_rd32(device, 0x00154c) & 0x1) + 1;
40 }
41
42 void
g84_pcie_set_version(struct nvkm_pci * pci,u8 ver)43 g84_pcie_set_version(struct nvkm_pci *pci, u8 ver)
44 {
45 struct nvkm_device *device = pci->subdev.device;
46 nvkm_mask(device, 0x00154c, 0x1, (ver >= 2 ? 0x1 : 0x0));
47 }
48
49 static void
g84_pcie_set_cap_speed(struct nvkm_pci * pci,bool full_speed)50 g84_pcie_set_cap_speed(struct nvkm_pci *pci, bool full_speed)
51 {
52 struct nvkm_device *device = pci->subdev.device;
53 nvkm_mask(device, 0x00154c, 0x80, full_speed ? 0x80 : 0x0);
54 }
55
56 enum nvkm_pcie_speed
g84_pcie_cur_speed(struct nvkm_pci * pci)57 g84_pcie_cur_speed(struct nvkm_pci *pci)
58 {
59 u32 reg_v = nvkm_pci_rd32(pci, 0x88) & 0x30000;
60 switch (reg_v) {
61 case 0x30000:
62 return NVKM_PCIE_SPEED_8_0;
63 case 0x20000:
64 return NVKM_PCIE_SPEED_5_0;
65 case 0x10000:
66 default:
67 return NVKM_PCIE_SPEED_2_5;
68 }
69 }
70
71 enum nvkm_pcie_speed
g84_pcie_max_speed(struct nvkm_pci * pci)72 g84_pcie_max_speed(struct nvkm_pci *pci)
73 {
74 u32 reg_v = nvkm_pci_rd32(pci, 0x460) & 0x3300;
75 if (reg_v == 0x2200)
76 return NVKM_PCIE_SPEED_5_0;
77 return NVKM_PCIE_SPEED_2_5;
78 }
79
80 void
g84_pcie_set_link_speed(struct nvkm_pci * pci,enum nvkm_pcie_speed speed)81 g84_pcie_set_link_speed(struct nvkm_pci *pci, enum nvkm_pcie_speed speed)
82 {
83 u32 mask_value;
84
85 if (speed == NVKM_PCIE_SPEED_5_0)
86 mask_value = 0x20;
87 else
88 mask_value = 0x10;
89
90 nvkm_pci_mask(pci, 0x460, 0x30, mask_value);
91 nvkm_pci_mask(pci, 0x460, 0x1, 0x1);
92 }
93
94 int
g84_pcie_set_link(struct nvkm_pci * pci,enum nvkm_pcie_speed speed,u8 width)95 g84_pcie_set_link(struct nvkm_pci *pci, enum nvkm_pcie_speed speed, u8 width)
96 {
97 g84_pcie_set_cap_speed(pci, speed == NVKM_PCIE_SPEED_5_0);
98 g84_pcie_set_link_speed(pci, speed);
99 return 0;
100 }
101
102 void
g84_pci_init(struct nvkm_pci * pci)103 g84_pci_init(struct nvkm_pci *pci)
104 {
105 /* The following only concerns PCIe cards. */
106 if (!pci_is_pcie(pci->pdev))
107 return;
108
109 /* Tag field is 8-bit long, regardless of EXT_TAG.
110 * However, if EXT_TAG is disabled, only the lower 5 bits of the tag
111 * field should be used, limiting the number of request to 32.
112 *
113 * Apparently, 0x041c stores some limit on the number of requests
114 * possible, so if EXT_TAG is disabled, limit that requests number to
115 * 32
116 *
117 * Fixes fdo#86537
118 */
119 if (nvkm_pci_rd32(pci, 0x007c) & 0x00000020)
120 nvkm_pci_mask(pci, 0x0080, 0x00000100, 0x00000100);
121 else
122 nvkm_pci_mask(pci, 0x041c, 0x00000060, 0x00000000);
123 }
124
125 int
g84_pcie_init(struct nvkm_pci * pci)126 g84_pcie_init(struct nvkm_pci *pci)
127 {
128 bool full_speed = g84_pcie_cur_speed(pci) == NVKM_PCIE_SPEED_5_0;
129 g84_pcie_set_cap_speed(pci, full_speed);
130 return 0;
131 }
132
133 static const struct nvkm_pci_func
134 g84_pci_func = {
135 .init = g84_pci_init,
136 .rd32 = nv40_pci_rd32,
137 .wr08 = nv40_pci_wr08,
138 .wr32 = nv40_pci_wr32,
139 .msi_rearm = nv46_pci_msi_rearm,
140
141 .pcie.init = g84_pcie_init,
142 .pcie.set_link = g84_pcie_set_link,
143
144 .pcie.max_speed = g84_pcie_max_speed,
145 .pcie.cur_speed = g84_pcie_cur_speed,
146
147 .pcie.set_version = g84_pcie_set_version,
148 .pcie.version = g84_pcie_version,
149 .pcie.version_supported = g84_pcie_version_supported,
150 };
151
152 int
g84_pci_new(struct nvkm_device * device,int index,struct nvkm_pci ** ppci)153 g84_pci_new(struct nvkm_device *device, int index, struct nvkm_pci **ppci)
154 {
155 return nvkm_pci_new_(&g84_pci_func, device, index, ppci);
156 }
157
